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prelab & Post lab Test Exp 1

lab question paper

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8 views

prelab & Post lab Test Exp 1

lab question paper

Uploaded by

abinavsundhar175
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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P9VD106-VLSI DIGITAL SYSTEM LABORATORY

I ME-VLSI DESIGN
Pre lab 1 Test

1)The utilization of CAD tools for drawing timing waveform diagram and transforming it
into a network of logic gates is known as ________.
a. Waveform Editor
b. Waveform Estimator
c. Waveform Simulator
d. Waveform Evaluator

2) Which among the following is a process of transforming design entry information of the
circuit into a set of logic equations?
a. Simulation
b. Optimization
c. Synthesis
d. Verification

3) _________ is the fundamental architecture block or element of a target PLD.


a. System Partitioning
b. Pre-layout Simulation
c. Logic cell
d. Post-layout Simulation

4) In VLSI design, which process deals with the determination of resistance & capacitance
of interconnections?
a. Floorplanning
b. Placement & Routing
c. Testing
d. Extraction

5) Among the VHDL features, which language statements are executed at the same time in
parallel flow?
a. Concurrent
b. Sequential
c. Net-list
d. Test-bench
6) In Net-list language, the net-list is generated _______synthesizing VHDL code.
a. Before
b. At the time of (during)
c. After
d. None of the above

7) In VHDL, which object/s is/are used to connect entities together for the model
formation?
a. Constant
b. Variable
c. Signal
d. All of the above

8) Which data type in VHDL is non synthesizable & allows the designer to model the
objects of dynamic nature?
a. Scalar
b. Access
c. Composite
d. File

9) Which type of simulation mode is used to check the timing performance of a design?
a. Behavioural
b. Switch-level
c. Transistor-level
d. Gate-level

10) In the simulation process, which step specifies the conversion of VHDL intermediate
code so that it can be used by the simulator?
a. Compilation
b. Elaboration
c. Initialization
d. Execution
P9VD106-VLSI DIGITAL SYSTEM LABORATORY
I ME-VLSI DESIGN
Post lab 1 Test

1) Which type of simulator/s neglect/s the intra-cycle state transitions by checking the
status of target signals periodically irrespective of any events?
a. Event-driven Simulator
b. Cycle-based Simulator
c. Both a and b
d. None of the above

2) Which among the following is not a characteristic of ‘Event-driven Simulator’?


a. Identification of timing violations
b. Storage of state values & time information
c. Time delay calculation
d. No event scheduling

3) Which among the following is an output generated by synthesis process?


a. Attributes & Library
b. RTL VHDL description
c. Circuit constraints
d. Gate-level net list

4) Register transfer level description specifies all of the registers in a design & ______
logic between them.
a. Sequential
b. Combinational
c. Both a and b
d. None of the above

5) In synthesis process, the load attribute specify/ies the existing amount of _________load
on a particular output signal.
a. Inductive
b. Resistive
c. Capacitive
d. All of the above

6) Which attribute in synthesis process specify/ies the resistance by controlling the


quantity of current it can source?
a. Load attribute
b. Drive attribute
c. Arrival time attribute
d. All of the above
7) Which type of digital systems exhibit the necessity for the existence of at least one
feedback path from output to input?
a. Combinational System
b. Sequential system
c. Both a and b
d. None of the above

8) The output of sequential circuit is regarded as a function of time sequence of


__________.
A. Inputs
B. Outputs
C. Internal States
D. External States
a. A & D
b. A & C
c. B & D
d. B & C

9) The time required for an input data to settle _____ the triggering edge of clock is
known as ‘Setup Time’.
a. Before
b. During
c. After
d. All of the above

10) Hold time is defined as the time required for the data to ________ after the triggering
edge of clock.
a. Increase
b. Decrease
c. Remain stable
d. All of the above

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