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prelab & Post lab Test Exp 2

lab experiment

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abinavsundhar175
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10 views

prelab & Post lab Test Exp 2

lab experiment

Uploaded by

abinavsundhar175
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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P9VD106-VLSI DIGITAL SYSTEM LABORATORY

I ME-VLSI DESIGN
Pre lab 2 Test

1) An Antifuse programming technology is predominantly associated with _____.


a. SPLDs
b. FPGAs
c. CPLDs
d. All of the above

2) In fusible link technologies, the undesired fuses are removed by the pulse application of
_____voltage & current to device input.
a. Low
b. Moderate
c. High
d. All of the above

3) Which programming technology/ies is/are predominantly associated with SPLDs and


CPLDs?
a. EPROM
b. EEPROM
c. FLASH
d. All of the above

4) Before the commencement of design, the clocking strategy determine/s __________


a. Number of clock signals necessary for routing throughout the chip
b. Number of transistors used per storage requirement
c. Power dissipated by chip & the size of chip
d. All of the above

5) Which method/s of physical clocking is/are a /the recursive structure where the
memory elements are grouped together to make the use of nearby or same distribution
points?
a. H tree
b. Balanced tree clock network
c. Both a and b
d. None of the above

6) Increase in the physical distance of H-tree _________the skew rate.


a. Increases
b. Stabilizes
c. Decreases
d. All of the above

7) Which type of MOSFET exhibits no current at zero gate voltage?


a. Depletion MOSFET
b. Enhancement MOSFET
c. Both a and b
d. None of the above

8) In enhancement MOSFET, the magnitude of output current __________ due to an


increase in the magnitude of gate potentials.
a. Increases
b. Remains constant
c. Decreases
d. None of the above

9) In DIBL, which among the following is/are regarded as the source/s of leakage?
a. Subthreshold conduction
b. Gate leakage
c. Junction leakage
d. All of the above

10) Which among the following can be regarded as an/the application/s of MOS switch in
an IC design?
a. Multiplexing & Modulation
b. Transmission gate in digital circuits
c. Simulation of a resistor
d. All of the above
P9VD106-VLSI DIGITAL SYSTEM LABORATORY
I ME-VLSI DESIGN
Post lab 2 Test

1) In MOS switch, clock feedthrough effect is also known as __________.


A. charge injection
B. charge feedthrough
C. charge carrier
D. charge ejaculation

a. A & B
b. B & C
c. C & D
d. B & D

2) Which among the following is/are regarded as an/the active resistor/s?


a. MOS diode
b. MOS transistor
c. MOS switch
d. All of the above

3) In testability, which terminology is used to represent or indicate the formal evidences of


correctness?
a. Validation
b. Verification
c. Simulation
d. Integration

4) Which among the following is regarded as an electrical fault?


a. Excessive steady-state currents
b. Delay faults
c. Bridging faults
d. Logical stuck-at-0 or stuck-at-1

5) Which among the following faults occur/s due to physical defects?


a. Process variations & abnormalities
b. Defects in silicon substrate
c. Photolithographic defects
d. All of the above
6) In logic synthesis, ________ is an EDIF that gives the description of logic cells & their
interconnections.
a. Netlist
b. Checklist
c. Shitlist
d. Dualist

7) Which level of system implementation includes the specific function oriented registers,
counters & multiplexers?
a. Module level
b. Logical level
c. Physical level
d. All of the above

8) Which among the following is/are taken into account for post-layout simulation?
a. Interconnect delays
b. Propagation delays
c. Logic cells
d. All of the above

9) Which among the following operation/s is/are executed in physical design or layout
synthesis stage?
a. Placement of logic functions in optimized circuit in target chip
b. Interconnection of components in the chip
c. Both a and b
d. None of the above

10) In VHDL, which class of scalar data type represents the values necessary for a specific
operation?
a. Integer types
b. Real types
c. Physical types
d. Enumerated types

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