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prelab & Post lab Test Exp 3

lab experiment 3

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3 views

prelab & Post lab Test Exp 3

lab experiment 3

Uploaded by

abinavsundhar175
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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P9VD106-VLSI DIGITAL SYSTEM LABORATORY

I ME-VLSI DESIGN
Pre lab 3 Test

1) Which among the following is pre-defined in the standard package as one-dimensional


array type comprising each element of BIT type?
a. Bit type
b. Bit_vector type
c. Boolean type
d. All of the above

2) In composite data type of VHDL, the record type comprises the elements of
_______data types.
a. Same
b. Different
c. Both a and b
d. None of the above

3) Which among the following wait statement execution causes the enclosing process to
suspend and then wait for an event to occur on the signals?
a. Wait until Clk = ‘1’
b. Wait on x,y,z
c. Wait on clock until answer > 80
d. Wait for 12 ns

4) After an initialization phase, the simulator enters the ______phase.


a. Compilation
b. Elaboration
c. Execution
d. None of the above

5) Which concept proves to be beneficial in acquiring concurrency and order


independence?
a. Alpha delay
b. Beta delay
c. Gamma delay
d. Delta delay

6) An event is nothing but ______ target signal, which is to be updated.


a. Fixed
b. Change on
c. Both a and b
d. None of the above

7) Which functions are performed by static timing analysis in simulation?


a. Computation of delay for each timing path
b. Logic analysis in a static manner
c. Both a and b
d. None of the above

8) Which among the following is/are regarded as the function/s of translation step in
synthesis process?
a. Conversion of RTL description to boolean unoptimized description
b. Conversion of an unoptimized to optimized boolean description
c. Conversion of unoptimized boolean description to PLA format
d. All of the above

9) In synthesis flow, which stage/s is/are responsible for converting an unoptimized


boolean description to PLA format?
a. Translation
b. Optimization
c. Flattening
d. All of the above

10) In synthesis flow, the flattening process generates a flat signal representation of
_____levels.
A. AND
B. OR
C. NOT
D. EX-OR

a. A & B
b. C & D
c. A & C
d. B & D
P9VD106-VLSI DIGITAL SYSTEM LABORATORY
I ME-VLSI DESIGN
Post lab 3 Test

1) If the level of fan-out is beyond a limit in synthesis, it results in an insertion of buffer by


ultimate effect of _____ the speed.
a. Enhancing
b. Reducing
c. Stabilizing
d. None of the above

2) Which among the following constraint/s is/are involved in a state-machine description?


a. State variable & clock
b. State transitions & output specifications
c. Reset condition
d. All of the above

3) Which among the following is/are identical in Mealy & Moore machines?
a. Combinational output signal
b. Clocked Process
c. Both a and b
d. None of the above

4) Which method/s is/are adopted for acquiring spike-free outputs?


a. Moore machine with clocked outputs
b. Mealy machine with clocked outputs
c. Output-state machine
d. All of the above

5) In SM chart for UART transmitter, which state/s indicate/s the waiting of sequential
machine for the rising edge of bit clock and the consequent clearing of low order bit of TSR
in order to transmit logic ‘0’ for one bit time?
a. IDLE State
b. Sync State
c. Transmit_Data_State
d. All of the above

6) The devices which are based on fusible link or antifuse are _________time/s
programmable.
a. one
b. two
c. four
d. infinite

7) Which among the following is/are not suitable for in-system programming?
a. EPROM
b. EEPROM
c. Flash
d. All of the above

8) Simple Programmable Logic Devices (SPLDs) are also regarded as _____________.


a. Programmable Array Logic (PAL)
b. Generic Array Logic (GAL)
c. Programmable Logic Array (PLA)
d. All of the above

9) In signal integrity, which noise/s occur/s due to impedance mismatch, stubs, vias and
other interconnection discontinuities?
a. Power/Ground Noise
b. Crosstalk Noise
c. Reflection Noise
d. All of the above

10) In floorplanning, placement and routing are __________ tools.


a. Front end
b. Back end
c. Both a and b
d. None of the above

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