INTEGRATED CIRCUITS

DATA SHEET

PCF8576D
Universal LCD driver for low
multiplex rates
Product specification 2004 Dec 22
Supersedes data of 2004 Oct 07
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

CONTENTS 7.4 Acknowledge

7.5 PCF8576D I2C-bus controller
1 FEATURES 7.6 Input filters
2 GENERAL DESCRIPTION 7.7 I2C-bus protocol
7.8 Command decoder
3 ORDERING INFORMATION
7.9 Display controller
4 BLOCK DIAGRAM 7.10 Cascaded operation
5 PINNING 8 LIMITING VALUES
6 FUNCTIONAL DESCRIPTION 9 HANDLING
6.1 Power-on reset 10 DC CHARACTERISTICS
6.2 LCD bias generator
11 AC CHARACTERISTICS
6.3 LCD voltage selector
6.3.1 LCD bias formulae 12 BONDING PAD INFORMATION
6.4 LCD drive mode waveforms 13 DEVICE PROTECTION
6.4.1 Static drive mode
14 TRAY INFORMATION
6.4.2 1 : 2 multiplex drive mode
6.4.3 1 : 3 multiplex drive mode 15 PACKAGE OUTLINE
6.4.4 1 : 4 multiplex drive mode 16 SOLDERING
6.5 Oscillator 16.1 Introduction to soldering surface mount
6.5.1 Internal clock
packages
6.5.2 External clock 16.2 Reflow soldering
6.6 Timing 16.3 Wave soldering
6.7 Display register 16.4 Manual soldering
6.8 Segment outputs 16.5 Suitability of surface mount IC packages for
6.9 Backplane outputs wave and reflow soldering methods
6.10 Display RAM
6.11 Data pointer 17 DATA SHEET STATUS
6.12 Subaddress counter 18 DEFINITIONS
6.13 Output bank selector 19 DISCLAIMERS
6.14 Input bank selector
20 PURCHASE OF PHILIPS I2C COMPONENTS
6.15 Blinker
7 CHARACTERISTICS OF THE I2C-BUS
7.1 Bit transfer
7.2 Start and stop conditions
7.3 System configuration

2004 Dec 22 2
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

1 FEATURES
• Single-chip LCD controller/driver
• Selectable backplane drive configuration: static or 2/3/4
backplane multiplexing
• Selectable display bias configuration: static, 1/2 and 1/3
• Internal LCD bias generation with voltage-follower • Compatible with 4, 8 or 16-bit microprocessors or
buffers microcontrollers
• 40 segment drives: up to twenty 8-segment numeric • May be cascaded for large LCD applications (up to
characters; up to ten 15-segment alphanumeric 2560 elements possible)
characters; or any graphics of up to 160 elements • No external components
• 40 × 4-bit RAM for display data storage • Compatible with chip-on-glass technology
• Auto-incremental display data loading across device • Manufactured in silicon gate CMOS process.
subaddress boundaries
• Display memory bank switching in static and duplex 2 GENERAL DESCRIPTION
drive modes
The PCF8576D is a peripheral device which interfaces to
• Versatile blinking modes
almost any Liquid Crystal Display (LCD) with low multiplex
• Independent supplies possible for LCD and logic rates. It generates the drive signals for any static or
voltages multiplexed LCD containing up to four backplanes and up
• Wide power supply range: from 1.8 to 5.5 V to 40 segments and can easily be cascaded for larger LCD
applications. The PCF8576D is compatible with most
• Wide logic LCD supply range: from 2.5 V for
microprocessors/microcontrollers and communicates via a
low-threshold LCDs and up to 6.5 V for guest-host LCDs
two-line bidirectional I2C-bus. Communication overheads
and high-threshold (automobile) twisted nematic LCDs
are minimized by a display RAM with auto-incremental
• Low power consumption addressing, by hardware subaddressing and by display
• 400 kHz I2C-bus interface memory switching (static and duplex drive modes).
• TTL/CMOS compatible

3 ORDERING INFORMATION

PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
PCF8576DH TQFP64 plastic thin quad flat package; 64 leads; body 10 × 10 × 1.0 mm SOT357-1
PCF8576DT TSSOP56 plastic thin shrink small outline package; 56 leads; body width SOT364-1
6.1 mm
PCF8576DU/DA − chips in tray −
PCF8576DH/2(1) TQFP64 plastic thin quad flat package; 64 leads; body 10 × 10 × 1.0 mm SOT357-1
PCF8576DT/2(1) TSSOP56 plastic thin shrink small outline package; 56 leads; body width SOT364-1
6.1 mm
PCF8576DU/DA/2(1) − chips in tray −
PCF8576DU/2DA/2(1) − chip with bumps in tray −

Note
1. These types have improved EMC immunity.

2004 Dec 22 3
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2004 Dec 22

Philips Semiconductors
multiplex rates
Universal LCD driver for low
BLOCK DIAGRAM
handbook, full pagewidth BP0 BP2 BP1 BP3 S0 to S39

25 26 27 28 29 to 32, 34 to 47,
49 to 64, 2 to 7
VLCD 21
BACKPLANE
DISPLAY SEGMENT OUTPUTS
OUTPUTS

LCD DISPLAY REGISTER

VOLTAGE
SELECTOR

DISPLAY OUTPUT BANK SELECT

LCD BIAS CONTROLLER AND BLINK CONTROL
20 GENERATOR
VSS
4

13 PCF8576DH DISPLAY
CLK CLOCK SELECT BLINKER RAM
12 AND TIMING TIMEBASE 40 × 4 BIT
SYNC

15 POWER-ON COMMAND WRITE DATA DATA POINTER AND

OSC OSCILLATOR
RESET DECODER CONTROL AUTO INCREMENT
14
VDD
11
SCL INPUT I2C-BUS SUB-ADDRESS
10 FILTERS CONTROLLER COUNTER
SDA
1, 8, 9, 22 to 24, 33, 48
19 16 17 18
MDB075
SA0 n.c. A0 A1 A2

Product specification
PCF8576D
Fig.1 Block diagram for version PCF8576DH.
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2004 Dec 22

Philips Semiconductors
multiplex rates
Universal LCD driver for low
BP0 BP2 BP1 BP3 S0 to S39

56 1 2 3 4 to 43

VLCD 55
BACKPLANE
DISPLAY SEGMENT OUTPUTS
OUTPUTS

LCD DISPLAY REGISTER

VOLTAGE
SELECTOR

DISPLAY OUTPUT BANK SELECT

LCD BIAS CONTROLLER AND BLINK CONTROL
54 GENERATOR
VSS
5

47 PCF8576DT DISPLAY
CLK CLOCK SELECT BLINKER RAM
46 AND TIMING TIMEBASE 40 × 4 BIT
SYNC

49 POWER-ON COMMAND WRITE DATA DATA POINTER AND

OSC OSCILLATOR
RESET DECODER CONTROL AUTO INCREMENT
48
VDD
45
SCL INPUT I2C-BUS SUB-ADDRESS
44 FILTERS CONTROLLER COUNTER
SDA
53 50 51 52

SA0 A0 A1 A2

Product specification
001aab131

PCF8576D
Fig.2 Block diagram for version PCF8576DT.
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

5 PINNING

PIN PAD
SYMBOL DESCRIPTION
PCF8576DH PCF8576DT PCF8576DU
SDA 10 44 1, 58 and 59 I2C-bus serial data input/output
SCL 11 45 2 and 3 I2C-bus serial clock input
CLK 13 47 5 external clock input/output
VDD 14 48 6 supply voltage
SYNC 12 46 4 cascade synchronization
input/output
OSC 15 49 7 internal oscillator enable input
A0 to A2 16 to 18 50 to 52 8 to 10 subaddress inputs
SA0 19 53 11 I2C-bus slave address input; bit 0
VSS 20 54 12 logic ground
VLCD 21 55 13 LCD supply voltage
BP0, BP2, BP1, BP3 25 to 28 56, 1, 2, 3 14 to 17 LCD backplane outputs
S0 to S39 29 to 32, 34 to 47, 4 to 43 18 to 57 LCD segment outputs
49 to 64, 2 to 7
n.c. 1, 8, 9, 22 to 24, − − not connected
33 and 48

2004 Dec 22 6
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

handbook, full pagewidth

64 S33

63 S32

62 S31

61 S30

60 S29

59 S28

58 S27

57 S26

56 S25

55 S24

54 S23

53 S22

52 S21

51 S20

50 S19

49 S18
n.c. 1 48 n.c.

S34 2 47 S17

S35 3 46 S16

S36 4 45 S15

S37 5 44 S14

S38 6 43 S13

S39 7 42 S12

n.c. 8 41 S11
PCF8576DH
n.c. 9 40 S10

SDA 10 39 S9

SCL 11 38 S8

SYNC 12 37 S7

CLK 13 36 S6

VDD 14 35 S5

OSC 15 34 S4

A0 16 33 n.c.
A1 17

A2 18

SA0 19

VSS 20

VLCD 21

n.c. 22

n.c. 23

n.c. 24

BP0 25

BP2 26

BP1 27

BP3 28

S0 29

S1 30

S2 31

S3 32

MDB073

Fig.3 Pin configuration (TQFP64).

2004 Dec 22 7
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

BP2 1 56 BP0
BP1 2 55 VLCD
BP3 3 54 VSS
S0 4 53 SA0
S1 5 52 A2
S2 6 51 A1
S3 7 50 A0
S4 8 49 OSC
S5 9 48 VDD
S6 10 47 CLK
S7 11 46 SYNC
S8 12 45 SCL
S9 13 44 SDA
S10 14 43 S39
PCF8576DT
S11 15 42 S38
S12 16 41 S37
S13 17 40 S36
S14 18 39 S35
S15 19 38 S34
S16 20 37 S33
S17 21 36 S32
S18 22 35 S31
S19 23 34 S30
S20 24 33 S29
S21 25 32 S28
S22 26 31 S27
S23 27 30 S26
S24 28 29 S25

001aab132

Fig.4 Pin configuration (TSSOP56).

2004 Dec 22 8
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

6 FUNCTIONAL DESCRIPTION The host microprocessor/microcontroller maintains the

2-line I2C-bus communication channel with the
The PCF8576D is a versatile peripheral device designed
PCF8576D. The internal oscillator is enabled by
to interface any microprocessor/microcontroller with a
connecting pin OSC to pin VSS. The appropriate biasing
wide variety of LCDs. It can directly drive any static or
voltages for the multiplexed LCD waveforms are
multiplexed LCD containing up to four backplanes and up
generated internally. The only other connections required
to 40 segments.
to complete the system are to the power supplies (VDD,
The display configurations possible with the PCF8576D VSS and VLCD) and the LCD panel chosen for the
depend on the number of active backplane outputs application.
required. A selection of display configurations is shown in
Table 1; all of these configurations can be implemented in
the typical system shown in Fig.5.

Table 1 Selection of display configurations

14-SEGMENTS
NUMBER OF 7-SEGMENTS NUMERIC
ALPHANUMERIC
DOT MATRIX
INDICATOR INDICATOR
BACKPLANES SEGMENTS DIGITS CHARACTERS
SYMBOLS SYMBOLS
4 160 20 20 10 20 160 dots (4 × 40)
3 120 15 15 8 8 120 dots (3 × 40)
2 80 10 10 5 10 80 dots (2 × 40)
1 40 5 5 2 12 40 dots (1 × 40)

VDD
tr
R≤
2CB
VDD VLCD
6 13
HOST SDA 1, 58, 59
40 segment drives LCD PANEL
MICRO-
SCL
PROCESSOR/ 2, 3 PCF8576DU (up to 160
MICRO- OSC elements)
CONTROLLER 7 4 backplanes
8 9 10 11 12
A0 A1 A2 SA0 VSS mdb079

VSS

The resistance of the power supply lines must be kept to a minimum.

For chip-on-glass applications, due to Indium Tin Oxide (ITO) track resistance, each supply line must be routed separately
between the chip and the connector.

Fig.5 Typical system configuration.

2004 Dec 22 9
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

6.1 Power-on reset 6.3.1 LCD BIAS FORMULAE

1
At power-on the PCF8576D resets to the following starting Bias is calculated by the formula -------------
1+a
conditions:
For 1⁄2 bias, a = 1; for 1⁄3 bias, a = 2.
• All backplane outputs are set to VLCD
The LCD on voltage (Von) is calculated by the formula
• All segment outputs are set to VLCD
2
• Drive mode ‘1 : 4 multiplex with 1⁄3 bias’ is selected ---- + ( N – 1 ) ⋅  -------------
1 1
N 1+a
• Blinking is switched off V op
------------------------------------------------------------
N
• Input and output bank selectors are reset (as defined in
Table 4) The LCD off voltage (Voff) is calculated by the formula
• The I2C-bus interface is initialized 2
a – ( 2a + N )
• The data pointer and the subaddress counter are
V op ---------------------------------
2
-
N ⋅ (1 + a)
cleared
• Display is disabled. where Vop is the resultant voltage at the LCD segment; N
is the LCD drive mode: 1 = static, 2 = 1 : 2, 3 = 1 : 3,
Data transfers on the I2C-bus should be avoided for 1 ms 4 = 1 : 4.
following power-on to allow completion of the reset action.
Discrimination is the ratio of Von to Voff, and is determined
6.2 LCD bias generator 2
V on (a + 1) + (N – 1)
by the formula --------- = --------------------------------------------
-
Fractional LCD biasing voltages are obtained from an V off (a – 1) + (N – 1)
2
internal voltage divider comprising three resistors
connected in series between VLCD and VSS. The middle Using the above formula, the discrimination for an LCD
resistor can be bypassed to provide a 1⁄2 bias voltage level drive mode of 1 : 3 with 1⁄2 bias is 3 = 1.732, and the
for the 1 : 2 multiplex configuration. The LCD voltage can
discrimination for an LCD drive mode of 1 : 4 with 1⁄2 bias
be temperature compensated externally via the supply to
pin VLCD. 21
is ---------- = 1.528.
3
6.3 LCD voltage selector
The advantage of these LCD drive modes is a reduction of
The LCD voltage selector co-ordinates the multiplexing of the LCD full-scale voltage VLCD as follows:
the LCD in accordance with the selected LCD drive
configuration. The operation of the voltage selector is 1 : 3 multiplex (1⁄2 bias):
controlled by MODE SET commands from the command VLCD = 6 × V off(rms) = 2.449 Voff(rms)
decoder. The biasing configurations that apply to the
preferred modes of operation, together with the biasing 1 : 4 multiplex (1⁄2 bias):
characteristics as functions of VLCD and the resulting
Discrimination ratios (D), are given in Table 2. VLCD = (4 × 3) = 2.309 Voff(rms)
----------------------
3
A practical value for VLCD is determined by equating
Voff(rms) with a defined LCD threshold voltage (Vth), These compare with VLCD = 3 Voff(rms) when 1⁄3 bias is
typically when the LCD exhibits approximately 10% used.
contrast. In the static drive mode a suitable choice is
VLCD > 3Vth.
Multiplex drive modes of 1 : 3 and 1 : 4 with 1⁄2 bias are
possible but the discrimination and hence the contrast
ratios are smaller.

2004 Dec 22 10
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

Table 2 Discrimination ratios

NUMBER OF LCD BIAS V off(rms) V on(rms) V on(rms)
LCD DRIVE MODE --------------------- --------------------- D = ---------------------
BACKPLANES LEVELS CONFIGURATION V lcd V lcd V off(rms)

static 1 2 static 0 1 ∞
1 : 2 multiplex 2 3 1⁄ 0.354 0.791 2.236
2
1 : 2 multiplex 2 4 1⁄ 0.333 0.745 2.236
3
1 : 3 multiplex 3 4 1⁄ 0.333 0.638 1.915
3
1 : 4 multiplex 4 4 1⁄ 0.333 0.577 1.732
3

6.4 LCD drive mode waveforms

6.4.1 STATIC DRIVE MODE
The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment
drive (Sn) waveforms for this mode are shown in Fig.4.

Tframe
handbook, full pagewidth
VLCD LCD segments

BP0
VSS
state 1 state 2
VLCD (on) (off)

Sn

VSS

VLCD
Sn + 1

VSS
(a) Waveforms at driver.

VLCD

state 1 0V

−VLCD

VLCD

state 2 0V

−VLCD
(b) Resultant waveforms
at LCD segment. MGL745

V on(rms) = V LCD
V state2(t) = V S (t) – V BP0(t)
n+1

V off(rms) = 0 V

Fig.6 Static drive mode waveforms.

2004 Dec 22 11
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

6.4.2 1 : 2 MULTIPLEX DRIVE MODE

The 1 : 2 multiplex drive mode is used when two backplanes are provided in the LCD. This mode allows fractional LCD
bias voltages of 1⁄2 bias or 1⁄3 bias as shown in Figs 7 and 8.

Tframe
handbook, full pagewidth
VLCD LCD segments
BP0 VLCD/2
VSS
state 1
VLCD
state 2
BP1 VLCD/2
VSS

VLCD
Sn
VSS

VLCD

Sn + 1
VSS
(a) Waveforms at driver.

VLCD
VLCD/2

state 1 0V
−VLCD/2

−VLCD

VLCD

VLCD/2

state 2 0V
−VLCD/2
−VLCD
(b) Resultant waveforms MGL746
at LCD segment.

V state1(t) = V S (t) – V BP0(t)

n

V on(rms) = 0.791V LCD

V state2(t) = V S (t) – V BP1(t)
n

V off(rms) = 0.354V LCD

Fig.7 Waveforms for the 1 : 2 multiplex drive mode with 1⁄2 bias.

2004 Dec 22 12
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

Tframe
handbook, full pagewidth
VLCD LCD segments
2VLCD/3
BP0
VLCD/3
VSS
state 1
VLCD
state 2
2VLCD/3
BP1
VLCD/3
VSS

VLCD
2VLCD/3
Sn
VLCD/3
VSS
VLCD
2VLCD/3
Sn + 1 VLCD/3
VSS
(a) Waveforms at driver.
VLCD
2VLCD/3
VLCD/3
state 1 0V
−VLCD/3
−2VLCD/3
−VLCD
VLCD
2VLCD/3
VLCD/3
state 2 0V
−VLCD/3
−2VLCD/3
−VLCD
(b) Resultant waveforms MGL747
at LCD segment.

V state1(t) = V S (t) – V BP0(t)

n

V on(rms) = 0.745V LCD

V state2(t) = V S (t) – V BP1(t)
n

V off(rms) = 0.333V LCD

Fig.8 Waveforms for the 1 : 2 multiplex drive mode with 1⁄3 bias.

2004 Dec 22 13
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

6.4.3 1 : 3 MULTIPLEX DRIVE MODE

When three backplanes are provided in the LCD, the 1 : 3 multiplex drive mode applies (see Fig.9).

handbook, full pagewidth

Tframe
VLCD
LCD segments
2VLCD/3
BP0 VLCD/3
VSS
state 1
VLCD
state 2
2VLCD/3
BP1 VLCD/3
VSS

VLCD
2VLCD/3
BP2
VLCD/3
VSS
VLCD
2VLCD/3
Sn
VLCD/3
VSS

VLCD
2VLCD/3
Sn + 1
VLCD/3
VSS

VLCD
2VLCD/3
Sn + 2 VLCD/3
VSS
(a) Waveforms at driver.
VLCD
2VLCD/3
VLCD/3
state 1 0V
−VLCD/3
−2VLCD/3
−VLCD

VLCD
2VLCD/3
VLCD/3
state 2 0V
−VLCD/3
−2VLCD/3
−VLCD
(b) Resultant waveforms
at LCD segment. MGL748

V state1(t) = V S (t) – V BP0(t)

n

V on(rms) = 0.638V LCD

V state2(t) = V S (t) – V BP1(t)
n

V off(rms) = 0.333V LCD

Fig.9 Waveforms for the 1 : 3 multiplex drive mode.

2004 Dec 22 14
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

6.4.4 1 : 4 MULTIPLEX DRIVE MODE

When four backplanes are provided in the LCD, the 1 : 4 multiplex drive mode applies (see Fig.10).

Tframe
handbook, full pagewidth
VLCD LCD segments
2VLCD/3
BP0 VLCD/3
VSS
state 1
VLCD
state 2
2VLCD/3
BP1
VLCD/3
VSS

VLCD
2VLCD/3
BP2
VLCD/3
VSS
VLCD
2VLCD/3
BP3 VLCD/3
VSS

VLCD
2VLCD/3
Sn
VLCD/3
VSS

VLCD
2VLCD/3
Sn + 1
VLCD/3
VSS

VLCD
2VLCD/3
Sn + 2
VLCD/3
VSS
VLCD
2VLCD/3
Sn + 3
VLCD/3
VSS
(a) Waveforms at driver.
VLCD
2VLCD/3
VLCD/3
state 1 0V
−VLCD/3
−2VLCD/3
−VLCD

VLCD
V state1(t) = V S (t) – V BP0(t)
n
2VLCD/3
VLCD/3 V on(rms) = 0.577V LCD
state 2 0V V state2(t) = V S (t) – V BP1(t)
−VLCD/3 n

−2VLCD/3 V off(rms) = 0.333V LCD

−VLCD
(b) Resultant waveforms
at LCD segment. MGL749

Fig.10 Waveforms for the 1 : 4 multiplex drive mode.

2004 Dec 22 15
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

6.5 Oscillator 6.9 Backplane outputs

6.5.1 INTERNAL CLOCK The LCD drive section includes four backplane outputs
BP0 to BP3 which should be connected directly to the
The internal logic of the PCF8576D and its LCD drive
LCD. The backplane output signals are generated in
signals are timed either by its internal oscillator or by an
accordance with the selected LCD drive mode. If less than
external clock. The internal oscillator is enabled by
four backplane outputs are required, the unused outputs
connecting pin OSC to pin VSS. If the internal oscillator is
can be left open-circuit. In the 1 : 3 multiplex drive mode,
used, the output from pin CLK can be used as the clock
BP3 carries the same signal as BP1, therefore these two
signal for several PCF8576Ds in the system that are
adjacent outputs can be tied together to give enhanced
connected in cascade. After power-up, pin SDA must be
drive capabilities. In the 1 : 2 multiplex drive mode, BP0
HIGH to guarantee that the clock starts.
and BP2, BP1 and BP3 respectively carry the same
signals and may also be paired to increase the drive
6.5.2 EXTERNAL CLOCK
capabilities. In the static drive mode the same signal is
Pin CLK is enabled as an external clock input by carried by all four backplane outputs and they can be
connecting pin OSC to VDD. connected in parallel for very high drive requirements.
The LCD frame signal frequency is determined by the
6.10 Display RAM
clock frequency (fCLK).
The display RAM is a static 40 × 4-bit RAM which stores
A clock signal must always be supplied to the device;
LCD data. A logic 1 in the RAM bit-map indicates the
removing the clock may freeze the LCD in a DC state.
on-state of the corresponding LCD segment; similarly, a
logic 0 indicates the off-state. There is a one-to-one
6.6 Timing
correspondence between the RAM addresses and the
The PCF8576D timing controls the internal data flow of the segment outputs, and between the individual bits of a RAM
device. This includes the transfer of display data from the word and the backplane outputs. The first RAM column
display RAM to the display segment outputs. In cascaded corresponds to the 40 segments operated with respect to
applications, the correct timing relationship between each backplane BP0 (see Fig.11). In multiplexed LCD
PCF8576D in the system is maintained by the applications the segment data of the second, third and
synchronization signal at pin SYNC. The timing also fourth column of the display RAM are time-multiplexed
generates the LCD frame signal whose frequency is with BP1, BP2 and BP3 respectively.
derived from the clock frequency. The frame signal
When display data is transmitted to the PCF8576D, the
frequency is a fixed division of the clock frequency from
display bytes received are stored in the display RAM in
either the internal or an external clock.
f CLK accordance with the selected LCD drive mode. The data is
Frame frequency = ---------- stored as it arrives and does not wait for an acknowledge
24
cycle as with the commands. Depending on the current
6.7 Display register multiplex drive mode, data is stored singularly, in pairs,
triplets or quadruplets. For example, in the 1 : 2 mode, the
The display latch holds the display data while the
RAM data is stored every second bit. To illustrate the filling
corresponding multiplex signals are generated. There is a
order, an example of a 7-segment numeric display
one-to-one relationship between the data in the display
showing all drive modes is given in Fig.12; the RAM filling
latch, the LCD segment outputs and each column of the
organization depicted applies equally to other LCD types.
display RAM.
With reference to Fig.12, in the static drive mode, the eight
6.8 Segment outputs transmitted data bits are placed in bit 0 of eight successive
display RAM addresses. In the 1 : 2 mode, the eight
The LCD drive section includes 40 segment outputs
transmitted data bits are placed in bits 0 and 1 of four
S0 to S39 which should be connected directly to the LCD.
successive display RAM addresses. In the 1 : 3 mode,
The segment output signals are generated in accordance
these bits are placed in bits 0, 1 and 2 of three successive
with the multiplexed backplane signals and with data
addresses, with bit 2 of the third address left unchanged.
residing in the display latch. When less than 40 segment
This last bit may, if necessary, be controlled by an
outputs are required, the unused segment outputs should
additional transfer to this address but care should be taken
be left open-circuit.
to avoid overriding adjacent data because full bytes are
always transmitted.

2004 Dec 22 16
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

In the 1 : 4 mode, the eight transmitted data bits are arriving data byte is stored at the display RAM address
placed in bits 0, 1, 2 and 3 of two successive display RAM indicated by the data pointer in accordance with the filling
addresses. order shown in Fig.12. After each byte is stored, the
contents of the data pointer are automatically incremented
6.11 Data pointer by a value dependent on the selected LCD drive mode:
eight (static drive mode), four (1 : 2 mode), three
The addressing mechanism for the display RAM is
(1 : 3 mode) or two (1 : 4 mode). If an I2C-bus data access
realized using the data pointer. This allows the loading of
is terminated early then the state of the data pointer will be
an individual display data byte, or a series of display data
unknown. The data pointer should be re-written prior to
bytes, into any location of the display RAM. The sequence
further RAM accesses.
commences with the initialization of the data pointer by the
LOAD DATA POINTER command. Following this, an

display RAM addresses (rows) / segment outputs (S)

0 1 2 3 4 35 36 37 38 39

0
display RAM bits
(columns) / 1
backplane outputs
(BP) 2

MBE525

Fig.11 Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs,
and between bits in a RAM word and backplane outputs.

6.12 Subaddress counter 6.13 Output bank selector

The storage of display data is determined by the contents The output bank selector selects one of the four bits per
of the subaddress counter. Storage is allowed to take display RAM address for transfer to the display latch. The
place only when the contents of the subaddress counter actual bit chosen depends on the selected LCD drive
agree with the hardware subaddress applied to A0, A1 mode and on the instant in the multiplex sequence. In 1 : 4
and A2. The subaddress counter value is defined by the mode, all RAM addresses of bit 0 are selected, these are
DEVICE SELECT command. If the contents of the followed by the contents of bit 1, bit 2 and then bit 3.
subaddress counter and the hardware subaddress do not Similarly in 1 : 3 mode, bits 0, 1 and 2 are selected
agree then data storage is inhibited but the data pointer is sequentially. In 1 : 2 mode, bits 0 and 1 are selected and,
incremented as if data storage had taken place. The in static mode, bit 0 is selected. Signal SYNC will reset
subaddress counter is also incremented when the data these sequences to the following starting points; bit 3 for
pointer overflows. 1 : 4 mode, bit 2 for 1 : 3 mode, bit 1 for 1 : 2 mode and
bit 0 for static mode.
The storage arrangements described lead to extremely
efficient data loading in cascaded applications. When a The PCF8576D includes a RAM bank switching feature in
series of display bytes are sent to the display RAM, the static and 1 : 2 drive modes. In the static drive mode,
automatic wrap-over to the next PCF8576D occurs when the BANK SELECT command may request the contents of
the last RAM address is exceeded. Subaddressing across bit 2 to be selected for display instead of the contents of
device boundaries is successful even if the change to the bit 0. In 1 : 2 mode, the contents of bits 2 and 3 may be
next device in the cascade occurs within a transmitted selected instead of bits 0 and 1. This allows display
character (such as during the 14th display data byte information to be prepared in an alternative bank and then
transmitted in 1 : 3 mode). selected for display when it is assembled.
The hardware subaddress should not be changed whilst
the device is being accessed on the I2C-bus interface.

2004 Dec 22 17
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

6.14 Input bank selector An additional feature allows an arbitrary selection of LCD
segments to be blinked in the static and 1 : 2 drive modes.
The input bank selector loads display data into the display
This is implemented without any communication
RAM in accordance with the selected LCD drive
overheads by the output bank selector which alternates
configuration. The BANK SELECT command can be used
the displayed data between the data in the display RAM
to load display data in bit 2 in static drive mode or in
bank and the data in an alternative RAM bank at the blink
bits 2 and 3 in 1 : 2 mode. The input bank selector
frequency. This mode can also be implemented by the
functions are independent of the output bank selector.
BLINK command.
6.15 Blinker In the 1 : 3 and 1 : 4 drive modes, where no alternative
RAM bank is available, groups of LCD segments can be
The PCF8576D has a very versatile display blinking
blinked by selectively changing the display RAM data at
capability. The whole display can blink at a frequency
fixed time intervals.
selected by the BLINK command. Each blink frequency is
a multiple integer value of the clock frequency; the ratio The entire display can be blinked at a frequency other than
between the clock frequency and blink frequency depends the nominal blink frequency by sequentially resetting and
on the blink mode selected, as shown in Table 3. setting the display enable bit E at the required rate using
the MODE SET command.

Table 3 Blinking frequencies

NORMAL OPERATING MODE
BLINK MODE NOMINAL BLINK FREQUENCY
RATIO
Off − blinking off
2 Hz f CLK 2 Hz
-----------
768
1 Hz f CLK 1 Hz
-------------
1536
0.5 Hz f CLK 0.5 Hz
-------------
3072

Note
1. Blink modes 0.5, 1 and 2 Hz, and nominal blink frequencies 0.5, 1 and 2 Hz correspond to an oscillator frequency
(fCLK) of 1536 Hz at pin CLK. The oscillator frequency range is given in Chapter 11.

2004 Dec 22 18
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2004 Dec 22

Philips Semiconductors
multiplex rates
Universal LCD driver for low
drive mode LCD segments LCD backplanes display RAM filling order transmitted display byte

a
Sn 2 n n 1 n 2 n 3 n 4 n 5 n 6 n 7
b BP0
f Sn 1
Sn 3 MSB LSB
Sn 4 g bit/ 0 c b a f g e d DP
Sn
BP 1 x x x x x x x x c b a f g e d DP
static e Sn 7
Sn 5 c 2 x x x x x x x x
d DP 3 x x x x x x x x
Sn 6

BP0
Sn a n n 1 n 2 n 3
b
1:2 Sn 1 f
MSB LSB
bit/ 0 a f e d
g
BP 1 b g c DP
BP1 a b f g e c d DP
multiplex Sn 2 e
c 2 x x x x
3 x x x x
d DP
Sn 3
19

BP0
Sn 1 a n n 1 n 2
b Sn
1:3 Sn 2 f
bit/ 0 b a f MSB LSB
g
BP 1 DP d e
BP1 BP2 b DP c a d g f e
multiplex e
c
2 c g x
3 x x x
d DP

Sn
a n n 1
b BP2
1:4 f BP0
bit/ 0 a f
g MSB LSB
BP 1 c e
multiplex e BP1 BP3
2 b g a c b DP f e g d
c
3 DP d
Sn 1 d DP

Product specification
PCF8576D
handbook, full pagewidth

MGL751

x = data bit unchanged.

Fig.12 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus.
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

7 CHARACTERISTICS OF THE I2C-BUS acknowledge clock pulse so that the SDA line is stable
LOW during the HIGH period of the acknowledge related
The I2C-bus is for bidirectional, two-line communication clock pulse (set-up and hold times must be taken into
between different ICs or modules. The two lines are a consideration). A master receiver must signal an end of
serial data line (SDA) and a serial clock line (SCL). Both data to the transmitter by not generating an acknowledge
lines must be connected to a positive supply via a pull-up on the last byte that has been clocked out of the slave.
resistor when connected to the output stages of a device. In this event the transmitter must leave the data line HIGH
Data transfer may be initiated only when the bus is not to enable the master to generate a STOP condition (see
busy. Fig.16).
In chip-on-glass applications where the track resistance
from the SDA pad to the system SDA line can be 7.5 PCF8576D I2C-bus controller
significant, a potential divider is generated by the bus
The PCF8576D acts as an I2C-bus slave receiver. It does
pull-up resistor and the Indium Tin Oxide (ITO) track
not initiate I2C-bus transfers or transmit data to an I2C-bus
resistance. It is therefore necessary to minimize the track
master receiver. The only data output from the PCF8576D
resistance from the SDA pad to the system SDA line to
are the acknowledge signals of the selected devices.
guarantee a valid LOW-level during the acknowledge
Device selection depends on the I2C-bus slave address,
cycle.
on the transferred command data and on the hardware
subaddress.
7.1 Bit transfer
In single device applications, the hardware subaddress
One data bit is transferred during each clock pulse. The
inputs A0, A1 and A2 are normally tied to VSS which
data on the SDA line must remain stable during the HIGH
defines the hardware subaddress 0. In multiple device
period of the clock pulse as changes in the data line at this
applications A0, A1 and A2 are tied to VSS or VDD in
time will be interpreted as a control signal (see Fig.13).
accordance with a binary coding scheme such that no two
devices with a common I2C-bus slave address have the
7.2 Start and stop conditions
same hardware subaddress.
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line while the 7.6 Input filters
clock is HIGH is defined as the START condition (S).
To enhance noise immunity in electrically adverse
A LOW-to-HIGH transition of the data line while the clock
environments, RC low-pass filters are provided on the
is HIGH is defined as the STOP condition (P), (see Fig.14).
SDA and SCL lines.
7.3 System configuration
7.7 I2C-bus protocol
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that Two I2C-bus slave addresses (01110000 and 01110010)
controls the message is the ‘master’ and the devices which are reserved for the PCF8576D. The least significant bit of
are controlled by the master are the ‘slaves’, (see Fig.15). the slave address that a PCF8576D will respond to is
defined by the level tied to its SA0 input. The PCF8576D
7.4 Acknowledge is a write-only device and will not respond to a read
access. Having two reserved slave addresses allows the
The number of data bytes that can be transferred from following on the same I2C-bus:
transmitter to receiver between the START and STOP
• Up to 16 PCF8576Ds for very large LCD applications
conditions is unlimited. Each byte of eight bits is followed
by an acknowledge bit. The acknowledge bit is a • The use of two types of LCD multiplex drive.
HIGH-level signal on the bus that is asserted by the The I2C-bus protocol is shown in Fig.17. The sequence is
transmitter during which time the master generates an initiated with a START condition (S) from the I2C-bus
extra acknowledge related clock pulse. An addressed master which is followed by one of two possible
slave receiver must generate an acknowledge after PCF8576D slave addresses available. All PCF8576Ds
receiving each byte. Also a master receiver must generate whose SA0 inputs correspond to bit 0 of the slave address
an acknowledge after receiving each byte that has been respond by asserting an acknowledge in parallel. This
clocked out of the slave transmitter. The acknowledging I2C-bus transfer is ignored by all PCF8576Ds whose SA0
device must pull-down the SDA line during the inputs are set to the alternative level.

2004 Dec 22 20
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

After an acknowledgement, one or more command bytes A1 and A2. After the last display byte, the I2C-bus master
follow that define the status of each addressed asserts a STOP condition (P). Alternately a START may
PCF8576D. be asserted to RESTART an I2C-bus access.
The last command byte sent is identified by resetting its
7.8 Command decoder
most significant bit, continuation bit C, (see Fig.18). The
command bytes are also acknowledged by all addressed The command decoder identifies command bytes that
PCF8576Ds on the bus. arrive on the I2C-bus. All available commands carry a
continuation bit C in their most significant bit position as
After the last command byte, one or more display data
shown in Fig.18. When this bit is set, it indicates that the
bytes may follow. Display data bytes are stored in the
next byte of the transfer to arrive will also represent a
display RAM at the address specified by the data pointer
command. If this bit is reset, it indicates that the command
and the subaddress counter. Both data pointer and
byte is the last in the transfer. Further bytes will be
subaddress counter are automatically updated and the
regarded as display data.
data directed to the intended PCF8576D device.
The five commands available to the PCF8576D are
An acknowledgement after each byte is asserted only by
defined in Table 4.
the PCF8576Ds that are addressed via address lines A0,

SDA

SCL

data line change

stable; of data
data valid allowed MBA607

Fig.13 Bit transfer.

handbook, full pagewidth

SDA SDA

SCL SCL
S P

START condition STOP condition

MBC622

Fig.14 Definition of START and STOP conditions.

2004 Dec 22 21
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

MASTER SLAVE SLAVE MASTER MASTER

TRANSMITTER/ RECEIVER TRANSMITTER/ TRANSMITTER TRANSMITTER/
RECEIVER RECEIVER RECEIVER

SDA

SCL
MGA807

Fig.15 System configuration.

handbook, full pagewidth

DATA OUTPUT
BY TRANSMITTER

not acknowledge
DATA OUTPUT
BY RECEIVER

acknowledge

SCL FROM
MASTER 1 2 8 9

S
clock pulse for
START acknowledgement
condition
MBC602

Fig.16 Acknowledgement on the I2C-bus.

acknowledge by acknowledge
k, full pagewidth
all addressed by A0, A1 and A2
PCF8576Ds selected
R/W
PCF8576D only
slave address

S
S 0 1 1 1 0 0 A 0 A C COMMAND A DISPLAY DATA A P
0

1 byte n ≥ 1 byte(s) n ≥ 0 byte(s)

update data pointers

and if necessary,
subaddress counter
MDB078

Fig.17 I2C-bus protocol.

2004 Dec 22 22
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

MSB LSB

C REST OF OPCODE

MSA833

C = 0 = last command.
C = 1 = commands continue.

Fig.18 Format of command byte.

Table 4 Definition of PCF8576D commands

COMMAND OPCODE OPTIONS DESCRIPTION
MODE SET C 1 0 (1) E B M1 M0 Table 5 Defines LCD drive mode.
Table 6 Defines LCD bias configuration.
Table 7 Defines display status; the possibility to
disable the display allows implementation
of blinking under external control.
LOAD DATA C 0 P5 P4 P3 P2 P1 P0 Table 8 Six bits of immediate data, bits P5 to P0,
POINTER are transferred to the data pointer to
define one of forty display RAM
addresses.
DEVICE C 1 1 0 0 A2 A1 A0 Table 9 Three bits of immediate data, bits A0 to
SELECT A2, are transferred to the subaddress
counter to define one of eight hardware
subaddresses.
BANK C 1 1 1 1 0 I O Table 10 Defines input bank selection (storage of
SELECT arriving display data).
Table 11 Defines output bank selection (retrieval of
LCD display data); the BANK SELECT
command has no effect in 1 : 3 and 1 : 4
multiplex drive modes.
BLINK C 1 1 1 0 A BF1 BF0 Table 12 Defines the blink frequency.
Table 13 Selects the blink mode; normal operation
with frequency set by BF1, BF0 or blinking
by alternating display RAM banks;
alternating RAM bank blinking does not
apply in 1 : 3 and 1 : 4 multiplex drive
modes.

Note
1. Not used.

2004 Dec 22 23
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

Table 5 Mode set option 1 Table 12 Blink option 1

LCD DRIVE MODE BITS BITS
BLINK FREQUENCY
DRIVE BF1 BF0
BACKPLANE M1 M0
MODE Off 0 0
Static BP0 0 1 2 Hz 0 1
1:2 BP0, BP1 1 0 1 Hz 1 0
1:3 BP0, BP1, BP2 1 1 0.5 Hz 1 1
1:4 BP0, BP1, BP2, BP3 0 0
Table 13 Blink option 2
Table 6 Mode set option 2
BLINK MODE BIT A
LCD BIAS BIT B Normal blinking 0
1⁄ bias 0
3 Alternate RAM bank blinking 1
1⁄
2 bias 1
Note
Table 7 Mode set option 3 1. Normal blinking is assumed when LCD multiplex drive
modes 1 : 3 or 1 : 4 are selected.
DISPLAY STATUS BIT E
Disabled (blank) 0 7.9 Display controller
Enabled 1 The display controller executes the commands identified
by the command decoder. It contains the device’s status
Table 8 Load data pointer option 1 registers and co-ordinates their effects. The display
controller is also responsible for loading display data into
DESCRIPTION BITS
the display RAM in the correct filling order.
6 bit binary value of 0 to 39 P5 P4 P3 P2 P1 P0
7.10 Cascaded operation
Table 9 Device select option 1
In large display configurations, up to 16 PCF8576Ds can
DESCRIPTION BITS be differentiated on the same I2C-bus by using the 3-bit
hardware subaddresses (A0, A1 and A2) and the
3 bit binary value of 0 to 7 A2 A1 A0
programmable I2C-bus slave address (SA0). PCF8576Ds
connected in cascade are synchronized to allow the
Table 10 Bank select option 1 (input)
backplane signals from only one device in the cascade to
MODE be shared. This arrangement is cost-effective in large LCD
BIT I applications since the backplane outputs of only one
STATIC 1:2 device need to be through-plated to the backplane
RAM bit 0 RAM bits 0 and 1 0 electrodes of the display. The other cascaded PCF8576Ds
RAM bit 2 RAM bits 2 and 3 1 contribute additional segment outputs but their backplane
outputs are left open-circuit (see Fig.19).
Table 11 Bank select option 2 (output)
MODE
BIT O
STATIC 1:2
RAM bit 0 RAM bits 0 and 1 0
RAM bit 2 RAM bits 2 and 3 1

2004 Dec 22 24
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

All PCF8576Ds connected in cascade are correctly Table 14 SYNC contact resistance
synchronized by the SYNC signal. This synchronization is
MAXIMUM CONTACT
guaranteed after the Power-on reset. The only time that NUMBER OF DEVICES
RESISTANCE
SYNC is likely to be needed is if synchronization is lost
accidentally, for example, by noise in adverse electrical 2 6000 Ω
environments, or if the LCD multiplex drive mode is 3 to 5 2200 Ω
changed in an application using several cascaded
6 to 10 1200 Ω
PCF8576Ds, as the drive mode cannot be changed on all
of the cascaded devices simultaneously. SYNC can be 10 to 16 700 Ω
either an input or an output signal; a SYNC output is
implemented as an open-drain driver with an internal The contact resistance between the SYNC input/output on
pull-up resistor. A PCF8576D asserts SYNC at the start of each cascaded device must be controlled. If the resistance
its last active backplane signal, and monitors the SYNC is too high, the device will not be able to synchronize
line at all other times. If cascade synchronization is lost, it properly; this is particularly applicable to chip-on-glass
will be restored by the first PCF8576D to assert SYNC. applications. The maximum SYNC contact resistance
The timing relationship between the backplane waveforms allowed for the number of devices in cascade is given in
and the SYNC signal for each LCD drive mode is shown in Table 14.
Fig.20.

handbook, full pagewidth

VDD VLCD
6 13
SDA 1, 58, 59
SCL 2, 3 40 segment drives

SYNC LCD PANEL

4 PCF8576DU
CLK (up to 2560
5
OSC 7 elements)
BP0 to BP3
8 9 10 11 12 (open-circuit)
A0 A1 A2 SA0 VSS
VLCD

VDD tr
R≤ V V
2CB DD LCD
6 13
HOST SDA
1, 58, 59 40 segment drives
MICRO- SCL
2, 3
PROCESSOR/
SYNC
MICRO- 4
CONTROLLER CLK
PCF8576DU 4 backplanes
5
OSC BP0 to BP3
7
MDB077
8 9 10 11 12
A0 A1 A2 SA0 VSS
VSS

Fig.19 Cascaded PCF8576D configuration.

2004 Dec 22 25
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

handbook, full pagewidth

1
Tframe = f frame

BP0

SYNC

(a) static drive mode.

BP1
(1/2 bias)

BP1
(1/3 bias)

SYNC

(b) 1 : 2 multiplex drive mode.

BP2

SYNC

(c) 1 : 3 multiplex drive mode.

BP3

SYNC
MGL755
(d) 1 : 4 multiplex drive mode.

Fig.20 Synchronization of the cascade for the various PCF8576D drive modes.

2004 Dec 22 26
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

8 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER MIN. MAX. UNIT
VDD supply voltage −0.5 +6.5 V
VLCD LCD supply voltage VSS − 0.5 +7.5 V
Vi1 input voltage CLK, SYNC, SA0, OSC, A0 to A2 VSS − 0.5 VDD + 0.5 V
Vi2 input voltage SCL and SDA VSS − 0.5 +6.5 V
VO output voltage S0 to S39, BP0 to BP3 VSS − 0.5 VDD + 0.5 V
II DC input current −10 +10 mA
IO DC output current −10 +10 mA
IDD VDD current −50 +50 mA
ISS VSS current −50 +50 mA
ILCD VLCD current −50 +50 mA
Ptot total power dissipation − 400 mW
PO power dissipation per output − 100 mW
Tstg storage temperature −65 +150 °C

9 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices” ).

2004 Dec 22 27
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

10 DC CHARACTERISTICS
VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies
VDD supply voltage 1.8 − 5.5 V
VLCD LCD supply voltage note 1 2.5 − 6.5 V
IDD supply current note 2; fCLK = 1536 Hz − 8 20 µA
ILCD LCD supply current note 2; fCLK = 1536 Hz − 24 60 µA
Logic
VIL LOW-level input voltage VSS − 0.3VDD V
CLK, SYNC, OSC, A0 to A2 and SA0
VIH HIGH-level input voltage 0.7VDD − VDD V
CLK, SYNC, OSC, A0 to A2 and SA0
VIL2 LOW-level input voltage SCL, SDA VSS − 0.3VDD V
VIH2 HIGH-level input voltage SCL, SDA note 3 0.7VDD − VDD V
IOL1 LOW-level output current CLK, SYNC VOL = 0.4 V; VDD = 5 V 1 − − mA
IOH1 HIGH-level output current CLK VOH = 4.6 V; VDD = 5 V −1 − − mA
IOL2 LOW-level output current SDA VOL = 0.4 V; VDD = 5 V 3 − − mA
IL1 leakage current VI = VDD or VSS −1 − +1 µA
CLK, SCL, SDA, A0 to A2 and SA0
IL2 leakage current OSC VI = VDD −1 − +1 µA
VPOR power-on reset voltage level 1.0 1.3 1.6 V
CI input capacitance note 4 − − 7 pF
LCD outputs
VBP DC voltage tolerance BP0 to BP3 −100 − +100 mV
VS DC voltage tolerance S0 to S39 −100 − +100 mV
RBP output resistance BP0 to BP3 note 5; VLCD = 5 V − 1.5 − kΩ
RS output resistance S0 to S39 note 5; VLCD = 5 V − 6.0 − kΩ

Notes
1. VLCD > 3 V for 1⁄3 bias.
2. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive.
3. When tested, I2C pins SCL and SDA have no diode to VDD and may be driven according to the Vi2 limiting values
given in Chapter 8. Also see Fig.24.
4. Periodically sampled, not 100% tested.
5. Outputs measured one at a time.

2004 Dec 22 28
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

11 AC CHARACTERISTICS
VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

fCLK oscillator frequency note 1 960 1890 2640 Hz
tCLKH input CLK HIGH time 60 − − µs
tCLKL input CLK LOW time 60 − − µs
tPD(SYNC) SYNC propagation delay − 30 − ns
tSYNCL SYNC LOW time 1 − − µs
tPD(LCD) driver delays with test loads VLCD = 5 V; note 2 − − 30 µs
Timing characteristics: I2C-bus; note 3
fSCL SCL clock frequency − − 400 kHz
tBUF bus free time between a STOP and START 1.3 − − µs
tHD;STA START condition hold time 0.6 − − µs
tSU;STA set-up time for a repeated START condition 0.6 − − µs
tLOW SCL LOW time 1.3 − − µs
tHIGH SCL HIGH time 0.6 − − µs
tr SCL and SDA rise time fSCL = 400 kHz − − 0.3 µs
fSCL < 125 kHz − − 1.0 µs
tf SCL and SDA fall time − − 0.3 µs
CB capacitive bus line load − − 400 pF
tSU;DAT data set-up time 100 − − ns
tHD;DAT data hold time 0 − − ns
tSU;STO set-up time for STOP condition 0.6 − − µs
tSW tolerable spike width on bus − − 50 ns

Notes
1. Typical output duty factor: 50% measured at the CLK output pin.
2. Not tested in production.
3. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSS to VDD.

handbook, full pagewidth 6.8 Ω

SYNC VDD
(2%)

3.3 k Ω SDA, 1.5 k Ω

CLK 0.5VDD SCL VDD
(2%) (2%)

BP0 to BP3, and 1 nF

S0 to S39 VSS
MCE439

Fig.21 Test loads.

2004 Dec 22 29
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

handbook, full pagewidth 1/fCLK

tCLKH tCLKL

0.7VDD
CLK
0.3VDD

0.7VDD
SYNC
0.3VDD

tPD(SYNC) tPD(SYNC)

tSYNCL
0.5 V
BP0 to BP3,
and S0 to S39 (VDD = 5 V)
0.5 V

tPD(LCD) MCE424

Fig.22 Driver timing waveforms.

handbook, full pagewidth

SDA

t BUF t LOW tf

SCL

t HD;STA tr t HD;DAT t HIGH t SU;DAT

SDA

t SU;STA
MGA728 t
SU;STO

Fig.23 I2C-bus timing waveforms.

2004 Dec 22 30
Philips Semiconductors Product specification

Universal LCD driver for low

PCF8576D
multiplex rates

12 BONDING PAD INFORMATION

COORDINATES
Table 15 Bonding pad locations SYMBOL PAD
x y
All x/y coordinates represent the position of the centre of
each pad (in µm) with respect to the centre (x/y = 0) of the S18 36 −1005.5 +625.59
chip (see Fig.23). S19 37 −1005.5 +541.62
COORDINATES S20 38 −1005.5 +458.19
SYMBOL PAD S21 39 −1005.5 +374.76
x y
S22 40 −1005.5 +291.33
SDA 1 −34.38 −876.6
S23 41 −1005.5 +207.9
SCL 2 +109.53 −876.6
S24 42 −1005.5 +124.47
SCL 3 +181.53 −876.6
S25 43 −1005.5 +41.04
SYNC 4 +365.58 −876.6
S26 44 −1005.5 −42.39
CLK 5 +469.08 −876.6
S27 45 −1005.5 −125.8
VDD 6 +577.08 −876.6
S28 46 −1005.5 −209.3
OSC 7 +740.88 −876.6
S29 47 −1005.5 −292.7
A0 8 +835.83 −876.6
S30 48 −1005.5 −376.1
A1 9 +1005.48 −630.9
S31 49 −1005.5 −459.5
A2 10 +1005.48 −513.9
S32 50 −1005.5 −543
SA0 11 +1005.48 −396.9
S33 51 −1005.5 −625.6
VSS 12 +1005.48 −221.4
S34 52 −735.03 −876.6
VLCD 13 1005.48 10.71
S35 53 −663.03 −876.6
BP0 14 1005.48 156.51
S36 54 −591.03 −876.6
BP2 15 1005.48 232.74
S37 55 −519.03 −876.6
BP1 16 1005.48 308.97
S38 56 −447.03 −876.6
BP3 17 1005.48 385.2
S39 57 −375.03 −876.6
S0 18 1005.48 493.2
SDA 58 −196.38 −876.6
S1 19 1005.48 565.2
SDA 59 −106.38 −876.6
S2 20 1005.48 637.2
Alignment marks
S3 21 1005.48 709.2
S4 22 347.22 876.6 C1 +930.42 −870.3

S5 23 263.97 876.6 C2 −829.98 −870.3

S6 24 180.72 876.6 Table 16 Gold bump dimension PCF8576DU/2DA/2

S7 25 97.47 876.6
DESCRIPTION DIMENSION
S8 26 14.22 876.6
Gold bump dimension 52 µm × 80 µm × 15 µm
S9 27 −69.03 +876.6
Gold bump tolerance 3 µm
S10 28 −152.28 +876.6
S11 29 −235.53 +876.6
S12 30 −318.78 +876.6
S13 31 −402.03 +876.6
S14 32 −485.28 +876.6
S15 33 −568.53 +876.6
S16 34 −651.78 +876.6
S17 35 −735.03 +876.6

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multiplex rates

handbook, full pagewidth

S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
35 34 33 32 31 30 29 28 27 26 25 24 23 22

21 S3

S18 36 20 S2

S19 37 19 S1

S20 38 18 S0

S21 39 17 BP3
S22 40 16 BP1
S23 41 15 BP2

S24 42 14 BP0

S25 43 x 13 VLCD
2.01
S26 44 0
mm 0
S27 45

S28 46 y
12 VSS
S29 47

S30 48
11 SA0
S31 49
PCF8576DU
S32 50 10 A2
S33 51 9 A1

C2 C1

52 53 54 55 56 57 58 59 1 2 3 4 5 6 7 8
S34
S35
S36
S37
S38
S39

SDA
SDA
SDA

SCL
SCL

SYNC
CLK

OSC
A0
VDD

2.26 mm MDB074

Chip dimensions: approximately 2.26 × 2.01 mm.

Bump dimensions (except pad 1): 52 × 80 × 17.5 (height) µm.
Bump dimensions (pad 1): 52 × 76 × 17.5 (height) µm.
Alignment marks: diameter = 72 µm.

Fig.23 Bonding pad locations.

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multiplex rates

13 DEVICE PROTECTION

VDD VDD
handbook, full pagewidth

SA0

VSS VSS

VDD

CLK
SCL

VSS

VDD

VSS
OSC

VSS

VDD SDA

SYNC

VSS VSS

VDD

A0, A1 A2

VSS

VLCD

BP0, BP1,
BP2, BP3

VSS

VLCD VLCD

S0 to S39

VSS VSS
MDB076

Fig.24 Device protection diagram.

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multiplex rates

14 TRAY INFORMATION

handbook, full pagewidth x

G A C

y H
1,1 2,1 x,1 D

1,2

1,y x,y

E
MCE404

For dimensions, see Table 17.

Fig.25 Tray details.

Table 17 Tray dimensions (see Fig.25)

SYMBOL DESCRIPTION VALUE handbook, halfpage

A pocket pitch, in x direction 5.59 mm

B pocket pitch, in y direction 6.35 mm
C pocket width, in x direction 3.16 mm
D pocket width, in y direction 3.16 mm
E tray width, in x direction 50.8 mm
PC8576DU
F tray width, in y direction 50.8 mm
G cut corner to pocket 1,1 centre 5.83 mm
H cut corner to pocket 1,1 centre 6.35 mm
x number of pockets in x direction 8
y number of pockets in y direction 7
MDB080

The orientation of the IC in a pocket is indicated by the

position of the IC type name on the die surface with
respect to the chamfer on the upper left corner of the tray.

Fig.26 Tray alignment.

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Universal LCD driver for low

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multiplex rates

15 PACKAGE OUTLINES

TQFP64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm SOT357-1

c
y

48 33

49 32 ZE

e
E HE
A2 A (A 3)
A 1
wM
pin 1 index θ
bp Lp
L
64 17

1 16 detail X

ZD v M A
e wM
bp
D B
HD v M B

0 2.5 5 mm
scale

DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y Z D(1) Z E(1) θ
max.
o
1.2 0.15 1.05 0.27 0.18 10.1 10.1 12.15 12.15 0.75 1.45 1.45 7
mm 0.25 0.5 1 0.2 0.08 0.1 o
0.05 0.95 0.17 0.12 9.9 9.9 11.85 11.85 0.45 1.05 1.05 0

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

00-01-19
SOT357-1 137E10 MS-026
02-03-14

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Universal LCD driver for low

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multiplex rates

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1

D E A
X

y HE v M A

56 29

Q
A2 (A 3) A
A1

pin 1 index
θ
Lp
L

1 28 detail X

w M
e bp

0 2.5 5 mm
scale

DIMENSIONS (mm are the original dimensions).

A
UNIT A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ
max.
o
0.15 1.05 0.28 0.2 14.1 6.2 8.3 0.8 0.50 0.5 8
mm 1.2 0.25 0.5 1 0.25 0.08 0.1 o
0.05 0.85 0.17 0.1 13.9 6.0 7.9 0.4 0.35 0.1 0

Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT364-1 MO-153
03-02-19

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Philips Semiconductors Product specification

Universal LCD driver for low

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multiplex rates

16 SOLDERING To overcome these problems the double-wave soldering

method was specifically developed.
16.1 Introduction to soldering surface mount
packages If wave soldering is used the following conditions must be
observed for optimal results:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in • Use a double-wave soldering method comprising a
our “Data Handbook IC26; Integrated Circuit Packages” turbulent wave with high upward pressure followed by a
(document order number 9398 652 90011). smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for – larger than or equal to 1.27 mm, the footprint
certain surface mount ICs, but it is not suitable for fine pitch longitudinal axis is preferred to be parallel to the
SMDs. In these situations reflow soldering is transport direction of the printed-circuit board;
recommended. – smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
16.2 Reflow soldering printed-circuit board.
Reflow soldering requires solder paste (a suspension of The footprint must incorporate solder thieves at the
fine solder particles, flux and binding agent) to be applied downstream end.
to the printed-circuit board by screen printing, stencilling or • For packages with leads on four sides, the footprint must
pressure-syringe dispensing before package placement. be placed at a 45° angle to the transport direction of the
Driven by legislation and environmental forces the printed-circuit board. The footprint must incorporate
worldwide use of lead-free solder pastes is increasing. solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example, During placement and before soldering, the package must
convection or convection/infrared heating in a conveyor be fixed with a droplet of adhesive. The adhesive can be
type oven. Throughput times (preheating, soldering and applied by screen printing, pin transfer or syringe
cooling) vary between 100 seconds and 200 seconds dispensing. The package can be soldered after the
depending on heating method. adhesive is cured.
Typical reflow peak temperatures range from Typical dwell time of the leads in the wave ranges from
215 °C to 270 °C depending on solder paste material. The 3 seconds to 4 seconds at 250 °C or 265 °C, depending
top-surface temperature of the packages should on solder material applied, SnPb or Pb-free respectively.
preferably be kept:
A mildly-activated flux will eliminate the need for removal
• below 225 °C (SnPb process) or below 245 °C (Pb-free
of corrosive residues in most applications.
process)
– for all BGA, HTSSON..T and SSOP..T packages 16.4 Manual soldering
– for packages with a thickness ≥ 2.5 mm Fix the component by first soldering two
– for packages with a thickness < 2.5 mm and a diagonally-opposite end leads. Use a low voltage (24 V or
volume ≥ 350 mm3 so called thick/large packages. less) soldering iron applied to the flat part of the lead.
• below 240 °C (SnPb process) or below 260 °C (Pb-free Contact time must be limited to 10 seconds at up to
process) for packages with a thickness < 2.5 mm and a 300 °C.
volume < 350 mm3 so called small/thin packages. When using a dedicated tool, all other leads can be
Moisture sensitivity precautions, as indicated on packing, soldered in one operation within 2 seconds to 5 seconds
must be respected at all times. between 270 °C and 320 °C.

16.3 Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

2004 Dec 22 37
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Universal LCD driver for low

PCF8576D
multiplex rates

16.5 Suitability of surface mount IC packages for wave and reflow soldering methods

SOLDERING METHOD
PACKAGE(1)
WAVE REFLOW(2)
BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, not suitable suitable
VFBGA, XSON
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, not suitable(4) suitable
HTQFP, HTSSOP, HVQFN, HVSON, SMS
PLCC(5), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(5)(6) suitable
SSOP, TSSOP, VSO, VSSOP not recommended(7) suitable
CWQCCN..L(8), PMFP(9), WQCCN..L(8) not suitable not suitable

Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature
must be kept as low as possible.
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
6. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted
on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.
9. Hot bar soldering or manual soldering is suitable for PMFP packages.

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multiplex rates

17 DATA SHEET STATUS

DATA SHEET PRODUCT

LEVEL DEFINITION
STATUS(1) STATUS(2)(3)
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).

Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

18 DEFINITIONS 19 DISCLAIMERS
Short-form specification  The data in a short-form Life support applications  These products are not
specification is extracted from a full data sheet with the designed for use in life support appliances, devices, or
same type number and title. For detailed information see systems where malfunction of these products can
the relevant data sheet or data handbook. reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
Limiting values definition  Limiting values given are in
for use in such applications do so at their own risk and
accordance with the Absolute Maximum Rating System
agree to fully indemnify Philips Semiconductors for any
(IEC 60134). Stress above one or more of the limiting
damages resulting from such application.
values may cause permanent damage to the device.
These are stress ratings only and operation of the device Right to make changes  Philips Semiconductors
at these or at any other conditions above those given in the reserves the right to make changes in the products -
Characteristics sections of the specification is not implied. including circuits, standard cells, and/or software -
Exposure to limiting values for extended periods may described or contained herein in order to improve design
affect device reliability. and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information  Applications that are
communicated via a Customer Product/Process Change
described herein for any of these products are for
Notification (CPCN). Philips Semiconductors assumes no
illustrative purposes only. Philips Semiconductors make
responsibility or liability for the use of any of these
no representation or warranty that such applications will be
products, conveys no license or title under any patent,
suitable for the specified use without further testing or
copyright, or mask work right to these products, and
modification.
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.

2004 Dec 22 39
Philips Semiconductors Product specification

Universal LCD driver for low

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multiplex rates

Bare die  All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for
a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be
separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips
Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die.
Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems
after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify
their application in which the die is used.

20 PURCHASE OF PHILIPS I2C COMPONENTS

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2004 Dec 22 40
Philips Semiconductors – a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825

For sales offices addresses send e-mail to: [email protected].

© Koninklijke Philips Electronics N.V. 2004 SCA76

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Printed in The Netherlands R15/05/pp41 Date of release: 2004 Dec 22 Document order number: 9397 750 14492