Mahendra Kumar Jangir

[email protected]
8826165224

MEMORY AND DIGITAL INTERFACING

INTRODUCTION:
Memory is simply a device that can be used to store the information. Memory is an integral part of a
microprocessor system. In designing of computer, semiconductor memories are used as primary storage
of data and code. The fundamentals of memory are memory capacity, memory organization and
memory speed.

 Memory Capacity: The number of bits that a semiconductor memory chip can store is called chip
capacity (bits or bytes)
 Memory Organization:
o Each memory chip contains 2n locations where n is number of address pins on chip
o Each location contain y bits where y is number of data pins on the chip
o The entire chip will contain 2n* y bits
o For example memory organization of 4K x 4: 212 = 4096 location, each location holding 4
bits. So n=12 and y = 4
 Memory Speed: It’s the Access time.

Each Memory device has at least one Chip Select (CS) or Chip Enable (CE) or Select (S) that enable the
memory device. This enables read and/or write operations.
Each memory device has at least one control pin. For ROMs an output enable (OE) or gate (G) is
present. The OE pin enables and disables a set of tri-state buffers. For RAMs a read/write (R/W) or
write enable (WE) or read enable (RE) are present.

MEMORY TYPES:
Every microprocessor-based system has a memory system, they are classified as below.

 Two basic types:

o Read-only memory (ROM): It stores system software and permanent system data
o Random access memory (RAM): It stores temporary data and application software (data
and instructions)
 Four commonly used memories:
o ROM
o Flashable EEPROM
o Static RAM (SRAM)
o Dynamic RAM (DRAM), SDRAM, RAMBUS, DDR RAM

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MEMORY DEVICE:
The generic pin configuration of memory devices is depicted below. Each memory device contains
Address pins (A0 to AN), Data pins which are bidirectional in read write memories, Selection pins and
Control pins.

Fig 1: Generic Pin configuration of Memory device

Address pins:
 All memory devices have address inputs.
 They select a memory location within the memory device.
 The number of address pins is related to the number of memory locations.
o Common sizes today are 1K to 256M locations.
o Therefore, between 10 and 28 address pins are present.
 Address inputs are labeled from A0 to AN.
 N is the total number of address pins minus 1.
 Example: The 2K memory:
o It has 11 address lines.
o The labels are (A0 to A10).
o If the start address is 10000H so the end address is:
o 10000H + ((2*1024)10= 800H)=107FFH

Data Pins:
 All memory devices have a set of data outputs or input/outputs.
 They are used to enter the data for storage or extract the data for reading.
 The data pins are typically bi-directional in read-write memories.
o The number of data pins is related to the size of the memory location.
o For example, an 8-bit wide (byte-wide) memory device has 8data pins.
o Catalog listing of 1K X 8 indicate a byte addressable 8Kbit memory with 10 address
pins.
 Memory devices are defined by memory locations times bit per location.
 Examples: 1Kx8, 16Kx1, 64Kx4.

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 Selection Pins:
 Each memory device has at least one chip select(𝐶𝑆 ̅̅̅̅) or chip enable(𝐶𝐸
̅̅̅̅ ) or select(𝑆̅) pin that
enables the memory device.
o This enables read and/or write operations.
o If more than one are present, then all must be 0 in order to perform a read or write.
 If they are active (logic 0), the memory device performs a read or write operation.
 If they are inactive (logic 1), the memory is disabled and do not do any operation.
 If more than one selection connection is present. All must be activated to read or write.

Control Pins:
 Each memory device has at least one control pin
 For ROMs, an Output Enable (𝑶𝑬 ̅̅̅̅) or Gate (𝑮
̅ ) is present.
 The 𝑂𝐸pin enables and disables a set of tri-state buffers.
 For RAMs, a read-write(R/𝑾 ̅̅̅) or write enable (𝑾𝑬 ̅̅̅̅) are present.
̅̅̅̅̅) and read enable (𝑶𝑬
 For dual control pin devices, it must be hold true that both are not 0 at the same time.

MEMORY INTERFACING IN 8085

Memory is an integral part of a microprocessor system, and in this section, we will discuss how to
interface a memory device with the microprocessor. The Memory Interfacing in 8085 is used to access
memory quite frequently to read instruction codes and data stored in memory. This read/write
operations are monitored by control signals. The microprocessor activates these signals when it wants
to read from and write into memory. In the last section we have already seen the memory read and
memory write machine cycles, and status of the RD, WR and IO/M status signals for read/write
operation. In the following section we will see memory structure and its requirements, concepts in
Memory Interfacing in 8085 and interfacing examples.

Memory Structure and its Requirements:

As mentioned earlier, read/write memories consist of an array of registers, in which each register
has unique address. The size of the memory is N x M as shown in Fig. below, where N is the number
of registers and M is the word length, in number of bits.

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 (a) (b)

Fig 2: (a) is Logic diagram for RAM and (b) is Logic diagram for EPROM

Basic Concepts in Memory Interfacing:

For Memory Interfacing in 8085, following important points are to be kept in mind.
 Microprocessor 8085 can access 64Kbytes memory since address bus is 16-bit. But it is not
always necessary to use full 64Kbytes address space. The total memory size depends upon
the application.
 Generally EPROM (or EPROMs) is used as a program memory and RAM (or RAMs) as a data
memory. When both, EPROM and RAM are used, the total address space 64Kbytes is shared
by them.
 The capacity of program memory and data memory depends on the application.
 It is not always necessary to select 1 EPROM and 1 RAM. We can have multiple EPROMs and
multiple RAMs as per the requirement of application.
 We can place EPROM/RAM anywhere in full 64 Kbytes address space. But program memory
(EPROM) should be located from address 0000H since reset address of 8085 microprocessor
is 0000H.
 It is not always necessary to locate EPROM and RAM in consecutive memory For example: If
the mapping of EPROM is from 0000H to OFFFH, it is not must to locate RAM from 1000H.
We can locate it anywhere between 1000H and FFFFH. Where to locate memory component
totally depends on the application.

The memory interfacing requires to:

 Select the chip
 Identify the register
 Enable the appropriate buffer.

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ADDRESSING AND ADDRESS DECODING
Microprocessor system includes memory devices and I/O devices. It is important to note that
microprocessor can communicate (read/write) with only one device at a time, since the data, address
and control buses are common for all the devices. In order to communicate with memory or I/O devices,
it is necessary to decode the address from the microprocessor. Due to this each device (memory or I/O)
can be accessed independently. The following section describes common address decoding techniques.

Address Decoding:
Address decoding is the process of generating chip select (CS*) signals from the address bus for each
device in the system.

In general all the address lines are not used by the memory devices to select particular memory
location. The remaining lines are used to generate chip select logic.

The address bus lines are split into two sections

 The N most significant bits are used to generate the CS* signals for the different devices
 The M least significant signals are passed to the devices as addresses to the different
memory cells or internal registers.

Fig 3: Address bus lines sections

Address Decoding Techniques:

Following two techniques are used to decode the address:

1. Absolute or Full address decoding:

o All the higher address lines are decoded to select the memory chip.
o The memory chip is selected only for the specified logic levels on these higher order
address lines.
o Each physical memory location is identified by a unique address
o This technique needs more hardware than partial address decoding technique.
2. Linear or Partial address decoding
o This technique is used in small systems
o All the address lines are not used to generate chip select logic.
o Individual higher order address lines are used to decode the chip select for memory
chips
o Comparatively less hardware is needed

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 o Drawback is address of location is not fixed, so each location may have multiple
addresses.

NAND Gate Decoder Example:

 When the 2K x 8 EPROM is used, address connections A10–A0 of the 8088 are connected to
address inputs A10–A0 of the EPROM.
 The remaining nine address pins (A19–A11) are connected to the inputs of a NAND gate
decoder (see Figure 4).
 The decoder selects the EPROM from one of the 2K-byte sections of the 1M-byte memory
system.
 In this circuit, a single NAND gate decodes the memory address.
 The output of the NAND gate is logic 0 whenever the 8088 address pins attached to its
inputs (A19–A11) are all logic 1s.
 The active low, logic 0 output of the NAND gate decoder is connected to the ̅̅̅̅ 𝐶𝐸 input pin
that selects (enables) the EPROM.
 Recall that whenever ̅̅̅̅ ̅̅̅̅ is also a
𝐶𝐸 is a logic 0, data will be read from the EPROM only if 𝑂𝐸
logic 0.
 The ̅̅̅̅
𝑂𝐸 pin is activated by the 8088 ̅̅̅̅𝑅𝐷 signal or the ̅̅̅̅̅̅̅̅̅
𝑀𝑅𝐷𝐶 (memory read control) signal
of other family members.
 Here, the 2K EPROM is decoded at memory address locations FF800H–FFFFFH.

Fig 4: A simple NAND gate decoder that selects a 2716 EPROM for memory location FF800H–FFFFFH.

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 Example: To determine the address range that a device is mapped into
A19 - A11 A10 – A0

1111 1111 1XXX XXXX XXXX

1111 1111 1000 0000 0000 (FF800H)

To

1111 1111 1111 1111 1111 (FFFFFH)

Note: NAND gate decoders are not often used

o Large fan-in NAND gates are not efficient
o Multiple NAND gate IC's might be required to perform such decoding

Rather the 3-to-8 Line Decoder (74LS138) is more common.

The 3-to-8 Line Decoder (74LS138):

The figure 5 below illustrates the 74LS138 3-to-8 line decoder. The truth table shows that only one
of the eight outputs ever goes low at any time. For any of the decoder’s outputs to go low, the three
̅̅̅̅̅̅ , ̅̅̅̅̅̅
enable inputs (𝐺2𝐴 𝐺2𝐵 and G1) must all be active. To be active, the ̅̅̅̅̅̅
𝐺2𝐴 and ̅̅̅̅̅̅
𝐺2𝐵 inputs
must both be low (logic 0), and G1 must be high (logic 1). Once the 74LS138 is enabled, the address
inputs (C, B, and A) select which output pin goes low. Eight EPROM ̅̅̅̅
𝐶𝐸 inputs connected to the
eight outputs of the decoder.

 Notice that the outputs of the decoder, illustrated in Figure 6 above , are connected to eight
different 2764 EPROM memory devices.
 Here, the decoder selects eight 8Kbyte blocks of memory for a total memory capacity of 64K
bytes.
 A three-input NAND gate is connected to address bits A19–A17.
 When all three address inputs are high, the output of this NAND gate goes low and enables
input ̅̅̅̅̅̅
𝐺2𝐵 of the 74LS138.
 Input G1 is connected directly to A16.
 In other words, in order to enable this decoder, the first four address connections (A19–
A16) must all be high.
 The address inputs C, B, and A connect to microprocessor address pins A15–A13.
 These three address inputs determine which output pin goes low and which EPROM is
selected whenever the 8088 outputs a memory address within this range to the memory
system.

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 Fig 5: The 74LS138 3-to-8 line decoder and function table.

Fig 6: A circuit that uses eight 2764 PROMs for a 64K 8 section of memory in an 8088
microprocessor-based system. The addresses selected in this circuit are F0000H– FFFFFH.

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 Example:
A19 - A16 A15 – A13 (CBA)

1111 000X XXXX XXXX XXXX

OR
1111 0000 0000 0000 0000 (F0000H)

To

1111 0001 1111 1111 1111 (F1FFFH)

RAM (Data Memory) Interfacing

Fig 7: Interfacing of RAM(Data Memory) to µc 8051.

Above figure shows how to connect or interface external RAM(data memory) to 8051. Port 0 is
used as multiplexed data & address lines. Address lines are decoded using external latch & ALE
signal from 8051 to provide lower order (A7-A0) address lines.
̅̅̅̅ & 𝑊𝑅
Port 2 gives higher order address lines. 𝑅𝐷 ̅̅̅̅̅̅signals from 8051 selects the memory read &
memory write operations respectively.

̅̅̅̅& 𝑊𝑅
𝑅𝐷 ̅̅̅̅̅̅signals: generally P3.6 & P3.7 pins of port 3 are used to generate memory read and
memory write signals.
Remaining pins of port 3 i.e. P3.0-P3.5 can be used for other functions.

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ROM (Program Memory) Interfacing

Fig 8: Interfacing of ROM/EPROM to µC 8051.

Above figure shows how to access or interface ROM to 8051.

Port 0 is used as multiplexed data & address lines. it gives lower order (A7-A0) 8 bit address in
initial T cycle & higher order (A8-A15) used as data bus. 8 bit address is latched using external
latch & ALE signal from 8051. port 2 provides higher order (A15-A8) 8 bit address. ̅̅̅̅̅̅̅̅
𝑃𝑆𝐸𝑁 is used
to activate the output enable signal of external ROM/EPROM.

Example: Design a µController system using 8051.Interface the external RAM of size 16k x 8.

Solution: Given, Memory size: 16k that means we require 2n=16k :: n address lines
Here n=14 :: A0 to A13 address lines are required.
A14 and A15 are connected through OR gate to CS pin of external RAM.
when A14 and A15 both are low (logic ‘0’), external data memory(RAM) is selected.
Address Decoding (Memory Map)for 16k x 8 RAM.

Address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 HEX

Add
Starting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H
End 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3FFFH

vss

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