DIODES

• The simplest and the most fundamental non-linear circuit element

is the diode.

• Just like a resistor a diode is a two terminal device.

• But unlike the resistor which has a linear (straight line)

characteristic between the current flowing through it and the
voltage across it, the diode has a nonlinear I-V characteristics.

• Of the many applications of diodes, their use in the design of

rectifier (which converts AC to DC) is the most common.

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The Ideal Diode

Current Voltage Characteristic

• The ideal diode may be considered the most fundamental non-linear circuit
element.
• It is a two terminal device having circuit symbol of Fig 3.1 (a) and the i-v
characteristic shown in Fig. 3.1 (b). The terminal characteristic of the ideal diode
can be interpreted as follows:
• If a negative voltage is applied to the diode, no current flows and the diode
behaves as an open circuit (Fig. 3.1 (c)). Diodes operated in this mode are said to
be reverse biased, or operated in the reverse direction. An ideal diode has zero
current when operated in the reverse direction and is said to be cut-off or simply
off.
• On the other hand, if a positive voltage is applied to then ideal diode, zero
voltage drop appears across the diode. In other words, the ideal diode behaves as
a short circuit in the forward direction (Fig. 3.1 (d)); it passes any current with
zero voltage drop.
• A forward-biased diode is said to be turned on, or simply on.
• The positive terminal of the diode is called the anode and the negative terminal
31
of diode is called the cathode.
Figure 3.1 The ideal diode: (a) diode circuit symbol; (b) i–v characteristic; (c) equivalent circuit in
the reverse direction; (d) equivalent circuit in the forward direction.

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Terminal Characteristics of Junction Diodes

Figure 3.7 shows the i-v characteristic of a silicon junction diode.

The same characteristic is shown in Fig. 3.8 with some scales

expanded and the others compressed to reveal details.

The characteristic curve consists of the three distinct regions:

1. The forward-bias region, determined by v > 0

2. The reverse-bias region, determined by v < 0

3. The breakdown region, determined by v < -VZK

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Figure 3.8 The diode i–v relationship with some scales expanded and others
compressed in order to reveal details. 34
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Figure 3.10 A simple circuit used to illustrate the analysis of circuits in which the diode is
forward conducting.

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Graphical Analysis Using the Exponential Model
• Graphical analysis is performed by plotting the relationships of
the previous two equations on the i-v plane.

• The solution can then be obtained as the coordinates of the point

of the intersection of the two graphs.

• A sketch of the construction is shown in Fig. 3.11.

• The curve represents the exponential diode equation and the

straight line represents the second equation. Such straight line is
known as load line.

• The load line intersects the diode curve at point Q, which

represents the operating point of the circuit. Its coordinates give
the values of ID and VD.
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Figure 3.11 Graphical analysis of the circuit in Fig. 3.10 using the exponential diode model.

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Figure 3.12 Approximating the diode forward characteristic with two straight lines: the piecewise-
linear model.

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Figure 3.13 Piecewise-linear model of the diode forward characteristic and its equivalent circuit
representation.

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Figure 3.16 The constant-voltage-drop model of the diode forward characteristics and its
equivalent-circuit representation.

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Rectifier Circuits
• One of the most important applications of diodes is in the design of rectifier
circuits.
• A diode rectifier forms an essential building block of the dc power supplies
required to power electronic equipment. A block diagram of such a power
supply is shown in Fig. 3.24.
• The dc voltage VO is required to be as constant as possible in spite of variations
in the ac line voltage and in the current drawn by the load.

Figure 3.24 Block diagram of a dc power supply.

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The Half Wave Rectifier

• The half wave rectifier utilizes alternate half-cycles of the input sinusoid.
Fig. 3.25 (a) shows the circuit of a half wave rectifier.
• Using the more realistic battery plus resistance diode model, we obtain
the circuit shown in Fig. 3.25 (b), from which we can write

• 𝑣𝑜 = 0, 𝑣𝑆 < 𝑉𝐷𝑂

𝑅 𝑅
• 𝑣𝑜 = 𝑣 − 𝑉𝐷𝑂
𝑅+𝑟𝐷 𝑆 𝑅+𝑟𝐷

• The transfer characteristic represented by these equations is sketched in

Fig. 3.25 (c). In many applications, 𝑟𝐷 ≪ 𝑅 and the second equation can
be simplified to

• 𝑣𝑜 = 𝑣𝑆 − 𝑉𝐷𝑂

• Where VDO = 0.7 V or 0.8 V. Fig. 3.25 (d) shows the output voltage
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obtained when the input vS is a sinusoid.
Figure 3.25 (a) Half-wave rectifier. (b) Equivalent circuit of the half-wave rectifier with the
diode replaced with its battery-plus-resistance model. (c) Transfer characteristic of the rectifier
circuit.
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Figure 3.25 (d) Input and output waveforms, assuming that rD << R.

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• In selecting diodes for rectifier, two important parameters must be
specified:

• the current handling capability of the diode, determined by the largest

current the diode is expected to conduct,

• and the peak inverse voltage (PIV) that the diode must be able to
withstand without breakdown, determined by the largest reverse voltage
that is expected to appear across the diode.

• From Fig. 3.25 (a) we observe that when vS is negative the diode will cut
off and vO will be zero.

• It follows that the PIV is equal to the peak of vS

• 𝑃𝐼𝑉 = 𝑉𝑆

• It is usually obvious that to select a diode that has a reverse that has a
reverse breakdown voltage at least 50 % greater than the expected PIV.
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The Full Wave Rectifier

• The full wave rectifier utilizes both halves of the input sinusoid. To provide a
unipolar output, it inverts the negative half of the sine wave.
• One possible implementation is shown in Fig. 3.26 (a).
• Here the transformer secondary winding is center tapped to provide two equal
voltages vS across the two halves of the secondary winding with the polarities
indicated.
• When the input line voltage (feeding the primary) is positive, both the signals
labelled vS will be positive. In this case D1 will conduct and D2 will be
reverse biased. The current through D1 will flow through R and back to the
center tap of the secondary.
• Now during the negative half cycle of the ac line voltage, both the voltages
are labelled vS will be negative. Thus D1 will be cut off while D2 will conduct.
• The important point here is that the current through R always flows in the
same direction, and thus vO will be unipolar, as indicated in the Fig. 3.26 (c).
• The output waveform shown is obtained by assuming that a conducting diode
has a constant voltage drop VD.
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Figure 3.26 Full-wave rectifier utilizing a transformer with a center-tapped secondary winding: (a)
circuit; (b) transfer characteristic assuming a constant-voltage-drop model for the diodes;

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Figure 3.26 Full-wave rectifier utilizing a transformer with a center-tapped secondary winding: (c)
input and output waveforms.

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• To find the PIV of the diodes in full wave rectifier circuit,
consider the situation during the positive half cycles.

• Diode D1 is conducting and D2 is cut off. The voltage at the

cathode of D2 is vo and that at its anode is –vs .

• Thus the reverse voltage across D2 will be (vo + vs), which will
reach the maximum when vo is at its peak value of (VS – VD), and
vs is at its peak value of VS ; thus

• 𝑃𝐼𝑉 = 2𝑉𝑆 − 𝑉𝐷

• Which is approximately twice that of the half wave rectifier.

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The Bridge Rectifier

• An alternative implementation of the full wave rectifier is shown in Fig. 3.27 (a).

• The circuit known as Bridge Rectifier because of the similarity with the Wheatstone
Bridge.

• The bridge rectifier, however, requires four diodes as compared to two in the
previous circuit.

• The bridge rectifier circuit operates as follows: During the positive half cycles of the
input voltage, vS is positive and thus current is conducted through diode D1 resistor
R and diode D2. Meanwhile diodes D3 and D4 will be reverse biased.

• vo will be lower than vs by two diode drops (compared with one drop in circuit
previously discussed). This is somewhat of a disadvantage of the bridge rectifier.

• Next consider the situation during the negative half cycles of the input voltage. The
secondary voltage vs will be negative and thus –vs will be positive forcing current
through D3 R and D4. Meanwhile diodes D1 and D2 will be reverse biased. vo will
always be positive as indicated in Fig. 3.27 (b).
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Figure 3.27 The bridge rectifier: (a) circuit

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Figure 3.27 The bridge rectifier: (b) input and output waveforms.

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• To determine the peak inverse voltage (PIV) of each diode,
consider the circuit during the positive half cycles.

• The reverse voltage across D3 can be determined form the loop

formed by D3, R and D2 as

• 𝑣𝐷3 𝑟𝑒𝑣𝑒𝑟𝑠𝑒 = 𝑣𝑜 + 𝑣𝐷2 (𝑓𝑜𝑟𝑤𝑎𝑟𝑑)

• Thus the maximum value of vD3 occurs at the peak of vo and is

given by

• 𝑃𝐼𝑉 = 𝑉𝑠 − 2𝑉𝐷 + 𝑉𝐷 = 𝑉𝑠 − 𝑉𝐷

• Observe that here PIV is about half of the value for the full-
wave rectifier with a center tapped transformer. This is another
advantage of the bridge rectifier.
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The Rectifier with a Filter Capacitor – The Peak Rectifier

• A simple way to reduce the variation of the output voltage is to place a

capacitor across the load resistor. The filter capacitor serves to reduce
substantially the variations in the output voltage.
• To see how the rectifier circuit with a filter capacitor works, consider
first the simple circuit shown in Fig. 3.28.
• Let the input vI be a sinusoid with a peak value VP , and assume the
diode to be ideal. As vI goes positive, the diode conducts and the
capacitor is charged so that vo = vI. This situation continues until vI
reaches its peak value VP. Beyond the peal value, as vI decreases the
diode becomes reverse biased and the output voltage remains constant at
the value VP.
• In fact theoretically speaking the capacitor will retain its charge and
hence its voltage indefinitely, because there is no way for the capacitor
to discharge.
• Thus the circuit provides a dc voltage output equal to the peak of the
input sine wave.
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Figure 3.28 (a) A simple circuit used to illustrate the effect of a
filter capacitor. (b) Input and output waveforms assuming an ideal
diode. Note that the circuit provides a dc voltage equal to the peak
of the input sine wave. The circuit is therefore known as a peak 82
rectifier or a peak detector.
• Next, we consider the more practical situation where a load
resistance R is connected across the capacitor C, as depicted in
Fig. 3.29 (a). However, we will continue to assume the diode to be
ideal.

• As before, for a sinusoidal input, the capacitor charges to the peak

of the input VP. Then the diode cuts off and the capacitor
discharges through the load resistor R.

• The capacitor discharge will continue for almost the entire cycle,
until the time at which vI exceeds the capacitor voltage.

• Then the diode turns on again and charges the capacitor up to the
peak of vI, and the process repeats itself. Observe that to keep the
output voltage from decreasing too much during capacitor
discharge, one selects a value of C so that the time constant CR is
much greater than the discharge interval. 83
 (a)

Figure 3.29 (a) Circuit Diagram with Filter Capacitor. The diode is assumed ideal.

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Figure 3.29 (b) & (c) Voltage and current waveforms in the peak rectifier circuit with CR @T.
The diode is assumed ideal.
• We are now ready to analyse the circuit in detail. Figure 3.29 (b) shows the
steady-state input and output voltage waveforms under the assumption that CR
>> T, where T is the period of the sinusoid. The waveforms of the load current

• 𝑖𝐿 = 𝑣𝑜 Τ𝑅

• and the diode current (when it is conducting)

𝑑𝑣𝐼
• 𝑖𝐷 = 𝑖𝐶 + 𝑖𝐿 = C + 𝑖𝐿
𝑑𝑡

• Are shown in Fig. 3.29 (c). The following observations are in order:

1. The diode conducts for a brief interval ∆𝑡, near the peak of the input sinusoid
and supplies the capacitor with the charge equal to that lost during the much
longer discharge interval.
2. Assuming an ideal diode, the diode conduction begins at time t1, at which the
input vI equals the exponential decaying output vo. Conduction stops at t2
shortly after the peak of vI; the exact value of t2 can be determined by setting iD
= 0 in the above equation.
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3. During the diode off interval, the capacitor C discharges through R and thus vo
decays exponentially with a time constant CR. The discharge interval begins just
past the peak of vI. At the end of discharge interval, which lasts for almost the
entire period T, vo = Vp – Vr, where Vr is the peak to peak ripple voltage. When CR
>> T, the value of Vr is small.

4. When Vr is small, vo is almost constant and equal to the peak value of vI. Thus
the dc output voltage is approximately equal to Vp. Similarly, the current iL is
almost constant, and its dc component IL is given by

𝑉𝑃
• 𝐼𝐿 =
𝑅

• If desired a more accurate expression for the output dc voltage can be obtained
by taking the average of the extreme value of vo,

1
• 𝑉𝑜 = 𝑉𝑃 − 𝑉𝑟
2

• With these observations in hand, we derive the expression for Vr and for the
average and peak to peak values of the diode current. During the diode off
interval, vo can be expressed as
• 𝑣𝑜 = 𝑉𝑝 𝑒 −𝑡Τ𝐶𝑅 87
Figure 3.30 Waveforms in the full-wave peak rectifier.

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Clipper and Clamper Circuits
Clippers
Clippers
Clippers
 Clippers
● Clipper circuits, also called limiter circuits, are used to eliminate
portion of a signal that are above or below a specified level – clip value.
● The purpose of the diode is that when it is turn on, it provides the clip
value
● Clip value = V’. To find V’, use KVL at L1
● The equation is : V’ – VB - V = 0 → V’ = VB + V

Vi

V’ = VB + V
L1

➢ Then, set the conditions

➢ If Vi > V’, what happens? → diode conducts, hence Vo = V’
➢ If Vi < V’, what happens? → diode off, open circuit, no current flow, Vo = Vi
Parallel Based Clippers

➢ Positive and negative clipping can be performed simultaneously

by using a double limiter or a parallel-based clipper.

➢ The parallel-based clipper is designed with two diodes and two

voltage sources oriented in opposite directions.
➢ This circuit is to allow clipping to occur during both cycles;
negative and positive
 Clampers
● Clamping shifts the entire signal voltage
by a DC level.
➢ Consider, the sinusoidal input voltage
signal, vI.
➢ 1st 900, the capacitor is charged up to
the peak value of Vi which is VM.
➢ Then, as Vi moves towards the –ve
cycle,
➢ the diode is reverse biased.
➢ Ideally, capacitor cannot discharge,
hence Vc = VM
➢ By KVL, we get

NOTE: The input signal is shifted by a dc

level; and that the peak-to-peak value is
the same
Clampers
● A clamping circuit that includes an independent voltage source VB.
Peak value VM

𝑣𝑜 = −𝑉𝑀 + 𝑉𝑀 𝑠𝑖𝑛𝜔𝑡 + 𝑉𝐵
Operation in Reverse Breakdown Region – Zener
Diodes

• The very steep i-v curve that the diode exhibits in the breakdown
region (Fig. 3.8) and the almost constant voltage drop that this
indicates suggest that diodes operating in the breakdown region
can be used in the design of voltage regulators.
• This in fact turns out to be an important application of the diodes
operating in the reverse breakdown region.
• Special diodes are manufactured to operate specifically in the
breakdown region.
• Such diodes are called breakdown diodes or more commonly,
Zener Diodes.
• Fig. 3.20 shows the circuit symbol of the zener diode.
• In normal applications of zener diodes, current flows into the
cathode, and the cathode is positive with respect to the anode.
Thus, IZ and VZ in Fig. 3.20 have positive values.
Figure 3.20 Circuit symbol for a zener diode.
Figure 3.21 The diode i–v characteristic with the breakdown region shown in some detail.
Specifying and Modelling the Zener Diode
• Figure 3.21 shows the details of the diode i-v characteristics in the breakdown
region.
• We observe that for the currents greater than the knee current IZ (which is specified
in the data sheet of the zener diode), the i-v characteristic is always a straight line.
• The manufacturer usually specifies the voltage across the zener diode VZ at the
specified test current IZT.
• Thus 6.8 V zener diode will exhibit at 6.8 V drop at a specified test current, of say,
10 mA.
• As the current through the zener diode deviates from IZT , the voltage across it will
change.
• Figure 3.21 shows that corresponding to current ∆𝐼 the zener voltage changes by
∆𝑉, which is related to ∆𝐼 by
• ∆𝑉 = 𝑟𝑍 ∆𝐼
• Where rZ is the inverse of the slope of the almost linear i-v curve at point Q.
• Resistance rZ is the incremental resistance of the zener diode at operating point Q.
• It is also known as the dynamic resistance of the zener, and its value is specified
on the device data sheet. Typically rZ is in the range of a few ohms to few tens of
ohms.
• Zener diodes are fabricated with voltage VZ in the range of a few volts to a few
hundred volts.
Figure 3.22 Model for the zener diode.
• The almost linear i-v characteristic of the zener diode suggests
that the device can be modelled as indicated in the Fig 3.22.

• Here VZ0 denotes the point at which the straight line of the slope
1Τ𝑟𝑍 intersects the voltage axis (Refer to Fig. 3.21).

• Although VZ0 is shown to be slightly different from the knee

voltage VZK , in practice their values are almost equal.

• The equivalent circuit model of the Fig. 3.22 can be analytically

described by

• 𝑉𝑍 = 𝑉𝑍0 + 𝑟𝑍 𝐼𝑍

• And it applies for 𝐼𝑍 > 𝐼𝑍𝐾 and obviously, 𝑉𝑍 > 𝑉𝑍0

Zener Breakdown
• This type of breakdown occurs for a reverse bias voltage between
2 to 8V.
• Even at this low voltage, the electric field intensity is strong
enough to exert a force on the valence electrons of the atom such
that they are separated from the nuclei.
• This results in formation of mobile electron hole pairs, increasing
the flow of current across the device. Approximate value of this
field is about 2*10^7 V/m.
• This type of break down occurs normally for highly doped diode
with low breakdown voltage and larger electric field.
• As temperature increases, the valence electrons gain more energy
to disrupt from the covalent bond and less amount of external
voltage is required.
• Thus zener breakdown voltage decreases with temperature.
Zener diode applications

Zener Diode as a voltage Regulator

• In a DC circuit, Zener diode can be used as a voltage regulator or to

provide voltage reference. The main use of zener diode lies in the
fact that the voltage across a Zener diode remains constant for a
larger change in current.
• This makes it possible to use a Zener diode as a constant voltage
device or a voltage regulator.
• In any power supply circuit, a regulator is used to provide a
constant output (load) voltage irrespective of variation in input
voltage or variation in load current.
• The variation in input voltage is called line regulation, whereas the
variation in load current is called load regulation.
• A simple circuit involving Zener diode as a regulator requires a
resistor of low value connected in series with the input voltage
source.

• The low value is required so as to allow the maximum flow of current

through the diode, connected in parallel.

• However, the only constraint being, the current through zener diode
should not be less than minimum zener diode current.

• Simply put, for a minimum input voltage and a maximum load

current, the Zener diode current should always be Izmin.
• While designing a voltage regulator using zener diode, the latter is
chosen with respect to its maximum power rating.

• In other words, the maximum current through the device should be:-

• Imax = Power/Zener Voltage

• Since the input voltage and the required output voltage is known, it
is easier to choose a zener diode with a voltage approximately equal
to the load voltage, i.e. Vz ~=Vo.

• The value of the series resistor is chosen to be

• R =(Vin – Vz)/(Izmin + IL),

• where IL = Load Voltage/Load resistance.

• Zener diode is a junction formed by combining highly doped
PN semiconductors.

• It works on the principle of Zener breakdown and is

operated in reverse breakdown region.

• In reverse breakdown region high current flow through the

diode leading to high power dissipation.

• Hence the Zener diodes are provided with adequate power

dissipation capabilities to operate in reverse breakdown
region.

• When a reverse bias is applied across the diode electric field

is generated by uncovered charges at the depletion region.
The electric field intensity across a PN junction diode
increases as doping level are increased.
Bipolar Junction Transistor
The bipolar junction transistor (BJT) is a three-element device formed
from two junctions which share the common semiconductor layer.
There are two types of BJTs: pnp and npn. The three elements of the
BJT are referred to as the emitter, base, and the collector. This is
depicted in the figure below. The arrow on the emitter lead specifies
the direction of the current when the emitter-base junction is forward-
biased.
Bipolar Junction Transistor
As illustrated in the figure above, the emitter area is considerably smaller than
the collector area. The difference is mainly due to the fact that in the most
prevalent uses of BJTs, the collector region must handle most power than the
emitter. Hence, more surface area is required for heat dissipation. A second
difference is the doping densities of the emitter and collector regions. The
emitter generally serves as the source of mobile charges. Therefore a high
density is used in emitter to make many carriers available. When the emitter-
base junction is forward biased, the emitter injects electrons into the base
region where they move towards the collector. If the collector-base junction is
reverse-biased, the minority carrier electron in the base are swept into the
collector region, where they become the major component of the collector
current. The base region is doped at a level between the emitter and collector
concentration.
BJT modes of operation
Cutoff EBJ is Reverse Biased CBJ is Reverse Biased
Active EBJ is Forward Biased CBJ is Reverse Biased
Reverse Active EBJ is Reverse Biased CBJ is Forward Biased
Saturation EBJ is Forward Biased CBJ is Forward Biased
Operation of The npn Transistor in the Active Mode
Operation of npn BJT in Active Mode
The forward bias on the emitter-base junction will cause the current to flow across this junction.
Current consists of two components: electrons injected from the emitter into the base, and holes
injected from the base into the emitter. It is highly desirable to have the first component
(electrons from emitter to base) at a much higher level than the second component (holes from
the base to emitter). This can be accomplished by fabricating the device with a heavily doped
emitter and a lightly doped base. The current that flows across the emitter-base junction will
constitute the emitter current iE.

The Electrons injected from emitter into the base will be minority carriers in the p-type base
region. Because the Base is usually very thin, in the steady state the electron concentration will
be highest at the emitter side and lowest at the collector side.

Some of the electrons that are diffusing through the base region will combine with holes which
are the majority carriers in the base. However, since the base is actually very thin, the proportion
of electrons lost due to recombination will be quite small.
The Collector Current
Most of the diffusing electrons from emitter will reach the boundary of the collector-base
depletion region. Since the collector is more positive than the base, these electrons will be
swept across the CBJ depletion region into the collector. They will get collected to constitute
the collector current iC.
VBE

iC  I S e VT

Where
iE  iC  iB
β = common-emitter current gain
iC   i B

iC 
 1
iE
α = common-base current gain
 
   
 1 1
The BJT as an Amplifier

The basis for the amplifier application is the fact that when the BJT is operated in the active
mode, it acts as a voltage controlled current source. Changes in the base-emitter voltage gives
rise to changes in the collector current iC. Thus in the active mode BJT can be used to
implement a transconductance amplifier. The amplifier circuit is illustrated below.
Large-Signal Operation of npn Transistor
The figure given below show the basic structure of the most commonly
used BJT amplifier, the grounded-emitter or common-emitter (CE)
circuit. The total input voltage vI (bias+signal) is applied between the
base and emitter (vBE = vI). The total output voltage vO (bias+signal) is
taken between collector and ground (vO = vCE). The resistor RC has two
functions, first to establish a desired dc bias voltage at the collector, and
to convert the collector signal current iC to an output voltage vCE or vO.
 VCC

iC

RC

+
+ vO = vCE
vBE = vI
- -

(a)
The transfer characteristics of the circuit in (a) is given in (b) above. The
amplifier is biased at the point Q, and a small signal vI is superimposed on the
bias voltage vBE. The resulting output signal vO, appears superimposed on the dc
collector voiltage VCE. The amplitude of vO is larger than that of vI by voltage
gain Av.

vO  vCE  VCC  RC iC
v BE

iC  I S e VT

vI

 ISe VT
Thus we obtain

vI

v O  V CC  R C I S e VT

We observe that the exponential term in this equation gives rise to the steep
slope of the YZ segment of the transfer curve. Active mode operation ends
when the collector voltage (vO or vCE) falls by 0.4 V or so below that of the
base (vI or vBE). At this point, the CBJ turns on, and the transistor enters the
saturation region. This is indicated by the point Z on the transfer curve. A
further increase in vBE causes vCE to decrease only slightly. In saturation region
vCE = VCEsat, which falls in the narrow range of 0.1 V to 0.2 V. The collector
current will also remain nearly constant at the value ICsat.
Amplifier Gain

To operated the BJT as a linear amplifier, it must be biased at the point in the
active region. The figure given above shows such point, labeled Q (for quiesent
point) and characterized by a dc base-emitter voltage VBE and a dc collector-
emitter voiltage VCE. Then,

VCE  VCC  RC IC
Small signal Amplifier gain AV can be found out by differentiating the
expression in vO given above and evaluating the derivative at point Q for vI =
VBE .
 dvO
Av  vI VBE
dvI

V BE
1 IC RC V RC
 ISe VT
RC    
VT VT VT

Where VRC is the dc voltage drop across RC

VRC  VCC  VCE

Observe that the CE amplifier is inverting, that is, the output is 1800 out of phase
relative to the input signal. It follows that to maximize the voltage gain we should
use as large a voltage drop across RC as possible. Thus for a given value of VCC,
to increase VRC we have to operate at lower VCE. The lowest VCE is VCEsat. Hence,

V  V
Av   CC CEsat
VT
VCC
Av max 
VT
Graphical Representation of Transistor Characteristics

The figure given below shows the iC-vBE characteristics of a BJT

As in silicon diodes the voltage across the emitter-base junction decreases by
about 2 mV for each rise of 10 C in temperature, provided that the junction is
operating at the constant current I as shown in the figure above.

v BE

iC  I S e VT
The Common-Emitter Characteristics

An alternative way of expressing the transistor common-emitter characteristics

is illustrated in figure below. Here the base current iB rather than the base-
emitter voltage vBE is used as a parameter.
An important parameter is the common-emitter current gain β. Consider the
transistor operating in the active region at the point labelled Q as shown in Fig (b)
above. The collector current at this point is ICQ and base current as IBQ and the
collector voltage VCEQ. The ratio of the collector current to base current is the
large-signal or dc β.
I CQ iC
 dc   ac  vCE  cons tan t
I BQ iB

Which is the β we have been using in our description of the transistor

operation. It is commonly referred to on the manufacturer’s data sheets as hfe .
One can define another β based on incremental or small-signal quantities. So,
keeping vCE constant at point VCEQ, changing iB from IBQ to (IBQ + ΔiB) results
in iC increasing from ICQ to (ICQ + ΔiC). Thus we can write the incremental or ac
β as βac .
The magnitude of βac and βdc differ, typically by approximately 10% to 20%. Finally, it
should be mentioned here that the small-signal β or βac is known by an alternate symbol
hfe. Because the small-signal β or hfe is defined and measured at a constant vCE, that is
with a zero signal component between collector and emitter, it is known as the short-
circuit common-emitter current gain.

The figure shows the typical dependence

of β on IC and on temperature in a modern
integrated-circuit npn silicon transistor
intended for operation around 1 mA. The
value of β depends on the current at which
the transistor is operating as shown by the
above relationship. It also shows the
temperature dependence of β.
An expanded view of the common-emitter characteristics in the saturation
region
As can be seen from the figure the
incremental β is lower in the
saturation region than in the active
region. A possible operating point in
the saturation region is that labelled
X. It is characterised by a base
current IB, a collector current Icsat
and a collector -emitter voltage
VCEsat. Note that ICsat < βFIB. Since
the value of ICsat is established by the
circuit designer, a saturation
transistor is said to be operating at a
forced β given by
 I Csat
 forced  Thus,  forced   F
IB

The ratio of βF to βforced is known as the overdrive factor. The greater the
overdrive factor, the deeper the transistor is driven into saturation and the lower
the VCEsat becomes.The collector to emitter resistance RCEsat is given below.
Typically RCEsat ranges between a few ohms to a few tens of ohms.

vCE
RCEsat  iB  I B ,iC  I Csat
iC
Figure (a) Basic common-emitter amplifier circuit. (b) Transfer characteristic of the circuit in (a). The amplifier is biased at a point Q, and a small voltage signal
vi is superimposed on the dc bias voltage VBE. The resulting output signal vo appears superimposed on the dc collector voltage VCE. The amplitude of vo is
larger than that of vi by the voltage gain Av.
Figure Circuit whose operation is to be analyzed graphically
Figure Graphical construction for the determination of the dc base current in the circuit of Fig. given before.
Figure Graphical construction for determining the dc collector current IC and the collector-to-emitter voltage VCE in the
circuit of Fig. given before.
Biasing in BJT Amplifier Circuits

The biasing problem is that of establishing a constant dc current in the collector of the
BJT. This current has to be calculated, predictable, and insensitive to the variations in
temperature and to a large variations in the value of β encountered among the
transistors of the same type.

Attempting to bias the BJT by fixing the voltage VBE by using a voltage divider across
the power supply VCC, as shown in figure below (a) is not viable approach. The very
sharp exponential relationship iC – vBE means that any small and inevitable differences
in VBE from the desired value will result in large differences in IC and VCE. Secondly,
biasing the BJT by establishing a constant current in the base, as shown in (b) below,
where IB ≡ (VCC – 0.7)/RB, is also not recommended approach. Here the typical large
variations in the value of β among units of the same device type will result in
corresponding large variations in IC and hence VCE.
Two obvious schemes for biasing the BJT: (a) by fixing VBE; (b) by fixing IB. Both
result in wide variations in IC and hence in VCE and therefore are considered to be
“bad.” Neither scheme is recommended.
Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

The transistor is fabricated on a p-type substrate, which is single-crystal silicon

wafer that provides physical support for the device. Two heavily doped n-type
regions, indicated in the figure below as n+ source and the n+ drain regions, are
created in the substrate. A thin layer of silicon dioxide (SiO2) of the thickness
typically between 2-50 nm serves as an excellent electrical insulator, is grown on
the surface of the substrate covering the area between the source and the drain
regions. Metal is deposited on top of the oxide layer to form the gate electrode of
the device.
Physical structure of the enhancement-type NMOS transistor

(a) Perspective View (b) Cross-section

Another name for the MOSFET is the insulated-gate FET or IGFET. This name also arise from
the physical structure of the device, emphasizing the fact that the gate electrode is electrically
insulated from the device body (by the oxide layer). It is this insulation that causes the current
in the gate terminal to be extremely small (of the order of 10-15 A).

The enhancement-type NMOS transistor

with a positive voltage applied to the gate is
shown in the figure. An n-channel is
induced at the top of the substrate beneath
the gate. The value of the vGS at which a
sufficient number of mobile electrons
accumulate in the channel region to form a
conducting channel is called the threshold
voltage and is denoted by Vt which is
positive for n-channel FET. The value of Vt
is controlled during device fabrication and
typically lies in the range 0.5 V to 1.0 V.
The gate and the channel region of the MOSFET form a parallel plate capacitor,
with the oxide layer acting as the capacitor dielectric. The positive gate voltage
causes positive charge to accumulate on the top plate of the capacitor. The
corresponding negative charge on the bottom plate is formed by electrons in the
induced channel. An Electrical field thus develops in the vertical direction. It is
this field that controls the amount of charge in the channel, and thus determines
the channel conductivity and, in turn, the current that will flow through the
channel when the voltage vDS is applied.
Applying a small vDS

An NMOS transistor with vGS > Vt and with

a small vDS applied. The device acts as a
resistance whose value is determined by vGS.
Specifically, the channel conductance is
proportional to vGS – Vt and thus iD is
proportional to (vGS – Vt) and vDS. Current is
carried by free electrons travelling from the
source to drain. By convention, the direction
of the current flow is opposite to that of the
flow of negative charge. Thus the current
flows from the drain to source in the channel.
The magnitude of iD depends upon the
density of the electrons in the channel, which
in turn depends upon the magnitude of vGS.
Specifically, for vGS = Vt, the channel is just
induced and the current conducted is still
negligibly small.
As vGS exceeds Vt, more electrons are attracted into the channel. We
may visualize the increase in charge carriers in the channel as the
increase in the channel depth. The result is a channel of increased
conductance or, equivalently, reduced resistance.

Figure given below shows a sketch of iD versus vDS for various values
of vGS. We observe that the MOSFET is operating as a linear
resistance whose value is controlled by vGS. The resistance is infinite
for vGS ≤ Vt and its value decreases vGS exceeds Vt.
The iD–vDS characteristics of the
MOSFET in this figure when the
voltage applied between drain and
source, vDS, is kept small. The device
operates as a linear resistor whose
value is controlled by vGS.
For the MOSFET to conduct a channel
has to be induced. Then, increasing the
vGS above the threshold voltage Vt
enhances the channel, hence the name
of this type of MOSFET is
enhancement-type MOSFET. Finally,
we note that the current that leaves the
source terminal (iS) is equal to the
current that enters the drain terminal
(iD) and the gate current iG = 0.
Operation as vDS is Increased

For this purpose let vGS be held constant at a value greater than Vt. The voltage
between the gate and the points along the channel decreases from vGS at the
source end to vGS – vDS at the drain end. Since the channel depth depends upon
this voltage, we find that the channel is no longer uniform in depth; rather the
channel is tapering as shown in figure below, being deepest at the source and
shallowest at the drain end. As vDS is increased, the channel becomes more
tapered and its resistance increases correspondingly. Eventually, when vDS is
increased to the value that reduces the voltage between gate and channel at the
drain end to Vt that is, vGD = Vt or vGS – vDS = Vt or vDS = VGS– Vt the channel
depth at the drain end decreases to almost zero, and the channel is said to be
pinched-off. The drain current thus saturates at this value and the MOSFET is
said to have entered the saturation region of operation. The voltage vDS at
which the saturation occurs is denoted by vDSsat where
vDSsat  vGS  Vt
Obviously for every value of vGS ≥ Vt, there is a corresponding value of vDSsat. The device operates in the saturation
region if vDS ≥ vDSsat. The region of iD-vDS characteristics obtained for vDS < vDSsat is called the triode region.
The iD-vDS Characteristics

The characteristics given in the following figure indicate that there are three distinct regions of
operation: the cutoff region, the triode region, and the saturation region. The saturation
region is used if the FET is to operate as an amplifier. For operation as a switch, the cutoff and
triode regions are utilized. The device is cut off when vGS < Vt. To operate the MOSFET in the
triode region we must first induce a channel,
vGS ≥ Vt (induced channel)
And then keep vDS small enough so that the channel remains continuous. This is achieved by
ensuring that the gate-to-drain voltage is
vGD > Vt (continuous channel)
This condition can be stated explicitly in terms of vDS by writing vGD = vGS + vSD = vGS – vDS
Thus,
vGS - vDS > Vt
Which can be rearranged to yield
vGD < vGS – Vt (continuous channel)
In words, the n-channel enhancement-type MOSFET operates in the triode region when vGS is
greater than Vt, and the drain voltage is lower than the gate voltage by at least Vt volts.
(a) An n-channel enhancement-type MOSFET with vGS and vDS applied and
with the normal directions of current flow indicated.

(b) The iD–vDS characteristics for a device with k’n (W/L) = 1.0 mA/V2.
Circuit Symbol

The figure below shows the circuit symbol for the n-channel enhancement-type
MOSFET. Although the MOSFET is a symmetrical device, it is often useful in
circuit design to designate one terminal as the source and the other as the drain
(without having to write S and D beside the terminals). The arrowhead points in
the normal direction of current flow and thus indicates the polarity of the device.
The figure clearly distinguishes the source from the drain, the drain is always
positive relative to the source in an n-channel FET.
(a) Circuit symbol for the n-channel enhancement-type MOSFET.

(b) Modified circuit symbol with an arrowhead on the source terminal to

distinguish it from the drain and to indicate device polarity (i.e., n channel).

(c)Simplified circuit symbol to be used when the source is connected to the body
or when the effect of the body on device operation is unimportant.
In the triode region the iD-vDS characteristics can be described by the relationship

W  1 2 
iD  k '
n  ( v GS  V t ) v DS  v DS 
L  2 

W
iD  k (vGS  Vt )vDS
'
n
L
This linear relationship represents the operation of the MOS transistor as a linear resistance
whose value is controlled by vGS. Specifically, for vGS set to a value VGS, rDS is given by
 1
vDS vDS small  ' W 
rDS   k n (VGS  Vt )
iD vGS  VGS  L 
The boundary between the triode and saturation regions is characterised by

v DS  v GS  V t
Substituting in the first equation above we get

1 ' W
iD  k n ( v GS  V t ) 2

2 L
Temperature Effects

Both Vt and k’ are temperature sensitive. The magnitude of Vt decreases by about 2 mV for
every 1oC rise in temperature. This decrease in |Vt| gives rise to a corresponding increase in
drain current as the temperature is increased. However, k’ decreases with the temperature and
its effect is dominant one, the overall observed effect of a temperature increase is a decrease
in drain current.
Where ID is the drain current without the channel-length modulation taken into account. That is

I D  k n VGS  Vt    n Cox VGS  Vt 

1 'W 2 1 W 2

2 L 2 L
Symbols for n channel
Depletion Mode MOSFET
Symbols for p channel
Depletion Mode MOSFET
Figure 4.59 (a) Circuit symbol for the n-channel depletion-type MOSFET. (b) Simplified circuit symbol applicable for the
case the substrate (B) is connected to the source (S).
Figure 4.60 The current-voltage characteristics of a
depletion-type n-channel MOSFET for which Vt = –4 V
and kn(W/L) = 2 mA/V2
(a) transistor with current and voltage polarities indicated;
(b) the iD–vDS characteristics;
(c) the iD–vGS characteristic in saturation.
INTRODUCTION TO NUMBER SYSTEMS
Which implies that:

153 10 = 231 8
The subtraction of two n-digit unsigned numbers (M – N) in base (r-1) can be done as follows:

1. Add the minuend M to the (r – 1)’s complement of the subtrahend N.

2. Inspect the result obtained in step 1 for an end carry.
a) If an end carry occurs, add 1 to the least significant digit (end – around carry).
b) If an end around carry does not occur, take the (r – 1)’s complement of the number
obtained in step 1 and place a negative sign in the front.