Unit-1 1

Unit- I

Functional Components of a Computer

Computer : A computer is a combination of hardware and software
resources which integrate together and provides various functionalities to
the user. Hardware are the physical components of a computer like the
processor, memory devices, monitor, keyboard etc. while software is the
set of programs or instructions that are required by the hardware resources
to function properly. There are a few basic components that aid the
working-cycle of a computer i.e. the Input- Process- Output Cycle and
these are called as the functional components of a computer. It needs
certain input, processes that input and produces the desired output. The
input unit takes the input, the central processing unit does the processing of
data and the output unit produces the output. The memory unit holds the
data and instructions during the processing.
Digital Computer: A digital computer can be defined as a programmable
machine which reads the binary data passed as instructions, processes this
binary data, and displays a calculated digital output. Therefore, Digital
computers are those that work on the digital data.
Details of Functional Components of a Digital Computer

 Input Unit: The input unit consists of input devices that are
attached to the computer. These devices take input and convert it
2 Functional Components of a Computer

into binary language that the computer understands. Some of the

common input devices are keyboard, mouse, joystick, scanner etc.
 Central Processing Unit (CPU) : Once the information is entered
into the computer by the input device, the processor processes it.
The CPU is called the brain of the computer because it is the
control center of the computer. It first fetches instructions from
memory and then interprets them so as to know what is to be done.
If required, data is fetched from memory or input device.
Thereafter CPU executes or performs the required computation
and then either stores the output or displays on the output device.
The CPU has three main components which are responsible for
different functions – Arithmetic Logic Unit (ALU), Control Unit
(CU) and Memory registers
 Arithmetic and Logic Unit (ALU): The ALU, as its name
suggests performs mathematical calculations and takes logical
decisions. Arithmetic calculations include addition, subtraction,
multiplication and division. Logical decisions involve comparison
of two data items to see which one is larger or smaller or equal.
 Control Unit : The Control unit coordinates and controls the data
flow in and out of CPU and also controls all the operations of
ALU, memory registers and also input/output units. It is also
responsible for carrying out all the instructions stored in the
program. It decodes the fetched instruction, interprets it and sends
control signals to input/output devices until the required operation
is done properly by ALU and memory.
 Memory Registers: A register is a temporary unit of memory in
the CPU. These are used to store the data which is directly used by
the processor. Registers can be of different sizes(16 bit, 32 bit, 64
bit and so on) and each register inside the CPU has a specific
function like storing data, storing an instruction, storing address of
a location in memory etc. The user registers can be used by an
assembly language programmer for storing operands, intermediate
results etc. Accumulator (ACC) is the main register in the ALU
and contains one of the operands of an operation to be performed
in the ALU.
 Memory : Memory attached to the CPU is used for storage of data
and instructions and is called internal memory The internal
memory is divided into many storage locations, each of which can
 Unit-1 3

store data or instructions. Each memory location is of the same

size and has an address. With the help of the address, the computer
can read any memory location easily without having to search the
entire memory. when a program is executed, it’s data is copied to
the internal memory ans is stored in the memory till the end of the
execution. The internal memory is also called the Primary memory
or Main memory. This memory is also called as RAM, i.e.
Random Access Memory. The time of access of data is indepen-
dent of its location in memory, therefore this memory is also called
Random Access memory (RAM).
 Output Unit: The output unit consists of output devices that are
attached with the computer. It converts the binary data coming
from CPU to human understandable form. The common output
devices are monitor, printer, plotter etc.
Interconnection between Functional Components
A computer consists of input unit that takes input, a CPU that processes the
input and an output unit that produces output. All these devices
communicate with each other through a common bus. A bus is a
transmission path, made of a set of conducting wires over which data or
information in the form of electric signals, is passed from one component
to another in a computer. The bus can be of three types – Address bus,
Data bus and Control Bus.
Following figure shows the connection of various functional components:

The address bus carries the address location of the data or instruction. The
data bus carries data from one component to another and the control bus
4 Functional Components of a Computer

carries the control signals. The system bus is the common communication
path that carries signals to/from CPU, main memory and input/output
devices. The input/output devices communicate with the system bus
through the controller circuit which helps in managing various input/output
devices attached to the computer.
Bus
Bus is a group of conducting wires which carries information; all the
peripherals are connected to microprocessor through Bus.

There are three types of buses.

1. Address bus –
It is a group of conducting wires which carries address only.Address bus is
unidirectional because data flow in one direction, from microprocessor to
memory or from microprocessor to Input/output devices (That is, Out of
Microprocessor).
The Length of the address bus determines the amount of memory a system
can address. Such as a system with a 32-bit address bus can address 2^32
memory locations.
Data bus
It is a group of conducting wires which carries Data only.Data bus is
bidirectional because data flow in both directions, from microprocessor to
memory or Input/output devices and from memory or Input/output devices
to microprocessor.
The width of the data bus is directly related to the largest number that the
bus can carry, such as an 8 bit bus can represent 2 to the power of 8 unique
values, this equates to the number 0 to 255.A 16 bit bus can carry 0 to
65535.
 Unit-1 5

2. Control bus
It is a group of conducting wires, which is used to generate timing and
control signals to control all the associated peripherals, microprocessor
uses control bus to process data that is what to do with selected memory
location. Some control signals are:
 Memory read
 Memory write
 I/O read
 I/O Write
 Opcode fetch
If one line of control bus may be the read/write line.If the wire is
low (no electricity flowing) then the memory is read, if the wire is high
(electricity is flowing) then the memory is written.
Bus Arbitration
Bus arbitration refers to the process by which the current bus master
accesses and then leaves the control of the bus and passes it to the another
bus requesting processor unit. The controller that has access to a bus at an
instance is known as Bus master.
A conflict may arise if the number of DMA controllers or other controllers
or processors try to access the common bus at the same time, but access
can be given to only one of those. Only one processor or controller can be
Bus master at the same point of time. To resolve these conflicts, Bus
Arbitration procedure is implemented to coordinate the activities of all
devices requesting memory transfers. The selection of the bus master must
take into account the needs of various devices by establishing a priority
system for gaining access to the bus. The Bus Arbiter decides who would
become current bus master.
There are two approaches to bus arbitration:
1. Centralized bus arbitration – A single bus arbiter performs the
required arbitration.
2. Distributed bus arbitration – All devices participate in the
selection of the next bus master.
6 Functional Components of a Computer

Methods of Centralized BUS Arbitration –

There are three bus arbitration methods:
(i) Daisy Chaining method –
It is a simple and cheaper method where all the bus masters use the same
line for making bus requests. The bus grant signal serially propagates
through each master until it encounters the first one that is requesting
access to the bus. This master blocks the propagation of the bus grant
signal; therefore any other requesting module will not receive the grant
signal and hence cannot access the bus. During any bus cycle, the bus
master may be any device – the processor or any DMA controller unit,
connected to the bus.

Advantages –
 Simplicity and Scalability.
 The user can add more devices anywhere along the chain, up to a
certain maximum value.
Disadvantages –
 The value of priority assigned to a device is depends on the position
of master bus.
 Propagation delay is arises in this method.
 If one device fails then entire system will stop working.
(ii) Polling or Rotating Priority method
In this, the controller is used to generate the address for the master(unique
priority), the number of address lines required depends on the number of
masters connected in the system. The controller generates a sequence of
master address. When the requesting master recognizes its address, it
activates the busy line and begins to use the bus.
 Unit-1 7

Advantages –
 This method does not favor any particular device and processor.
 The method is also quite simple.
 If one device fails then entire system will not stop working.
Disadvantages –
 Adding bus masters is difficult as increases the number of address
lines of the circuit.
(iii) Fixed priority or Independent Request method
In this, each master has a separate pair of bus request and bus grant lines
and each pair has a priority assigned to it.
The built-in priority decoder within the controller selects the highest
priority request and asserts the corresponding bus grant signal.
8 Functional Components of a Computer

Advantages –
 This method generates fast response.
Disadvantages –
 Hardware cost is high as large no. of control lines are required.
Distributed BUS Arbitration
In this, all devices participate in the selection of the next bus master. Each
device on the bus is assigned a 4bit identification number. The priority of
the device will be determined by the generated ID.
Bus and Memory Transfers
A digital system composed of many registers, and paths must be provided
to transfer information from one register to another. A bus structure, on the
other hand, is more efficient for transferring information between registers
in a multi-register configuration system.
A bus consists of a set of common lines, one for each bit of register,
through which binary information is transferred one at a time. Control
signals determine which register is selected by the bus during a particular
register transfer. The following block diagram shows a Bus system for four
registers. It is constructed with the help of four 4 * 1 Multiplexers each
having four data inputs (0 through 3) and two selection inputs (S1 and S2).

The two selection lines S1 and S2 are connected to the selection inputs of
all four multiplexers. The selection lines choose the four bits of one
register and transfer them into the four-line common bus.
 Unit-1 9

When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data
inputs of all four multiplexers are selected and applied to the outputs that
forms the bus. This, in turn, causes the bus lines to receive the content of
register A since the outputs of this register are connected to the 0 data
inputs of the multiplexers.
Similarly, when S1S0 = 01, register B is selected, and the bus lines will
receive the content provided by register B.
The following function table shows the register that is selected by the bus
for each of the four possible binary values of the Selection lines.

A bus system can also be constructed using three-state gates instead of

multiplexers.
The three state gates can be considered as a digital circuit that has three
gates, two of which are signals equivalent to logic 1 and 0 as in a
conventional gate. However, the third gate exhibits a high-impedance state.
The most commonly used three state gates in case of the bus system is
a buffer gate.
The graphical symbol of a three-state buffer gate can be represented as:

The following diagram demonstrates the construction of a bus system with

three-state buffers.
10 Functional Components of a Computer

o The outputs generated by the four buffers are connected to form a

single bus line.
o Only one buffer can be in active state at a given point of time.
o The control inputs to the buffers determine which of the four
normal inputs will communicate with the bus line.
o A 2 * 4 decoder ensures that no more than one control input is
active at any given point of time.
Memory Transfer
Most of the standard notations used for specifying operations on memory
transfer are stated below.
o The transfer of information from a memory unit to the user end is
called a Read operation.
o The transfer of new information to be stored in the memory is
called a Write operation.
o A memory word is designated by the letter M.
o We must specify the address of memory word while writing the
memory transfer operations.
 Unit-1 11

o The address register is designated by AR and the data

register by DR.
o Thus, a read operation can be stated as:
1. Read: DR ← M [AR]
o The Read statement causes a transfer of information into the data
register (DR) from the memory word (M) selected by the address
register (AR).
o And the corresponding write operation can be stated as:
1. Write: M [AR] ← R1
o The Write statement causes a transfer of information from register
R1 into the memory word (M) selected by address register (AR).

PROCESSOR ORGANIZATION
Figure below is a simplified view of a processor, indicating its connection
to the rest of the system via the system bus.
12 Functional Components of a Computer

The ALU does the actual computation or processing of data. The control
unit controls the movement of data and instructions into and out of
the processor and controls the operation of the ALU. In addition, the figure
shows a minimal internal memory, consisting of a set of storage locations,
called registers.
Figure below depicts is a slightly more detailed view of the processor.

The data transfer and logic control paths are indicated, including an
element labeled internal processor bus. This element is needed to transfer
data between the various registers and the ALU because the ALU in fact
operates only on data in the internal processor memory. The figure also
shows typical basic elements of the ALU. Note the similarity between the
internal structure of the computer as a whole and the internal structure of
the processor. In both cases, there is a small collection of major
elements (computer: processor, I/O, memory; processor: control unit,
ALU, registers) connected by data paths.
General Register based CPU Organization
When we are using multiple general purpose registers, instead of single
accumulator register, in the CPU Organization then this type of
organization is known as General register based CPU Organization. In this
type of organization, computer uses two or three address fields in their
instruction format. Each address field may specify a general register or a
memory word. If many CPU registers are available for heavily used
 Unit-1 13

variables and intermediate results, we can avoid memory references much

of the time, thus vastly increasing program execution speed, and reducing
program size.

Consider R1 ← R2 + R3, the following are the functions implemented

within the CPU −
MUX A Selector (SELA) − It can place R2 into bus A.
MUX B Selector (SELB) − It can place R3 into bus B.
ALU Operation Selector (OPR) − It can select the arithmetic addition
(ADD).
Decoder Destination Selector (SELD) − It can transfers the result into
R1.
The multiplexers of 3-state gates are performed with the buses. The state of
14 binary selection inputs determines the control word. The 14-bit control
word defines a micro-operation.
14 Functional Components of a Computer

The encoding of register selection fields is specified in the table.

Encoding of Register Selection Field
Binary Code SELA SELB SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
There are several micro-operations are implemented by the ALU. Few of
the operations implemented by the ALU are displayed in the table.

Encoding of ALU Operations

OPR Select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 Add A + B ADD
00101 Subtract A - B SUB
00110 Decrement A DECA
01000 ADD A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA
There are some ALU micro-operations are shown in the table.
 Unit-1 15

ALU Micro-Operations
Micro- SELA SELB SELD OPR Control Word
operation
R1 ← R2 – R2 R3 R1 SUB 010 011 001 00101
R3
R4 ← R4 ∨ R4 R5 R4 OR 100 101 100 01010
R5
R6 ← R6 + - R6 R1 INCA 110 000 110 00001
R1
R7 ← R1 R1 - R7 TSFA 001 000 111 00000
Output ← R2 R2 – None TSFA 010 000 000 00000
Output ← Input - None TSFA 000 000 000 00000
Input
R4 ← shl R4 R4 - R4 SHLA 100 000 100 11000
R5 ← 0 R5 R5 R5 XOR 101 101 101 01100

The advantages of General register based CPU organization –

 Efficiency of CPU increases as there are large numbers of registers
are used in this organization.
 Less memory space is used to store the program since the
instructions are written in compact way.
The disadvantages of General register based CPU organization –
 Care should be taken to avoid unnecessary usage of registers. Thus,
compilers need to be more intelligent in this aspect.
 Since large number of registers is used, thus extra cost is required in
this organization.
Stack based CPU Organization
Stack is also known as the Last in First out (LIFO) list. It is the most
important feature in the CPU. It saves data such that the element stored last
is retrieved first. A stack is a memory unit with an address register. This
register influences the address for the stack, which is known as Stack
Pointer (SP). The stack pointer continually influences the address of the
element that is located at the top of the stack.
It can insert an element into or delete an element from the stack. The
insertion operation is known as push operation and the deletion operation
16 Functional Components of a Computer

is known as pop operation. In a computer stack, these operations are

simulated by incrementing or decrementing the SP register.
Register Stack
The stack can be arranged as a set of memory words or registers. Consider
a 64-word register stack arranged as displayed in the figure. The stack
pointer register includes a binary number, which is the address of the
element present at the top of the stack. The three-element A, B, and C are
located in the stack.
The element C is at the top of the stack and the stack pointer holds the
address of C that is 3. The top element is popped from the stack through
reading memory word at address 3 and decrementing the stack pointer by
1. Then, B is at the top of the stack and the SP holds the address of B that
is 2. It can insert a new word; the stack is pushed by incrementing the stack
pointer by 1 and inserting a word in that incremented location.

The stack pointer includes 6 bits, because 26 = 64, and the SP cannot
exceed 63 (111111 in binary). After all, if 63 is incremented by 1, therefore
the result is 0(111111 + 1 = 1000000). SP holds only the six least
significant bits. If 000000 is decremented by 1 thus the result is 111111.
Therefore, when the stack is full, the one-bit register ‘FULL’ is set to 1. If
the stack is null, then the one-bit register ‘EMTY’ is set to 1. The data
register DR holds the binary information which is composed into or
readout of the stack.
 Unit-1 17

First, the SP is set to 0, EMTY is set to 1, and FULL is set to 0. Now, as

the stack is not full (FULL = 0), a new element is inserted using the push
operation.
The push operation is executed as follows −
SP←SP + 1 It can increment stack pointer
K[SP] ← DR It can write element on top of the stack
If (SP = 0) then (FULL ← 1) Check if stack is full
EMTY ← 0 Mark the stack not empty

The stack pointer is incremented by 1 and the address of the next higher
word is saved in the SP. The word from DR is inserted into the stack using
the memory write operation. The first element is saved at address 1 and the
final element is saved at address 0. If the stack pointer is at 0, then the
stack is full and ‘FULL’ is set to 1. This is the condition when the SP was
in location 63 and after incrementing SP, the final element is saved at
address 0. During an element is saved at address 0, there are no more
empty registers in the stack. The stack is full and the ‘EMTY’ is set to 0.
A new element is deleted from the stack if the stack is not empty (if EMTY
= 0). The pop operation includes the following sequence of micro-
operations −
DR←K[SP] It can read an element from the top of the
stack
SP ← SP – 1 It can decrement the stack pointer
If (SP = 0) then (EMTY Check if stack is empty
← 1)
FULL ← 0 Mark the stack not full

The top element from the stack is read and transfer to DR and thus the
stack pointer is decremented. If the stack pointer reaches 0, then the stack
is empty and ‘EMTY’ is set to 1. This is the condition when the element in
location 1 is read out and the SP is decremented by 1.
The advantages of Stack based CPU organization –
 Efficient computation of complex arithmetic expressions.
18 Functional Components of a Computer

 Execution of instructions is fast because operand data are stored in

consecutive memory locations.
 Length of instruction is short as they do not have address field.
The disadvantages of Stack based CPU organization –
 The size of the program increases.
Note:Stack based CPU organisation uses zero address instruction.
Addressing Modes–
The term addressing modes refers to the way in which the operand of an
instruction is specified. The addressing mode specifies a rule for
interpreting or modifying the address field of the instruction before the
operand is actually executed.
IMPORTANT TERMS
 Starting address of memory segment.
 Effective address or Offset: An offset is determined by adding
any combination of three address elements: displacement, base
and index.
 Displacement: It is an 8 bit or 16 bit immediate value given in the
instruction.
 Base: Contents of base register, BX or BP.
 Index: Content of index register SI or DI.
 Implied addressing mode:: In implied addressing the operand is
specified in the instruction itself. In this mode the data is 8 bits or
16 bits long and data is the part of instruction. Zero address
instruction is designed with implied addressing mode.

Example: CLC (used to reset Carry flag to 0)

 Immediate addressing mode (symbol #):In this mode data is
present in address field of instruction .Designed like one address
instruction format.
 Unit-1 19

 Note: Limitation in the immediate mode is that the range of

constants is restricted by size of address field.

Example: MOV AL, 35H (move the data 35H into AL register)
 Register mode: In register addressing the operand is placed in one
of 8 bit or 16 bit general purpose registers. The data is in the
register that is specified by the instruction.
Here one register reference is required to access the data.

Example: MOV AX, CX (move the contents of CX register to AX

register)
 Register Indirect mode: In this addressing the operand’s offset is
placed in any one of the registers BX,BP,SI,DI as specified in the
instruction. The effective address of the data is in the base register
or an index register that is specified by the instruction.
Here two register referencesare required to access the data.

The 8086 CPUs let you access memory indirectly through a register using
the register indirect addressing modes.
 MOV AX, [BX](move the contents of memory location s
Addressed by the register BX to the register AX)
 Auto Indexed (increment mode): Effective address of the
operand is the contents of a register specified in the instruction.
20 Functional Components of a Computer

After accessing the operand, the contents of this register are

automatically incremented to point to the next consecutive
memory location.(R1)+. Here one register reference,one memory
reference and one ALU operation is required to access the data.
Example:
 Add R1, (R2)+ // OR
 R1 = R1 +M[R2]
 R2 = R2 + d
Useful for stepping through arrays in a loop. R2 – start of array d – size of
an element
 Auto indexed ( decrement mode): Effective address of the
operand is the contents of a register specified in the instruction.
Before accessing the operand, the contents of this register are
automatically decremented to point to the previous consecutive
memory location. –(R1) Here one register reference,one memory
reference and one ALU operation is required to access the data.
Example:
 Add R1,-(R2) //OR
 R2 = R2-d
 R1 = R1 + M[R2]
Auto decrement mode is same as auto increment mode. Both can also be
used to implement a stack as push and pop. Auto increment and Auto
decrement modes are useful for implementing “Last-In-First-Out” data
structures.
 Direct addressing Mode (symbol [ ]): The operand’s offset is
given in the instruction as an 8 bit or 16 bit displacement element.
In this addressing mode the 16 bit effective address of the data is
the part of the instruction. Here only one memory reference
operation is required to access the data.

Example:ADD AL,[0301] //add the contents of offset address 0301 to AL

 Unit-1 21

 Indirect addressing Mode (symbol @ or () ):In this mode

address field of instruction contains the address of effective
address. Here two references are required. 1st reference to get
effective address. 2nd reference to access the data.
Based on the availability of Effective address, Indirect mode is of two
kind:
1. Register Indirect:In this mode effective address is in the register,
and corresponding register name will be maintained in the address
field of an instruction. Here one register reference,one memory
reference is required to access the data.
2. Memory Indirect:In this mode effective address is in the memory,
and corresponding memory address will be maintained in the
address field of an instruction. Here two memory reference is
required to access the data.
 Indexed addressing mode: The operand’s offset is the sum of the
content of an index register SI or DI and an 8 bit or 16 bit
displacement.
Example:MOV AX, [SI +05]
 Based Indexed Addressing: The operand’s offset is sum of the
content of a base register BX or BP and an index register SI or DI.
Example: ADD AX, [BX+SI]
Based on Transfer of control, addressing modes are:
 PC relative addressing mode: PC relative addressing mode is
used to implement intra segment transfer of control, In this mode
effective address is obtained by adding displacement to PC.
 EA= PC + Address field value
PC= PC + Relative value.
 Base register addressing mode: Base register addressing mode is
used to implement inter segment transfer of control. In this mode
effective address is obtained by adding base register value to
address field value.
 EA= Base register + Address field value.
 PC= Base register + Relative value.
22 Functional Components of a Computer

Note:
1. PC relative and based register both addressing modes are suitable
for program relocation at runtime.
2. Based register addressing mode is best suitable to write position
independent codes.
Advantages of Addressing Modes
1. To give programmers to facilities such as Pointers, counters for loop
controls, indexing of data and program relocation.
2. To reduce the number bits in the addressing field of the Instruction.

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