ISO15, ISO35, ISO15M, ISO35M

SLOS580H – MAY 2008 – REVISED AUGUST 2023

ISOx5 Isolated 3.3-V Half- and Full-Duplex RS-485 Transceivers

1 Features 3 Description
• Meets or exceeds TIA/EIA RS-485 requirements The ISO15 is an isolated half-duplex differential
• 1/8 unit load – Up to 256 nodes on a bus line transceiver while the ISO35 is an isolated full-
• Signaling rates up to 1 Mbps duplex differential line driver and receiver for TIA/EIA
• Thermal shutdown protection 485/422 applications. The ISO15M and ISO35M have
• Low bus capacitance – 16 pF (typical) extended ambient temperature ratings of –55°C to
• 50 kV/μs typical transient immunity 125°C while the ISO15 and ISO35 are specified over
• Fail-safe receiver for bus open, short, idle –40°C to 85°C.
• 3.3-V inputs are 5-V tolerant
These devices are ideal for long transmission lines
• Safety and regulatory approvals
because the ground loop is broken to allow for a much
– 4000-VPK VIOTM, 560-VPK VIORM per DIN EN larger common-mode voltage range. The symmetrical
IEC 60747-17 (VDE 0884-17) barrier of the device is tested to provide isolatlion of
– 2500 VRMS isolation rating per UL 1577 4000 VPK per VDE and 2500 VRMS per UL and CSA
– 2500 VRMS isolation rating per CSA 62368-1. between the bus-line transceiver and the logic-level
2 Applications interface.
• Security systems Any cabled I/O can be subjected to electrical
• Chemical production noise transients from various sources. These noise
• Factory automation transients can cause damage to the transceiver
• Motor and motion control and/or nearby sensitive circuitry if they are of
• HVAC and building automation networks sufficient magnitude and duration. These isolated
• Networked security stations devices can significantly increase protection and
reduce the risk of damage to expensive control
circuits.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
ISO15
SOIC (16) 10.30 mm × 7.50 mm
ISO35

(1) For all available packages, see the orderable addendum at

the end of the data sheet.
ISO15x ISO35x
GALVANIC ISOLATION

GALVANIC ISOLATIO N

5
DE 14
3 A
R
6 4 13
D RE B
13
3 B DE 5
R 12 12
4 A Z
RE 6
D 11
Simplified Schematic Y

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7 Parameter Measurement Information.......................... 14
2 Applications..................................................................... 1 8 Detailed Description......................................................18
3 Description.......................................................................1 8.1 Overview................................................................... 18
4 Revision History.............................................................. 2 8.2 Functional Block Diagrams....................................... 18
5 Pin Configuration and Functions...................................4 8.3 Device Functional Modes..........................................18
6 Specifications.................................................................. 5 9 Application and Implementation.................................. 22
6.1 Absolute Maximum Ratings........................................ 5 9.1 Application Information............................................. 22
6.2 ESD Ratings............................................................... 5 9.2 Typical Application.................................................... 22
6.3 Recommended Operating Conditions.........................5 10 Layout...........................................................................24
6.4 Thermal Information....................................................7 10.1 Layout Guidelines................................................... 24
6.5 Power Ratings.............................................................7 10.2 Layout Example...................................................... 25
6.6 Insulation Specifications............................................. 7 11 Device and Documentation Support..........................26
6.7 Safety-Related Certifications...................................... 8 11.1 Documentation Support.......................................... 26
6.8 Safety Limiting Values.................................................8 11.2 Receiving Notification of Documentation Updates.. 26
6.9 Electrical Characteristics: Driver................................. 9 11.3 Support Resources................................................. 26
6.10 Electrical Characteristics: Receiver.......................... 9 11.4 Trademarks............................................................. 26
6.11 Supply Current.........................................................11 11.5 Electrostatic Discharge Caution.............................. 26
6.12 Switching Characteristics: Driver............................ 12 11.6 Glossary.................................................................. 26
6.13 Switching Characteristics: Receiver........................12 13 Mechanical, Packaging, and Orderable
6.14 Insulation Characteristics Curves........................... 13 Information.................................................................... 26
6.15 Typical Characteristics............................................ 13

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (March 2015) to Revision H (August 2023) Page
• Updated the CSA standard to CSA 62368-1, Updated VDE standard to DIN EN IEC 60747-17 (VDE
0884-17)............................................................................................................................................................. 1
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Updated Thermal Characteristics, Safety Limiting Values, and Thermal Derating Curves to provide more
accurate system-level thermal calculations........................................................................................................ 7

Changes from Revision F (January 2012) to Revision G (October 2014) Page

• Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
• Changed VDE standard to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12. ................................................ 1

Changes from Revision E (April 2010) to Revision F (January 2012) Page

• Changed the FEATURES From: 4000-Vpeak 560-Vpeak VIORM per IEC....Rev 2) To: 4000-VPK VIOTM, 560-
VPKVIORM, IEC 60747-5-2 (VDE 0884, Rev 2)....................................................................................................1
• Changed Description From: The symmetrical isolation......interface. To; The symmetrical isolation barrier of
the device is tested to provide isolatlion of 4000 VPK per VDE and 2500 VRMS per UL and CSA
between ....interface........................................................................................................................................... 1
• Updated electrical and switching characteristics to match device performance.................................................9

Changes from Revision D (March 2009) to Revision E (April 2010) Page

• Added devices ISO15M and ISO35M to the data sheet.....................................................................................1
• Changed Description - From: The ISO15 and ISO35 are qualified for use from –40°C to 85°C. To: The
ISO15M and ISO35M have extended ambient temperature ratings of –55°C to 125°C while the ISO15 and
ISO35 are specified over –40°C to 85°C............................................................................................................1
• Added the Driver output pins Note for Figure 7-1 through Figure 7-4 ............................................................. 14

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• Changed the Driver output pins Note for Figure 7-5 through Figure 7-6 ......................................................... 14

Changes from Revision B (July 2008) to Revision C (December 2008) Page

• Added added IEC......Approved..........................................................................................................................1

Changes from Revision A (June 2008) to Revision B (July 2008) Page

• Changed From: 4000-Vpeak Isolation To: 4000-Vpeak Isolation, 560-Vpeak VIORM UL 1577, IEC 60747-5-2
(VDE 0884, Rev 2)............................................................................................................................................. 1
• Changed Figure 7-13, Full-Duplex Common-Mode Transient Immunity Test Circuit........................................14

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5 Pin Configuration and Functions

VCC1 1 16 VCC2 VCC1 1 16 VCC2

GND1 2 15 GND2 GND1 2 15 GND2
R 3 14 A R 3 14 NC
RE 4 13 B RE 4 13 B
DE 5 12 Z DE 5 12 A
D 6 11 Y D 6 11 NC
GND1 7 10 GND2 GND1 7 10 GND2
GND1 8 9 GND2 GND1 8 9 GND2

Figure 5-1. ISO35x DW Package Figure 5-2. ISO15x DW Package

16-Pin SOIC 16-Pin SOIC
Top View Top View

Table 5-1. Pin Functions

PIN
ISO15x ISO35x I/O DESCRIPTION
NAME
NO. NO.
I/O ISO15x: Noninverting bus input or output
A 12 14
I ISO35x: Noninverting bus input
I/O ISO15x: Inverting bus input or output
B 13 13
I ISO35x: Inverting bus input
D 6 6 I Driver input
DE 5 5 I Driver logic-high enable input
GND1 2,7,8 2,7,8 — Logic side ground; internally connected
GND2 9,10,15 9,10,15 — Bus side ground; internally connected
NC 11,14 — — Not connected internally; may be left floating
R 3 3 O Receiver output
RE 4 4 I Receiver logic-low enable
VCC1 1 1 — Logic side power supply
VCC2 16 16 — Bus side power supply
Y — 11 O Noninverting bus output
Z — 12 O Inverting bus output

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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC1 Supply voltage, side 1(2) -0.3 6 V
VCC2 Supply voltage, side 2(2) -0.3 6 V
VO Voltage at any bus I/O terminal -9 14 V
Voltage input, transient pulse, A, B, Y, and Z
Vit -50 50 V
(through 100Ω, see Figure 13)
VI Voltage input at any D, DE or RE terminal -0.5 6 V
IO Receiver output current -10 10 mA
TJ Junction temperature 150 ℃
TSTG Storage temperature -65 150 ℃

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/
V(ESD) Bus pins and GND1 ±6000 V
ESDA/JEDEC JS-001(1)
Human body model (HBM), per ANSI/
V(ESD) Bus pins and GND2 ±16000 V
ESDA/JEDEC JS-001(1)
Human body model (HBM), per ANSI/
V(ESD) All pins ±4000 V
ESDA/JEDEC JS-001(1)
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
V(ESD) ±1000 V
pins(2)

V(ESD) Machine model ANSI/ESDS5.2-1996 ±200 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN TYP MAX UNIT
VCC1 Supply Voltage, Side 1 3.15 3.3 3.6 V
VCC2 Supply Voltage, Side 2 3.15 3.3 3.6 V
VOC Common Mode voltage at any bus terminal: A or B -7 12 V
VIH High-level input voltage (D, DE, RE inputs) 2 VCC1 V
VIL Low-level input voltage (D, DE, RE inputs) 0 0.8 V
VID Differential input voltage, A with respect to B -12 12 V
RL Differential load resistance 54 60 Ω
IO Output current, Driver -60 60 mA
1/tUI Signaling rate ISO15x and ISO35x 1 Mbps
Operating ambient temperature (ISO15 and ISO35) -40 25 85 °C
TA
Operating ambient temperature (ISO15M and ISO35M) -55 25 125 °C

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MIN TYP MAX UNIT

Operating juntion temperature (ISO15 and ISO35) -40 150 °C
TJ
Operating junction temperature (ISO15M and ISO35M) -55 150 °C

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6.4 Thermal Information

ISO15, ISO35
THERMAL METRIC(1) DW (SOIC) UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 79.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 39.7 °C/W
RθJB Junction-to-board thermal resistance 44.6 °C/W
ψJT Junction-to-top characterization parameter 11.8 °C/W
ψJB Junction-to-board characterization parameter 44 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC1 = VCC2 = 3.6 V, TJ = 150°C, CL =
PD Maximum power dissipation (both sides) 15 pF, Input a 0.5 MHz 50% duty cycle 220 mW
square wave

6.6 Insulation Specifications

VALUE
PARAMETER TEST CONDITIONS UNIT
DW-16
CLR External clearance(1) Shortest terminal-to-terminal distance through air 8 mm
Shortest terminal-to-terminal distance across the
CPG External creepage(1) 8 mm
package surface
DTI Distance through the insulation Minimum internal gap (internal clearance) 8 um
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 >400 V
Material group According to IEC 60664-1 II
Rated mains voltage ≤ 150 VRMS I-IV
Overvoltage category per IEC 60664-1
Rated mains voltage ≤ 300 VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17) (2)

VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 560 VPK
VTEST = VIOTM,
t = 60 s (qualification);
VIOTM Maximum transient isolation voltage 4000 VPK
VTEST = 1.2 x VIOTM,
t= 1 s (100% production)
Method b; At routine test (100% production)
qpd Apparent charge(3) Vini = 1.2 x VIOTM, tini = 1 s; ≤5 pC
Vpd(m) = 1.5 x VIORM, tm = 1 s
CIO Barrier capacitance, input to output(4) VIO = 0.4 x sin (2πft), f = 1 MHz 2 pF
CI Input capacitance to ground VI = VCC/ 2 + 0.4×sin(2πft), f = 1 MHz, VCC = 3.3 V 2 pF
VIO = 500 V, TA = 25°C >1012
RIO Isolation resistance(4) Ω
VIO = 500 V, TS = 150°C >109
Pollution degree 2
Climatic Category 40/125/21
UL 1577

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VALUE
PARAMETER TEST CONDITIONS UNIT
DW-16
VTEST = VISO , t = 60 s (qualification),
VISO Maximum withstanding isolation voltage 2500 VRMS
VTEST = 1.2 x VISO , t = 1 s (100% production)

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become
equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed-circuit board are used to help increase these
specifications.
(2) This coupler is suitable for basic electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Apparent charge is electrical discharge caused by a partial discharge (pd).
(4) All pins on each side of the barrier tied together creating a two-terminal device.

6.7 Safety-Related Certifications

VDE CSA UL
Certified according to DIN EN IEC 60747-17 Certified according to IEC 60950-1 and IEC Certified according to UL 1577 Component
(VDE 0884-17) 62368-1 Recognition Program
Basic insulation, 2500 VRMS Isolation rating,
4000 VPK Maximum transient isolation Reinforced insulation per CSA 60950-1 and
voltage, IEC 60950-1 148VRMS working voltage; Single protection, 2500 VRMS
560 VPK Maximum repetitive peak isolation Basic insulation per CSA 62368-1 and IEC
voltage 62368-1 300VRMS working voltage
Certificate number: 40047657 Master contract number: 220991 File number: E181974

6.8 Safety Limiting Values

Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DW-16 PACKAGE
RθJA = 79.6°C/W, VI = 3.6 V, TJ = 150°C,
IS Safety input, output, or supply current 436 mA
TA = 25°C.
TS Maximum safety temperature 150 °C

(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.

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6.9 Electrical Characteristics: Driver

All typical specs are at VCC1=3.3V, VCC2=5V, TA=27°C, (Min/Max specs are over recommended operating conditions unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IO = 0 mA, no load
2.5 VCC2 V

RL = 54 Ω, See Figure 3
1.5 2 V
Driver differential-output voltage
|VOD|
magnitude RL = 100 Ω (RS-422), See Figure 3
2 2.3 V

Vtest from –7 V to +12 V, See Figure 4

1.5 V

Change in differential output voltage

Δ|VOD| See Figure 3 and Figure 4 –200 200 mV
between two states
VOC Common-mode output voltage See Figure 5 1 2.6 3 V
change in steady-state common-mode
ΔVOC(SS) See Figure 5 –100 100 mV
output voltage between two states
Peak-to-peak common-mode output
VOC(PP) See Figure 5 0.5 V
voltage
D, DE, VI at 0 V or VCC1
II Input current –10 10 µA

ISO15 See receiver input current

ISO35 VY or VZ = 12 V 90 µA
IOZ High-impedance state output current ISO35 VY or VZ = 12 V, VCC = 0 90 µA
ISO35 VY or VZ = –7 V -10 µA
ISO35 VY or VZ = –7 V, VCC = 0 -10 µA
VA or VB at –7 V
–250 250 mA
IOS Short-circuit output current
VA or VBat 12 V
–250 250 mA

VI = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V

COD Differential output capacitance 16 pF

VI = VCC or 0 V, See Figure 14 and Figure 15

CMTI Common-mode transient immunity 25 50 kV/µs

6.10 Electrical Characteristics: Receiver

All typical specs are at VCC1=3.3V, VCC2=5V, TA=27°C, (Min/Max specs are over recommended operating conditions unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IO = –8 mA
VIT+ Positive-going input threshold voltage –20 mV

Negative-going input threshold IO = 8 mA

VIT– –200 mV
voltage
Vhys Input hysteresis (VIT+ – VIT–) 50 mV
VID = 200mV, IO = -8mA 2.4 V
VO Output Voltage
VID = –200mV, IO = 8mA 0.4 V
Output high-impedance current on VI = –7 to 12 V, Other input = 0 V
IOZ –1 1 µA
the R pin
-55℃ ≤ TA ≤ 85℃ VA or VB = 12 V 50 100 µA
-55℃ ≤ TA ≤ 85℃ VA or VB = 12 V, VCC = 0 50 100 µA

IA or IB 85℃ ≤ TA ≤ 125℃ VA or VB = 12 V 200 µA

Bus input current
85℃ ≤ TA ≤ 125℃ VA or VB = 12 V, VCC = 0 200 µA
-55℃ ≤ TA ≤ 125℃ VA or VB = –7 V -100 -40 µA
-55℃ ≤ TA ≤ 125℃ VA or VB = –7 V, VCC = 0 -100 -30 µA
IIH VIH = 2 V
High-level input current, RE -10 µA

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All typical specs are at VCC1=3.3V, VCC2=5V, TA=27°C, (Min/Max specs are over recommended operating conditions unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIL VIL = 0.8 V
Low-level input current, RE -10 µA

RID Differential input resistance A, B 48 kohm

VI = 0.4 sin (4E6πt) + 0.5V, DE at 0 V
CID Differential input capacitance 16 pF

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6.11 Supply Current

Bus loaded or unloaded (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRIVER ENABLED, RECEIVER DISABLED
ICC1 ISO35x and ISO15x: RE at 0 V or VCC, DE at 0 V, No load (driver disabled) 8 mA
ICC1 ISO35x and ISO15x: RE at 0 V or VCC, DE at VCC, No load (driver enabled) 8 mA
ICC2 ISO35x and ISO15x: RE at 0 V or VCC, DE at 0 V, No load (driver disabled) 15 mA
ICC2 ISO35x and ISO15x: RE at 0 V or VCC, DE at VCC, No Load (driver enabled) 19 mA

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6.12 Switching Characteristics: Driver

All typical specs are at VCC1=3.3V, VCC2= 3.3V, TA=27°C, (Min/Max specs are over recommended operating conditions
unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
500-kbps DEVICES
tr, tf Differential output rise time and fall time ISO15M and ISO35M 120 180 350 ns
tPHZ Propagation delay, high-level-to-high-
See Figure 7 205 ns
impedance output
tPLZ Propagation delay, low-level to high-
See Figure 8 330 ns
impedance output
tPZL Propagation delay, standby-to-low-level
See Figure 8 530 ns
output
tPHL, tPLH Propagation delay See Figure 6 340 ns
Pulse skew (|tPHL – tPLH|)
tsk(p) See Figure 6 6 ns

tr, tf Differential output rise time and fall time ISO15 and ISO35 120 180 300 ns
tPZH Propagation delay, high-impedance-to-
See Figure 7 530 ns
high-level output

6.13 Switching Characteristics: Receiver

All typical specs are at VCC1=3.3V, VCC2= 3.3V, TA=27°C, (Min/Max specs are over recommended operating conditions
unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
500-kbps DEVICES
tPHL, tPLH Propagation delay See Figure 10 100 ns
Pulse skew (|tPHL – tPLH|)
tsk(p) ISO15 and ISO35 13 ns

Pulse skew (|tPHL – tPLH|)

tsk(p) ISO15M and ISO35M 18 ns

tr, tf Differential output rise time and fall time ISO15 and ISO35 2 4 ns
tr, tf Differential output rise time and fall time ISO15M and ISO35M 2 6 ns
Propagation delay, high-impedance-to-
tPHZ, tPLZ high-level output, Propagation delay, DE at 0 V, See Figure 11 and Figure 12 13 25 ns
high-impedance-to-low-level output
Propagation delay, high-level-to-high-
tPZH, tPZL impedance output, Propagation delay, DE at 0 V, See Figure 11 and Figure 12 13 25 ns
low-level to high-impedance output

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6.14 Insulation Characteristics Curves

500
VCC1 = VCC2 = 3.6 V

Safety Limiting Current (mA)

400

300

200

100

0
0 50 100 150 200
Case Temperature (°C)

Figure 6-1. Thermal Derating Curve for Safety Limiting Power for DW-16 Package

6.15 Typical Characteristics

70 35
ICC1 (3.3V) ICC1 (3.3V)
60 ICC2 (3.3V) 30 ICC2 (3.3V)

50 25
Supply Current (mA)

Supply Current (mA)

40 20

30 15

20 10

10 5

0 0
0 200 400 600 800 1000 0 200 400 600 800 1000
Data Rate (kbps) Data Rate (kbps)
Figure 6-2. ISOx5 Supply Current vs Data Rate Figure 6-3. ISOx5 Supply Current vs Data Rate
With Load With No Load

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7 Parameter Measurement Information

VCC1 VCC2
IOA
DE
A
DE 375 W
0 or II A
VCC1 VOD
D B D +
0 or 3 V B VOD 60 W
IOB - -7 V to 12 V
GND1 GND2
VI

VOB VOA 375 W

GND2
GND1 GND2
Figure 7-1. Driver VOD Test and Current Definitions
Figure 7-2. Driver VOD With Common-Mode
Loading Test Circuit

VCC1
IOA 27 W
DE
A A VA
II
Input VOD B VB
D B

27 W VOC VOC(SS)
GND1 GND2 IOB VOC(PP)
VI

VOB VOA VOC

GND1 GND2

Figure 7-3. Test Circuit and Waveform Definitions for the Driver Common-Mode Output Voltage

3V
VCC1 DE
50% 50%
A VI
VOD
D tPHL
RL = 54 W CL = 50 pF tPLH
VOD(H)
Input B ±1% ±20% 90% 90%
Generator VI 50% 50%
50 W VOD
10% 10%
GND1 tr tf VOD(L)

Generator: PRR = 500 kHz, 50% duty CL includes fixture and

cycle, tr <6ns, tf <6ns, ZO = 50 W Instrumentation Capacitance

Figure 7-4. Driver Switching Test Circuit and Voltage Waveforms

Note
Driver output pins are A and B for the ISO15 (see Figure 7-1 through Figure 7-4). These correspond to
ISO35 pins Y and Z

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A
S1 VO
D 3V
3V
VI 50% 50%
B
DE RL = 110 W 0V
CL = 50 pF ±20% ±20% tPZH
VOH
Input 90%
CL includes fixture and
Generator 50 W 50%
Instrumentation VO
capacitance tPHZ 0V

Figure 7-5. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms

3V

RL = 110W
A 3V
±1%
D S1 VI 50% 50%
0V VO
0V
B tPZL tPLZ
DE 5V
VO
CL = 50 pF ±20% 50%
Input 10%
VI 50 W VOL
Generator

GND1 GND2
Generator: PRR = 500 kHz, 50% duty cycle, CL includes fixture and
tr <6ns, tf <6ns, ZO = 50W Instrumentation capacitance

Figure 7-6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveform

Note
Driver output pins are A and B for the ISO15 (see Figure 7-5 through Figure 7-6). These correspond to
ISO35 pins Y and Z

IA A
IO
R
VA V
ID
B
VIC VO
VA+ V B VB IB
2

Figure 7-7. Receiver Voltage and Current Definitions

3V
A
VI 50% 50%
Input R VO
0V
VI 50 W tPLH tPHL
Generator CL = 15 pF VOH
B 90%
1.5 V RE ±20% 50% 50%
VO
10%
tf VOL
tr
Generator: PRR = 500 kHz, 50% duty cycle, CL includes fixture and
tr <6ns, tf <6ns, ZO = 50 W instrumentation capacitance

Figure 7-8. Receiver Switching Test Circuit and Waveforms

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VCC
1.5 V A 3V
R VO 1 kW ±1% VI
S1 50% 50%
CL = 15 pF ±20% 0V
0V B
RE tPZH tPHZ
CL includes fixture VOH
and instrumentation 90%
capacitance VO 50%
Input ˜˜ 0V
VI 50 W
Generator
Generator: PRR = 500 kHz, 50% duty cycle,
tr <6ns, tf <6ns, ZO = 50W

Figure 7-9. Receiver Enable Test Circuit and Waveforms, Data Output High

VCC
0V A
R VO 1 kW ±1% 3V
S1
VI 50% 50%
B CL = 15 pF ±20%
1.5 V RE CL includes fixture 0V
and instrumentation tPZL tPLZ
capacitance VCC
Input VO 50%
VI 50 W 10%
Generator VOL
Generator: PRR = 500 kHz, 50% duty cycle,
tr <6ns, tf <6ns, ZO = 50W

Figure 7-10. Receiver Enable Test Circuit and Waveforms, Data Output Low

0V
RE
A
R
B
Pulse Generator 100 W ±1%
15 ms duration
1% duty cycle +
- D
tr, tf <100 ns

DE
3V
Note: This test is conducted to test survivability only.
Data stability at the R output is not specified.

Figure 7-11. Transient Overvoltage Test Circuit

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2V C = 0.1 mF VCC1 VCC2

±1%
C = 0.1 mF ±1%
DE
GND 1 D
S1 54 W VOH or VOL

0.8 V
R

RE
VOH or VOL 1 kW
GND 1 GND 2
CL = 15 pF
(includes probe and
jig capacitance)

V TEST

Figure 7-12. Half-Duplex Common-Mode Transient Immunity Test Circuit

2V C = 0.1 mF V VCC2
±1% CC1

Y C = 0.1 mF ±1%
DE
GND1
D VOH or VOL
S1 54 W
Z

A
1.5 V or 0V
0.8 V
R
54 W
RE
VOH or VOL 1 kW B
0 V or 1.5 V
GND 1 GND 2
CL = 15 pF
(includes probe and
jig capacitance)

V TEST

Figure 7-13. Full-Duplex Common-Mode Transient Immunity Test Circuit

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8 Detailed Description
8.1 Overview
The ISO15 and ISO15M are isolated half-duplex differential line drivers and receivers while the ISO35 and
ISO35M are isolated full-duplex differential line transceivers for TIA/EIA 485/422 applications. They are rated
to provide galvanic isolation of up to 2500 Vrms for 60 sec as per the standard. They have active-high driver
enables and active-low receiver enables to control the data flow.
When the driver enable pin, DE, is logic high, the differential outputs Y and Z follow the logic states at data
input D. A logic high at D causes Y to turn high and Z to turn low. In this case the differential output voltage
defined as VOD = V(Y) – V(Z) is positive. When D is low, the output states reverse, Z turns high, Y becomes low,
and VOD is negative. When DE is low, both outputs turn high-impedance. In this condition the logic state at D
is irrelevant. The DE pin has an internal pulldown resistor to ground, thus when left open the driver is disabled
(high-impedance) by default. The D pin has an internal pullup resistor to VCC, thus, when left open while the
driver is enabled, output Y turns high and Z turns low.
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = V(A) – V(B) is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and less than the negative and lower than the negative input threshold, VIT– ,
the receiver output, R, turns low. If VID is between VIT+ and VIT– the output is indeterminate. When RE is logic
high or left open, the receiver output is high-impedance and the magnitude and polarity of VID are irrelevant.
Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected
from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus).
8.2 Functional Block Diagrams
ISO15x
GALVANIC ISOLATION

5
DE

6
D
13
3 B
R 12
4 A
RE

ISO35x
GALVANIC ISOLATIO N

14
3 A
R
4 13
RE B
DE 5
12
Z
6
D 11
Y

8.3 Device Functional Modes

Table 8-1. Driver Function Table(2)
INPUT ENABLE INPUT
OUTPUTS(1)
VCC1 VCC2 (D) (DE)
Y/A Z/B
PU PU H H H L
PU PU L H L H
PU PU X L Hi-Z Hi-Z
PU PU X OPEN Hi-Z Hi-Z
PU PU OPEN H H L
PD PU X X Hi-Z Hi-Z
PU PD X X Hi-Z Hi-Z

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Table 8-1. Driver Function Table(2) (continued)

INPUT ENABLE INPUT
OUTPUTS(1)
VCC1 VCC2 (D) (DE)
Y/A Z/B
PD PD X X Hi-Z Hi-Z

(1) Driver output pins are Y and Z for full-duplex devices and A & B for half-duplex devices.
(2) PU = Powered Up; PD = Powered Down; H = Logic High; L= Logic Low; X = Irrelevant, Hi-Z = High Impedance (off)

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Table 8-2. Receiver Function Table(1)

DIFFERENTIAL INPUT ENABLE OUTPUT
VCC1 VCC2
VID = (VA – VB) ( RE) (R)
PU PU –0.01 V ≤ VID L H
PU PU –0.2 V < VID < –0.01 V L ?
PU PU VID ≤ –0.2 V L L
PU PU X H Hi-Z
PU PU X OPEN Hi-Z
PU PU Open circuit L H
PU PU Short Circuit L H
PU PU Idle (terminated) bus L H
PD PU X X Hi-Z
PU PD X L H

(1) PU = Powered Up; PD = Powered Down; H = Logic High; L= Logic Low; X = Irrelevant, Hi-Z = High Impedance (off), ? = Indeterminate

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8.3.1 Device I/O Schematics

Figure 8-1. Device I/O Schematics

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

The ISO15x and ISO35x family consists of RS-485 transceivers commonly used for asynchronous data
transmissions. Full-duplex implementation requires two signal pairs (four wires), and allows each node to
transmit data on one pair while simultaneously receiving data on the other pair. For half-duplex transmission
there is only one pair which shared for both transmission and reception of data. To eliminate line reflections,
each cable end is terminated with a termination resistor, R(T), whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over
longer cable length.
9.2 Typical Application

R R R
R R R
RE A RE A RE A

DE B DE B DE B
D D D
D D D

a) Independent driver and b) Combined enable signals for c) Receiver always on

receiver enable signals use as directional control pin
Copyright © 2016, Texas Instruments Incorporated

Figure 9-1. Half-Duplex Transceiver Configurations

Y A
R D Z R(T) R(T) B R R
DE RE
Master Slave
RE DE
B Z
D R A R(T) R(T) Y D D

A B Z Y

R Slave
D

R RE DE D

Figure 9-2. Typical RS-485 Network With Full-Duplex Transceivers

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9.2.1 Design Requirements

RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
Table 9-1. Design Parameters
PARAMETER VALUE
Pullup and Pulldown Resistors 1 kΩ to 10 kΩ
Decoupling Capacitors 100 nF

9.2.2 Detailed Design Procedure

There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
shorter the cable length; and conversely, the lower the data rate, the longer the cable length. When connecting
a node to the bus, the distance between the transceiver inputs and the cable trunk, known as the stub, should
be as short as possible. Stubs present a nonterminated piece of bus line which can introduce reflections as the
length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of a stub should
be less than one-tenth of the rise time of the driver. The RS-485 standard specifies that a compliant driver must
be able to driver 32 unit loads (UL), where 1 unit load represents a load impedance of approximately 12 kΩ.
Because these devices consists of 1/8 UL transceivers, connecting up to 256 receivers to the bus is possible.
9.2.3 Application Curve

Driver Input

Driver Output

Receiver Input

Receiver Output

Figure 9-3. Typical Input and Output Waveforms

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Power Supply Recommendations

To ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501 . For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 data sheet (SLLSEA0).
10 Layout
10.1 Layout Guidelines
On-chip IEC-ESD protection is good for laboratory and portable equipment but never sufficient for EFT and
surge transients occurring in industrial environments. Therefore robust and reliable bus node design requires the
use of external transient protection devices. Because ESD and EFT transients have a wide frequency bandwidth
from approximately 3-MHz to 3-GHz, highfrequency layout techniques must be applied during PCB design. A
minimum of four layers is required to accomplish a low EMI PCB design (see Figure 10-1).
• Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power
plane and low-frequency signal layer.
• Place the protection circuitry close to the bus connector to prevent noise transients from penetrating the
board.
• Use VCC and ground planes to provide low-inductance. High-frequency currents might follow the path of
least inductance and not necessarily the path of least resistance.
• Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
• Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC-pins of transceiver, UART,
controller ICs on the board (see Figure 10-1).
• Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance (see Figure 10-1).
• Use 1-kΩ to 10-kΩ pullup and pulldown resistors for enable lines to limit noise currents in theses lines during
transient events (see Figure 10-1).
• Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up (see Figure 10-1).
• While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power and ground plane system
to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping.
Also the power and ground plane of each power system can be placed closer together, thus increasing the
high-frequency bypass capacitance significantly.

Note
For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide.

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10.2 Layout Example

High-speed traces
10 mils

Ground plane

Keep this space FR-4

40 mils free from planes, 0r ~ 4.5
traces, pads, and
vias

Power plane
10 mils

Low-speed traces

Figure 10-1. Recommended Layer Stack

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11 Device and Documentation Support

11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Digital Isolator Design Guide data sheet
• Texas Instruments, Transformer Driver for Isolated Power Supplies application report
• Texas Instruments, Isolation Gloassary application report
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

11.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 25-Jun-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

ISO15DWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ISO15 Samples

ISO35DWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ISO35 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 25-Jun-2024

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-Aug-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO15DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO15MDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO35DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
ISO35MDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-Aug-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO15DWR SOIC DW 16 2000 350.0 350.0 43.0
ISO15MDWR SOIC DW 16 2000 350.0 350.0 43.0
ISO35DWR SOIC DW 16 2000 350.0 350.0 43.0
ISO35MDWR SOIC DW 16 2000 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-Aug-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
ISO15DW DW SOIC 16 40 506.98 12.7 4826 6.6
ISO15DWG4 DW SOIC 16 40 506.98 12.7 4826 6.6
ISO15MDW DW SOIC 16 40 506.98 12.7 4826 6.6
ISO35DW DW SOIC 16 40 506.98 12.7 4826 6.6
ISO35DWG4 DW SOIC 16 40 506.98 12.7 4826 6.6
ISO35MDW DW SOIC 16 40 506.98 12.7 4826 6.6

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
DW 16 SOIC - 2.65 mm max height
7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224780/A

www.ti.com
 PACKAGE OUTLINE
DW0016B SCALE 1.500
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
14X 1.27
16
1

10.5 2X
10.1 8.89
NOTE 3

8
9
0.51
16X
0.31
7.6
B 0.25 C A B 2.65 MAX
7.4
NOTE 4

0.33
TYP
0.10

SEE DETAIL A
0.25
GAGE PLANE

0.3
0 -8 0.1
1.27
0.40 DETAIL A
(1.4) TYPICAL

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0016B SOIC - 2.65 mm max height
SOIC

SYMM SYMM
16X (2) 16X (1.65) SEE
SEE DETAILS
DETAILS
1 1
16 16

16X (0.6) 16X (0.6)

SYMM SYMM

14X (1.27) 14X (1.27)

8 9 8 9
R0.05 TYP R0.05 TYP
(9.3) (9.75)

IPC-7351 NOMINAL HV / ISOLATION OPTION

7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0016B SOIC - 2.65 mm max height
SOIC

SYMM SYMM
16X (2) 16X (1.65)

1 1
16 16

16X (0.6) 16X (0.6)

SYMM SYMM

14X (1.27) 14X (1.27)

8 9 8 9

R0.05 TYP R0.05 TYP

(9.3) (9.75)

IPC-7351 NOMINAL HV / ISOLATION OPTION

7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
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