2 - Logic Family and Logic Gates

2.1 Difference between Analog and Digital

signals, Logic levels, TTL logic family
Books referred:
1. John F. Warkerly, “Digital Design Principles
and Practices”, Pearson Education, Fifth
Edition (2018).
2. R. P. Jain, “Modern Digital Electronics”, Tata
McGraw Hill Education, Forth Edition
(2010).

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 2 - Logic Family and Logic Gates
2.2 Digital logic gates, Universal gates, Realization
using NAND and NOR gates, Boolean Algebra,
De Morgan’s Theorem.
Books referred:
1. John F. Warkerly, “Digital Design Principles and
Practices”, Pearson Education, Fifth Edition
(2018).
2. R. P. Jain, “Modern Digital Electronics”, Tata
McGraw Hill Education, Forth Edition (2010).

2
 Difference between Analog and Digital
signals
An analog signal is a time varying signal that can take
on any value across a continuous range of voltage,
current or any other metric. This type of signals are
continuous signals and can have any value.
A digital signal is modeled as taking on, at any time,
only one of two discrete values, which we call 0 and 1
(or Low and High, or False and True) The signal will
always be of one of the two levels. Here, the actual
value of the signal is immaterial as long as it is within
the specified range.
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 Logic levels & Representations
Two different representations of digital signals are
shown in figure below. In each case there are two
discrete levels.

(a) Positive logic (b) Negative logic 4/52

 Boolean Algebra
In the middle of 19th century, an English
mathematician George Boole developed rules for
manipulations of binary variables, known as
Boolean algebra. This is the basis of all digital systems
like computers, calculators, etc.
Binary variables can be represented by a letter symbol
such as A, B, X, Y, …. The variable can have only one
of the two possible values at any time, i.e. 0 or 1.

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 Complement, Prime operator
A logic circuit whose output signal level is the
opposite (or complement ) of its input signal level is
called an inverter. We use a prime ( ꞌ ) to denote an
inverter’s function. If a variable X denotes an
inverter’s input signal, then Xꞌ denotes the value of a
signal on the inverter’s output. This notation is
formally specified in the second pair of axioms
(A2) If X = 0, then X′ = 1 (A2′) If X = 1 then X′ = 0
(~, !, )

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 Algebraic operator, expression

The output of an inverter with input signal X may have

an arbitrary signal name, say Y. However,
algebraically we write Y = A′ to say “signal Y always
has the opposite value as signal A”. The prime ( ꞌ ) is
an Algebraic operator, and A′ is an expression, which
can be read as “A prime” or “NOT A”. 7
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 Logical Multiplication, dot · ()

The function of a two input AND gate is sometimes

called logical multiplication and is symbolized
algebraically by a multiplication dot (·). An AND gate
with inputs A and B has an output signal whose value
is A · B.
(&, Λ conjunction) 9
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 Logical Addition, plus (+)

The function of a two input OR gate is sometimes

called logical addition and is symbolized algebraically
by a plus sign (+). An OR gate with inputs A and B
has an output signal whose value is A + B.
(|, V disjunction)
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NOR Gate

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XOR

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 DeMorgan’s Theorems
DeMorgan’s theorems (T13 and T13′) are probably the
most commonly used of all the theorems of switching
algebra.

(X1·X2· ··· ·Xn) ′ = X1′ + X2′ + ··· + Xn′ (T13)

(X1 + X2 + ··· + Xn)′ = X1′ ·X2′ · ··· ·Xn′ (T13′)

Theorem T13 says that an n-input AND gate whose

output is complemented is equivalent to an n-input OR
gate whose inputs are complemented. That is, the
circuits of Figure (a) and (b) are equivalent. 21
DeMorgan’s Theorems

Figure (a): AND - NOT

Figure (b): NOT – OR

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 DeMorgan’s Theorems
The output of a NAND gate for any set of inputs is the
complement of an AND gate’s output for the same
inputs, so a NAND gate can have the logic symbol in
Figure (c). However, the CMOS NAND circuit is not
designed as an AND gate followed by NOT gate; it’s
just a collection of transistors that happens to perform
the AND-NOT function. In fact, theorem T13 tells us
that the logic symbol in Figure (d) denotes the same
logic function (bubbles on the OR-gate inputs indicate
logical inversion). That is, a NAND gate may be
viewed as performing a NOT-OR function or a
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bubbled OR function.
 DeMorgan’s Theorems

Figure (c): Logic symbol for NAND gate

Figure (d): Equivalent symbol for a NAND gate

(Bubbled OR) 24
 DeMorgan’s Theorems
By observing the inputs and output of a NAND gate, it
is impossible to determine whether it has been built
internally as an AND gate followed by an inverter, as
inverters followed by an OR gate, or as a direct CMOS
realization, because all NAND circuits perform
precisely the same logic function. Although the choice
of symbol has no bearing on the functionality of a
circuit, the proper choice can make the circuit’s
function much easier to understand.

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 DeMorgan’s Theorems
A similar symbolic equivalence can be inferred from
theorem T13′. As shown in Figure (a), a NOR gate
may be realized as an OR gate followed by an inverter,
the symbol of which is as shown in Figure (b).

Figure (a): OR - NOT

Figure (b): Logic symbol for NOR gate 26

 DeMorgan’s Theorems**
Or as inverters followed by an AND gate.

Figure (c): NOT – AND

Figure (d): Equivalent symbol for a NOR gate

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(Bubbled AND)
 DeMorgan’s Theorems Proof
These theorems can be proved by first considering the
two variable case and then extending this result. From
the truth table given below we get the relations
(X·Y)′ = X′+Y′ and (X+Y)′ = X′·Y′

X Y Xʹ Y′ (X·Y)ʹ Xʹ+Yʹ (X+Y)ʹ Xʹ·Yʹ

0 0 1 1 1 1 1 1
0 1 1 0 1 1 0 0
1 0 0 1 1 1 0 0
1 1 0 0 0 0 0 0
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 DeMorgan’s Theorems Proof
The relation (X·Y)′ = X′ + Y′ can be represented as
(X1·X2)′ = X1′ + X2′ (a)
Now consider the NAND operation of 3 variables
(X1·X2·X3)′ = ((X1·X2) ·X3 )′ from T7′
= (X1·X2)′ + X3′ from (a)
= X1′ + X2′ + X3′ from (a)
The above result can be extended to any number of
variables
Hence we prove
(X1·X2· ··· ·Xn) ′ = X1′ + X2′ + ··· + Xn′ (T13)
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 DeMorgan’s Theorems Proof
The relation (X+Y)′ = X′·Y′ can be represented as
(X1 + X2)′ = X1′ · X2′ (b)
Now consider the NOR operation of 3 variables
(X1+X2+X3)′ = ((X1+X2) +X3)′ from T7
= (X1+X2)′ · X3′ from (b)
= X1′ · X2′ · X3′ from (b)
The above result can be extended to any number of
variables
Hence we prove
(X1 + X2 + ··· + Xn)′ = X1′ ·X2′ · ··· ·Xn′ (T13′)
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 DeMorgan’s Theorems
Theorems T13 and T13′ are just special cases of a
generalized DeMorgan’s theorem, T14, that applies to
an arbitrary logic expression F. By definition, the
complement of a logic expression, denoted (F)′, is an
expression whose value is the opposite of F’s for every
possible input combination. Theorem T14 is very
important because it gives us a way to manipulate and
simplify the complement of an expression.

[F(X1,X2, ··· ·Xn,+, ·)]′ = F(X1′, X2′,···Xn′, ·,+) (T14)

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 Principle of Duality
We stated all of the axioms of switching algebra in
pairs. The primed version of each axiom (e.g., A5′) is
obtained from the unprimed version (e.g., A5) by
simply swapping 0 and 1 and, if present, · and +. As a
result, we can state the following metatheorem, a
theorem about theorems:
Principle of Duality: Any theorem or identity in
switching algebra remains true if 0 and 1 are swapped
and · and + are swapped throughout.

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 Principle of Duality
Duality is important because it doubles the usefulness
of everything that you learn about switching algebra
and manipulation of switching functions. Stated more
practically, from a student’s point of view, it halves
the amount that you have to learn! For example, once
you learn how to synthesize two-stage AND-OR logic
circuits from sum-of-products expressions, you
automatically know a dual technique to synthesize
OR-AND circuits from product-of-sums expressions.

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 Assignment 6:

Digital logic gates, Universal gates, Realization using

NAND and NOR gates, Boolean algebra, De Morgan’s
Theorem.

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 Assignment 6:
1. Explain laws of Boolean algebra.
2. Design XOR and XNOR using all universal gates.
3. Prove that a dual of exclusive or is also its
complement.
4. Using Boolean algebra, prove that
AB+BC+A’C=AB+A’C.

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 Assignment 6:
5. What are universal gates? Why are they so called?
Design any one basic logic gate using only
universal gates.
i) Implement the XOR using minimum number of
universal gates
ii) Also implement AND operation using universal
gates.

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 Assignment 6:
6. State and Prove DeMorgan’s Theorem.
7. Justify NAND and NOR gates are universal gates.
8. Which of the following expressions is equivalent to
Z = [(A(AB)′)′·(B(AB)′)′]′
i) , ii) , iii) , iv)
Prove it.

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 Z = [(A(AB)′)′·(B(AB)′)′]′

• Z=(A(AB)′)′‘ + (B(AB)′)′′
• Z=(A(AB)′) + (B(AB)′)
• Z=A(A′+B′)+B(A′+B′)
• Z=AA′+AB′ +A′B+BB′
• Z=AB’+ A′B
• Where (AB)’=A’+B’
• AA′=0
• A’’=A

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