Design Guide

For DDR2 Memory Devices

Application Note
AN_CD036
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Design Guide Consumer DDR/DDR2

Design Guide
Revision History: 2008-06-06 Rev.1.00

Page Subjects(major changes since last revision)

All New Qimonda Template

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Preface
The purpose of this application note is to help designers select the proper components and design
effective layouts to maximize the success of designing with DDR2 memories. This application note
will outline the key considerations a designer should be aware of when designing a PCB for a DDR2
application. This document should answer common questions and help to assure a stable design. It is
assumed that the reader is familiar with the basic concept and features of DDR2 memory devices.

1 PCB Design Considerations

There are five major issues when designing a DDR2 based system:

1. Resistive signal termination

2. PCB signal routing requirements
3. Usage of power planes
4. Number of PCB board layers
5. Generation and supply of required reference voltages

All of these issues are critical to produce a reliable DDR2 based memory subsystem. Unfortunately,
these points are very much dependent on the application and the PCB layout, so it is difficult to give a
“one solution-fits-all” set of guidelines. The following chapters will familiarize the designer with the
most critical design and layout issues, thus leading to a stable design with sufficient margin to operate
at the required frequencies.

1.1 DDR2 Termination Considerations

In order to properly terminate a DDR2 design, please follow the attached recommendations. As
always, there is no substitute for proper simulation and testing to assure a reliable design with
excellent signal integrity.

For the DQ Bus - Qimonda does not recommend operating the DQ bus without proper
termination. A combination of controller termination and DRAM termination (using ODT) is
recommended for these signals. Simulation of the controller and the DRAM can help optimize a
solution that meets the SI needs with minimal costs and power consumption. During testing, be sure
to vary the ODT resistances to determine what combinations produce the highest signal integrity and
margin while meeting the necessary power budget. It is important to verify that the eye diagram of the
simulation and actual circuits have sufficient opening (as shown in figure 1) to assure proper
operation.

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Figure 1: Eye Diagram

The operation of the ODT (on-die termination) feature in DDR2 is controlled though the EMR
registers, specifically, EMR1. Bits A2 and A6 of the address field control the 4 combinations of ODT
resistance which includes: (1) ODT disabled (2) 75 Ohms (3) 150 Ohms and (4) 50 Ohms. For
additional information on ODT, see section 2.4 and the Qimonda data sheet. If the use of ODT is not
an optimal solution due to power consumption or other issues, consider using the OCD (Off Chip
Driver) at half-strength with no termination resistors. Another possibility is the use of the OCD at full-
strength along with a series termination resistor placed near the output of the driver. As always, SI
simulation is critical to determine the performance of any termination scheme.

For the CA (Command/Address) Bus

Level 1 – Select the normal drive strength for the device with NO TERMINATION components
added. Clearly, this is the lowest cost approach for operating a DDR2 system but results can vary
depending on a number of factors related to board design, board layout, clock rates, and many other
variables. If initial results are not acceptable, adjust the drive strength and monitor the system for
improved performance. If this approach does not provide acceptable results in simulated
environments or hardware implementations, move to level 2 termination. Be sure to evaluate
undershoot and overshoot against Qimonda specifications (attached) for simulations and during
actual operation of the system. Please pay very close attention to the overshoot specifications
including area and the peak undershoot / overshoot values.

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Level 2 - To achieve better results with additional costs – use a series termination resistor which
should be placed in series with the transmitter output. The value of this resistor is chosen based on
the impedance of the channel and should be chosen to match the characteristic impedance of the
system. Choose a resistor value to match the combined impedance of the channel. This series
resistor can be used along with the DDR2 OCD impedance selections that range from 20-40 Ohms,
depending on the settings. Bit A1 of the EMRS register controls the OCD. Setting EMRS bit A1 to 0
invokes the full strength driver setting. Similarly, setting EMRS bit A1 to 1 sets the driver to “reduced”
drive strength. Place this series termination resistor as close to the controller or the driver of CA
signals as possible. A single termination resistor placed at the transmitter side will dampen any
reflections that occur as a result of a mismatch at the receiver. The use of a series resistor eliminates
the need for termination to VTT and results in less components and lower power consumption. Be
sure to simulate this circuit for signal integrity to assure proper operation followed by a physical test of
the actual circuitry. Based on actual and simulated results at Qimonda using internally designed
modules, we have seen good results using this technique along with “tuned” driver strength for point-
to-point applications DDR2 applications.

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Level 3 – If the series termination resistor as outlined above provides insufficient signal integrity for
your design, the addition of a parallel termination resistor at the receiver can significantly improve
performance, albeit at the expense of additional components and power consumption. Place the
termination resistor (approximately 50 Ohms) in parallel with the CA signal inputs as close to the
DRAM as possible. However, if the CA bus is split, the parallel termination resistor should be placed
directly at the split-point of the bus. The remaining end of the termination resistor should be
connected to Vtt (which is nominally 0.5 * VDDQ).

For the CK Bus - Clock signals, CK and CK#, are differential. Differential signals can be
terminated by placing a 120 Ohm resistor (your values may be different) across the differential signal
lines and located as close to the receiver as possible or at the splitting point of any branches. Placing
a capacitor in parallel may help reduce induced noise.

As always, please simulate the design to assure sufficient SI before layout and construction of the
hardware. Qimonda can provide IBIS models and other technical assistance as appropriate. For
additional information on termination principles, techniques, and costs, please see the AP NOTE -
SDRAM Termination Considerations at www.Qimonda.com.

1.1.1 On-Die Termination (ODT)

The ODT feature has been added to the DDR2 on DQ, DQS and DQM lines to improve signal
integrity. For details on the usage of the On-Die termination, please refer to Chapter 2.4 and the
Qimonda Data Sheets.

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1.2 Recommended Routing Rules

Proper routing of all DDR2 signals is absolutely essential in order to achieve a stable design. If the
importance of the PCB routing is neglected, the memory subsystem may not operate at the maximum
system frequency. In order to allow the highest possible operating frequency, we strongly recommend
that the following guidelines be observed.

If signal lines need to connect to several devices on the PCB, the circuit traces should be split like a
“T” and the section after the “T-point” should be as short as possible. It is important to do the line
splitting in a symmetrical way in order to avoid interference of the signals with reflections from the
different splitting points. See figure 2 for details.

It is important to reference each signal line to the same reference plane over the entire length of the
signal path. Changes between the reference planes interrupt the current return path and deteriorates
signal integrity. Since this is not always possible, care should be taken during layout to reduce layer
changes to a minimum by staying on the same plane for as much of the signal route as possible.
Increasing the number of decoupling capacitors can help reduce the effect of current return path
issues. It is best, to add a decoupling capacitor in the immediate area where the referencing change
occurs.

1.2.1 Data Signal Routing

On a four-layer board, the data would typically be routed on the top layer only. It is important, that the
DQ-bus is referenced to the same plane over the entire length to improve the current return path. In
cases where a layer needs to be changed, the same number of vias should be used for all DQ/DQS
lines within one Byte-lane. Maintain separation from the address and control signals. Data signals are
captured at the DRAM using the data strobe signals rather than the clock, so they must maintain a
length relationship to the data strobe (DQS) path on the PCB. Differences in trace length should not
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exceed ±100 mils in order to maintain a minimal timing difference of less than 50ps. An example of
this line matching is shown in Figure 3.

DDR2 also has the option of having a data strobe complement (DQS#) signals. If the DQS# signal is
implemented, it must be routed as a differential pair with the data strobe (DQS). To achieve the
double data rate, data is captured on the rising and falling edges of the DQS or on each crossing
point of the differential signals if the DQS/DQS# signals are used. Therefore, exact trace length
matching is very important between the DQS and DQS# line. Each eight bits of data has an
associated data strobe (xDQS), optional data strobe complement (xDQS#) and a data mask bit
(xDM). Since the data is captured off the strobe, the data bits associated with the strobe must be
length-matched closely to their strobe bit. This group of data and data strobe is referred to as a byte
lane. The length matching between byte lanes is not as tight as it is within the byte lane. A singled-
ended DQS DDR2 system is not recommended. At clock rates exceeding 667MHz, single-ended
DDR2 DQS is not supported by the device.

Data Guidelines
• Typical trace width: 4 mils (depending on layer stack)
• Trace space: 12 - 15 mils
• Trace space to other signal groups: 20 - 25 mils
• Trace space between DQS differential pairs: 5 mils
• Trace space of DQS to other signals: 25 mils
• Target impedance: 60 Ω
• Max. trace length difference between DQS and DQS#: ±20 mils (< 10 ps)
• Max. trace length difference between DQS and DQ lines: ±100 mils (< 50 ps)

1.2.2 Clock Signal Routing

On a four-layer board, clock lines can be routed on the bottom layer, together with the CA-bus. Unlike
address and control signals, clocks are not typically connected to VTT or Vss. Clock signals are
differential pairs and must be routed as a differential pair and GND referenced over the entire length.
Each clock pair has to be differentially terminated. Please see also the chapter about termination
referenced aboved. Spice simulation is recommended to determine the best value for differential
termination schemes.

The clocks are used to capture the address and control signals at the DRAM, which occurs when the
input clock voltage transitions the crossing point (Vix = 0.5 × VDD). Therefore, the differential clock
lines are required to maintain an exact relationship in trace length to each other. These signals also
need to maintain a very similar length to the address and control signals that depend on accurate
clock timing for proper operation.

Most controllers have the ability to prelaunch the address and control signals. The prelaunch is used
to center the clock in the address-valid eye. This requirement is typically a result of the lighter overall
loading that is experienced by the clock lines when compared to the address and command lines that
travel from the controller to the DRAM. This situation is exacerbated when more than one SDRAM is
on the memory bus. Differentially routed signals typically have a shorter flight time than single ended
signals. This effect causes the clock signals to arrive at the DRAM in advance of the Address,
Command and Control signals. To compensate for the difference in propagation delay, it is

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considered necessary to route clock signals such that the lengths are greater than or equal to the
address, command, and control signals.

Clock Guidelines
• Typical trace width: 4 - 6 mils (depending on layer stack)
• Trace space: 5 mils
• Trace space to other signal groups: 20 - 30 mils
• Target impedance: 50 Ω
• Differential impedance: 100 - 120 Ω
• Max. trace length difference between CK and CK#: ±20 mils (< 10 ps)
• Max. trace length difference between CK/CK# and CMD lines: ±200 mils (< 100 ps)

1.2.3 Control Signal Routing

On a four-layer board, the command would typically be routed together with the address lines on the
bottom layer. They should be power referenced over the entire bus length to provide a low impedance
current return path. Maintain acceptable distances from the data path signals. Control signals are
captured at the DRAM and are referenced to the clock signals, so a carefully controlled length
relationship with respect to the cock must be maintained. Differences in trace length should not
exceed ±200 mils. The parallel termination resistors should be placed close to the chip and attached
to the VTT power island. As discussed above, the possible ranges of the termination resistors can
vary depending on the application. Simulation is recommended to determine the best overall values
for the best signal integrity.

Control Guidelines
• Typical trace width: 4 - 6 mils (depending on layer stack)
• Trace space: 12 - 15 mils verify these numbers
• Trace space to other signal groups: 20 - 25 mils.
• Target impedance: 50 Ω
• Max. trace length difference between CK/CK# and command lines: ±200 mils (<100ps)

1.3 Address Signal Routing

On a four-layer board, the address lines would typically be routed on the bottom layer. They should be
power-referenced over the entire bus length to provide a low-impedance current return path. Care
should be taken to separate the address signals from the group of data signals. Generally, all circuit
paths that connect to multiple devices should be split like a “T” and the section beyond the split
should be as short as possible and symmetrical in length to improve the overall signal integrity of the
system.

Address signals are timing referenced to the DRAM with respect to the clock signals, so they must
maintain a length relationship to the clock signals and beneath each other to minimize impedance /
path-length differences that result in timing skews. Since the flight-time difference of the signals
should be less than 100 ps, differences in trace length should not exceed ±200 mils. The parallel
termination resistors should be placed close to the chip or split point and attached to the VTT power
island. The value of the parallel resistor can vary depending on the bus topology and the layout. As

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discussed above, the possible ranges of the termination resistors can be determined from extensive
testing and simulation.

Address Routing Guidelines

• Typical trace width: 4 - 6 mils (depending on layer stack)
• Trace space: 12 - 15 mils
• Trace space to other signal groups: 20 - 25 mils
• Target impedance: 50 Ω
• Max. trace length difference between CK/CK# and address lines: ±200 mils (< 100 ps)

PCB designers should carefully simulate their layout using IBIS models of the DDR2 component and
the controller. Although an ideal layout might not be possible, it is important to make sure that thought
has been given to the points listed above. Deviating from the ideal layout might not cause a sudden
failure, but it might reduce the margin in setup and hold times, resulting in a reduced maximum
operating speed.

1.4 Power Planes

In order to create transmission lines with a well defined impedance value, power and ground planes
should be used on the PCB board. These big uninterrupted areas, which are connected either to VSS
or VDD, provide a reference plane with a low-impedance current return path and a shield against
cross-talk from other signal groups. Traces within one signal group should always be referenced to
the same voltage in order to avoid varying distortions between individual signals within one signal
group.

If possible, no signal traces should be routed on these power planes to avoid impedance jumps for
neighboring signal traces that may create reflection-induced signal distortion. Depending on the board
layout, it may be necessary to split the power planes and use one layer for VSS and VDD. If this is
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done, care should be taken in the routing of the adjacent signal lines to avoid crossings of the split in
the power plane.

Another good practice is to use copper pour and fill all empty space between the traces with an
additional power plane. This might also help, if signal traces need to be routed on a power layer. Care
needs to be taken, that all copper pour shapes are well coupled to the VSS or VDD plane, with many
vias and that no (AC wise) floating structures are created. Each shape should be connected to the
associated plane on both ends. See also Fig 4 as a example of some floating structures.

Figure 4: Marked in pink are some copper fill areas, which are insufficiently coupled to the
VSS plane (red dots)

1.5 PCB Board Layers

As mentioned above, it is typical to use a minimum of four layers in the PCB for applications using
DDR2 SDRAM. Additional layers offer simpler routing and help develop consistent transmission line
impedances, resulting in improved signal integrity, a necessary ingredient for high-speed operation. At
frequencies above DDR2-400, designers typically opt for the usage of a six layer PCB. This gives two
additional routing layers, thus simplifying the board layout and potentially reducing impedance
variations resulting from split power planes. The typical construction of multilayer PCB is shown in
Figure 5.

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Figure 5: Example of the Construction of a Typical Multi-Layer PCB

1.6 Supply and Reference Voltages

Care must be taken with the generation and distribution of the necessary power supply and
references voltages for the SDRAM. The sections below can help achieve a power distribution system
that will result in a stable memory system.

1.6.1 Generation of VREF and VTT

The best way to generate VREF is to use a simple resistor divider (using 1% accuracy components)
referenced to VDDQ. This assures an accurate VREF that tracks VDDQ over voltage and
temperature changes (see Figure 6 for additional information). Peak-to-peak AC noise on VREF may
not exceed ±2 percent VREF (DC). A global VREF distribution is recommended for these designs as
shown in Figure 6 . VREF is not required to source or sink any significant current (leakage only) thus
allowing a wide range of component values for this circuit.

The VTT voltage generator must provide sufficient current sourcing and sinking capabilities to source
and sink all of the terminated signal currents. . The signal VTT is generally very noisy, since it must be
the source and sink of the data line currents. In many cases, the generator can be developed by using
a Low-Drop-Out (LDO) regulator or a switching regulator.

During the power-up sequence, VTT should be switched on after VDD. If VTT is switched on before
VDD, the limit of VTT < VDDQ (VTT < 0.95 V for DDR2) is to prevent excessive current through the
I/O ESD devices to prevent latch up. This practice is NOT recommended. There are several
monolithic IC devices on the market, which can provide all three voltages DRAM voltages (VDDQ,
VREF, VTT).

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VREF and VTT Routing Suggestions

• Trace between decoupling cap and destination: 30 mil
• Clearance from other nets: 25 mil
• Isolate VREF and/or shield with ground
• Simplify implementation by routing VREF on the top signal trace layer
• Decouple using distributed 470 pF and 100 nF capacitors close to the regulator, controller and
SDRAM
• Use a distributed decoupling scheme

Figure 6: Tracking of Vref and Vdd

Note: Vref should tack VDDQ and VSSQ over noise, voltage and temperature

1.6.2 Separation of Supply Voltages

Internal supply voltages for the DDR2 devices (VDD, VSS), the I/O drivers (VDDQ, VSSQ) and the
DLL1 (VDDL, VSSDL), are all separated to minimize noise coupling across power supply voltages.
However, in most applications, all three voltages can be supplied from the same power plane. If
VDDQ exhibits noise caused by inefficient coupling the various voltage lines should be separated.
Typically, the VSS, VSSQ and VSSDL can share the same plane on the PCB.

1.6.3 Decoupling of the DDR2 Memory Power Supplies

In order to stabilize power supply voltages near the DRAM devices and to minimize noise spikes on
the power lines VDD and VDDQ, the power supply traces typically need to be decoupled by bypass
capacitors. Each DDR2 device should have bypassing capacitors which should be placed as close to
the power pins as possible. In addition, the reference voltage should be decoupled by placing a
capacitor as close to the VREF pin as possible.

The actual number of capacitors and the actual values of the capacitors may vary widely depending
on the application and the general noise conditions associated with the system. A larger number of
decoupling caps typically also helps to reduce Electro-Magnetic-Emissions (EMI).The ideal case
would be to use capacitors to cover the complete frequency spectrum, but such an arrangement
would require placing a large number of bypass capacitors with various values near each of the
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memory devices. This is typically not feasible due to cost and real-estate issues. Therefore, a
selection of compromised values should be chosen to provide good overall performance without
excessive cost or area penalties. A typical selection would consist of a 470 pF, 2.7nF, 10 nF, 100nF,
470 nF, and a 10uF bypass capacitor from VDD and VDDQ to GND, along with a 470 pF and 100 nF
placed from VREF to GND. This sequence of decoupling should be duplicated for each DDR2 chip
on the board. If board space or cost is a concern, a simplified array of decoupling capacitors should
include, of at least two caps (470 pF, 100 nF) should be used for each supply voltage and VRE. All
capacitors should be placed close to the device as possible and between the via and the power pin. If
placed after the power pin, the effect of the decoupling cap is strongly reduced. All capacitors should
be ceramic and should have an XR5 material rating. Package types are typically SMD 0402 or 0603.

In general, the PCB should have plenty of GND or Power layers, to allow for good HF operation.
Typically, a 6 layer PCB should have at least 3 GND/PWR layers. Some signal lines could be routed
on these layers, but this should be avoided when possible. Please review the section below on EMI
for additional information on decoupling.

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2 General Considerations

2.1 Simulations
Unfortunately, routing and termination solutions are highly dependent on the application and the PCB
layout. Therefore, it is almost impossible to provide a “one-solution-fits-all” for every DRAM design.
The only way to find the optimum termination and layout scheme is by extensive simulation that
includes the layout, PCB parasitics, stray capacitances, etc. To assist simulations, Qimonda provides
IBIS models to our customers thus providing a convenient mechanism to model signal integrity work.
These models provide data for:
• Pull-up and pull-down curves
• Rise/fall waveforms
• ESD diode protection
• Package parasitic
More information is available at:
http://www.eigroup.org/IBIS/Default.htm

2.2 Unused Signal Pins

Memory chips typically have a small number of pins which are not used in the application. These can
be either classical NC-pins or other functional pins. Unused pins are usually a result of a feature that
is not implemented on all DRAM packages.

NC Pins
DDR2 memory chips typically have a number of NC pins (no connect). Qimonda components with NC
pins are not connected to anything inside the device. They can be left floating or can be strapped to
GND or any other voltage.

If NC pins on the SDRAM are address pins for the next higher density component, it is also possible
to connect these pins to the DRAM controller’s appropriate address output pins. This may avoid a
later PCB board redesign in case of memory upgrades.

2.2.1 DQS#
If DQS is used as a single ended signal, the unused DQS# of Qimonda parts can be left unconnected.
It does not need a pull-down resistor. The JEDEC specification says: “Note, that when differential data
strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS
through a 20 Ω to 10 kΩ resistor to insure proper operation.”

Qimonda does not recommend using a single-ended DQS signal.

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2.2.2 UDM/LDM
If the data mask is not used (always reading or writing 16 bit), the DM pins can simply be connected
to ground. A pull-down resistor can range from 0 Ω to 10 kΩ.

2.3 Electromagnetic Interference (EMI) Considerations for

DDR2
A simple piece of wire can form an antenna. Emission is proportional to a number of factors, including
the current through the wire. If a piece of wire is leading from a voltage source to a load and a second
piece of wire is leading back to the voltage source (GND) then radiation is minimized once the two
wires are very close together because the magnetic fields of forward and return current cancel each
other. As the area between the wires becomes larger, the amount of radiated energy becomes larger.

When considering the choice of packages, keep in mind that some packages have a longer distance
from a signal pin to a return path for source or sink current. Such is not the case with a BGA package.
As described above, a larger area between a current path translates to more emissions. This is the
reason that SMT technology is preferred over TSOP packages if lower overall EMI is desired. As
DDR2 devices are manufactured using BGA packages only, unintended EMI is generally a result of
systems-level design issues.

Bypassing is also very effective tool for eliminating or minimizing EMI issues. While bypass capacitors
provide a low impedance path to ground for high frequency energy, the larger values of bypass
capacitance near the DRAM devices serve as local charge storage devices. When a DRAM demands
a large and immediate increase in supply current, the local bypass capacitor can supply a portion of
this current to the device. As the capacitor is supplying local current to the DRAM, power supply
currents are replacing the charge in the capacitor. Without bypass capacitors, the transient current
demands of the DRAM devices can only be supplied from the power supply. These transient current
spikes may travel paths that are conducive to radiation, thus aggravating EMI issues. As the charts
below show, the impedance of the power path to the device is irregular as a function of frequency.
Flattening this curve with proper decoupling and simulation will improve the EMI properties of the
system.

No Bypass Cap.: Flatten impedance

high impedance achieved with
can cause EMI sufficient decoupling
problems

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2.4 On-Die Termination (ODT)

On-Die Termination (ODT) is a new feature implemented on DDR2 components. ODT allows the
memory controller to activate/deactivate an internal DRAM parallel-termination resistor which can also
be controlled by the ODT-pin of the DDR2 chip. ODT is available on all DQ, DQS and DM pins. The
value of the parallel termination resistor RTT is adjustable by altering EMRS(1) (extended mode
register S) setting. The termination resistance can be selected from the following values: 50 Ω, 75 Ω
or 150 Ω. For additional understanding on the impact of these termination resistors, please refer to the
examples shown in Figure 7.

ODT should be turned on during a DATA-WRITE to the DRAM. During DATA-READ from the DRAM,
the ODT on the controller (if available) should be turned on and the ODT of the DRAM should be
turned off. Figure 8 demonstrates the different termination schemes during READ and WRITE with
ODT.

The needed time delay between asserting ODT-High and the actual switching of the termination
resistors (tAOND and TAOFD) should be programmed into the memory controller. An example for
ODT-timing is shown in Figure 9.

If the ODT feature is used, no external termination on the SDRAM side should be necessary. If the
memory controller also has ODT, there is also no requirement for external termination on the
controller side. If no ODT on the controller is available, some form of external termination is likely to
be necessary at the controller. As always, there is no substitute for system simulation to optimize the
system’s signal integrity.

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ODT Control during Self Refresh Mode

During Self refresh mode, the On-Die-Termination is disabled and the ODT pin is ignored, regardless
of the register settings in the EMRS. Since a memory system in self refresh can not read or write
data, disabling of the ODT does not degrade system performance and it allows the DDR2 chip to
minimize power consumption.

Note: The screen shots are taken from a DDR2-533 memory system. The influence of different valuesfor RTT is best seen in
the amplitude of the signal and the overshoot of the postamble. The application under test used a setting of RTT = 75
Ω. Violet = DQS; Green = DQ; Blue = ODT.

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Note: The blue line shows the logic level on the ODT pin of the DDR2 memory chip. It is set to high approximately 20 ns
before the actual data are sent on the DQ line (green). The violet trace shows the differential signal of the DQS line.

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Conclusion
The new features added to the DDR2 architecture enable the DDR2 SDRAM to operate at
frequencies as high as 800MHz. These new features, along with a properly designed PCB, will
improve signal integrity of a design while increasing overall data transfer rates. Depending on the
design, termination costs can be reduced along with a possible reduction of overall power
consumption resulting from the use of built-in programmable termination devices.

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Appendix A – High Level Comparison of DDR Vs. DDR2

With the introduction of DDR2 SDRAM, operating frequencies are increased up to 400 MHz clock rate. To achieve these
higher data rates, it was necessary to include some new features into the DDR2 memory. A summary or the DDR2 features
in comparison to DDR SDRAM is given in.

Table 1 Overview of the Features of DDR2 Memory

Feature/Option DDR DDR2

Data transfer rate 266, 333, 400 MHz 400, 533, 667, 800 MHz
Package TSOP, FBGA FBGA only
Operating voltage 2.5 V 1.8 V
I/O Voltage 2.5 V 1.8 V
I/O Type SSTL_2 SSTL_18
Densities 64 MB - 1 GB 256 MB - 4 GB
Internal banks 4 4 and 8
Prefetch (Min. burst length) 2 4
CAS latency (CL) 2, 2.5, 3 clocks 3, 4, 5 clocks
Additive latency (AL) – 0, 1, 2, 3, 4 clocks
READ latency (RL) RL = CL RL = AL + CL
WRITE latency (WL) 1 clock fixed WL = RL - 1
I/O width x4, x8, x16 x4, x8, x16
Output calibration – OCD
Data strobes bidirectional strobe (single ended) bidirectional strobe (single ended
or differential) with RDQS
On-Die termination – selectable
Burst length 2, 4, 8 4, 8

Rev. 1.0 , 2008-06-06 21

06062008-XXXX-YYYY
 Application Note AN_CD035

Edition 2008-05
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2008.
All Rights Reserved.

LEGAL DISCLAIMER
THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION OF THE
QIMONDA COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A
CERTAIN FUNCTIONALITY, CONDITION OR QUALITY OF THE QIMONDA COMPONENT. THE RECIPIENT OF THIS
APPLICATION NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION. QIMONDA
HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND (INCLUDING WITHOUT LIMITATION
WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY) WITH
RESPECT TO ANY AND ALL INFORMATION GIVEN IN THIS APPLICATION NOTE.

Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.

Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.

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