Aalborg Universitet

A Multilevel Inverter With Minimized Components Featuring Self-Balancing and

Boosting Capabilities for PV Applications

Jahan, Hossein Khoun; Abapour, Mehdi; Zare, Kazem; Hosseini, Seyed Hossein; Blaabjerg,
Frede; Yang, Yongheng
Published in:
IEEE Journal of Emerging and Selected Topics in Power Electronics

DOI (link to publication from Publisher):

10.1109/JESTPE.2019.2922415

Publication date:
2023

Document Version
Accepted author manuscript, peer reviewed version

Link to publication from Aalborg University

Citation for published version (APA):

Jahan, H. K., Abapour, M., Zare, K., Hosseini, S. H., Blaabjerg, F., & Yang, Y. (2023). A Multilevel Inverter With
Minimized Components Featuring Self-Balancing and Boosting Capabilities for PV Applications. IEEE Journal of
Emerging and Selected Topics in Power Electronics, 11(1), 1169 - 1178. Article 8735794. Advance online
publication. https://doi.org/10.1109/JESTPE.2019.2922415

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2922415, IEEE
Journal of Emerging and Selected Topics in Power Electronics

A Multilevel Inverter with Minimized Components

Featuring Self-balancing and Boosting Capabilities
for PV Applications
Hossein Khoun jahan1, Mehdi Abapour1, Kazem Zare1, Seyed Hossein Hosseini1,4, Frede Blaabjerg2, and Yongheng Yang3

1- Electrical and Computer Engineering Faculty, University of Tabriz

2-Aalborg University, Energy Technology Faculty, Fellow, IEEE
3-Aalborg University, Energy Technology Department
4- Engineering Faculty, Near East University, Nicosia 99138, North Cyprus, Mersin 10, Turkey

Abstract—Cascaded H-bridge Multilevel Inverter (CMI) hence, they are justified in the application where the
attracts much attention as a versatile converter in photovoltaic galvanic isolation is required. In the HFT-CMIs, the size of
(PV) applications. Requiring several isolated dc sources and the transformer is deservedly reduced. The high-frequency
many switches are the main demerits of the CMI. In PV link and/or transformer in this inverter are used to develop
applications with the CMI, PV modules can be used as the
several isolated dc sources. The main advantage of the HFT-
isolated dc sources, which, however, may contribute to inter-
module and grid leakage currents due to the module stray CMIs is also the ability to provide a galvanic isolation. On
capacitors. In this context, a switched-capacitor-based the contrary, the high-frequency link increases the power
cascaded half-bridge multilevel inverter is proposed in this losses. Compared to transformers, capacitors are cheap and
paper to address the above issues. The proposed topology only compact, and thus, the SC-CMIs are more compact in size
requires one dc source, and it achieves the minimum number and lower in cost. Nevertheless, the lack of the galvanic
of switches, spontaneous capacitor charging, voltage boosting, isolation and the inrush current of the capacitors are the
and continuous input current. The inter-module leakage main shortcomings of the SC-CMIs. The inrush current can
currents can also be eliminated in the proposed topology. The increase the failure rate of the capacitors and decrease the
feasibility and effectiveness of the proposed topology are
reliability of the SC-CMIs. In the topologies in [16] and
validated through simulations and experimental tests.
Index Terms—Switched capacitor module, Component-count [17], the inrush current of the capacitors is mitigated
reduction, Multilevel inverter, Photovoltaic applications, through a charging inductor. In this case, the dc source is
Leakage currents. not used to directly supply the load current. Alternatively,
I. INTRODUCTION the dc-source charges the capacitors through the charging
inductor and then the capacitors provide the load current.
The integration of distributed generation systems into
In the CMI with PV applications, the dc-sources are
the modern power grid along with the fast advancement of
replaced with PV modules; however, this is not an easy task,
power electronic devices necessitates employing versatile
as the inter-module leakage currents may appear [18]. As
and expedient converters. Multilevel inverters (MIs) are of
shown in Fig. 1, the leakage currents (ICM) in the CMI for
importance in modern power systems that can fulfil many
PV applications may be generated due to the common-mode
requirements. These inverters employ components of low
voltage and differential-mode voltage variations across the
power rating, produce staircase voltages of high quality, and
stray capacitor of the PV modules (e.g., Cpv1, Cpv2, Cpv3).
mitigate the electromagnetic interference (EMI) to a large
extent [1], [2]. Nevertheless, using extra components makes The voltage across the stray capacitors and the associated
them bulky, expensive, and complicated with low reliability. leakage currents for a three-cell CMI are, respectively,
As a result, many efforts have been devoted into reducing obtained by.
the component count, while improving the performances V DM i  S iV pvk
S  0,1 (1)
[3], [4].  i
Among the multilevel topologies, the CMI stands out i  1, 2, 3, 4, 5, 6
k  1, 2, 3
due to its modular structure, possibility of using low voltage
dV Cpv k
rating devices, and flexibility to develop high magnitude I CM k  C pv k (2)
voltages. The main drawback of these types of inverters is dt
that many isolated dc sources are required, increasing the where VDMi, Si, Vpvk, Cpvk, ICMk and VCpvk are differential mode
system complexity and cost. Thus, several topologies are voltage, switching state of the ith switch, voltage of the kth
suggested to reduce the switches and dc sources of the CMI. PV cell, stray capacitor of the kth PV cell, leakage current
In terms of the dc-source reduction, the prior-art topologies through the kth stray capacitor, and voltage across the kth
can be classified into three categories: i) low-frequency stray capacitor, respectively.
transformer-based CMIs (LFT-CMIs) [5]-[7], ii) high- The inter-module leakage currents bring power losses,
frequency transformer-based CMIs (HFT-CMIs) [8]-[10], and increase output harmonics, leading to safety and
and iii) switched-capacitor-based CMIs (SC-CMIs) [11]- electromagnetic interference (EMI) issues.
[15]. Instead of using separated dc-sources, the LFT-CMIs
adopt several low-frequency transformers at the load side.
Due to the transformers, these MIs are bulky and expensive;

2168-6777 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2922415, IEEE
Journal of Emerging and Selected Topics in Power Electronics

S1 S2 S3 S4 S5 S6 proposed topology in PV systems is then discussed in

Section IV. The performance of the proposed CMI has been
Lf validated through simulations and experimental tests in
Vpv1 PV1 Vpv2 PV2 Vpv3 PV3
Vgr id
Sections V and VI. Finally, concluding remarks are
provided in Section VII.
S1 S2 S3 S5
Cpv3 Cpv2 S 4 Cpv1 S 6
II. CONFIGURATION AND OPERATION OF THE PROPOSED
TOPOLOGY
(a) The proposed topology is synthesized with several
S1Vpv1 S2Vpv1 S3Vpv2 S4Vpv2 S5Vpv3 S6Vpv3 cascaded switched-capacitor-based half-bridge cells and
three auxiliary switches. The capacitors in the half-bridge
cells are spontaneously charged through diodes termed as
VCpv2

Lf charging diodes and a charging inductor. Fig. 2(a) shows the

VCpv1

VCpv3
Cpv1 Cpv2 Cpv3
ICM1 ICM2 ICM3 building block of the proposed topology (half-bridge cell)
and Fig. 2(b) presents the auxiliary switch configuration.
ICM_line
The general configuration of the proposed topology is
(b) depicted in Fig. 2(c). For clarity, the dc-source, the charging
Fig.1. A CMI for PV applications: (a) three-cell CMI and (b) equivalent circuits inductor and the charging diodes are highlighted in red,
illustrating the leakage currents and voltage across the stray capacitors.
while the half-bridges and auxiliary switches are in black in
Fig. 2(c).
Attempts have thus been made to tackle the inter-module
Suk Sua
leakage currents for PV applications with the CMIs. The
suggested solutions are primarily based on topology Cuk
reconfigurations, passive filters, and modulation Sma

modifications. The H5 and H6 inverters are two well-known Clk

topologies that suppress the leakage currents in grid-tied PV
applications [19], [20]. Accordingly, in order to eliminate Slk Sla
the inter-module leakage currents in the CMI, the H-bridge (a) (b)
cells were replaced with H5 and H6 cells in [21] and [22],
respectively. Additionally, dc-side and ac-side filters were
designed to limit the leakage currents in [18]. The designed
Vdc
filters can also reduce the EMI due to the inter-module
Vdc 2Vdc 2nVdc
leakage currents. In another attempt, a modified phase
disposition pulse width modulation (MPDPWM) is Vout
introduced for symmetrical CMIs to eliminate leakage
currents [23]. One effective solution to suppress the inter-
module leakage current is to use the single-source CMIs (c)
[24]. In PV systems with single-source CMIs, the PV Fig. 2. Proposed multilevel inverter topology: (a) basic module, (b)
modules are connected to a common dc link. This can lower auxiliary switch configuration, and (c) general configuration
the overall system cost and complexity. Nevertheless, the
leakage current issue in grid-tied single-source MIs should A. Building Block of the Proposed Topology
be addressed further. As it is seen in Fig. 2(a), the half-bridge cells can only
In light of the above, a new single-source SC-MI is develop positive and negative voltage values. In order to
proposed in this paper. The proposed topology features a produce all the voltage levels, at least one of the cells should
high boosting capability. In order to mitigate the inrush be able to develop zero voltages. To do so, the auxiliary
current of the capacitors, an inductor is added in the switches (Fig. 2(b)) are connected to the first cell and enable
charging current path of the capacitors, as discussed in it to develop five voltage levels (including zero voltages).
Section II. Compared to the conventional CMI, the proposed B. Charging Circuit
topology requires half the number of switches, but it uses As depicted in Fig. 2(c), the charging circuit of the
certain extra diodes to charge the capacitors. It is worth proposed topology consists of a charging inductor (Lch) and
mentioning that the capacitors in this topology are several charging diodes (two diodes in each cell). The
spontaneously charged without any active component. charging inductor is used to limit the inrush current of the
Furthermore, the proposed topology draws a smooth and capacitors. Additionaly, it acts as a fault current limiter
continuous current from the dc source, but it provides a under faulty conditions. Furthermore, in PV applications,
unidirectional power flow. The proposed topology is this inductor can be used as the input inductor of the boost
analyzed in detail in Section III in terms of voltage stresses converter (this will be discussed in Section IV).
and power losses. Considering the mentioned features, the
proposed topology can be a promising solution for PV C. Operation Principle
applications, where the continuous input current can The operation principle of the proposed topology is
facilitate the maximum power point tracking and prolong examplified on a three-cell configuration, as shown in Fig.
the life span of the storage unit. Moreover, using only one 3.
dc-source can eradicate the inter-module leakage currents
and simplify the control approach. The application of the

2168-6777 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2922415, IEEE
Journal of Emerging and Selected Topics in Power Electronics

Lch du1 Su1 du2 Su2 du3 Su3

Sua
Cu2 Cu3 Vdc
Vdc Cu1 0.5Vdc Vdc 2Vdc
a 1/2 Vdc b Vdc c 2Vdc d
0.5Vdc Vdc
Sma Cl1 1/2 Vdc Vdc 2Vdc
Cl2 Cl3 Vout

dl3 Vout
Sla d Sl1 dl2 Sl2 Sl3
l1
(b)
Fig. 3. Seventeen-level (three-cell) configuration of the proposed topology

Since the two capacitors in the first cell (Cu1 and Cl1) are Vdc
0.5Vdc 2Vdc
connected in series with the dc source, each of them is 0.5Vdc Vdc
charged to half the input dc voltage (0.5Vdc). The charging
Vout
path goes through the dc source, Lch, du1, Cu1, Cl1 and dl1, as
indicated by the dash line in Fig. 4(c). As it is seen in Fig. 3,
the first cell, which includes the ancillary switches, can (c)
develop 0.5Vdc, Vdc, 0 , -Vdc, and -0.5Vdc across the points a
and b. The two capacitors in the second cell (Cu2, Cl2) are
both charged to Vdc, and thus, this cell will only develop Vdc Vdc
0.5Vdc 2Vdc
and -Vdc across the points b and c. The capacitors in the third 0.5Vdc Vdc
cell are charged to 2Vdc, and hence, this cell can develop
2Vdc and -2Vdc across the points c and d. Figs. 4(a) to (i) Vout

further show the switching patterns to achieve the voltage

levels from zero to eight. According to the charging current (d)
flowing through the dc source, Lch, du1, Su1, Cl2, and dl2, in
Figs. 4(c), (d), (g), (h), and (i), it is understood that, while
developing certain voltage levels, Cl2 is spontaneously Vdc
0.5Vdc Vdc 2Vdc
charged to Vdc. The charging path is shown by the dash line 0.5Vdc
in Fig. 4(h). As it is seen in Figs. 4(a), (b), (e) and (f), Cu2 is
charged when developing the voltage levels in which Sl1 is Vout
turned on (when Sl1 is turned on, the charging current goes
though the dc source, Lch, du2, Cu2, Sl1, and dl1, as highlighted (e)
by the dash line in Fig. 4(a)). Moreover, Cu3 and Cl3 in the
third cell will be charged to 2Vdc. As demonstrated in Figs.
4(g), (h) and (i), the charging path for Cl3 goes though the dc Vdc
0.5Vdc Vdc 2Vdc
source, Lch, du1, Su1, Cu2, Su2, Cl3, and dl3 (the dash line in
0.5Vdc
Fig. 4(g)). Similarly, for Cu3, the charging current flows
though the dc source, Lch, du3, Cu3, Sl2, Cl2, Sl1 and dl1, which Vout
is depicted by the dash line in Fig. 4(b). Notably, in Fig. 4,
the output current and the possible charging paths are (f)
colored in black and red, respectively.
It is worth mentioning that, only positive voltage levels
are exhibited in Fig. 4. The negative voltage, however, can Vdc
0.5Vdc Vdc 2Vdc
be conjured up by referring to Table I, which shows the 2Vdc
0.5Vdc Vdc
switching-states for a seventeen-level configuration with
three cells. Moreover, in Table I, "on" and "off" states of the Vout
switches and diodes are demonstrated by ''1'' and ''0",
respectively. In addition, "C", "D", "F" and "N", indicate the (g)
charging, discharging, floating, and non-defined states of the
capacitors, correspondingly.
Vdc
0.5Vdc Vdc 2Vdc

Vdc 0.5Vdc
Vout
Vdc 2Vdc
0.5Vdc Vdc

Vout (h)

(a)

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2922415, IEEE
Journal of Emerging and Selected Topics in Power Electronics


100
v C n (%)  i l (t ) dt (6)
2n -2C nV dc
Tdn
Vdc
0.5Vdc Vdc 2Vdc where Cn, Tdn, il(t) are the capacitance of the capacitors in
0.5Vdc Vdc 2Vdc
the nth cell, discharging duration of the capacitors in the nth
Vout cell, and the instantaneous load current, respectively.
The input current variation, which is non-linear and
(i) depends on the voltage variation of the capacitors, can be
estimated by
Fig. 4. Operation modes: (a) to (i) switching patterns to achieve zero
v c max
to eight voltage levels. I dc Tch (7)
Lch
TABLE I.
OPERATION STATES FOR THE INVERTER IN FIG. 3. where ∆vcmax and Tch are the maximum voltage variation of
Switches Charging Capacitors the capacitors and charging duration of the capacitors,
respectively.
Level

states Diodes states

Vout
Sua,Sma,Sla,Su1, du1,du2,du3, Cu1,Cu2,Cu3,
Su2,Su3,Sl1,Sl2,Sl3 dl1,dl2,dl3 Cl1,Cl2,Cl3 C. Switching Frequency
8 001,111000 100111 C,D,D,C,C,C 4Vdc Referring to Table I, it is seen that in the proposed
7 010,101010 100111 C,D,D,C,C,C 7/2Vdc topology the switches in the last cell operate at the line
001,011100 110100 C,C,D,C,F,F frequency (fl), while the switches in the first cell operate at
6 3Vdc
100,111000 100111 C,D,D,C,C,C the switching frequency. For an m-cell configuration, the
5 010,011010 110100 C,C,D,C,F,F 5/2Vdc
001,100110 100110 C,F,D,C,N,F switching frequency of the switches (fm) in the nth cell is
4 2Vdc given as
100,011010 110100 C,C,D,C,F,F
3 010,100110 100110 C,F,D,C,C,F 3/2Vdc f m  2n m f l (8)
001,010110 111100 C,C,C,C,N,F
2 Vdc D. Power Loss Analysis
100,100110 100110 C,C,C,N,C,F
1 010,010110 111100 C,C,C,N,C,F 1/2Vdc Each module of the proposed topology is considered as a
100,010110 111100 C,C,C,N,C,F half-bridge cell. The power loss of a half-bridge is given by
0 0
001,101001 111100 C,C,C,N,C,F
-1 010,101001 100111 N,C,F,C,C,C -1/2Vdc
001,011001 110100 N,C,F,C,C,C
Pcell  v c f sw (Qrr  Qtc ) v e i  re i 2 (9)
-2 - Vdc
100,101001 110100 C,N,F,C,F,D v  v d  f sw (Q rr  Qtc )ron v c t rr f sw
-3 010,011001 110100 C,C,F,C,F,D -3/2Vdc with  e
-4
001,100101 100110 C,F,F,C,C,D
-2Vdc re  (1  t rr f sw )ron
100,011001 110100 C,C,F,C,F,D
-5 010,100101 100110 C,F,F,C,C,D -5/2Vdc
where vc, fsw, Qrr, Qtc, i, vd, trr, and ron, are the voltage across
001,000111 111100 C,C,C,C,D,D the switches, switching frequency, reverse recovery charge
-6 -3Vdc of the switch, reverse recovery charge of the anti-parallel
100,100011 100110 C,F,F,C,N,D
-7 010,010101 111100 C,C,C,C,D,D -7/2Vdc diode, the current passing through the switches, on-state
-8 100,000111 111100 C,C,C,C,D,D -4Vdc voltage, reverse recovery interval and on-state resistance,
accordingly.
III. VOLTAGE STRESS AND POWER LOSS ANALYSIS
A. Voltage Stress of the Components The total power loss of the main part (cascaded half-
As described previously, each cell in the proposed bridge cells) for an n-cell configuration is obtained as
topology obtains different voltage values. Eqs. (3) and (4) n
show the voltage across the capacitors in the nth cell (vnm), Pcell
t
  Pcell j (10)
and the maximum value of the output voltage (vom) of an m- j 1
cell configuration, respectively. The power loss of a diode is given as
v nm  2n 2v dc (3)  
v om  v dc
m
 2(k 2) (4)  
Pd  f sw   v sd i ch (t )  Rd n i ch (t )2 dt  E doff   (11)

k 1 Tch 
It is seen that each switch in the nth cell experiences the in which Tch, , ich(t), , and Edoff are the charging
overall voltage across its capacitors. The voltage stress of period, on-state reverse voltage of the diode, instantaneous
the charging diodes connected to the first cell is current, on-state resistance of the diode, and the wasted
insignificant, and the voltage stress of the diodes in the nth energy due to the reverse recovery stage of the diode.
cell is obtained by Since, two diodes reside in the charging path at any
v dss  2n 3v dc (5) instant; the power loss from the charging diodes is given as
where vdss is the voltage stress of the diodes. Pchd  2Pd (12)
B. Voltage and Current Ripples Power losses of the charging inductor are obtained as
In the proposed topology, the capacitors in the cells have
various discharging time. Hence, the capacitors experience PLch  R l i dc
2
(13)
different voltage ripples. The voltage ripple of the capacitors with Rl being the resistance of the inductor.
in the nth cell can be generalized as
Finally, the total power loss of a single-phase configuration
is illustrated by

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2922415, IEEE
Journal of Emerging and Selected Topics in Power Electronics

Ploss  Pcell
t
 Pchd  PLch (14) IV. PROPOSED TOPOLOGY IN PV APPLICATIONS
The converters in PV applications are required to fulfill
Using the characteristics of the commercially available certain specific requirements. Since the generated power of
components listed in Table II and assuming an output the PV modules is uncertain and environmental-dependent,
voltage with the peak value of 320 V and frequency of 50 the converter should offer a maximum efficiency for a wide
Hz, the efficiency of a 9-level (2-cell), 17-level (3-cell) and power range through a Maximum Power Point Tracking
33-level (4-cell) configurations of the proposed topology are (MPPT) control. The other important issue in PV systems is
assessed. The results are shown in Fig. 5. As it is evident, the leakage current. In order to simplify the MPPT in the
due to lower conduction losses, the 9-level configuration proposed topology, an extra switch (Sb) is added, as shown
offers the highest efficiency (96.3%) among the considered
in Fig. 6(a). Under this condition, the cell capacitors in the
configurations.
first cell are used as the capacitor bank, where the boost
TABLE II. COMPONENT CHARACTERISTICS.
Module # Main Switches Charging diode converters push their switched current into. The charging
1 TK3R1P04PL 200CNQ040 inductor in this configuration takes three roles: i) filtering
2 HUF75545P3 VS-249NQ150PbF the input current harmonics, ii) preventing the inrush current
3 STP30NF20 VS-249NQ150PbF of the capacitor, and iii) facilitating the MPPT process.
4 IXFT50N50P3 STTH20003TV
Furthermore, regarding the use of only one dc-link, the
Parasitic resistances of the capacitors, the charging
inductor, and switching frequency are considered proposed topology can be used as a central inverter, as
5mΩ, 3 mΩ, and 8 kHz respectively. shown in Fig. 6(b). In such an application, several PV
modules can be separately connected to the dc-link through
individual dc-dc converters to facilitate the MPPT under
partial shading conditions.
The common strategy to track the maximum power in PV
systems is to use a dc-dc boost converter. This converter is
also used to boost the output voltage of the PV modules.
Although it is possible to approach to any arbitrary voltage
level through the dc-dc boost converter in theory, the power
loss increases in line with the increase of the duty cycle (d)
and imposes a limitation on the boosting capability. To
Fig. 5. Efficiency of the proposed topology
tackle the issue, high-step up dc-dc converters are
suggested. Considering that the voltage is boosted through
E. Cost Analysis
the switched-capacitor cells in the proposed topology, the
The reduction in components will certainly lead to
dc-dc stage does not shoulder the boosting burden. The dc-
reduction in size and cost in any converter. Hence, by
dc section in this topology is essentially used to facilitate the
assuming a 17-level structure (with the input voltage being
MPPT process. The boost ratio of the voltage in the
50 V, peak output voltage being 320 V and output power
proposed topology is expressed as
being 5 kW), the cost of the proposed topology is briefly
v pv n
compared with that of the conventional HFL-CMI. In this
comparison, only the main components are considered.
v out 
1- d
 2k  2 (15)
k 1
These components and their prices, which are extracted
from Mouser and RS On-line stores, are shown in Table III. PV Lch
According to Table III, the proposed topology can reduce
the total cost by around 25.38%. Vdc 2Vdc 2nVdc
Sb
TABLE III. COST OF THE MAIN COMPONENTS Vout
Price
Components Type # of component
($)
IXTH30N50L 9.32 - 2 (a)
IXTR48P20P 8.21 4 2
Semiconductor + -
IXFP130N10T2 4.18 4 6
switches
IRFP044NPBF 1.62 4 - PVn Sbn
IXTP80N10T 2.57 4 -
Gate driver HCPL-316J 8.71 16 9
Proposed topology

Gate power supply TMH515s 7.29 16 9

HFT-CMI

200 V 3300 µF 13.2 1 2 Vdc 2Vdc 2nVdc

PV2
Capacitors 100 V 3300 µF 4.47 1 2 Sb2
Vout
50 V 3300 µF 3.02 1 2
KBPC3502T 3.31 1 -
H-bridge diodes PV1
KBPC3501T 3.31 2 - Sb1
VS-30.PF0.PBF 3.98 - 2
Single diode DSA70C200HB 3.27 - 2 DC-Link
MBR30H100CT 1.12 - 2
(b)
DSP TMS320F28335 24.49 1 1 Fig. 6. Proposed topology in PV application: (a) single-converter structure
HF link HF transformer 6.3 1 - and (b) multi-converter structure.
The total price of the The total price of the proposed
inverter = $ 286.69
It is worth mentioning that the proposed topology can
HFT-CMI= $384.23
only eliminate the inter-module leakage currents. The line

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2922415, IEEE
Journal of Emerging and Selected Topics in Power Electronics

leakage current, resulting from the common mode voltage In addition, the output voltage and load current in the
(CMV) variation remains. Consequently, this topology is presence of a purely resistive load of 2 kW are shown in
specifically suitable for stand-alone transformerless PV Fig. 9. As seen in Fig. 9, due to voltage ripple of the
applications. In other words, the proposed topology with capacitors, insignificant ramps appear over the voltage
grid-tied PV applications necessitates an isolation levels.
transformer to block the line leakage current.
Under faulty conditions, the charging inductor delays the
fault current and provides enough time for the protection
system to operate. The rise time of the fault current is given
as
L I
t rise  ch in (16)
v dc
where trise and Iin is the rise time of the fault current and the
Fig. 9. Output voltage and load current under the purely resistive loading
input current, respectively. Fig. 7 shows the proposed
condition.
topology which is equipped with a protection system.
Lch
The input and capacitor charging currents under the
mentioned loading condition are shown in Fig. 10(a). As
Relay Fault observed, the input current is smooth and continuous. It is
diagnosing
Proposed
Vdc system inverter accomplished through the charging inductor. To further
Protection system Load
clarify, considering the mentioned loading condition without
the charging inductor, the input and the capacitors charging
Fig. 7. Proposed topology equipped with a protection system currents are demonstrated in Fig. 10(b). When comparing
V. SIMULATION RESULTS Figs. 10(a) and (b), it is seen that the charging inductor has
The 17-level configuration shown in Fig. 3 is simulated in properly smoothed the input current and mitigated the inrush
Matlab/Simulink. The characteristics of the simulation currents.
model are listed in Table IV. Notably, the output voltage
and currents are described in per-unit values. The base
values for the voltage and current are 320 V and 20 A,
respectively.
TABLE IV. CHARACTERISTICS OF THE SIMULATED MODEL
Input voltage 80 V
Output voltage (RMS) 230 V
Output voltage frequency 50 Hz
Charging inductor 0.3 mH
Capacitors 3300 μF
Switching frequency 8 kHz

Fig. 8(a) shows the output and capacitor voltages under (a)
no-load condition. Furthermore, the Fast Fourier Transform
(FFT) analysis of the developed voltage is depicted in Fig.
8(b). According to the voltage waveform and its FFT
analysis, it is evident that the proposed topology can
develop the desired voltage with a high quality.

(b)
Fig. 10. Simulation results of the input and capacitor currents under a
purely resistive loading condition: (a) input current together with the
charging current of the capacitor in the presence of the charging inductor,
(a) and (b) Input current together with the charging current of the capacitor
without using the charging inductor.

In order to show the effect of the voltage ripple of the

capacitor on the output voltage, the capacitor voltages along
with the output voltage are exhibited in Fig. 11(a). To
further clarify, the voltage across the capacitors and the
input current are individually shown in Figs. 11(b) and (c),
(b) respectively. As it is seen in Fig. 11, the total voltage ripple
Fig. 8. Simulation results of a 17-level configuratopn of the proposed
topology under the no-load condition: (a) output voltage under no-load
of the capacitors is 0.07 p.u. (0.07*320 = 22 V), and the
condition, and (b) FFT analysis of the output voltage. input current ripple is 3 A. Fig. 11(a) explicitly shows the

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2922415, IEEE
Journal of Emerging and Selected Topics in Power Electronics

effect of the capacitors voltage ripple on the output voltage. the proposed inverter is demonstrated in Fig. 13. As shown
According to Fig. 11(a), the voltage ripple is high when in Fig. 13, the proposed topology can satisfactorily operate
developing the peak value of the output voltage. The reason under the considered conditions.
is that, when developing the peak value all the capacitors are
in the discharging mode, so they have the highest voltage
ripples, which are added up to bring the highest voltage
ripple of the capacitor voltage. As shown in Fig. 11(b) the
capacitors in the first cell experience low voltage ripple
because they situate in the charging mode more than the
other capacitors. in contrast, the capacitor in the last cell
experience the highest voltage ripple as they reside in the
charging mode less than the other capacitors.
Fig. 13. Dynamic performance of the proposed inverter under different
loading conditions and modulation indexes.

VI. EXPERIMENTAL RESULTS

In order to verify the feasibility of the proposed topology,
experimental tests are performed on a laboratory-scale
prototype. The prototype consists of four cells, so it can
develop 33 voltage levels. The characteristics of the
prototype are listed in Table V. In addition, the prototype is
(a) shown in Fig. 14.
TABLE V.
COMPONENT CHARACTERISTICS.
Components Type
Switches IRFP350 PbF
Opto-coupler TLP250
Microprocessor DSP-F28335
Capacitors 3300 μF
(b) Switching power supply iS0515s
Charging inductor 360 μH
Diodes FFPF20UP40S

Oscilloscop
e
(c)
Fig. 11. Simulation results of voltage and current ripples under a purely
resistive loading condition: (a) voltage ripple of the capacitors along with
the output voltage (b) voltage across the capacitors, and (c) the input
current.
dc-source

The IEEE 1547 standard requires inverters to provide the

reactive power upon demand. In order to assess the
performance of the proposed topology with reactive power Charging
injection, a resistive-inductive load of 1.7 kW+0.85 kVar is inductor
Switching Power
assumed. The output voltage and load current under the Supply
mentioned loading condition are shown in Fig. 12. As it is Switches & cooling
System Driver Circuits
observed in Fig. 12, the proposed topology can satisfy the
Capacitors
mentioned standard in a good manner. Switch Driver
DSP- Circuits Diode
F28335

Fig. 14. Experimental setup of the proposed multilevel inverter (33-level).

The peak value and the frequency of the output voltage

are 320 V and 50 Hz, respectively. The input voltage and
switching frequency are 40 V and 8 kHz, respectively. Fig.
15(a) shows the output voltage under no-load condition.
Fig. 12. Output voltage and load current under the resistive-inductive Furthermore, a purely resistive load of 500 W is connected
loading condition. to the output terminals. The output voltage and load current
in the presence of the mentioned load are presented in Fig.
By considering different apparent power (S), power factor 15(b).
(PF) and modulation indexes, the dynamic performance of

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2922415, IEEE
Journal of Emerging and Selected Topics in Power Electronics

Furthermore, by performing the FFT analysis, the quality

Vout [100 V/div] of the developed voltage can be analyzed. The FFT result in
Fig. 17 describes different harmonic contents of the output
voltage. Since the switching frequency is 8 kHz, the
harmonics around this frequency are of higher magnitude.
Nonetheless, the developed multilevel voltage features a low
Total Harmonic Distortion (THD) level.
Time [10 ms/div]

Vout [100V/div]
(a)

Vout [100 V/div] Load current

[5A/div] Time [5 ms/div]

[1V/div]

[5 kHz/div]

Time [10 ms/div]

(b)
Fig. 15. Experimental results of the proposed inverter under no-load and
purely resistive loading conditions. (a) output voltage in no-load Fig. 17. FFT analysis of the output voltage.
condition and (b) output voltage and load current under a purely resistive
loading condition.
The performance of the proposed topology in the presence
Moreover, the load current along with the input current is of a resistive-inductive load of 510 W + 330 Var is also
shown in Fig. 16(a). As it is demonstrated in Fig. 16(a), the obtained. The experimental results are presented in Fig. 18.
inverter has drawn a continuous current from the dc source. As demonstrated in Fig. 18, the inverter has provided the
These results validate the feature of the proposed multilevel considered reactive power. In all, the above simulations and
inverter achieving a continuous input current. As discussed experimental tests have confirmed the superior
previously, one of the interesting features of the proposed performances of the proposed multilevel inverter topology
topology is the ability to limit the inrush current of the in terms of lower component-count, self-balancing and
capacitors. This performance is demonstrated in Fig. 16(b). continuous input current.
As it is observed in Fig. 16(b), the charging currents are
limited within a reasonable range. Hence, the capacitors are Vout [100 V/div] Load current
[5A/div]
charged by a safe charging current.
Load Current [2 A/div]

Time [10 ms/div]

Input Current [2 A/div]

Fig. 18. Output voltage and load current in the resistive-inductive loading
condition.
Time [10 ms/div]
VII. CONCLUSION
(a)
In this paper, a new multilevel inverter topology was
Ic4 [ 5 A/div] proposed. The proposed topology uses fewer switches
compared to the conventional single source CMI topology.
Ic3 [2 A/div] The proposed topology consists of several half-bridge cells.
The half-bridges in this topology use two capacitors instead
of isolated dc sources. The capacitors are charged through a
Ic2 [2 A/div]
charging unit. The charging unit is synthesized with a
charging inductor, a dc source, and several diodes. The
Ic1 [ 5 A/div] charging inductor can both smooth the input current and
avoid the inrush current of the capacitors. In addition, it can
Time [ 5 ms/div] limit the fault current. This topology features self-balancing,
and boosting abilities, draws a smooth and continuous
(b) current from the dc side. Considering the mentioned features
Fig. 16. Experimental results of the input and capacitor charging currents and unidirectional power flow possibility, the proposed can
(a) output and input current and (b) charging current of capacitors. be a versatile converter in PV applications. Simulations and

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2922415, IEEE
Journal of Emerging and Selected Topics in Power Electronics

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components nine-level cascaded-transformer multilevel inverter in grid- Tabriz. Tabriz, Iran, 2019. He spent six months
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429 - 440, 2018. currently a senior engineer at Azerbaijan Regional Electric Company,
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Seyed Hossein Hosseini (M’93) was born in
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Polytechnique de Lorraine, Nancy, France, in
on improved series–parallel conversion with less number of
1978 with first class honors and 1981,
components," IEEE Trans. Ind. Electron., vol. 63, no. 6, pp. 3582-3582,
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Jun. 2016.
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an Assistant Professor in the Department of
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University of Tabriz.
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Engineering, University of Tabriz. From September 1996 to September
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1997, he was a Visiting Professor with the University of Western
multilevel inverter," in Proc International Conference Electrical
Ontario, London, ON, Canada. Since January 2017 he is Professor with
Machines and Systems, pp. 1-5, Aug. 2011.
the Near East University of North Cyprus, Turkey. He is the author of
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more than 700 Journal and Conference papers. Being announced by the
capacitor multilevel inverter with asymmetric input sources for
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microgrids," in Proc 20th International Conference on Electrical
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Machines and Systems (ICEMS), pp. 1-6. Aug. 2017.
His research interests include power electronics, application of power
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electronics in renewable energy sources, power quality issues,
based single-source cascaded H-bridge multilevel inverter featuring
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and FACTS devices.
1113-1124, Feb. 2019.
[17] H. Khoun Jahan, M. Abapour, K. Zare, S. H. Hosseini, Y. Yang, and
Frede Blaabjerg (S’86–M’88–SM’97–F’03)
F. blaabjerg, "A high step-up multilevel inverter with minimized
was with ABB-Scandia, Randers, Denmark,
components featuring self-balancing and continuous input current
from 1987 to 1988. From 1988 to 1992, he got
capabilities," in Proc 4th Southern Power Electronics Conference
the PhD degree in Electrical Engineering at
(SPEC), Dec 2018.
Aalborg University in 1995. He became an
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Assistant Professor in 1992, an Associate
cascaded-multilevel-inverter-based PV systems," IEEE Trans. Power
Professor in 1996, and a Full Professor of
Electron., vol. 29, no. 10, pp. 5265-5277, Oct. 2014.
power electronics and drives in 1998. From
[19] S. Saridakis, E. Koutroulis, and F. Blaabjerg, "Optimization of SiC-
2017 he became a Villum Investigator. He is
based H5 and conergy-NPC transformerless PV inverters,” IEEE J.
honoris causa at University Politehnica
Emerg. Sel. Top. Power Electron., vol. 3, no. 2, pp. 555-567, Jun.
Timisoara (UPT), Romania and Tallinn
2015.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2019.2922415, IEEE
Journal of Emerging and Selected Topics in Power Electronics

Technical University (TTU) in Estonia.

His current research interests include power electronics and its
applications such as in wind turbines, PV systems, reliability, harmonics
and adjustable speed drives. He has published more than 600 journal
papers in the fields of power electronics and its applications. He is the
co-author of four monographs and editor of ten books in power
electronics and its applications.

He has received 30 IEEE Prize Paper Awards, the IEEE PELS

Distinguished Service Award in 2009, the EPE-PEMC Council Award
in 2010, the IEEE William E. Newell Power Electronics Award 2014
and the Villum Kann Rasmussen Research Award 2014. He was the
Editor-in-Chief of the IEEE TRANSACTIONS ON POWER
ELECTRONICS from 2006 to 2012. He has been Distinguished
Lecturer for the IEEE Power Electronics Society from 2005 to 2007 and
for the IEEE Industry Applications Society from 2010 to 2011 as well as
2017 to 2018. In 2019-2020 he serves a President of IEEE Power
Electronics Society. He is Vice-President of the Danish Academy of
Technical Sciences too.
He is nominated in 2014-2018 by Thomson Reuters to be between the
most 250 cited researchers in Engineering in the world.

Yongheng Yang (SM’17) received the B.Eng.

degree in electrical engineering and
automation from Northwestern Polytechnical
University, Shaanxi, China, in 2009 and the
Ph.D. degree in electrical engineering from
Aalborg University, Aalborg, Denmark, in
2014.
He was a postgraduate student at Southeast
University, China, from 2009 to 2011. In
2013, he spent three months as a Visiting
Scholar at Texas A&M University, USA. Dr.
Yang is currently an Associate Professor with
the Department of Energy Technology, Aalborg University. His research
focuses on the grid integration of renewable energy, particularly
photovoltaic, power converter design, analysis and control, and
reliability in power electronics.
Dr. Yang is the Chair of the IEEE Denmark Section. He serves as an
Associate Editor of the CPSS Transactions on Power Electronics and
Applications, the IET Electronics Letters, the IET Renewable Power
Generation, and the IEEE Journal of Emerging and Selected Topics in
Power Electronics. He was the recipient of the 2018 IET Renewable
Power Generation Premium Award, and the 2018 IEEE Transactions on
Power Electronics’ Outstanding Reviewers Award.

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