#### Template Script for RTL->Gate-Level Flow #### all basic steps except for DFT-scan #### Fill

in the <...> fields for your module #### and update library search paths for your system if {[file exists /proc/cpuinfo]} { sh grep "model name" /proc/cpuinfo sh grep "cpu MHz" /proc/cpuinfo } #### Set up set DESIGN <design name> set SYN_EFF medium set MAP_EFF medium set DATE <date> set global_map_report 1 set map_fancy_names 1 set iopt_stats 1 set set set set SYN_PATH "." _OUTPUTS_PATH outputs_${DATE} _LOG_PATH logs_${DATE} _REPORTS_PATH reports_${DATE} lib_search_path {. ./lib} / hdl_search_path {. ./rtl} / wireload_mode <value> / information_level 7 / map_timing true /

set_attribute set_attribute set_attribute set_attribute set_attribute

set_attribute retime_reg_naming_suffix __retimed_reg / set_attribute library <libname> #### Turn on TNS, affects global and incr opto #### optimize for Total Negative Slack ( TNS ) set_attribute endpoint_slack_opto true / #### Power root attributes #### enable clock-gating for low-power ( lp ) set_attribute lp_insert_clock_gating true / #### enable operand-isolation for low-power set_attribute lp_insert_operand_isolation true / set_attribute hdl_track_filename_row_col true / #### enable VT optimization set_attribute lp_multi_vt_optimization_effort low / read_hdl <hdl file name(s)> elaborate $DESIGN puts "Runtime & Memory after 'read_hdl'" timestat #### look for any missing sub-designs check_design -unresolved #### read the consraints , in Native RC .g format #### can also use the .sdc format here

include rtl-compiler-constraints.g #### power estimate at rtl level report power -rtl -detail #### PLE #### uncomment the following if your want to use #### PLE models instead of wireload models ##set_attribute lef_library <lef file(s)> / ##set_attribute cap_table_file <file> / ##set_attribute tech_file <file> / ##set_attribute interconnect_mode ple / #set_attribute force_wireload <wireload name> "/designs/$DESIGN" #### make dirs for reports etc. if {![file exists ${_LOG_PATH}]} { exec mkdir ${_LOG_PATH} puts "Creating directory ${_LOG_PATH}" } if {![file exists ${_OUTPUTS_PATH}]} { exec mkdir ${_OUTPUTS_PATH} puts "Creating directory ${_OUTPUTS_PATH}" } if {![file exists ${_REPORTS_PATH}]} { exec mkdir ${_REPORTS_PATH} puts "Creating directory ${_REPORTS_PATH}" } #### good idea to check timing at this point #### and validate your constraints report timing -lint #### now set the basic cost groups, inputs-2-clocks ( I2C), clock2-2-outputs ( C 2O) #### and clocks-2-clocks ( C2C ) if {[llength [all::all_seqs]] > 0} { define_cost_group -name I2C -weight <integer> -design $DESIGN define_cost_group -name C2O -weight <integer> -design $DESIGN define_cost_group -name C2C -weight <integer> -design $DESIGN path_group -from [all::all_seqs] -to [all::all_seqs] -group C2C -name C2C path_group -from [all::all_seqs] -to [all::all_outs] -group C2O -name C2O path_group -from [all::all_inps] -to [all::all_seqs] -group I2C -name I2C } define_cost_group -name I2O -weight <integer> -design $DESIGN path_group -from [all::all_inps] -to [all::all_outs] -group I2O -name I2O #### check the constraints again foreach cg [find / -cost_group -null_ok *] { report timing -cost_group $cg >> $_REPORTS_PATH/${DESIGN}_pretim.rpt } #### Retime

set_attribute retime 1 "/designs/$DESIGN" #### Leakage/Dynamic power/Clock Gating setup. # uncomment only if your library has a clock-gating ( cg ) cell #set_attribute lp_clock_gating_cell [find /lib* -libcell <cg_libcell_name>] / #or #set_attribute clock_gating_module <cg_module_name> "/designs/$DESIGN" set_attribute max_leakage_power 0.0 "/designs/$DESIGN" #### uncomment only if you have a TCF ( SAIF ) file available for # power-driven optimizations #set_attribute lp_power_optimization_weight <value from 0 to 1> "/designs/$DESIG N" #set_attribute max_dynamic_power <number> "/designs/$DESIGN" #set_attr lp_optimize_dynamic_power_first true "/designs/$DESIGN" #set_attribute lp_clock_gating_test_signal <test_signal_object> "/designs/$DESIG N" #set_attribute lp_map_to_srpg_cells true "/designs/$DESIGN" #set_attribute lp_srpg_pg_driver <driver> "/designs/$DESIGN" #read_tcf <TCF file name> ## read_saif <SAIF file name> compress_constraints #### Synthesizing to generic synthesize -to_generic -eff $SYN_EFF puts "Runtime & Memory after 'synthesize -to_generic'" timestat #### Synthesizing to gates synthesize -to_mapped -eff $MAP_EFF -no_incr puts "Runtime & Memory after 'synthesize -to_map -no_incr'" timestat #### Retime # uncomment only if you want to move flops accross end-points ## if {[llength [all::all_seqs]] > 0} { ##set_attribute dont_retime true [all::all_seqs -clock <clock_name>] #for mu ltiple clock designs ## } ## retime -min_delay #manual retiming for minimum delay ## or ## retime -min_area #manual retiming for minimum area foreach cg [find / -cost_group -null_ok *] { report timing -cost_group $cg > $_REPORTS_PATH/${DESIGN}_[basename $cg]_post_m ap.rpt } #### Incremental Synthesis synthesize -to_mapped -eff $MAP_EFF -incr puts "Runtime & Memory after incremental synthesis" timestat foreach cg [find / -cost_group -null_ok *] { report timing -cost_group $cg > $_REPORTS_PATH/${DESIGN}_[basename $cg]_post_i

ncr.rpt } #### write Encounter file set (verilog, SDC, config, etc.) ##write_encounter design -basename <path & base filename> -lef <lef_file(s)> report clock_gating > $_REPORTS_PATH/${DESIGN}_clockgating.rpt report power -depth 0 > $_REPORTS_PATH/${DESIGN}_power.rpt report gates -power > $_REPORTS_PATH/${DESIGN}_gates_power.rpt report operand_isolation > $_REPORTS_PATH/${DESIGN}_op_isolation.rpt report area > $_REPORTS_PATH/${DESIGN}_area.rpt write -m > ${_OUTPUTS_PATH}/${DESIGN}_m.hvsyn write_sdc > ${_OUTPUTS_PATH}/${DESIGN}_m.sdc #### write_do_lec #### For non-checkpoint flow to compare RTL to final optimized netlist. ## write_do_lec -revised_design ${_OUTPUTS_PATH}/${DESIGN}_m.hvsyn -logfile ${_L OG_PATH}/rtl2final.lec.log > ${_OUTPUTS_PATH}/rtl2final.lec.do ##or #### For checkpoint flow to compare final last checkpoint file to final optimize d netlist. ## write_do_lec -revised_design ${_OUTPUTS_PATH}/${DESIGN}_m.hvsyn -logfile [get _attribute checkpoint_directory /designs/$DESIGN]/last.lec.log > [get_attribute checkpoint_directory /designs/$DESIGN]/last.lec.do puts "Final Runtime & Memory." timestat puts "============================" puts "Synthesis Finished ........." puts "============================" ##quit