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Dvlsi Unit-1 Notes

The document outlines various exercises related to digital VLSI system design, focusing on Verilog and sequential circuit design. It includes questions on simplifying logic expressions, designing sequential circuits, analyzing clock periods, and deriving state transition tables for different types of counters and state machines. The content emphasizes practical applications and calculations relevant to digital circuit design.

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Sasi Bhushan
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
1 views

Dvlsi Unit-1 Notes

The document outlines various exercises related to digital VLSI system design, focusing on Verilog and sequential circuit design. It includes questions on simplifying logic expressions, designing sequential circuits, analyzing clock periods, and deriving state transition tables for different types of counters and state machines. The content emphasizes practical applications and calculations relevant to digital circuit design.

Uploaded by

Sasi Bhushan
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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LAKIREDDY BALI REDDY COLLEGE OF ENGINEERING (AUTONOMOUS)

L.B.Reddy Nagar :: Mylavaram – 521 230 :: Krishna Dist.:: A.P.


20VE01 DIGITAL VLSI SYSTEM DESIGN

UNIT- 2
INTRODUCTION TO VERILOG

1 Mention the different ways of simplifying a logic expression using the theorems
Ans

2 summarize the steps required to design a sequential circuit


Ans 1. Given the design specifications, determine the required relationship between the input and output
sequences. Then find a state graph and state table.
2. Reduce the table to a minimum number of states. First eliminate duplicate rows by row matching; then
form an implication table
3. If the reduced table has m states (2n-1 < m ≤ 2n), n flip-flops are required. Assign a unique combination
of flip-flop states to correspond to each state in the reduced table. This is the encoded state assignment
technique. Alternately, a one-hot assignment with m flip-flops can be used.
4. Form the transition table by substituting the assigned flip-flop states for each state in the reduced state
tables. The resulting transition table specifies the next states of the flip-flops and the output in terms of
the present states of the flip-flops and the input.
5. Plot next-state maps and input maps for each flip-flop and derive the flip-flop input equations. Derive
the output functions.
6. Realize the flip-flop input equations and the output equations using the available logic gates.
7. Check your design using computer simulation or another method.
Steps 2 through 7 may be carried out using a suitable Computer Aided Design (CAD) program.
3 Consider the following circuit where the combinational circuit is represented by COMB and clock skew is
represented by tskew.
Given the following parameters:
FF setup time = 10 ns
FF hold time = 2 ns
FF propagation delay 5 12 to 20 ns
Tcomb 1 = 5 ns to 7 ns
Tcomb 2 = 6 ns to 11 ns

(a) What is the minimum clock period with tskew1 = 0; tskew2 = 3?


(b) Now set Tcomb1 = 1 to 4 ns. Is there a setup time violation for the middle flip-flop? If no, what is the
setup time margin?
(c) Now set Tcomb1 = 1 to 4 ns. Is there a hold-time violation for the middle flip-flop? If no, what is the
hold-time margin?
(d) What are the minimum values of tskew1 and tskew2 that will fix the violations?
(e) What is the minimum clock period after violations have been fixed?
Ans

4 Consider the following circuit where the combinational circuit is represented by COMB and clock skew is
represented by tskew.

Given the following parameters:


FF setup time = 20 ns; FF hold time = 10 ns; FF propagation delay = 5 to 10 ns
Tcomb 1 = 5 ns to 7 ns; Tcomb 2 = 6 ns to 11 ns
(a) What is the minimum clock period with tskew1 = tskew2 = 0?
(b) Now set Tcomb1 = 1 to 4 ns. Is there a setup time violation for the middle flip-flop? If no, what is the
setup time margin?
(c) Now set Tcomb1 = 1 to 4 ns. Is there a hold-time violation for the middle flip-flop? If no, what is the
hold-time margin?
(d) What are the minimum values of tskew1 and tskew2 that will fix the violations?
(e) What is the minimum clock period after violations have been fixed?
Ans

5 In the following circuit, the XOR gate has a delay in the range of 2 to 16 ns. The D flip-flop has a
propagation delay from clock to Q in the range 12 to 24 ns. The setup time is 8 ns, and the hold time is 4
ns.
What is the minimum clock period for proper operation of the circuit?
What are the earliest and latest times after the rising clock edge at which X is allowed to change and still
have proper synchronous operation?

Ans 16 ns + 24 ns + 8 ns = 48 ns. (to satisfy setup time) (hold time is not a problem because it takes at least
12 + 2 = 14 ns from rising clock edge until D changes)
earliest time: to satisfy hold time, th - tcmin = 4 ns – 2 ns = 2 ns
latest time: to satisfy setup time, 8 ns + 16 ns = 24 ns before rising clock edge. 48 ns clock – 24 ns = 24
ns after rising clock edge
6 A D flip-flop has a setup time of 5 ns, a hold time of 3 ns, and a propagation delay from the rising edge of
the clock to the change in flip-flop output in the range of 6 to 12 ns. An OR gate delay is in the range of 1
to 4 ns.
(a) What is the minimum clock period for proper operation of the following circuit?
(b) What is the earliest time after the rising clock edge at which X is allowed to change?
Ans

7 Derive the state transition table and flip-flop input equations for a modulo-6 counter that counts 000
through 101 and then repeats. Use J-K flip-flops.
Ans

8 Derive a Moore state graph and table for the circuit that has one input and one output. The output goes to
1 when the input sequence 111 has occurred, and the output goes to 0 if the input sequence 000 occurs.
At all other times, the output holds its value.
For example,
X=01011101000111001000
Z=000000111110001111110
Ans

9 Derive a Mealy state graph and table with a minimum number of states (six states) for the sequential
circuit which has one input (X) and two outputs (D and B). X represents a 4-bit binary number N, which
is input least significant bit first. D represents a 4-bit binary number equal to N – 2, which is output least
significant bit first. At the time the fourth input occurs, B = 1 if N – 2 is negative; otherwise, B = 0. The
circuit always resets after the fourth bit of X is received.
Ans

10 A sequential circuit has one input (X) and two outputs (S and V). X represents a 4-bit binary number N,
which is input least significant bit first. S represents a 4-bit binary number equal to N + 2, which is
output least significant bit first. At the time the fourth input occurs, V = 1 if N + 2 is too large to be
represented by 4 bits; otherwise, V = 0. The value of S should be the proper value, not a don’t care, in
both cases. The circuit always resets after the fourth bit of X has been received. (a) Derive a Mealy state
graph and table with a minimum number of states (six states).
Ans

11 Derive a Mealy state graph and table with a minimum number of states (eight states) for a sequential
circuit that has one input (X) and two outputs (Z1 and Z2). An output Z1 =1 occurs every time the input
sequence 010 is completed provided that the sequence 100 has never occurred. An output Z2 = 1 occurs
every time the input sequence 100 is completed. Note that once a Z2 = 1 output has occurred, Z1 = 1 can
never occur, but not vice versa.
Ans

12 Derive a Mealy state graph and table with a minimum number of states (six states) for a synchronous
sequential circuit which has one input and one output. If the input sequence 0101 or 0110 occurs, an
output of two successive 1s will occur. The first of these 1s should occur coincident with the last input of
the 0101 or 0110 sequence. The circuit should reset when the second 1 output occurs.
For example:
input sequence: X = 010011101010 101101 ...
output sequence: Z = 000000000011 000011 ...
Ans

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