ChapterFive:

Control Unit
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In this chapter:
 Introduction
 Micro – Operation
 Control Unit(CU)
 CU Implementation
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Introduction
In Previous Chapter, seen
 Machine instructions
 Operations performed by the processor to
execute each instruction
But how exactly each individual operation
is caused to happen ?
 The job of the Control Unit
The control unit
 Portion of the processor that actually causes
things to happen by - Issuing a control signal
 Micro-Operations ( ops) 4

A computer executes a program of instructions (or

instruction cycles)
The execution of an instruction involves a sequence of
substeps, generally called cycles.
Each instruction cycle has a number of steps or phases:
 Fetch, Indirect (if specified), Execute, Interrupt (if
requested)
Each cycle is in turn made up of a sequence of more
fundamental operations, called micro operations.
 Micro-Operations . . . 5

A diagram showing the elements of a program execution

 Micro-Operations . . . 6

Micro-​operations are functional or atomic

operations of a CPU.
 How the events of any instruction cycle can be
described as a sequence of micro operations

 How the concept of micro operations serve as a

guide to the design of the control unit
 Micro-Operations . . . 7

Fetch Cycle
 Sequence of events, seen from point of view of its
effects on processor registers
 First Step - to move the address from PC to MAR
 Second Step - overall effect is to bring in the
instruction
- Address (in the MAR) is placed on address bus
- Control unit issues READ command
- Result (data from memory) appears on data bus
- Data from data bus copied into MBR
- PC incremented by 1 (in parallel with data fetch from
memory)
 Third Step - Data (instruction) moved from MBR to IR
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Micro-Operations . . .
Fetch cycle (symbolic)
- t1: MAR  (PC)
- t2: MBR  memory
PC  (PC) +I
- t3: IR  (MBR)
Fetch cycle - involves three steps and four µop
- Note that each µop involves movement of data
into or out of a register
- Several µops can be performed in one clock
cycle, so long as these movements do not interfere
with one another
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Micro-Operations . . .
Assumptions
 A clock is available for timing purpose
- It emits regularly spaced clock pulses
- Each clock pulse defines a time unit
 Each single micro operation can be performed within a
time of a single time unit
 Notations t1,t2 and t3 represents successive time units

Note
 The second and third micro operations (µops) , both ,
takes place during the second time unit
 The third µop could have been grouped with the
fourth without affecting the fetch operation
 Micro-Operations . . . 10

Rules for grouping of µops

 Proper sequence of events must be followed
- MAR  (PC) must precede MBR  (M)
- As memory read operation makes use of
the address in the MAR
 Conflicts must be avoided
- Must not read & write same register in one time
unit
- As the result would be unpredictable
- MBR  memory and IR  (MBR) must
not be in same cycle
 Micro-Operations . . . 11

Indirect Cycle
- t1: MAR  (IR[Address])
- t2: MBR  memory
- t3: IR(Address)  (MBR[Address])
Note:
 IR[Address]
- Refers to the address field of the instruction
 MBR contains an address
 IR is now in the same state as if direct
addressing had been used
 Micro-Operations . . . 12

Interrupt Cycle
- t1: MBR  (PC)
- t2: MAR  Save_Address
PC  Routine_Address
- t3: memory  (MBR)
 Note:
- Save_Address
- The address at which the contents of the PC are to be saved
- Routine_Address
- The starting address of the interrupt processing routine
 This is a minimum
- May be additional micro-ops to get addresses
- The nature of this cycle varies greatly from one machine to another
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Micro-Operations . . .
Execute Cycle
 Different for each instruction
 For a machine with N different opcodes
- N different sequence of micro operation
Example:
 ADD R1,X
- (add the contents of location X to Register 1 , result
in R1)
- t1: MAR  (IR[Address])
- t2: MBR  memory
- t3: R1  (R1) + (MBR)
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The Control Unit
Issues control signals to:
 Cause data exchange with M and I/O modules
 Move data between registers
 Cause ALU to perform a specified function
 Regulate other internal operations
Execution of instructions is accomplished by
effect of control signals
 These emanate from CU to ALU, registers, and
system interconnection
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The Control Unit . . .
Functional requirements:
 Those functions that the control unit must
perform
 Defining these is basis for the design and
implementation of the control unit
 Three step process to characterize CU:
-Define basic elements of the processor
-Describe µops that the processor performs
-Determine function of CU to cause µops
performed
 The Control Unit . . . 16

Basic functional elements of processor:

 ALU
 Registers
 Internal data paths
 External data paths
 Control unit
Execution of a program consists of operations
involving these processor elements
All ops fall into one of the ff catagories:
 Transfer data from one register to another, from a register to an
external interface, from an external interface to a register, or
perform an arithmetic or logic operation
 The Control Unit . . . 17

Functional description of CU
Two tasks of CU:
 Sequencing:
- cause processor to step through a series of
µops in proper sequence
 Execution:
- causing each µop to be performed
It does these by use of control signal
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The Control Unit . . .
For the control unit to perform its function, it
needs
 Inputs - to determine the state of the system
 Outputs - to control the behavior of the system
The above are external specification of the control
unit
Internally the control unit
 Must have the logic required to perform its
function
- Sequencing
- Execution
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The Control Unit . . .
General model of the control unit
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The Control Unit . . .
Inputs:
 Clock:
- for “keeping time”
- CU causes one µop to be performed for each clock
pulse
- Processor cycle time
 Instruction register:
- Opcode determines which µop to perform during
execute cycle
 Flags:
- To determine status of the processor and outcome
of previous operations (e.g. ISZ)
 From control bus: Interrupts , Acknowledgements
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The Control Unit . . .
Outputs:
 Control signals within the processor – two types:
- Those that cause data to be moved from one
register to another
- Those that activate specific ALU functions
 Control signals to control bus – also two types:
- Control signals to memory
- Control signals to I/O modules
 All of these signals applied as binary inputs to
individual logic gates
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The Control Unit . . .
How does the control unit maintain control ?
- Control signals
 Example : consider the fetch cycle
Control unit generates the following control signals
- MAR  (PC)
- Open gates between PC and MAR
- MBR  memory
- Open gates between MAR and address bus
- Memory read control signal
- Open gates between data bus and MBR
- Add 1 to contents of PC and store the result back to PC
- IR  (MBR)
- Open gates between MBR and IR 2
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The Control Unit . . .

Reading assignment: control signal example

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Control Unit Implementation
Two ways to implement the control unit:
 Hardwired implementation
 Microprogrammed implementation

Hardwired:
 CU is essentially a combinational circuit
 Inputs:
- Flags and control bus signals – directly used
- IR input – opcode used to issue d/f combination of
control signals for different instructions
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Control Unit Implementation . . .
 A unique logic i/p is produced for each opcode by
using decoder
 Clock – issues repetitive sequence of pulses – for
measuring duration of pulses
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Control Unit Implementation . . .
Control unit with decoded inputs
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Control Unit Implementation . . .
Control unit logic:
 Produces o/p signals (C0, C1, …) as a function of i/p
signal
- i.e. for each control signal, drive Boolean
expression of that signal as a function of inputs:

 Example:
- Consider two control signals P and Q with the following
characteristics
- PQ= 00 Fetch cycle, PQ=01 Indirect cycle,
- PQ=10 Execute cycle and PQ=11 Interrupt cycle
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Control Unit Implementation . . .
 Then the boolean expression for C5 (a control signal
that causes the data to be read from the external data
bus into MBR)
- C5=P’Q’T2 + P’QT2
(C5 will be asserted during the second time unit of both
the fetch and indirect cycles)
 Repeat the above process for every control signal
generated by the CU
 Result
-A set of boolean equations that define the behavior of the
control unit
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Control Unit Implementation . . .
Microprogrammed control
 Hardwired :
- difficult to design
- Inflexible
 Alternative:
- Microprogrammed control implementation
- Control variables at any given time can be
represented by a string of 1’s and 0’s called
control word
- Control word can be programmed to perform
various and stored in memory
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Control Unit Implementation . . .
A control unit whose binary control variables are
stored in memory is called microprogrammed
control unit
Each word in memory – microinstruction
 It specifies one/more microoperations
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Control Unit Implementation . . .
Microprogram
 Program stored in memory that generates all the
control signals required to execute the instruction set
correctly
 Consists of microinstructions
Microinstruction
 Contains a control word and a sequencing word
Control Word - All the control information required
for one clock cycle
Sequencing Word - Information needed to decide
 the next microinstruction address
 Vocabulary to write a microprogram
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