PAC5222

Data Sheet
Power Application Controller®

Multi-Mode Power ManagerTM

Configurable Analog Front EndTM
Application Specific Power DriversTM
Arm® Cortex®-M0 Controller Core

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
1 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

TABLE OF CONTENTS
1 General Description ........................................................................................................................................................ 8
2 PAC Family Applications ................................................................................................................................................. 9
3 Product Selection Summary.......................................................................................................................................... 10
4 Ordering Information ..................................................................................................................................................... 10
5 Features ........................................................................................................................................................................ 11
6 Absolute Maximum Ratings .......................................................................................................................................... 13
7 Architectural Block Diagram .......................................................................................................................................... 14
8 Pin Configuration ........................................................................................................................................................... 15
8.1 PAC5222QM...................................................................................................................................................... 15
9 Pin Description .............................................................................................................................................................. 16
10 Multi-Mode Power manager (MMPM) ........................................................................................................................... 22
10.1 Features............................................................................................................................................................. 22
10.2 Block Diagram ................................................................................................................................................... 22
10.3 Functional Description ....................................................................................................................................... 23
10.3.1 Multi-Mode Switching Supply (MMSS) Controller ............................................................................. 23
10.3.2 Linear Regulators .............................................................................................................................. 25
10.3.3 Power Up Sequence ......................................................................................................................... 25
10.3.4 Hibernate Mode ................................................................................................................................. 26
10.3.5 Power and Temperature Monitor ...................................................................................................... 26
10.3.6 Voltage Reference............................................................................................................................. 27
10.4 Electrical Characteristics ................................................................................................................................... 28
10.5 Typical Performance Characteristics ................................................................................................................. 32
11 Configurable Analog Front End (CAFE) ........................................................................................................................ 33
11.1 Block Diagram ................................................................................................................................................... 33
11.2 Functional Description ....................................................................................................................................... 34
11.2.1 Differential Programmable Gain Amplifier (DA) ................................................................................ 34
11.2.2 Single-Ended Programmable Gain Amplifier (AMP) ......................................................................... 34
11.2.3 General Purpose Comparator (CMP)................................................................................................ 34
11.2.4 Phase Comparator (PHC) ................................................................................................................. 34
11.2.5 Protection Comparator (PCMP) ........................................................................................................ 35
11.2.6 Analog Output Buffer (BUF) .............................................................................................................. 35
11.2.7 Analog Front End I/O (AIO) ............................................................................................................... 35
11.2.8 Push Button (PBTN) .......................................................................................................................... 35

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
2 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

11.2.9 HP DAC and LP DAC ........................................................................................................................ 36

11.2.10 CLKOUT ............................................................................................................................................ 36
11.2.11 ADC Pre-Multiplexer.......................................................................................................................... 36
11.2.12 Configurable Analog Signal Matrix (CASM) ...................................................................................... 36
11.2.13 Configurable Digital Signal Matrix (CDSM) ....................................................................................... 37
11.3 Electrical Characteristics ................................................................................................................................... 37
11.4 Typical Performance Characteristics ................................................................................................................. 42
12 Application Specific Power Drivers (ASPD) .................................................................................................................. 44
12.1 Features............................................................................................................................................................. 44
12.2 Block Diagram ................................................................................................................................................... 44
12.3 Functional Description ....................................................................................................................................... 44
12.3.1 Low-Side Gate Driver ........................................................................................................................ 45
12.3.2 High-Side Gate Driver ....................................................................................................................... 45
12.3.3 High-Side Switching Transients ........................................................................................................ 45
12.3.4 Power Drivers Control ....................................................................................................................... 46
12.3.5 Gate Driver Fault Protection .............................................................................................................. 46
12.4 Electrical Characteristics ................................................................................................................................... 47
12.5 Typical Performance Characteristics ................................................................................................................. 48
Typical Performance Characteristics (Continued) ........................................................................................................ 49
13 ADC With Auto-Sampling Sequencer ........................................................................................................................... 50
13.1 Block Diagram ................................................................................................................................................... 50
13.2 Functional Description ....................................................................................................................................... 50
13.2.1 ADC ................................................................................................................................................... 50
13.2.2 Auto-Sampling Sequencer ................................................................................................................ 50
13.2.3 EMUX Control ................................................................................................................................... 51
13.3 Electrical Characteristics ................................................................................................................................... 51
14 Memory System ............................................................................................................................................................ 52
14.1 Features............................................................................................................................................................. 52
14.2 Block Diagram ................................................................................................................................................... 52
14.3 Functional Description ....................................................................................................................................... 52
14.3.1 Program and Data FLASH ................................................................................................................ 52
14.3.2 SRAM ................................................................................................................................................ 52
14.4 Electrical Characteristics ................................................................................................................................... 53
15 Clock Control System .................................................................................................................................................... 54
15.1 Features............................................................................................................................................................. 54

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
3 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

15.2 Block Diagram ................................................................................................................................................... 54

15.3 Functional Description ....................................................................................................................................... 55
15.3.1 Free Running Clock (FRCLK) ........................................................................................................... 55
15.3.2 Fast Clock (FCLK) ............................................................................................................................. 55
15.3.3 High-Speed Clock (HCLK) ................................................................................................................ 55
15.3.4 Auxiliary Clock (ACLK) ...................................................................................................................... 55
15.3.5 Clock Gating ...................................................................................................................................... 55
15.3.6 Ring Oscillator (ROSC) ..................................................................................................................... 55
15.3.7 Trimmed 4MHz RC Oscillator............................................................................................................ 55
15.3.8 Internal Slow RC Oscillator ............................................................................................................... 56
15.3.9 Crystal Oscillator Driver..................................................................................................................... 56
15.3.10 External Clock Input .......................................................................................................................... 56
15.3.11 PLL .................................................................................................................................................... 56
15.4 Electrical Characteristics ................................................................................................................................... 57
16 ARM CORTEX®-M0 Microcontroller Core ................................................................................................................... 58
®

16.1 Features............................................................................................................................................................. 58
16.2 Block Diagram ................................................................................................................................................... 58
16.3 Functional Description ....................................................................................................................................... 58
16.4 Electrical Characteristics ................................................................................................................................... 59
16.5 Typical Performance Characteristics ................................................................................................................. 59
17 I/O Controller ................................................................................................................................................................. 60
17.1 Features............................................................................................................................................................. 60
17.2 Block Diagram ................................................................................................................................................... 60
17.3 Functional Description ....................................................................................................................................... 61
17.4 GPIO Current Injection ...................................................................................................................................... 61
17.5 Electrical Characteristics ................................................................................................................................... 62
18 Serial Interface .............................................................................................................................................................. 63
18.1 Block Diagram ................................................................................................................................................... 63
18.2 Functional Description ....................................................................................................................................... 63
18.2.1 I2C Controller ..................................................................................................................................... 64
18.3 UART Controller ................................................................................................................................................ 64
18.4 SPI Controller .................................................................................................................................................... 64
18.5 Dynamic Characteristics .................................................................................................................................... 65
19 Timers ........................................................................................................................................................................... 69
19.1 Block Diagram ................................................................................................................................................... 69

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
4 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

19.2 Functional Description ....................................................................................................................................... 70

19.2.1 Timer A .............................................................................................................................................. 70
19.2.2 Timer B .............................................................................................................................................. 70
19.2.3 Timer C .............................................................................................................................................. 71
19.2.4 Timer D .............................................................................................................................................. 71
19.2.5 Watchdog Timer ................................................................................................................................ 71
19.2.6 CAFE Watchdog Timer ..................................................................................................................... 71
19.2.7 Wake-Up Timer ................................................................................................................................. 71
19.2.8 Real-Time Clock ................................................................................................................................ 71
20 Thermal Characteristics ................................................................................................................................................ 72
21 Application Examples .................................................................................................................................................... 73
22 Package Outline and Dimensions ................................................................................................................................. 74
22.1 TQFN66-48 Package Outline and Dimensions ................................................................................................. 74

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
5 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

LIST OF TABLES
Table 3-1 Product Selection Summary ................................................................................................................................. 10
Table 4-1 Ordering Information ............................................................................................................................................. 10
Table 6-1 Absolute Maximum Ratings .................................................................................................................................. 13
Table 9-1 Multi-Mode Power Manager and System Pin Description .................................................................................... 16
Table 9-2 Configurable Analog Front End Pin Description ................................................................................................... 17
Table 9-3 Application Specific Power Drivers Pin Description.............................................................................................. 18
Table 9-4 I/O Ports Pin Description ...................................................................................................................................... 18
Table 9-5 I/O Ports Pin Description (Continued)................................................................................................................... 19
Table 9-6 I/O Ports Pin Description (Continued)................................................................................................................... 20
Table 10-1 Multi-Mode Switching Supply Controller Electrical Characteristics .................................................................... 28
Table 10-2 Linear Regulators Electrical Characteristics ....................................................................................................... 30
Table 10-3 Power System Electrical Characteristics ............................................................................................................ 31
Table 11-1 Differential Programmable Gain Amplifier (DA) Electrical Characteristics ......................................................... 37
Table 11-2 Single-Ended Programmable Gain Amplifier (AMP) Electrical Characteristics .................................................. 38
Table 11-3 General Purpose Comparator (CMP) Electrical Characteristics ........................................................................ 38
Table 11-4 Phase Comparator (PHC) Electrical Characteristics .......................................................................................... 38
Table 11-5 Protection Comparator (PCMP) Electrical Characteristics ................................................................................. 39
Table 11-6 Analog Output Buffer (BUF) Electrical Characteristics ....................................................................................... 39
Table 11-7 Analog Front End I/O (AIO) Electrical Characteristics ........................................................................................ 40
Table 11-8 Push Button (PBTN) Electrical Characteristics ................................................................................................... 40
Table 11-9 HP DAC and LP DAC Electrical Characteristics ................................................................................................. 40
Table 11-10 CLKOUT Electrical Characteristics ................................................................................................................... 41
Table 12-1 Power Driver Resources by Part Numbers ......................................................................................................... 44
Table 12-2 Microcontroller Port and PWM to Power Driver Mapping ................................................................................... 46
Table 12-3 Power Driver Propagation Delay ........................................................................................................................ 46
Table 12-4 Gate Drivers Electrical Characteristics ............................................................................................................... 47
Table 13-1 ADC and Auto-Sampling Sequencer Electrical Characteristics ......................................................................... 51
Table 14-1 Memory System Electrical Characteristics ......................................................................................................... 53
Table 15-1 Clock Control System Electrical Characteristics ................................................................................................. 57
Table 16-1 Microcontroller and Clock Control System Electrical Characteristics ................................................................. 59
Table 17-1 I/O Controller Electrical Characteristics .............................................................................................................. 62
Table 18-1 Serial Interface Dynamic Characteristics ............................................................................................................ 65
Table 18-2 I2C Dynamic Characteristics ............................................................................................................................... 66
Table 18-3 SPI Dynamic Characteristics .............................................................................................................................. 68
Table 20-1 Thermal Characteristics ...................................................................................................................................... 72
Table 22-1 Dimensions ......................................................................................................................................................... 75

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
6 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

LIST OF FIGURES
Figure 1-1 Power Application Controller ................................................................................................................................. 8
Figure 2-1 Simplified Application Diagram .............................................................................................................................. 9
Figure 7-1 Architectural Block Diagram ................................................................................................................................ 14
Figure 8-1 PAC5222QM Pin Configuration (TQFN66-48 Package) ..................................................................................... 15
Figure 9-1 Power Supply Bypass Capacitor Routing ............................................................................................................ 21
Figure 10-1 Multi-Mode Power Manager .............................................................................................................................. 22
Figure 10-2 Buck Mode ......................................................................................................................................................... 24
Figure 10-3 SEPIC Mode ...................................................................................................................................................... 24
Figure 10-4 Linear Regulators .............................................................................................................................................. 25
Figure 10-5 Power Up Sequence .......................................................................................................................................... 26
Figure 11-1 Configurable Analog Front End ......................................................................................................................... 33
Figure 12-1 Application Specific Power Drivers .................................................................................................................... 44
Figure 12-2 Typical Gate Driver Connections ....................................................................................................................... 45
Figure 12-3 High-Side Switching Transients and Optional Circuitry ..................................................................................... 46
Figure 13-1 ADC with Auto-Sampling Sequencer................................................................................................................. 50
Figure 14-1 Memory System ................................................................................................................................................. 52
Figure 15-1 Clock Control System ........................................................................................................................................ 54
Figure 16-1 Arm Cortex-M0 Microcontroller Core ................................................................................................................. 58
Figure 17-1 I/O Controller ..................................................................................................................................................... 60
Figure 18-1 Serial Interface................................................................................................................................................... 63
Figure 18-2 I2C Timing Diagram ........................................................................................................................................... 67
Figure 18-3 SPI Timing Diagram........................................................................................................................................... 68
Figure 19-1 Timers A, B, C, and D ........................................................................................................................................ 69
Figure 19-2 AFE Watchdog and Wake-Up Timer ................................................................................................................. 70
Figure 19-3 Real-Time Clock and Watchdog Timer.............................................................................................................. 70
Figure 21-1 3-Phase Motor Drive Using PAC5222 (Simplified Diagram) ............................................................................. 73

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
7 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

1 GENERAL DESCRIPTION
The PAC5222 belongs to Active-Semi's broad portfolio of full-featured Power Application Controller® (PAC) products that
are highly optimized for controlling and powering next generation smart energy appliances, devices, and equipment. These
application controllers integrate a 50MHz Arm® Cortex®-M0 32-bit microcontroller core with Active-Semi's proprietary and
patent-pending Multi-Mode Power ManagerTM, Configurable Analog Front EndTM, and Application Specific Power DriversTM
to form the most compact microcontroller-based power and general purpose application systems ranging from digital power
supply to motor control. The PAC5222 microcontroller features up to 32kB of embedded FLASH and 8kB of SRAM memory,
a high-speed 10-bit 1µs analog-to-digital converter (ADC) with dual auto-sampling sequencers, 5V/3.3V I/Os, flexible clock
sources, timers, a versatile 14-channel PWM engine, and several serial interfaces.

The Multi-Mode Power Manager (MMPM) provides “all-in-one” efficient power management solution for multiple types of
power sources. It features a configurable multi-mode switching supply controller capable of operating in buck or SEPIC
mode, and up to four linear regulated voltage supplies. The Application Specific Power Drivers (ASPD) are high-voltage
power drivers designed for each target set of control applications, including half bridge, H-bridge, 3-phase, intelligent power
module (IPM), and general purpose driving. The Configurable Analog Front End (CAFE) comprises differential
programmable gain amplifiers, single-ended programmable gain amplifiers, comparators, digital-to-analog converters, and
I/Os for programmable and inter-connectible signal sampling, feedback amplification, and sensor monitoring of multiple
analog input signals. Together, these modules and microcontroller enable a wide range of compact applications with highly
integrated power management, driving, feedback, and control for DC supply up to 44V.

Figure 1-1 Power Application Controller

PWM ENGINE
MULTI-MODE
SERIAL
POWER MANAGER
INTERFACE 4 16-bit timers,
14 channels,
22 AC/DC, DC/DC,
SPI, I C, UART HW dead-time control,
linear regulators
10ns resolution control

APPLICATION
50MHz ARM®® CORTEX®®-M0
SPECIFIC POWER
MICROCONTROLLER CORE & MEMORY
DRIVERS
1-cycle 32-bit multiplier,
High-side & low-side
24-bit RTC, 24-bit WDT, 24-bit SysTick, NVIC,
gate drivers
FLASH & SRAM

CONFIGURABLE ANALOG FRONT END

DATA ACQUISITION
& SEQUENCER
3 Differential PGAs,
4 Single-ended PGAs,
10-bit 1µs ADC,
10 Comparators,
dual auto-sampling
2 DACs (10-bit & 8-bit),
sequencer
Temperature monitor

The PAC5222 is available in a 48-pin, 6x6 mm TQFN package. The PAC family includes a range of part numbers optimized
to work with different targeted primary applications.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
8 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

2 PAC FAMILY APPLICATIONS

• Power Tools (up to 24V)
• 12V Server Fans
• Embedded Speed Controllers (ESCs)

Figure 2-1 Simplified Application Diagram

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
9 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

3 PRODUCT SELECTION SUMMARY

Table 3-1 Product Selection Summary

APPLICATION
CONFIGURABLE
POWER SPECIFIC
ANALOG FRONT MICROCONTROLLER
MANAGER POWER
END
DRIVERS

PRIMARY

FAULT PROTECT
MULTI-MODE SW
INPUT VOLTAGE

POWER DRIVER
PART PIN

PWM CHANNEL
ADC CHANNEL
COMPARATOR
APPLICAT
NUMBER PKG

SPEED (MHz)
ION

INTERFACE
FLASH (kB)

SRAM (kB)
DIFF-PGA

XTAL
GPIO
PGA

DAC

3 LS
(1.5A/ SPI 3 half
48-pin
1.5A) I2 C bridge,
PAC5222 6x6 5.2-44V Y 3 4 10 2 10 6 Int 50 32 8 25 N
3 HS UART 3-phase
TQFN
(1.5A/ SWD control
1.5A)

Notes: DIFF-PGA = differential programmable gain amplifier, PGA = programmable gain amplifier HS = high-side , LS = low-side

4 ORDERING INFORMATION
Table 4-1 Ordering Information

PART NUMBER(1) TEMPERATURE RANGE PACKAGE PINS PACKING

PAC5222QM -40C to 105C TQFN66-48 48 + Exposed Pad Tray

(1) See Product Selection Summary for product features for each part number.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
10 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

5 FEATURES
• Proprietary Multi-Mode Power Manager
 Direct DC supply up to 20V
 Multi-mode switching supply controller configurable for Buck or SEPIC topologies with supply up to 44V
 4 linear regulators with power and hibernate management
 Power and temperature monitor, warning, and fault detection

• Proprietary Configurable Analog Front End

 10 analog front end I/O pins
 3 differential programmable gain amplifiers
 4 single-ended programmable gain amplifiers
 10 comparators
 2 DACs (10-bit and 8-bit)
 Low-speed clock output for optimizing UL/IEC60730 Class B Safety Applications

• Proprietary Application Specific Power Drivers

 3 low-side and 3 high-side gate drivers with 1.5A gate driving capability
 Configurable delays and fast fault protection

• 50MHz Arm® Cortex®-M0 32-bit microcontroller core

 Fast single cycle 32-bit x 32-bit multiplier
 24-bit SysTick timer
 Nested vectored interrupt controller (NVIC) with 20 external interrupts
 Wake-up interrupt controller allowing power-saving sleep modes
 Clock-gating allowing low power operation

• 32kB FLASH and 8kB SRAM memory

• 10-bit 1µs ADC with multi-input/multi-sample control engine

 9 ADC inputs including input from configurable analog front end

• 3.3V I/Os
 3 general purpose I/Os with tri-state and dedicated analog input to ADC

• True 5V I/Os
 12 general purpose I/Os with tri-state, pull-up and pull-down and dedicated I/O supply
 Configurable as true 5V or 3.3V I/Os

• Flexible clock and PLL from internal 2% oscillator, ring oscillator, external clock, or crystal

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
11 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

• 9 timing generators
 Four 16-bit timers with up to 16 PWM/CC blocks and 7 independent dead-time controllers
 24-bit watchdog timer
 4s or 8s watchdog timer
 24-bit real time clock
 24-bit SysTick timer
 Wake-up timer for sleep modes from 0.125s to 8s

• SPI, I2C, and UART communication interfaces

• SWD debug interface with interface disable function

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
12 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

6 ABSOLUTE MAXIMUM RATINGS

Table 6-1 Absolute Maximum Ratings
(Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may affect
device reliability.)

PARAMETER VALUE UNIT

VHM, DRM to VSSP -0.3 to 44 V
VP to VSS -0.3 to 20 V
CSM, REGO to VSS -0.3 to VP + 0.3 V
VSYS, AIO6 to VSS -0.3 to 6 V
VCC33 to VSS -0.3 to 4.1 V
VCC18 to VSS -0.3 to 2.5 V
AIO[9:7, 5:0], VCCIO to VSS -0.3 to VSYS + 0.3 V
PAx, PDx, PEx to VSS -0.3 to VCCIO + 0.3 V
PCx.. to VSSA -0.3 to VCC33 + 0.3 V
PAx/.., PBx/.., PCx/.., PDx/.., PEx/.. pin injection current 7.5 mA
PAx/.., PBx/.., PCx/.., PDx/.., PEx/.. sum of all pin injection current 25 mA
DRLx to VSSP -0.3 to VP + 0.3 V
DRBx to VSSP -0.3 to 56 V
DRSx to VSSP -6 to 44 V
DRSx allowable offset slew rate (dVDRSx/dt) 5 V/ns
DRBx, DRHx to respective DRSx -0.3 to 20 V
VSSP, VSSA to VSS -0.3 to 0.3 V
VSS, VSYS, DRM, DRLx, DRHx, REGO RMS current 0.2 ARMS
VSSP RMS current(1) 0.4 ARMS
VP RMS current(1) 0.6 ARMS
Operating temperature range -40 to 105 C
Human body model (JEDEC) 2 kV
Electrostatic discharge (ESD)
Charge device model (JEDEC) 1 kV

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
13 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

7 ARCHITECTURAL BLOCK DIAGRAM

Figure 7-1 Architectural Block Diagram

PAC5222 MULTI-MODE POWER

Power Application Controller MANAGER

VHM
MULTI-
SWDIO, SWDCL DRM
MODE
VP
SWITCHING
CSM
SUPPLY
VSSP, VSS, VSSA
DEBUG

32kB FLASH REGO

LINEAR
VSYS
REGU-
VCCIO
LATORS
(4) VCC33
Arm® VCC18
Cortex®-M0
8kB SRAM

PAC SOC BUS

CORE

APPLICATION SPECIFIC
POWER DRIVERS
DRBx
AHB/APB

HSGD (3) DRHx

DRSx
PWM ENGINE
CLOCK
CONTROL
TIMERS (4)
LSGD (3) DRLx

PWMAx, PWMBx,
PWMCx, PWMDx PWM /
CC (14)
CONFIGURABLE
RTC ANALOG FRONT END
DEAD TIME
(7)

OSC CLKOUT
PAx, PCx, PDx, PEx GPIO (15)

SOC BUS
BRIDGE

SPICSx, SPIMISO, PGA/

SPI AMPx/CMPx/PHCx
SPIMOSI, SPICLK CMP (4)
WATCHDOG

I2CSDA, I2CSCL I2C DAC (2)

DATA ACQUISITION &

SEQUENCER DAxP/PCMPx
DIFF-PGA/
UARTRX, UARTTX UART PCMP (3) DAxN
MUX

10-BIT
ADC
ADx

AUTO AIO AIOx

SYSTEM
nRESET1 SAMPLING CONTROL BUF6
CONTROL
(10) PBTN

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
14 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

8 PIN CONFIGURATION
8.1 PAC5222QM

Figure 8-1 PAC5222QM Pin Configuration (TQFN66-48 Package)

37 PD2/PWMA3/PWMA4/PWMB0
42 PE2/SPIMISO/UARTRX

41 PE1/SPIMOSI/UARTTX
43 PE3/SPICS0/nRESET1

38 PD1/SWDCL/EXTCLK
45 PE5/SPICS2/I2CSDA

44 PE4/SPICS1/I2CSCL

40 PE0/SPICLK

39 PD0/SWDIO
48 VCC18

46 VCCIO
47 VSS

PC4/AD4 1 36 PD3/PWMA5/PWMA7/PWMB1

PC3/AD3 2 35 PD5/PWMA5/PWMC1

PC2/AD2 3 34 PD7/PWMA6/PWMD0

VCC33 4 33 PA7/PWMA5/PWMA7/PWMC1/CLKOUT

AIO0/DA0N 5 32 DRB5
PAC5222QM
AIO1/DA0P/PCMP0 6 31 DRH5
TQFN66-48
AIO2/DA1N 7 30 DRS5

AIO3/DA1P/PCMP1 8 29 DRB4

AIO4/DA2N 9 28 DRH4

AIO5/DA2P/PCMP2 10 27 DRS4

AIO6/AMP6/CMP6/BUF6/PBTN 11 EP (VSS) 26 DRB3

AIO7/AMP7/CMP7/PHC7 12 25 DRH3
AIO8/AMP8/CMP8/PHC8 13

AIO9/AMP9/CMP9/PHC9 14

VSYS 15

REGO 16

CSM 17

VP 18

VHM 19

DRM 20

DRL0 21

DRL1 22

DRL2 23

DRS3 24

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
15 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

9 PIN DESCRIPTION
Table 9-1 Multi-Mode Power Manager and System Pin Description

PIN NAME PIN NUMBER TYPE DESCRIPTION

Switching supply current sense input. Connect to the positive side of the current
CSM 17 Analog
sense resistor.
Switching supply driver output. Connect to the base or gate of the external power
DRM 20 Analog
NPN or n-channel MOSFET. See PAC User Guide and application notes.
Exposed pad. Must be connected to VSS in a star ground configuration. Connect to a
EP (VSS) EP Power
large PCB copper area for power dissipation heat sinking.
VSS 47 Power Ground.
System regulator output. Connect to VSYS directly or through an external power-
REGO 16 Power
dissipating resistor.
Internally generated 1.8V core power supply. Connect a 2.2μF or higher value
VCC18 48 Power ceramic capacitor from VCC18 to VSSA. See Figure 9-1. Power Supply Bypass
Capacitor Routing below.
Internally generated 3.3V power supply. Connect a 2.2μF or higher value ceramic
VCC33 4 Power
capacitor from VCC33 to VSSA. See PCB layout note below.
Internally generated digital I/O power supply. Connect a 4.7μF or higher value
VCCIO 46 Power ceramic capacitor from VCCIO to VSSA. See Figure 9-1. Power Supply Bypass
Capacitor Routing below.
Switching supply controller supply input. Connect a 1μF or higher value ceramic
capacitor, or a 0.1μF ceramic capacitor in parallel with a 10μF or higher electrolytic
VHM 19 Power capacitor from VHM to VSSP. This pin requires good capacitive bypassing to VSSP, so
the ceramic capacitor must be connected with a shorter than 10mm trace from the
pin. See Figure 9-1. Power Supply Bypass Capacitor Routing below.
Main power supply. Provides power to the power drivers as well as voltage feedback
path for the switching supply. Connect a properly sized supply bypass capacitor in
parallel with a 0.1μF ceramic capacitor from VP pin to VSS for voltage loop stabilization.
VP 18 Power
This pin requires good capacitive bypassing to VSS, so the ceramic capacitor must be
connected with a shorter than 10mm trace from the pin. See Figure 9-1. Power Supply
Bypass Capacitor Routing below.
5V system power supply. Connect a 4.7μF or higher value ceramic capacitor from
VSYS 15 Power
VSYS to VSSP. See Figure 9-1. Power Supply Bypass Capacitor Routing below.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
16 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Table 9-2 Configurable Analog Front End Pin Description

PIN NAME PIN NUMBER FUNCTION TYPE DESCRIPTION

AIO0 I/O Analog front end I/O 0.
AIO0/DA0N 5
DA0N Analog Differential PGA 0 negative input.
AIO1 I/O Analog front end I/O 1.
AIO1/DA0P/PCMP0 6 DA0P Analog Differential PGA 0 positive input.
PCMP0 Analog Protection comparator input 0.
AIO2 I/O Analog front end I/O 2.
AIO2/DA1N 7
DA1N Analog Differential PGA 1 negative input.
AIO3 I/O Analog front end I/O 3.
AIO3/DA1P/PCMP1 8 DA1P Analog Differential PGA 1 positive input.
PCMP1 Analog Protection comparator input 1.
AIO4 I/O Analog front end I/O 4.
AIO4/DA2N 9
DA2N Analog Differential PGA 2 negative input.
AIO5 I/O Analog front end I/O 5.
AIO5/DA2P/PCMP2 10 DA2P Analog Differential PGA 2 positive input.
PCMP2 Analog Protection comparator input 2.
AIO6 I/O Analog front end I/O 6.
AMP6 Analog PGA input 6.
AIO6/AMP6/CMP6/BUF6/PBTN 11 CMP6 Analog Comparator input 6.
BUF6 Analog Buffer output 6.
PBTN Analog Push button input.
AIO7 I/O Analog front end I/O 7.
AMP7 Analog PGA input 7.
AIO7/AMP7/CMP7/PHC7 12
CMP7 Analog Comparator input 7.
PHC7 Analog Phase comparator input 7.
AIO8 I/O Analog front end I/O 8.
AMP8 Analog PGA input 8.
AIO8/AMP8/CMP8/PHC8 13
CMP8 Analog Comparator input 8.
PHC8 Analog Phase comparator input 8.
AIO9 I/O Analog front end I/O 9.
AMP9 Analog PGA input 9.
AIO9/AMP9/CMP9/PHC9 14
CMP9 Analog Comparator input 9.
PHC9 Analog Phase comparator input 9.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
17 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Table 9-3 Application Specific Power Drivers Pin Description

PIN NAME PIN NUMBER TYPE DESCRIPTION

DRB3 26 Analog High-side gate driver bootstrap 3.
DRB4 29 Analog High-side gate driver bootstrap 4.
DRB5 32 Analog High-side gate driver bootstrap 5.
DRH3 25 Analog High-side gate driver 3.
DRH4 28 Analog High-side gate driver 4.
DRH5 31 Analog High-side gate driver 5.
DRL0 21 Analog Low-side gate driver 0.
DRL1 22 Analog Low-side gate driver 1.
DRL2 23 Analog Low-side gate driver 2.
DRS3 24 Analog High-side gate driver source 3.
DRS4 27 Analog High-side gate driver source 4.
DRS5 30 Analog High-side gate driver source 5.

Table 9-4 I/O Ports Pin Description

PIN NAME PIN NUMBER FUNCTION TYPE DESCRIPTION

PC2 I/O I/O port C2.
PC2/AD2 3
AD2 Analog ADC input 2.
PC3 I/O I/O port C3.
PC3/AD3 2
AD3 Analog ADC input 3.
PC4 I/O I/O port C4.
PC4/AD4 1
AD4 Analog ADC input 4.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
18 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Table 9-5 I/O Ports Pin Description (Continued)

PIN NAME PIN NUMBER FUNCTION TYPE DESCRIPTION

PA7 Digital I/O port A7.
PWMA5 Digital Timer A PWM/Capture 5.
PA7/PWMA5/PWMA7/PAMC1/CLKOUT 33 PWMA7 Digital Timer A PWM/Capture 7.
PWMC1 Digital Timer C PWM/Capture 1.
CLKOUT Digital Low-speed clock output
PD0 I/O I/O port D0.
PD0/SWDIO 39
SWDIO I/O Serial wire debug I/O.
PD1 I/O I/O port D1.
PD1/SWDCL/EXTCLK 38 SWDCL I Serial wire debug clock.
EXTCLK I External clock.
PD2 I/O I/O port D2.
PWMA3 I/O Timer A PWM/capture 3.
PD2/PWMA3/PWMA4/PWMB0 37
PWMA4 I/O Timer A PWM/capture 4.
PWMB0 I/O Timer B PWM/capture 0.
PD3 I/O I/O port D3.
PWMA5 I/O Timer A PWM/capture 5.
PD3/PWMA5/PWMA7/PWMB1 36
PWMA7 I/O Timer A PWM/capture 7.
PWMB1 I/O Timer B PWM/capture 1.
PD5 I/O I/O port D5.
PD5/PWMA5/PWMC1 35 PWMA5 I/O Timer A PWM/capture 5.
PWMC1 I/O Timer C PWM/capture 1.
PD7 I/O I/O port D7.
PD7/PWMA6/PWMD0 34 PWMA6 I/O Timer A PWM/capture 6.
PWMD0 I/O Timer D PWM/capture 0.
PE0 I/O I/O port E0.
PE0/SPICLK 40
SPICLK I/O SPI clock.
PE1 I/O I/O port E1.
PE1/SPIMOSI/UARTTX 41 SPIMOSI I/O SPI master out slave in (MOSI).
UARTTX O UART transmit output.
PE2 I/O I/O port E2.
PE2/SPIMISO/UARTRX 42 SPIMISO I/O SPI master in slave out (MISO).
UARTRX I UART receive input.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
19 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Table 9-6 I/O Ports Pin Description (Continued)

PIN NAME PIN NUMBER FUNCTION TYPE DESCRIPTION

PE3 I/O I/O port E3.
PE3/SPICS0/nRESET1 43 SPICS0 O SPI chip select 0.
nRESET1 I Reset input 1 (active low).
PE4 I/O I/O port E4.
PE4/SPICS1/I2CSCL 44 SPICS1 O SPI chip select 1.
I2CSCL I/O I2C clock.
PE5 I/O I/O port E5.
PE5/SPICS2/I2CSDA 45 SPICS2 O SPI chip select 2.
I2CSDA I/O I2C data.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
20 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Figure 9-1 Power Supply Bypass Capacitor Routing

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
21 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

10 MULTI-MODE POWER MANAGER (MMPM)

10.1 Features

• Direct DC supply up to 20V

• Multi-mode switching supply controller configurable as Buck or SEPIC DC/DC controller up to 44V
• 4 linear regulators with power and hibernate management
• Power and temperature monitor, warning, and fault detection

10.2 Block Diagram

Figure 10-1 Multi-Mode Power Manager

MULTI-MODE POWER MANAGER

MULTI-MODE SWITCHING
SUPPLY CONTROLLER COMP & START UP &
CLAMP
CURR LIMIT MODE CTRL
1.2V VHM
ERROR
MUX

AMP
VP VOLTAGE PWM DRM
DRIVER
SETTING ERROR LOGIC
COMP
VSSP
MUX
IMOD
DAC
POWER CURR
OK & OVP SENSE
CSM

SYSTEM TIMERS 2.5V VREF VSSA

MUX

REGO POWER
SUPPLY VMON
LINEAR LINEAR LINEAR & TEMP
REG
REG REG REG VTHREF MON VSS
HIBERNATE VTEMP
VSYS

VCCIO VCC33 VCC18

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
22 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

10.3 Functional Description

The Multi-Mode Power Manager (Figure 10-1) is optimized to efficiently provide "all-in-one" power management required
by the PAC and associated application circuitry from a wide range of input power sources. It incorporates a dedicated
multi-mode switching supply (MMSS) controller operable as a buck or SEPIC DC/DC to efficiently convert power from a DC
input source to generate a main supply output VP. Four linear regulators provide VSYS, VCCIO, VCC33, and VCC18 supplies for
5V system, 5V or 3.3V I/O, 3.3V mixed signal, and 1.8V microcontroller core circuitry. The power manager also
handles system functions including internal reference generation, timers, hibernate mode management, and power and
temperature monitoring.

10.3.1 Multi-Mode Switching Supply (MMSS) Controller

The MMSS controller drives an external power transistor for pulse-width modulation switching of an inductor or transformer
for power conversion. The DRM output drives the gate of the n-channel MOSFET or the base of the NPN between the VHM
on state and VSSP off state at proper duty cycle and switching frequency to ensure that the main supply voltage VP is
regulated. The VP regulation voltage is initially set to 15V during start up, and can be reconfigured to be 9V or 12V by the
microcontroller after initialization. When VP is lower than the target regulation voltage, the internal feedback control circuitry
causes the inductor current to increase to raise VP. Conversely, when VP is higher than the regulation voltage, the feedback
loop control causes the inductor current to decrease to lower VP. The feedback loop is internally stabilized. The output
current capability of the switching supply is determined by the external current sense resistor. In the high-side current sense
buck or SEPIC mode, the inductor current signal is sensed differentially between the CSM pin and VP, and has a peak
current limit threshold of 0.26V.

The MMSS controller is flexible and configurable as a buck, SEPIC or an AC/DC converter. Input sources include battery
supply for buck mode (Figure 10-2) or SEPIC mode (Figure 10-3). The MMSS controller operational mode is determined by
external configuration and register settings from the microcontroller after power up. It can operate in either high-side or
low-side current sense mode, and does not require external feedback loop compensation circuitry. For optional extended
application range, the MMSS also incorporates additional digital control by the microcontroller to add accurate computations
for outer feedback loop control such as power factor correction and accurate current control.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
23 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Figure 10-2 Buck Mode

VHM VIN

PAC52xx
PAC5222

DRM

VP (15V default)

CSM
VP

Figure 10-3 SEPIC Mode

VHM VIN

PAC5222

VP

DRM

CSM
VP (9V/12V/15V)

The MMSS detects and selects between high-side and low-side mode during start up based on the placement of the current
sense resistor and the CSM pin voltage. It employs a safe start up mode with a 9.5kHz switching frequency until VP exceeds
4.3V under-voltage-lockout threshold, then transitions to the 45kHz default switching frequency for at least 6ms to bring VP
close to the target voltage, before enabling the linear regulators. Any extra load should only be applied after the supplies
are available and the microprocessor has initialized. The switching frequency can be reconfigured by the microprocessor to
be 181kHz to 500kHz in the high switching frequency mode for battery-based applications, and to be 45kHz to 125kHz in
the low switching frequency mode for AC applications. Upon initialization, the microcontroller must reconfigure the MMSS
to the desired settings for VP regulation voltage, switching mode, switching frequency, and VHM clamp. Refer to the PAC
application notes and user guide for MMSS controller design and programming.

If a stable external 5V to 18V power source is available, it can power the VP main supply and all the linear regulators directly
without requiring the MMSS controller to operate. In such applications, VHM can be connected directly to VP and the
microcontroller should disable the MMSS upon initialization to reduce power loss.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
24 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

10.3.2 Linear Regulators

The MMPM includes up to four linear regulators. The system supply regulator is a medium voltage regulator that takes the
VP supply and sources up to 200mA at REGO until VSYS, externally coupled to REGO, reaches 5V. This allows a properly
rated external resistor to be connected from REGO to VSYS to close the current loop and offload power dissipation between
VP and VSYS. Once VSYS is above 4V, the three additional 40mA linear regulators for VCCIO, VCC33, and VCC18 supplies
sequentially power up. Figure 10-4 shows typical circuit connections for the linear regulators. For 5V I/O systems, short the
VCCIO pin to VSYS to bypass the VCCIO regulator. For 3.3V I/O systems, the VCCIO regulator generates 3.3V. The VCC33 and
VCC18 regulators generate 3.3V and 1.8V, respectively. When VSYS, VCCIO, VCC33, and VCC18 are all above their respective
power good thresholds, and the configurable power on reset duration has expired, the microcontroller is initialized.

Figure 10-4 Linear Regulators

VP VP (15V typical)

PAC5222

REGO VSYS & VCCIO (5V)

VSYS
VCCIO (1) 4.7µF

VCC33
VCC18
VSS
VSSA 1µF 1µF
(1)
5V I/O connection shown.
Connect instead to a 4.7µF
capacitor for 3.3V I/O.

10.3.3 Power Up Sequence

The MMPM follows a typical power up sequence as in the Figure 10-5 below. A typical sequence begins with input power
supply being applied, followed by the safe start up and start up durations to bring the switching supply output VP to 15V,
before the linear regulators are enabled. When all the supplies are ready, the internal clocks become available, and the
microcontroller starts executing from the program memory. During initialization, the microcontroller can reconfigure the
switching supply to a different VP regulation voltage such as 12V and to an appropriate switching frequency and switching
mode. The total loading on the switching supply must be kept below 25% of the maximum output current until after the
reconfiguration of the switching supply is complete. For AC input supply applications, the start up sequence includes an
additional charging time for VHM depending on the start-up resistor and capacitor values.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
25 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Figure 10-5 Power Up Sequence

10.3.4 Hibernate Mode

The IC can go into an ultra-low power hibernate mode via the microcontroller firmware or via the optional push button
(PBTN, see Push Button description in Configurable Analog Front End). In hibernate mode, only a minimal amount (typically
18µA) of current is used by VHM, and the MMSS controller and all internal regulators are shut down to eliminate power drain
from the output supplies. The system exits hibernate mode after a wake-up timer duration (configurable from 125ms to 8s
or infinite) has expired or, if push button enabled, after an additional push button event has been detected. When exiting
the hibernate mode, the power manager goes through the start up cycle and the microcontroller is reinitialized. Only the
persistent power manager status bits (resets and faults) are retained during hibernation.

10.3.5 Power and Temperature Monitor

Whenever any of the VSYS, VCCIO, VCC33, or VCC18 power supplies falls below their respective power good threshold voltage,
a fault event is detected and the microcontroller is reset. The microcontroller stays in the reset state until VSYS, VCCIO, VCC33,
and VCC18 supply rails are all good again and the reset time has expired. A microcontroller reset can also be initiated by a
maskable temperature fault event that occurs when the IC temperature reaches 170°C. The fault status bits are persistent
during reset, and can be read by the microcontroller upon re-initialization to determine the cause of previous reset.

A power monitoring signal VMON is provided onto the ADC pre-multiplexer for monitoring various internal power supplies.
VMON can be set to be VCC18, 0.4•VCC33, 0.4•VCCIO, 0.4•VSYS, 0.1•VREGO, 0.1•VP, or the internal compensation voltage VCOMP
for switching supply power monitoring.

For power and temperature warning, a VP low event at 77% of the regulation voltage and an IC temperature warning event
at 140°C are provided as maskable interrupts to the microcontroller. This condition will assert an interrupt on IRQ1 (pin
PB0).

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
26 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

These warnings allow the microcontroller to safely power down the system.

In addition to the temperature warning interrupt and fault reset, a temperature monitor signal VTEMP = 1.5 + 5.04e-3 •
(T - 25°C) (V) is provided onto the ADC pre-multiplexer for IC temperature measurement.

10.3.6 Voltage Reference

The reference block includes a 2.5V high precision reference voltage that provides the 2.5V reference voltage for the ADC,
the DACs, and the 4-level programmable threshold voltage VTHREF (0.1V, 0.2V, 0.5V, and 1.25V).

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
27 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

10.4 Electrical Characteristics

Table 10-1 Multi-Mode Switching Supply Controller Electrical Characteristics

(VHM = 30V, VP = 12V, and TA = -40°C to 105°C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

Input Supply (VHM)
IHIB;VHM VHM hibernate mode supply current VHM, hibernate mode 18 36 µA
ISU;VHM VHM start up supply current VHM < VUVLOR;VHM 75 120 µA
IOP;VHM VHM operating supply current DRM floating 0.3 0.5 mA
VOP:VHM VHM operating voltage range 5.0 40 V
VUVLOR;VHM VHM under-voltage lockout rising 6.1 7.4 8 V
VUVLOF;VHM VHM under-voltage lockout falling 5.1 6.6 7 V
VCLAMP;VHM VHM clamp voltage Clamp enabled, sink current = 100µA 14.5 16.9 19.5 V
ICLAMP;VHM VHM clamp sink current limit Clamp enabled 4 mA
Output Supply and Feedback (VP)
Programmable to 9V, 12V, or 15V
VREG;VP VP output regulation voltage -7 -1 5 %
Load = 0 to 500mA
kPOK;VP VP power OK threshold VP rising, hysteresis = 10% 82 87 92 %
VP rising, hysteresis = 15%
kOVP;VP VP over voltage protection threshold 136 %
MMPM Controller enabled
Switching Control

Switching frequency High frequency mode, 8 settings 181 500

fSWM;DRM kHz
programmable range Low frequency mode, 8 settings 45 125
fSSU;DRM Safe start up switching frequency 9.5 kHz
tONMIN;DRM Minimum on time 440 ns
Low duty-cycle & Low-frequency mode 25 %
tOFFMIN;DRM Minimum off time Low duty-cycle & High frequency mode 440 ns
High duty-cycle mode 820 ns

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
28 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

Current Sense (CSM Pin)

VDET;CSM CSM mode detection threshold Rising, hysteresis = 50mV 0.40 0.55 0.69 V

VHSLIM;CSM High-side current limit threshold 181kHz, duty = 25%, relative to VP 0.17 0.26 0.35 V

VLSLIM;CSM Low-side current limit threshold 45kHz, duty = 25% 0.7 1 1.48 V

tBLANK;CSM Current sense blanking time 200 ns

Low-side abnormal current sense VP < 4.3V 0.8

VPROT;CSM V
protection threshold VP > 4.3V 1.9

Gate Driver Output (DRM Pin)

VOH;DRM High-level output voltage IDRM = -20mA VHM−1 V

VOL;DRM Low-level output voltage IDRM = 20mA 0.6 V

IOH;DRM High-level output source current VDRM = VHM - 5V -0.3 A

IOL;DRM Low-level output sink current VDRM = 5V 0.5 A

tPD;DRM Strong pull down pulse width High-side current sense mode 240 ns

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
29 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Table 10-2 Linear Regulators Electrical Characteristics

(VP = 12V and TA = -40C to 105C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

VOP;VP VP operating voltage range 4.7 18 V

VUVLO;VP VP under-voltage-lockout threshold VP rising, hysteresis = 0.2V 4 4.3 4.7 V

IQ;VP VP quiescent supply current Power manager only, including IQ;VSYS 400 750 µA

IQ;VSYS VSYS quiescent supply current VCCIO, VCC33, and VCC18 regulators only 350 600 µA

VSYS VSYS output voltage Load = 10µA to 200mA 4.8 5 5.15 V

VCCIO shorted to VSYS VSYS
VCCIO VCCIO output voltage Load = 10mA V
VCCIO from regulator 3.152 3.3 3.398
VCC33 VCC33 output voltage Load = 10mA 3.185 3.3 3.415 V
VCC18 VCC18 output voltage Load = 10mA 1.834 1.9 1.975 V
ILIM;VSYS VSYS regulator current limit 220 330 mA
ILIM;VCCIO VCCIO regulator current limit 45 80 mA
ILIM;VCC33 VCC33 regulator current limit 45 80 mA
ILIM;VCC18 VCC18 regulator current limit 45 80 mA
kSCFB Short circuit current fold back 50 %
VDO;VSYS VSYS dropout voltage VP =5V, ISYS=100mA 350 680 mV
VUVLO;VSYS VSYS under-voltage-lockout threshold VSYS rising, hysteresis = 0.2V 3.5 3.95 4.4 V
kPOKIO VCCIO Power OK threshold VCCIO rising, hysteresis = 10% 79 85 91 %
kPOK33 VCC33 Power OK threshold VCC33 rising, hysteresis = 10% 79 85 91 %
kPOK18 VCC18 Power OK threshold VCC18 falling, hysteresis = 10% 79 85 91 %

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
30 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Table 10-3 Power System Electrical Characteristics

(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

TA = 25°C 2.487 2.5 2.513
VREF Reference voltage V
TA = -40°C to 105°C 2.463 2.5 2.537

VCC18 1
Power monitoring voltage (VMON)
kMON VSYS, VCCIO, VCC33 0.36 0.4 0.43 V/V
coefficient
VP, VREGO 0.09 0.1 0.11
VTEMP Temperature monitor voltage at 25°C TA = 25°C, at ADC 1.475 1.5 1.540 V
kTEMP Temperature monitor coefficient At ADC 5.04 mV/K
TWARN Over-temperature warning threshold Hysteresis = 10°C 140 °C
TFAULT Over-temperature fault threshold Hysteresis = 10°C 170 °C

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
31 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

10.5 Typical Performance Characteristics

(VP = 12V and TA = 25°C unless otherwise specified.)

Buck Mode Efficiency Buck Mode Hibernate Input Current

vs. Output Current vs. Input Voltage
100 50
VIN = 24V

PACMMPM-001

PACMMPM-002
90

80 40

Input Current (µA)

70
Efficiency (%)

VIN = 48V
60 30

50

40 20

30
20 10
VP = 12V,
10
fSW;DRM = 181kHz
0 0
0 0.1 0.2 0.3 0.4 0.5 20 30 40 50 60
Output Current (A) Input Voltage (V)

DRM Driver Output

On Resistance vs. Temperature
80
PACMMPM-005

70
On Resistance (Ω)

60

50

40 Pull up

30

20
Pull down
10

0
-40 0 40 80 120
Temperature (°C)

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
32 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

11 CONFIGURABLE ANALOG FRONT END (CAFE)

11.1 Block Diagram

Figure 11-1 Configurable Analog Front End

CONFIGURABLE ANALOG FRONT END

LP DAC

DIFF-PGA & PCOMP

INT1
PROTECT
HP DAC PR1, PR2

S/H

MUX

ADC PRE-MUX
DAxP/PCMPx

ADC MUX
DAxN
OFFSET
CAL

CONFIGURABLE ANALOG SIGNAL MATRIX

PGA VTEMP, VMON, VREF/
2
AMPx
MUX
MUX

BUF6 CONFIGURABLE DIGITAL SIGNAL MATRIX

COMPARATOR
CMPx
DINx
MUX

VTHREF
MUX

VSYS

(except AIO6) AFE I/O VSYS

DINx
MUX

AIOx I/O
CONTROL

PHASE COMPARATOR
PHCx DINx
3V
MUX

PHASE INT2/POS
MUX

POS
PHASE
REF
PBTN PUSH
BUTTON

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
33 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

11.2 Functional Description

The device includes a Configurable Analog Front End (CAFE, Figure 11-1) accessible through up to 10 analog and I/O pins.
These pins can be configured to form flexible interconnected circuitry made up of up to 3 differential programmable gain
amplifiers, 4 single-ended programmable gain amplifiers, 4 general purpose comparators, 3 phase comparators, 10
protection comparators, and one buffer output. These pins can also be programmed as analog feed-through pins, or as
analog front end I/O pins that can function as digital inputs or digital open-drain outputs. The PAC proprietary configurable
analog signal matrix (CASM) and configurable digital signal matrix (CDSM) allow real time asynchronous analog and digital
signals to be routed in flexible circuit connections for different applications. A push button function is provided for optional
push button on, hibernate, and off power management function. A low speed clock output is provided for optimizing system
design for UL/IEC60730 Class B Safety Applications.

11.2.1 Differential Programmable Gain Amplifier (DA)

The DAxP and DAxN pin pair are positive and negative inputs, respectively, to a differential programmable gain amplifier.
The differential gain can be programmable to be 1x, 2x, 4x, 8x, 16x, 32x, and 48x for zero ohm signal source impedance.
The differential programmable gain amplifier has -0.3V to 2.5V input common mode range, and its output can be configured
for routing directly to the ADC pre-multiplexer, or through a sample-and-hold circuit synchronized with the ADC
auto-sampling mechanism. Each differential amplifier is accompanied by offset calibration circuitry, and two protection
comparators for protection event monitoring. The programmable gain differential amplifier is optimized for use with signal
source impedance lower than 500Ω and with matched source impedance on both positive and negative inputs for
minimal offset. The effective gain is scaled by 13.5k / (13.5k + RSOURCE), where RSOURCE is the matched source impedance
of each input.

11.2.2 Single-Ended Programmable Gain Amplifier (AMP)

Each AMPx input goes to a single-ended programmable gain amplifier with signal relative to VSSA. The amplifier gain can
be programmed to be 1x, 2x, 4x, 8x, 16x, 32x, and 48x, or as analog feed-through. The programmable gain amplifier output
is routed via a multiplexer to the configurable analog signal matrix CASM.

11.2.3 General Purpose Comparator (CMP)

The general purpose comparator takes the CMPx input and compares it to either the programmable threshold voltage
(VTHREF) or a signal from the configurable analog signal matrix CASM. The comparator has 0V to VSYS input common mode
range, and its polarity-selectable output is routed via a multiplexer to either a data input bit or the configurable digital signal
matrix CDSM. Each general purpose comparator has two mask bits to prevent or allow rising or falling edge of its output to
trigger second microcontroller interrupt INT2, where INT2 can be configured to active protection event PR1.

11.2.4 Phase Comparator (PHC)

The phase comparator takes the PHCx input and compares it to either the programmable threshold voltage (VTHREF) or a
signal from the configurable analog signal matrix CASM. The comparison signal can be set to a phase reference signal
generated by averaging the PHCx input voltages. In a three-phase motor control application, the phase reference signal
acts as a virtual center tap for BEMF detection. The PHCx inputs are optionally fed through to the CASM. The phase
comparator has 0V to VSYS input common mode range, and its polarity-selectable output is routed to a data input bit and to

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
34 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

the phase/position multiplexer synchronized with the auto-sampling sequencers. The PHC inputs can be compared to the
virtual center-tap, or phase to phase for the most efficient BEMF zero-cross detection. The phase comparators have
configurable asymmetric hysteresis.

The phase comparator has 0V to VSYS input common mode range, and its polarity-selectable output is routed to a data input
bit and to the phase/position multiplexer synchronized with the auto-sampling sequencers.

11.2.5 Protection Comparator (PCMP)

Two protection comparators are provided in association with each differential programmable gain amplifier, with outputs
available to trigger protection events and accessible as read-back output bits. The high-speed protection (HP) comparator
compares the PCMPx pin to the 8-bit HP DAC output voltage, with full scale voltage of 2.5V. The limit protection (LP)
comparator compares the differential programmable gain amplifier output to the 10-bit LP DAC output voltage, with full scale
voltage of 2.5V.

Each protection comparator has a mask bit to prevent or allow it to trigger the main microcontroller interrupt INT1. Each
protection comparator also has one mask bit to prevent or allow it to activate protection event PR1, and another mask bit to
prevent or allow it to activate protection event PR2. These two protection events can be used directly by protection circuitry
in the Application Specific Power Drivers (ASPD) to protect devices being driven.

11.2.6 Analog Output Buffer (BUF)

A subset of the signals from the configurable analog signal matrix CASM can be multiplexed to the BUF6 pin for external
use. The buffer offset voltage can be minimized with the built-in swap function.

11.2.7 Analog Front End I/O (AIO)

Up to 10 AIOx pins are available in the device. In the analog front end I/O mode, the pin can be configured to be a digital
input or digital open-drain output. The AIOx input or output signal can be set to a data input or output register bit, or
multiplexed to one of the signals in the configurable digital signal matrix CDSM. The signal can be set to active high (default)
or active low, with VSYS supply rail. Where AIO6,7,8,9 supports microcontroller interrupt for external signals. Each has
two mask bits to prevent or allow rising or falling edge of its corresponding digital input to trigger second microcontroller
interrupt INT2.

11.2.8 Push Button (PBTN)

The push button PBTN, when enabled, can be used by the microcontroller to detect a user active-low push button event
and to put the system into an ultra-low-power hibernate mode. Once the system is in hibernate mode, PBTN can be used
to wake up the system. In addition, PBTN can also be used as a hardware reset for the microcontroller when it is held low
for longer than 8s during normal operation. The PBTN input is active low and has a 55kΩ pull-up resistor to 3V.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
35 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

11.2.9 HP DAC and LP DAC

The 8-bit HP DAC can be used as the comparison voltage for the high-speed protection (HP) comparators, or routed for
general purpose use via the AB2 signal in the CASM. The HP DAC output full scale voltage is 2.5V.

The 10-bit LP DAC can be used as the comparison voltage for the limit protection (LP) comparators, or routed for general
purpose use via the AB3 signal in the CASM. The LP DAC output full scale voltage is 2.5V.

11.2.10 CLKOUT

There is a low-speed clock output that may be enabled and configured on this device. The clock output is disabled by default
and may be enabled or disabled through a register bit. The clock output may be configured for 580Hz or 1.16kHz.

This clock output is useful for generating a second clock source that is needed by UL or IEC60730 Class B Safety standards.
This output may be connected to a digital input on the PCB on this device so that the MCU firmware may detect any issues
with the clock such as failure, or drifting of the frequency.

The CLKOUT pin is shared with PA7, as an open-drain output. If the CLKOUT pin is enabled, then PA7 may be configured
as a weak-pull up or a high-impedance input, with a 100k pull-up resistor that connects PA7 to VCCIO. The digital input
functions will still be enabled, but no output functions are allowed.

11.2.11 ADC Pre-Multiplexer

The ADC pre-multiplexer is a 16-to-1 multiplexer that selects between the 3 differential programmable gain amplifier outputs,
AB1 through AB9, temperature monitor signal (VTEMP), power monitor signal (VMON), and offset calibration reference
(VREF / 2). The ADC pre-multiplexer can be directly controlled or automatically scanned by the auto-sampling sequencer.

When the ADC pre-multiplexer is automatically scanned, the unbuffered or sensitive signals should be masked by setting
appropriate register bits.

11.2.12 Configurable Analog Signal Matrix (CASM)

The CASM has 9 general purpose analog signals labeled AB1 through AB9 that can be used for:

• Routing the single-ended programmable gain amplifier or analog feed-through output to AB1 through AB9
• Routing an analog signal via AB1, AB2, or AB3 to the negative input of a general purpose comparator or
phase comparator
• Routing the 8-bit HP DAC output to AB2
• Routing the 10-bit LP DAC output to AB3
• Routing analog signals via AB1 through AB12 to the ADC pre-multiplexer
• Routing phase comparator feed-through signals to AB7, AB8, and AB9, and averaged voltage to AB1

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
36 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

11.2.13 Configurable Digital Signal Matrix (CDSM)

The CDSM has 7 general purpose bi-directional digital signals labeled DB1 through DB7 that can be used for:

• Routing the AIOx input to or output signals from DB1 through DB7
• Routing the general purpose comparator output signals to DB1 through DB7

11.3 Electrical Characteristics

Table 11-1 Differential Programmable Gain Amplifier (DA) Electrical Characteristics

(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

ICC;DA Operating supply current Each enabled amplifier 150 300 µA

VICMR;DA Input common mode range -0.3 2.5 V

VOLR;DA Output linear range 0.1 VSYS – 0.1 V

VSHR;DA Sample and hold range 0.1 3.5 V

VOS;DA Input offset voltage Gain = 48x, VDAxP= VDAxN = 0V, TA = 25°C -8 8 mV

Gain = 1x 1

Gain = 2x 2

Gain = 4x 4
Differential amplifier gain
Gain = 8x, VDAxP = 125mV, VDAxN = 0V,
AVZI;DA (zero ohm source -2% 8 2%
TA = 25°C
impedance)
Gain = 16x 16

Gain = 32x 32

Gain = 48x 48

kCMRR;DA Common mode rejection ratio Gain = 8x, VDAxP= VDAxN = 0V, TA = 25°C 55 dB

RINDIF;DA Differential input impedance 27 kΩ

(1)
Slew rate Gain = 8x 7 10 V/µs

tST;DA Settling time (1) To 1% of final value 200 400 ns

(1) Guaranteed by design.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
37 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Table 11-2 Single-Ended Programmable Gain Amplifier (AMP) Electrical Characteristics

(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

ICC;AMP Operating supply current Each enabled amplifier 80 140 µA

VICMR;AMP Input common mode range 0 VSYS V

VOLR;AMP Output linear range 0.1 VSYS - 0.1 V

VOS;AMP Input offset voltage Gain = 1x, TA = 25°C, VAMPX = 2.5V -10 10 mV

Gain = 1x 1

Gain = 2x 2

Gain = 4x 4

AV;AMP Amplifier gain Gain = 8x, VAMPx = 125mV, TA = 25°C -2% 8 2%

Gain = 16x 16

Gain = 32x 32

Gain = 48x 48

IIN;AMP Input current 0 1 µA

Slew rate (1) Gain = 8x 8 12 V/µs

(1)
tST;AMP Settling time To 1% of final value 150 300 ns

(1) Guaranteed by design.

Table 11-3 General Purpose Comparator (CMP) Electrical Characteristics

(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

ICC;CMP Operating supply current Each enabled comparator 35 110 µA
VICMR;CMP Input common mode range 0 VSYS V
VOS;CMP Input offset voltage VCMPx = 2.5V, TA = 25°C -10 10 mV
VHYS;CMP Hysteresis HYSMODE = 0; HYS[1:0] = 10b 23 mV
IIN;CMP Input current 0 1 µA
tDEL;CMP Comparator delay (1) 100 ns

(1) Guaranteed by design.

Table 11-4 Phase Comparator (PHC) Electrical Characteristics

(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
38 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

ICC;PHC Operating supply current Each enabled comparator 35 110 µA
VICMR;PHC Input common mode range 0 VSYS V
VOS;PHC Input offset voltage VPHCx = 2.5V, TA = 25°C -10 10 mV
VHYS;PHC Hysteresis HYSMODE = 0; HYS[1:0] = 10b 23 mV
IIN;PHC Input current 0 1 µA
(1)
tDEL;PHC Comparator delay 100 ns

(1) Guaranteed by design.

Table 11-5 Protection Comparator (PCMP) Electrical Characteristics

(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

ICC;PCMP Operating supply current Each enabled comparator 35 100 µA
VICMR;PCMP Input common mode range 0.3 VSYS -1 V
VOS;PCMP Input offset voltage VPCMPx = 2.5V, TA = 25°C -10 10 mV
VHYS;PCMP Hysteresis 20 mV
IIN;PCMP Input current 0 1 µA
tDEL;PCMP Comparator delay (1) 100 ns
(1) Guaranteed by design.

Table 11-6 Analog Output Buffer (BUF) Electrical Characteristics

(VSYS = VCCIO = 5V, VCC33 = 3.3V, and TA = -40°C to 105°C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

ICC;BUF Operating supply current No load 35 100 µA
VICMR;BUF Input common mode range 0 3.5 V
VOLR;AMP Output linear range 0.1 3.5 V
VOS;BUF Offset voltage VBUF = 2.5V, TA = 25°C -18 18 mV
IOMAX Maximum output current CL = 0.1nF 0.8 1.3 mA

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
39 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Table 11-7 Analog Front End I/O (AIO) Electrical Characteristics

(VSYS = VCCIO = 5V, and TA = -40°C to 105°C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

VAIO Pin voltage range 0 5 V
VIH;AIO High-level input voltage 2.2 V
VIL;AIO Low-level input voltage 0.8 V
RPD;AIO Pull-down resistance Input mode 0.5 1 1.8 MΩ
VOL;AIO Low-level output voltage IAIOx = 7mA, open-drain output mode 0.4 V
IOL;AIO Low-level output sink current VAIOx = 0.4V, open-drain output mode 6 14 mA
ILK;AIO High-level output leakage current VAIOx = 5V, open-drain output mode 0 10 μA

Table 11-8 Push Button (PBTN) Electrical Characteristics

(VSYS = VCCIO = 5V, and TA = -40°C to 105°C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

VI;PBTN Input voltage range 0 5 V
VIH;PBTN High-level input voltage 2 V
VIL;PBTN Low-level input voltage 0.35 V
RPU;PBTN Pull-up resistance To 3V, push-button input mode 40 55 95 kΩ

Table 11-9 HP DAC and LP DAC Electrical Characteristics

(VSYS = VCCIO = 5V, and TA = -40°C to 105°C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

TA = 25°C 2.480 2.5 2.520
VDACREF DAC reference voltage V
TA = -40°C to 105°C 2.453 2.5 2.547
HP 8-bit DAC INL(1) -1 1 LSB
HP 8-bit DAC DNL(1) -0.5 0.5 LSB
LP 10-bit DAC INL(1) -2 2 LSB
LP 10-bit DAC DNL(1) -1 1 LSB

(1) Guaranteed by design and characterization.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
40 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Table 11-10 CLKOUT Electrical Characteristics

(VSYS = VCCIO = 5V, and TA = -40°C to 105°C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

FCLKOUT Low-speed clock output frequency 520 580 640 Hz
TA = 25°C, FCLKOUT reference from
FCLKOUT_ERR Low-speed clock output frequency error1 -10 10 %
stored value in INFO FLASH.
TA = -40°C to 105°C, FCLKOUT
reference from stored value in INFO -25 25 %
FLASH.

1
To improve the accuracy tolerance, the user may use calibrated values for CLKOUT measurements available in INFO
FLASH. See the PAC5222 User Guide for more information.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
41 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

11.4 Typical Performance Characteristics

(VSYS = 5V and TA = 25°C unless otherwise specified.)

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
42 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
43 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

12 APPLICATION SPECIFIC POWER DRIVERS (ASPD)

12.1 Features
• 3 low-side and 3 high-side gate drivers
• 1.5A gate driving capability
• Configurable delays and fast fault protection

12.2 Block Diagram

Figure 12-1 Application Specific Power Drivers

APPLICATION SPECIFIC POWER DRIVERS

HIGH-SIDE GATE DRIVERS DRBx

DELAY LEVEL PRE-

DRHx
SHIFT DRIVER
PORT/PWM SIGNALS

HS
DRSx
FAULT
PROTECT
LS LOW-SIDE GATE DRIVERS VP

PRE-
DELAY DRLx
DRIVER

ENDRV

12.3 Functional Description

The Application Specific Power Drivers (ASPD, Figure 12-1) module handles power driving for power control applications.
The PAC5222 has three low-side gate drivers (DRLx), three high-side gate drivers (DRHx). Each gate driver can drive an
external MOSFET or IGBT switch in response to high-speed control signals from the microcontroller ports, and a pair of
high-side and low-side gate drivers can form a half-bridge driver.

Figure 12-2 below shows typical gate driver connections and Table 12-1 shows the ASPD available resources. The
PAC5222 gate drivers support up to a 56V boot-strap supply.

Table 12-1 Power Driver Resources by Part Numbers

PART LOW-SIDE GATE DRIVER HIGH-SIDE GATE DRIVER

NUMBER DRLx SOURCE /SINK CURRENT DRHx MAX SUPPLY SOURCE/ SINK CURRENT
PAC5222 3 1.5A/1.5A 3 56V 1.5A/1.5A

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
44 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Figure 12-2 Typical Gate Driver Connections

DRBx VP
VIN

DRHx

DRSx

(To loads/inductors.)

DRLx

PAC5222

The ASPD includes built-in configurable fault protection for the internal gate drivers.

12.3.1 Low-Side Gate Driver

The DRLx low-side gate driver drives the gate of an external MOSFET or IGBT switch between the low-level VSSP power
ground rail and high-level VP supply rail. The DRLx output pin has sink and source output current capability of 1.5A. Each
low-side gate driver is controlled by a microcontroller port signal with 4 configurable levels of propagation delay.

12.3.2 High-Side Gate Driver

The DRHx high-side gate driver drives the gate of an external MOSFET or IGBT switch between its low-level DRSx driver
source rail and its high-level DRBx bootstrap rail. The DRSx pin can go up to 40V steady state. The DRHx output pin has
sink and source output current capability of 1.5A. The DRBx bootstrap pin can have a maximum operating voltage of 16V
relative to the DRSx pin, and up to 52V steady state. The DRSx pin is designed to tolerate momentary switching negative
spikes down to -5V without affecting the DRHx output state. Each high-side gate driver is controlled by a microcontroller
port signal with 4 configurable levels of propagation delay.

For bootstrapped high-side operation, connect an appropriate capacitor between DRBx and DRSx and a properly rated
bootstrap diode from VP to DRBx. To operate the DRHx output as a low-side gate driver, connect its DRBx pin to VP and its
DRSx pin to VSSP.

12.3.3 High-Side Switching Transients

Typical high-side switching transients are shown in Figure 12-3(a). To ensure functionality and reliability, the DRSx and
DRBx pins must not exceed the peak and undershoot limit values shown. This should be verified by probing the DRBx and
DRSx pins directly relative to VSS pin. A small resistor and diode clamp for the DRSx pin can be used to make sure that
the pin voltage stays within the negative limit value. In addition, the high-side slew rate dV/dt must be kept within ±5V/ns for
DRSx. This can be achieved by adding a resistor-diode pair in series, and an optional capacitor in parallel with the power
switch gate. The parallel capacitor also provides a low impedance and close gate shunt against coupling from the switch
drain. These optional protection and slew rate control are shown in Figure 12-3(b).

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
45 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Figure 12-3 High-Side Switching Transients and Optional Circuitry

VDRBx ≤ 52V
DRBx VP

VIN

DRHx

DRSx

dV/dt
VDRBx PAC5222
dV/dt
DRLx

VDRSx

VDRSx ≥ -5V

(a) High-Side Switching Transients (b) Optional Transient Protection and Slew Rate Control

12.3.4 Power Drivers Control

All power drivers are initially disabled from power-on-reset. To enable the power drivers, the microprocessor must first set
the driver enable bit to '1'. The gate drivers are controlled by the microcontroller ports and/or PWM signals according to
Table 12-2, with configurable delays as shown in Table 12-3. Refer to the PAC application notes and user guide for
additional information on power drivers control programming.

Table 12-2 Microcontroller Port and PWM to Power Driver Mapping

PWMA3/PWMA4/
PART NUMBER PWMA0 PWMA1 PWMA2 PWMA5/PWMC0 PWMA6/PWMD0
PWMB0
PAC5222 DRL0 DRL1 DRL2 DRH3 DRH4 DRH5

Table 12-3 Power Driver Propagation Delay

DRLx DRHx
RISING FALLING RISING FALLING
130ns 140ns 160ns 140ns

12.3.5 Gate Driver Fault Protection

The ASPD incorporates a configurable fault protection mechanism using protection signal from the Configurable Analog
Front End (CAFE), designated as protection event 1 (PR1) signal. The DRL0/DRL1/DRL2 drivers are designated as low-
side group 1. The DRH3/DRH4/DRH5 gate drivers are designated as high-side group 1. The PR1 signal from the CAFE
can be used to disable low-side group 1, high-side group 1, or both depending on the PR1 mask bit settings.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
46 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

12.4 Electrical Characteristics

Table 12-4 Gate Drivers Electrical Characteristics

(VP = 12V, VSYS = 5V, and TA = -40°C to 105°C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

Low-Side Gate Drivers (DRLx Pins)
VOH,DRL High-level output voltage IDRLx = -50mA VP−0.5 VP−0.25 V
VOL,DRL Low-level output voltage IDRLx = 50mA 0.175 0.35 V
IOHPK,DRL High-level pulsed peak source current 10µs pulse -1.5 A
IOLPK,DRL Low-level pulsed peak sink current 10µs pulse 1.5 A
High-Side Gate Drivers (DRHx, DRBx and DRSx Pins)
Repetitive, 10µs pulse -5 40
VDRS Level-shift driver source voltage range V
Steady state 0 40
Repetitive, 10µs pulse 3 52
VDRB Bootstrap pin voltage range V
Steady state 5.2 52
VBS;DRB Bootstrap supply voltage range VDRBx, relative to respective VDRSx 5.2 16 V
VDRBx rising, relative to respective
VUVLO;DRB Bootstrap UVLO threshold 3.5 4.5 V
VDRSx, hysteresis= 1V
Gate Driver Disabled 23 35
IBS;DRB Bootstrap circuit supply current µA
Gate Driver Enabled 30 45
Gate Driver Disabled 0.5 10
IOS;DRB Offset supply current µA
Gate Driver Enabled 0.5 10
VDRBx-
VOH;DRH High-level output voltage IDRHx = -50mA VDRBx−0.6 V
0.25
VDRSx+ VDRSx
VOL;DRH Low-level output voltage IDRHx = 50mA V
0.175 +0.35
IOHPK;DRH High-level pulsed peak source current 10µs pulse -1.5 A
IOLPK;DRH Low-level pulsed peak sink current 10µs pulse 1.5 A
High-Side and Low-Side Gate Driver Propagation Delay
Delay setting 00b 10 ns
Delay setting 01b 50 ns
tPD Propagation Delay2
Delay setting 10b 120 ns
Delay setting 11b 250 ns

2
Delay from Power Driver Propagation Delay

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
47 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

12.5 Typical Performance Characteristics

(VP = 12V, VSYS = 5V and TA = 25°C unless otherwise specified.)

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
48 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Typical Performance Characteristics (Continued)

(VP = 12V, VSYS = 5V and TA = 25°C unless otherwise specified.)

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
49 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

13 ADC WITH AUTO-SAMPLING SEQUENCER

13.1 Block Diagram

Figure 13-1 ADC with Auto-Sampling Sequencer

ADC WITH AUTO-SAMPLING SEQUENCER

AHB/APB
ADC RESULT REGISTERS
(16)

REGISTER
REGISTER
REGISTER
REGISTER

ADx

ADC

MUX
10-BIT
CONFIGURABLE ANALOG FRONT END ADC

DIFFERENTIAL PGA
AUTO-SAMPLING
DAxP S/H SEQUENCER
MUX

ADC PRE-MUX

DIFF-PGA STATE MACHINE 0

DAxN
STATE MACHINE 1

EMUX CONTROL
VTEMP, VMON, VREF/
2
CASM

EMUX

13.2 Functional Description

13.2.1 ADC

The analog-to-digital converter (ADC) is a 10-bit succesive approximation register (SAR) ADC with 1 μs conversion time
and up to 1MSPS capability. The ADC input clock has a user-configurable divider from /1 to /8 of the system clock. The
integrated analog multiplexer allows selection from up to 6 direct ADx inputs, and from up to 10 analog inputs signals in the
Configurable Analog Front End (CAFE), including up to 3 differential input pairs. The ADC can be configured for repeating
or non-repeating conversions and can interrupt the microcontroller when a conversion is finished.

13.2.2 Auto-Sampling Sequencer

Two independent and flexible auto-sampling sequencer state machines allow signal sampling using the ADC without
interaction from microcontroller core. Each auto-sampling sequencer state machine can be programmed to take and store
up to 8 samples each in the ADC result register from different analog inputs, able to control the ADC MUX and ADC Premux
as well as the precise timing of the S/H in the Configurable analog front end. The sampling start of the auto-sampling
sequencer can be precisely triggered using timers A, B, C, or D or any of their associated PWM edges (high-to-low or low-

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
50 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

to-high). It also supports manual start or a ping-pong-scheme, where one auto-sampling sequencer state machine triggers
the other when it finishes sampling.

The auto‑sampling sequencer can interrupt the microcontroller when either conversion sequence is finished.

13.2.3 EMUX Control

A dedicated low latency interface controllable by the auto-sampling sequencer or register control allows changing the ADC
premultiplexer and asserting/deasserting the S/H circuit in the configurable analog front end, allowing back to back
conversions of multiple analog inputs without microcontroller interaction.

13.3 Electrical Characteristics

Table 13-1 ADC and Auto-Sampling Sequencer Electrical Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = -40°C to 105°C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

ADC
fADCLK ADC conversion clock input 16 MHz
tADCONV ADC conversion time fADCLK = 16MHz 1 μs
ADC resolution 10 bits
ADC effective resolution 9.2 bits
ADC differential non-linearity (DNL) ±0.5 LSB
ADC integral non-linearity (INL) ±1 LSB
ADC offset error 0.6 %FS
ADC gain error 0.12 %FS
Reference Voltage
VREFADC ADC reference voltage input 2.5 V
Sample and Hold
tADCSH ADC sample and hold time fADCLK = 16MHz 188 ns
CADCIC ADC input capacitance 1.3 pF
Input Voltage Range
VADCIN ADC input voltage range ADC multiplexer input 0 VREFADC V
EMUX Clock Speed
fEMUXCLK EMUX engine clock input 50 MHz
PLL Clock Speed
fOUTPLL PLL output frequency TA = -40°C to 85°C 3.5 100 MHz
TA = 85°C to 105°C 3.5 80 MHz

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
51 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

14 MEMORY SYSTEM
14.1 Features
• 32kB embedded FLASH
 100,000 program/erase cycles
 10 years data retention
• 8kB SRAM

14.2 Block Diagram

Figure 14-1 Memory System

MEMORY SYSTEM

INFO ROM FLASH SRAM

AHB/APB
256B INFO 1kB FLASH 8kB
ROM PAGES SRAM

14.3 Functional Description

The device has multiple banks of embedded FLASH memory, SRAM memory, as well as peripheral control registers that
are all program-accessible in a flat memory map.

14.3.1 Program and Data FLASH

32kB in 32 pages of 1kB each is available for program or data memory. Each of them can be individually erased or written
to while the microcontroller is executing a program from SRAM.

14.3.2 SRAM

Up to 8kB contiguous array of SRAM is available for non-persistent data storage. The SRAM memory supports word
(4‑byte), half-word (2-byte) and byte address aligned access. The microcontroller may execute code out of SRAM for time-
critical applications, or when modifying the contents of FLASH memory.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
52 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

14.4 Electrical Characteristics

Table 14-1 Memory System Electrical Characteristics

(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = -40°C to 105°C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

Embedded FLASH
tREAD;FLASH FLASH read time 40 ns
tWRITE;FLASH FLASH write time 20 μs
tPERASE;FLASH FLASH page erase time 10 ms
NPERASE;FLASH FLASH program/erase cycles 100k cycles
tDR;FLASH FLASH data retention 10 years
SRAM
tSRAM SRAM access cycle time 20 ns

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
53 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

15 CLOCK CONTROL SYSTEM

15.1 Features
• Ring oscillator with 7.5MHz, 9.6MHz, 13.8MHz, and 25.7MHz settings
• High accuracy 2% trimmed 4MHz RC oscillator
• Crystal oscillator driver supporting 2MHz to 10MHz crystals
• External clock input up to 40MHz
• PLL with 1MHz to 25MHz input, and 3.5MHz to 100MHz output
• /1 to /8 clock divider for HCLK
• /1 to /128 clock divider for ACLK

15.2 Block Diagram

Figure 15-1 Clock Control System

CLOCK CONTROL SYSTEM

FRCLK
DIV RTC

DIV WDT

DIV WIC

CLOCK
DIV ADC
GATING

DIV SYSTICK

CORTEX M0

CLOCK SOURCES PLL CLOCK TREE

SRAM
RING
OSCILLATOR
FLASH
FCLK
FRCLK

2% RC
DIV UART
MUX

OSCILLATOR HCLK CLOCK

DIV
MUX

GATING
PLL
EXTCLK
DIV I2C
XIN
CRYSTAL ACLK
DIV
DRIVER SOC BUS
XOUT DIV
BRIDGE

DIV SPI

DIV ADC EMUX

TIMERS A, B, C & D

CLOCK DIV TIMER

GATING

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
54 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

15.3 Functional Description

The PAC clock control system covers a wide range of applications.

15.3.1 Free Running Clock (FRCLK)

The free running clock (FRCLK) is generated from one of the 4 clock sources: ring oscillator, trimmed RC oscillator, crystal
driver or external clock input. The FRCLK is used for the real-time clock (RTC), watchdog timer (WDT), input to the PLL, or
FCLK source to clock the system in low power and sleep mode.

15.3.2 Fast Clock (FCLK)

The fast clock (FCLK) is generated from the PLL or supplied by the FRCLK directly. The FCLK supplies the watchdog timer
(WDT), ADC, wake-up interrupt controller (WIC), SysTick timer, Arm® Cortex®-M0 peripheral high speed clock (HCLK) and
low speed clock (LSCLK).

15.3.3 High-Speed Clock (HCLK)

The high-speed clock (HCLK) is derived from the FCLK with a /1, /2, /4 or /8 divider. It supplies the peripheral AHB/APB
bus, Timers A to D, dead-time controllers, SPI interface, I2C interface, UART interface, EMUX interface, SOC bus bridge
and memory subsystem, and can go as high as 50MHz.

15.3.4 Auxiliary Clock (ACLK)

The auxiliary clock (ACLK) is derived from FCLK with a /1, /2, to /128 divider, and supplies the timer and dead‑time blocks.
It can be clocked faster or slower than HCLK and can go as high as 100MHz.

15.3.5 Clock Gating

The clock tree supports clock gating in deep-sleep mode for the timer block, ADC, SPI interface, I2C interface, UART
interface, memory subsystem and the Arm® Cortex®-M0 itself.

15.3.6 Ring Oscillator (ROSC)

The integrated ring oscillator provides 4 different clocks with 7.5MHz, 9.6MHz, 13.8MHz, and 25.7MHz settings. After reset,
the clock tree always defaults to this clock input with the lowest frequency setting.

15.3.7 Trimmed 4MHz RC Oscillator

The 2% trimmed 4MHz RC oscillator provides an accurate clock suitable for many applications. It is also used to derive the
clock for the Multi-Mode Power Manager.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
55 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

15.3.8 Internal Slow RC Oscillator

An internal 32kHz RC oscillator is used during start up to provide an initial clock to analog circuitry. It is not used as a clock
input to the clock tree.

15.3.9 Crystal Oscillator Driver

The optional crystal oscillator driver can drive crystals from 2MHz to 10MHz to provide a highly accurate and stable clock
into the system.

15.3.10 External Clock Input

The clock tree can be supplied with an external clock up to 10MHz.

15.3.11 PLL
The integrated PLL input clock is supplied by the FRCLK with an input frequency range of 1MHz to 25MHz. The PLL output
frequency is adjustable from 3.5MHz to 100MHz.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
56 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

15.4 Electrical Characteristics

Table 15-1 Clock Control System Electrical Characteristics

(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = -40°C to 105°C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

Clock Tree (FRCLK, FCLK, HCLK, and ACLK)
fFRCLK Free running clock frequency 50 MHz
fFCLK Fast clock frequency 100 MHz
fHCLK High-speed clock frequency 50 MHz
fACLK Auxiliary clock frequency 100 MHz
Internal Oscillators
Frequency setting = 11b 7.5
Frequency setting = 10b 9.6
fROSC Ring oscillator frequency MHz
Frequency setting = 01b 13.8
Frequency setting = 00b 25.7
TA = 25°C -2% 4 2%
fTRIM Trimmed RC oscillator frequency MHz
TA = -40°C to 105°C -3% 4 3%
Trimmed RC oscillator clock jitter TA = -40°C to 85°C 0.5 %
Crystal Oscillator Driver
VIH;XIN XIN high-level input voltage 0.65•VCC18 V
VIL;XIN XIN low-level input voltage 0.35•VCC18 V
fXTAL Crystal oscillator frequency range 2 10 MHz
fXTAL = 2MHz to 3MHz 25
Recommended capacitive load fXTAL = 3MHz to 6MHz 20 pF
fXTAL = 6MHz to 10MHz 16
fXTAL = 2MHz to 3MHz 1000
External circuit ESR fXTAL = 3MHz to 6MHz 400 Ω
fXTAL = 6MHz to 10MHz 100
External Clock Input
fEXTCLK External clock input frequency range 40 MHz
tHIGH;EXTCLK External clock high time 10 ns
tLOW;EXTCLK External clock low time 10 ns
PLL
fINPLL PLL input frequency range 2 25 MHz
fOUTPLL PLL output frequency range 3.5 100 MHz
PLL settling time 0.5 ns
RMS 30
PLL period jitter ps
Peak to peak ±150

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
57 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

16 ARM® CORTEX®-M0 MICROCONTROLLER CORE

16.1 Features
• Arm® Cortex®-M0 core
• Fast single-cycle 32-bit x 32-bit multiplier
• 24-bit SysTick timer
• Up to 50MHz operation
• Serial wire debug (SWD), with 4 break-point and 2 watch-point unit comparators
• Nested vectored interrupt controller (NVIC) with 25 external interrupts
• Wake-up interrupt controller (WIC) with GPIO, real-time clock (RTC) and watchdog timer (WDT) interrupts enabled
• Sleep and deep-sleep mode with clock gating

16.2 Block Diagram

Figure 16-1 Arm Cortex-M0 Microcontroller Core

ARM® CORTEX®-M0 MICROCONTROLLER CORE

AHB/APB
NESTED
SWDCL SERIAL WIRE ARM® 1-CYCLE WAKE-UP
24-BIT VECTORED
DEBUG WITH CORTEX®- 32X32
SYSTICK INTERRUPT
INTERRUPT
SWDDA DISABLE M0 MULTIPLIER CONTROLLER
CONTROLLER

16.3 Functional Description

The Arm® Cortex®-M0 microcontroller core is configured for little endian operation and includes the fast single‑cycle 32-bit
multiplier and 24-bit SysTick timer and can operate at a frequency of up to 50MHz.

The microcontroller nested vectored interrupt controller (NVIC) supports 25 external interrupts for the device's peripherals
and sub-systems. For low-latency interrupt processing, the NVIC also supports interrupt tail-chaining. The wake-up interrupt
controller (WIC) is able to wake up the device from low-power modes using any GPIO interrupt, as well as from the RTC or
WDT. The Arm® Cortex®-M0 supports both sleep and deep-sleep low-power modes. The deep-sleep mode supports clock
gating to limit standby power even further.

Firmware debug support includes 4 break-point and 2 watch-point unit comparators using the serial wire debug (SWD)
protocol. The serial wire debug mechanism can be disabled to prevent device access to the firmware in the field.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
58 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

16.4 Electrical Characteristics

Table 16-1 Microcontroller and Clock Control System Electrical Characteristics

(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = -40°C to 105°C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

Microcontroller
fHCLK HCLK 50 MHz
clock
fFRCLK = fHCLK = fACLK = ROSC 11b, PLL disabled, CPU halt; other
2.5(1) 3.4 7
clock sources, ADC, timers, and serial interface disabled
fFRCLK = fHCLK = fACLK = ROSC 10, PLL disabled, CPU halt; other
3.0(1) 4 7.8
clock sources, ADC, timers, and serial interface disabled
fFRCLK = fHCLK = fACLK = ROSC 01, PLL disabled, CPU halt; other
4.1(1) 5.3 9.5
clock sources, ADC, timers, and serial interface disabled
fFRCLK = fHCLK = fACLK = ROSC 00, PLL disabled, CPU halt; other
VSYS operating 7.4(1) 9 15
IOP;VSYS clock sources, ADC, timers, and serial interface disabled mA
supply current
fFRCLK = fHCLK = fACLK = CLKREF, PLL disabled, CPU halt; other
1.5(1) 2.3 4.4
clock sources, ADC, timers, and serial interface disabled
fFRCLK = fHCLK = fACLK = 10MHz XTAL, PLL disabled, CPU halt;
3.6(1) 4.5 6.7
other clock sources, ADC, timers, and serial interface disabled
fFRCLK = 4MHz CLKREF, fHCLK = 50MHz, fACLK = fOUTPLL = 100MHz,
CPU halt; other clock sources, ADC, timers, and serial interface 20.9(1) 23.3 26.5
disabled
VCCIO quiescent
IQ;VCCIO 0.02 mA
supply current

(1) All minimum operating supply current values are for room temperature only

16.5 Typical Performance Characteristics

(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = 25°C unless otherwise specified.)

IVCC18 vs. PLL Frequency

25
PACMCU-001

20
fHCLK = fACLK = fOUTPLL
IVCC18 (mA)

15
fHCLK = 0.5•fOUTPLL,
fACLK = fOUTPLL
10

0
0 20 40 60 80 100
PLL Frequency (MHz)

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
59 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

17 I/O CONTROLLER
17.1 Features
• 5V-compliant I/O PAx, PDx, PEx
• 3.3V-compliant I/O PCx
• Configurable drive strength on PAx, PDx, PEx
• Configurable pull-up or pull-down on PAx, PDx, PEx

17.2 Block Diagram

Figure 17-1 I/O Controller

DIGITAL I/O

GPIO (PAx, PDx, PEx)

VCCIO (5V/3.3V)
PERIPHERAL
PULL UP
GPIO INPUT

PAx, PDx, PEx VCCIO (5V/3.3V)

PULL DOWN PERIPHERAL

GPIO OUTPUT

OUTPUT ENABLE

DRIVE STRENGTH

GPIO (PCx)

ADC MUX

GPIO INPUT

INPUT ENABLE
PCx VCC33 (3.3V)
AHB/APB

GPIO OUTPUT

OUTPUT ENABLE

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
60 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

17.3 Functional Description

The PAC can support up to 4 ports with 8 I/Os each from PAx, PCx, PDx, and PEx, in addition to the I/Os on the analog
front end. All PAx, PCx, PDx, and PEx ports have interrupt capability with configurable interrupt edge.

PAx, PDx, and PEx I/Os use VCCIO as the I/O supply voltage that is 5V on default parts (and 3.3V available from factory).
The drive current can be configured as 8mA or 16mA. They also support weak pull-up and pull-down to save external
components.

PCx uses VCC33 as its I/O supply voltage. The drive current is fixed to 8mA. PC0 to PC5 are also associated with analog
inputs AD0 to AD5 to the ADC.

17.4 GPIO Current Injection

Under normal operation, there should not be current injected into the GPIOs on the device due to the GPIO voltage below
ground or above the GPIO supply.3 Current injected occurs when the GPIO pin voltage is less than -0.3V or when greater
than GPIO supply + 0.3V.

In order provide a robust solution when this situation occurs, this device allows a small amount of injected current into the
GPIO pins, to avoid excessive leakage or device damage.

For information on the GPIO current injection thresholds, see the absolute maximum parameters for this device.

Sustained operation with the GPIO pin voltage greater than the GPIO supply or when the GPIO pin voltage is less than -
0.3V may result in reduced lifetime of the device. GPIO current injection should only be a temporary condition.

3
VCC33 is the supply for any PC GPIO pin and VCCIO is the supply for any other GPIO pins.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
61 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

17.5 Electrical Characteristics

Table 17-1 I/O Controller Electrical Characteristics

(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = -40°C to 105°C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

PAx, PDx, PEx (5V Operation)
VIH High-level input voltage VCCIO = 5V 3 V
VIL Low-level input voltage VCCIO = 5V 0.8 V

VCCIO = 5V, Drive strength setting = 0b 7

IOL Low-level output sink current mA
VOL = 0.4V Drive strength setting = 1b 15

VCCIO = 5V, Drive strength setting = 0b -7

IOH High-level output source current mA
VOH = 2.4V Drive strength setting = 1b -15
RPU Weak pull-up resistance VCCIO = 5V 53 66 87 kΩ
RPD Weak pull-down resistance VCCIO = 5V 63 108 244 kΩ
IIL Input leakage current TA = 125°C -10 0 10 μA
PAx, PDx, PEx (3.3V Operation)
VIH High-level input voltage VCCIO = 3.3V 2 V
VIL Low-level input voltage VCCIO = 3.3V 0.8 V

VCCIO = 3.3V, Drive strength setting = 0b 4

IOL Low-level output sink current mA
VOL = 0.4V Drive strength setting = 1b 8

VCCIO = 3.3V, Drive strength setting = 0b -4

IOH High-level output source current mA
VOH = 2.4V Drive strength setting = 1b -8
RPU Weak pull-up resistance VCCIO = 3.3V 47 74 104 kΩ
RPD Weak pull-down resistance VCCIO = 3.3V 50 84 121 kΩ
IIL Input leakage current TA = 125°C -10 0 10 μA
PCx (3.3V Operation)
VIH High-level input voltage VCC33 = 3.3V 2 V
VIL Low-level input voltage VCC33 = 3.3V 0.8 V
IOL Low-level output sink current VCC33 = 3.3V, VOL = 0.4V 7 mA
IOH High-level output source current VCC33 = 3.3V, VOH = 2.4V -7 mA
IIL Input leakage current TA = 125°C -10 0 10 μA

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
62 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

18 SERIAL INTERFACE
18.1 Block Diagram

Figure 18-1 Serial Interface

SERIAL INTERFACE

I2C

I2C
SCL MASTER

SDA
I2C
SLAVE

UART

TX
16550-COMPATIBLE
UART
RX

AHB/APB
SPI

SPICLK
SPI
SPIMISO MASTER

SPIMOSI

SPI
SLAVE
SPICS0, 1, 2

18.2 Functional Description

The device has up to three serial interfaces: I2C, UART, and SPI.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
63 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

18.2.1 I2C Controller

The I2C controller is a configurable peripheral that can support various modes of operation:

• I2C master operation

 Normal mode (100kHz), fast mode (400kHz), or fast mode plus (1MHz)
 Single and multi-master
 Synchronization (multi-master)
 Arbitration (multi-master)
 7-bit or 10-bit slave addressing

• I2C slave operation

 Normal mode (100kHz), fast mode (400kHz), or fast mode plus (1MHz)
 Clock stretching
 7-bit or 10-bit slave addressing

The I2C peripheral may operate either by polling, or can be configured to be interrupt driven for both receive and
transmit data.

18.3 UART Controller

The UART peripheral is a configurable peripheral that can support various features and modes of operation:

• Programmable clock selection

• National Instruments PC16550D compatible
• 16-deep transmit and receive FIFO and fractional clock divisor
• Up to 3.125Mbps communication speed (with HCLK = 50MHz)

The UART peripheral may operate either by polling, or can be configured to be interrupt driven for both receive and
transmit data.

18.4 SPI Controller

The device contains an SPI controller that can each be used in either master or slave operation, with the following features:

• SPI master operation

 Control of up to three different SPI slaves
 Operation up to 25MHz
 Flexible multiple transmit mode for variable-size SPI data with user-defined chip-select behavior
 Chip select “shaping” through programmable additional delay for chip-select setup, hold and wait time for
back-to-back transfers

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
64 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

• SPI master or slave operation

 Supports clock phase and polarity control
 Data transmission/reception can be on 8-, 16-, 24- or 32-bit boundary
 Selectable data bit ordering (LSB or MSB first)
 Programmable chip select polarity
 Selectable “auto-retransmit” mode

The SPI peripheral may operate either by polling, or can be configured to be interrupt driven for both receive and
transmit data.

18.5 Dynamic Characteristics

Table 18-1 Serial Interface Dynamic Characteristics
(VSYS = VCCIO = 5V, VCC33 = 3.3V, VCC18 = 1.8V, and TA = -40°C to 105°C unless otherwise specified.)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

I2 C

Standard mode (100kHz) 2.8 MHz

fI2CCLK I2C input clock frequency Fast mode (400kHz) 2.8 MHz

Fast mode plus (1MHz) 6.14 MHz

UART

fUARTCLK UART input clock frequency fHCLK/16 MHz

UART baud rate fHCLK = 50MHz 3.125 Mbps

SPI

Master mode fHCLK/2 MHz

fSPICLK SPI input clock frequency
Slave mode fHCLK/2 MHz

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
65 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Table 18-2 I2C Dynamic Characteristics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

Standard mode 0 100
fSCL SCL clock frequency Fast mode 0 400 kHz
Fast mode plus 0 1000
Standard mode 4.7
tLOW SCL clock low Fast mode 1.3 μs
Fast mode plus 0.5
Standard mode 4.0
tHIGH SCL clock high Fast mode 0.6 μs
Fast mode plus 0.26
Standard mode 4.0
Hold time for a repeated
tHD;STA Fast mode 0.6 μs
START condition
Fast mode plus 0.26
Standard mode 4.7
Set-up time for a repeated
tSU;STA Fast mode 0.6 μs
START condition
Fast mode plus 0.26
Standard mode 0 3.45
tHD;DAT Data hold time Fast mode 0 0.9 μs
Fast mode plus 0
Standard mode 250
tSU;DAT Data set-up time Fast mode 100 ns
Fast mode plus 50
Standard mode 4.0
tSU;STO Set-up time for STOP condition Fast mode 0.6 μs
Fast mode plus 0.26
Standard mode 4.7
Bus free time between a STOP
tBUF Fast mode 1.3 μs
and START condition
Fast mode plus 0.5
Standard mode 1000
tr Rise time for SDA and SCL Fast mode 20 300 ns
Fast mode plus 120
Standard mode 300
tf Fall time for SDA and SCL Fast mode 300 ns
Fast mode plus 120
Standard mode, Fast
Capacitive load for each 400 pF
Cb mode
bus line
Fast mode plus 550 pF

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
66 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Figure 18-2 I2C Timing Diagram

tHD;STA tSU;DAT tSU;STA tr tf tBUF

SDA

tHD;DAT tf tr tSU;STO

SCL

S tLOW tHIGH Sr P S

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
67 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Table 18-3 SPI Dynamic Characteristics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

tSCLK;HIGH SPICLK Input High Time 30 ns
tSCLK;LOW SPICLK Input Low Time 30 ns
tSS;SCLK SPICSn to SPICLK Time 120 ns
tSS;MOSI SPICSn to SPIMISO High-impedance time 10 50 ns
tr(SCLK) SPICLK Rise Time 10 25 ns
SPICLK = 25MHz
tf(SCLK) SPICLK Fall Time 10 25 ns
tr(MOSI) SPIMISO Rise Time 10 25 ns
tf(SMOSI) SPIMISO Fall Time 10 25 ns
tSU;MISO SPIMISO Setup Time 20 ns
tH;MISO SPIMISO Hold Time 20 ns

Figure 18-3 SPI Timing Diagram

SPICSn

tSS;CLK tf(SCLK)
tSCLK;LOW tSCLK;HIGH tSS;MOSI

SPICLK
[SPICFG.RCVCP = 0b]

SPICLK
[SPICFG.RCVCP = 1b]

tr(SCLK)

SPIMOSI

tr(MOSI)
tf(MOSI)

SPIMISO

tSU;MISO
tH;MISO

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
68 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

19 TIMERS
19.1 Block Diagram

Figure 19-1 Timers A, B, C, and D

TIMERS A, B, C, AND D

TIMER A PWM

SYNC
CAPTURE & TIMER A
PWMA0, PWMA1, COMPARE 16-BIT
PWMA2, PWMA3 DEAD TIME
PWMA4, PWMA5, GENERATOR
PWMA6, PWMA7 CAPTURE &
COMPARE

TIMER B PWM

CAPTURE & TIMER B

COMPARE 16-BIT
PWMB0
DEAD TIME
GENERATOR
PWMB1
CAPTURE &
COMPARE

TIMER C PWM

CAPTURE & TIMER C

COMPARE 16-BIT
PWMC0
DEAD TIME
GENERATOR
PWMC1
CAPTURE &
COMPARE

AHB/APB

TIMER D PWM

CAPTURE & TIMER D

COMPARE 16-BIT
PWMD0
DEAD TIME
GENERATOR
PWMD1
CAPTURE &
COMPARE

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
69 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Figure 19-2 AFE Watchdog and Wake-Up Timer

AFE WATCHDOG AND WAKE-UP TIMER

AHB/APB
CAFE

AFE WAKE-UP SOC BUS

WATCHDOG TIMER BRIDGE

Figure 19-3 Real-Time Clock and Watchdog Timer

REAL-TIME CLOCK AND WATCHDOG TIMER

RTC
24-BIT

AHB/APB
WDT
24-BIT

19.2 Functional Description

The device includes 9 timers: timer A, timer B, timer C, timer D, watchdog timer 1 (WDT), watchdog timer 2, wake-up timer,
real-time clock (RTC), and SysTick timer. The device supports up to 14 different PWM signals and has up to 7 dead-time
controllers. Timers A, B, C and D can be concatenated to synchronize to a single clock and start/stop signal for applications
that require a synchronized timer period between timers.

19.2.1 Timer A

Timer A is a general purpose 16-bit timer with 8 PWM/capture and compare units. It has 4 pairs of PWM signals going into
4 dead-time controllers. Timer A can be concatenated with timers B, C, and D to synchronize the PWM/capture and compare
units. It can use either ACLK or HCLK as clock input with an additional clock divider from /1 to /128.

19.2.2 Timer B

Timer B is a general purpose 16-bit timer with 2 PWM/capture and compare units. It has one pair of PWM signals going into
one dead-time controller, as well as 2 additional compare units that can be used for additional system time bases for
interrupts. Timer B can be concatenated with timers A, C, and D to synchronize the PWM/capture and compare units. It can
use either ACLK or HCLK as clock input with an additional clock divider from /1 to /128.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
70 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

19.2.3 Timer C

Timer C is a general purpose 16-bit timer with 2 PWM/capture and compare units. It has one pair of PWM signals going into
one dead-time controller. Timer C can be concatenated with timers A, B, and D to synchronize the PWM/capture and
compare units. It can use either ACLK or HCLK as clock input with an additional clock divider from /1 to /128.

19.2.4 Timer D

Timer D is a general purpose 16-bit timer with 2 PWM/capture and compare units. It has one pair of PWM signals going into
one dead-time controller. Timer D can be concatenated with timers A, B, and C to synchronize the PWM/capture and
compare units. It can use either ACLK or HCLK as clock input with an additional clock divider from /1 to /128.

19.2.5 Watchdog Timer

The 24-bit watchdog timer (WDT) can be used for long time period measurements or periodic wake up from sleep mode.
The watchdog timer can be used as a system watchdog, or as an interval timer, or both. The watchdog timer can use either
FRCLK or FCLK as clock input with an additional clock divider from /2 to /65536.

19.2.6 CAFE Watchdog Timer

There is a second watchdog timer in the AFE that can be used to monitor communication between the MCU and AFE on
the PAC SOC bus. If this timer expires, it will trigger a device reset when there is no communication for a period of either
4s or 8s.

19.2.7 Wake-Up Timer

The wake-up timer can be used for very low power hibernate and sleep modes to wake up the micro controller periodically.
It can be configured to be 125ms, 250ms, 500ms, 1s, 2s, 4, or 8s.

19.2.8 Real-Time Clock

The 24-bit real-time clock (RTC) can be used for time measurements when an accurate clock source is used. This timer
can also be used for periodic wake up from sleep mode. The RTC uses FRCLK as clock input with an additional clock
divider from /2 to /65536.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
71 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

20 THERMAL CHARACTERISTICS
Table 20-1 Thermal Characteristics

PARAMETER VALUE UNIT

Operating ambient temperature range -40 to 105 C
Operating junction temperature range -40 to 125 C
Storage temperature range -55 to 150 C
Lead temperature (Soldering, 10 seconds) 300 C
Junction-to-case thermal resistance (θJC) 2.897 C/W
Junction-to-ambient thermal resistance (θJA) 23.36 C/W

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
72 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

21 APPLICATION EXAMPLES
The following simplified diagrams show different examples of PAC applications. Refer to application notes for detailed
design description.

Figure 21-1 3-Phase Motor Drive Using PAC5222 (Simplified Diagram)

VHM

VBAT
PAC5222 DRM

INTERFACE

GPIO
MONITORING CSM
SIGNALS VP
VP

DRBx

DRHx

DRSx
M

DRLx

DAxP, DAxN

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
73 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

22 PACKAGE OUTLINE AND DIMENSIONS

22.1 TQFN66-48 Package Outline and Dimensions

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
74 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Table 22-1 Dimensions

Millimeters Inches
Dimensions Minimum Maximum Minimum Maximum
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.203 0.008
b 0.150 0.250 0.006 0.010
D 5.924 6.076 0.233 0.239
D1 4.100 4.400 0.161 0.173
E 5.924 6.076 0.233 0.239
E1 4.100 4.400 0.161 0.173
e 0.400 0.016
L 0.324 0.476 0.013 0.019
K 0.200 0.008

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
75 of 76 www.qorvo.com
 PAC5222
®
Power Application Controller

Product Compliance
This part complies with RoHS directive 2011/65/EU as amended by (EU) 2015/863.

This part also has the following attributes:

• Lead Free
• Halogen Free (Chlorine, Bromine)
Pb

Contact Information
For the latest specifications, additional product information, worldwide sales and distribution locations:
Web: www.qorvo.com Tel: 1-844-890-8163
Email: [email protected]

For technical questions and application information:

Email: [email protected]

Important Notice
The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information contained
herein and assumes no responsibility or liability whatsoever for the use of the information contained herein. All information contained
herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for
Qorvo products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any
patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by
such information. THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED
HEREIN, AND QORVO HEREBY DISCLAIMS ANY AND ALL WARRANTIES WITH RESPECT TO SUCH PRODUCTS WHETHER
EXPRESS OR IMPLIED BY LAW, COURSE OF DEALING, COURSE OF PERFORMANCE, USAGE OF TRADE OR OTHERWISE,
INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.

Without limiting the generality of the foregoing, Qorvo products are not warranted or authorized for use as critical components in medical,
life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal
injury or death.

Copyright 2019 © Qorvo, Inc. | Qorvo®, Active-Semi®, Power Application Controller®, Multi-Mode Power Manager™, Configurable Analog
Front End™ and Application Specific Power Drivers™ are trademarks of Qorvo, Inc.

Arm® and Cortex® are registered trademarks of Arm Limited. All referenced brands and trademarks are the property of their respective
owners.

Data Sheet Rev. 2.6, November 3, 2020

Subject to change without notice
76 of 76 www.qorvo.com