Module-3

Semiconductor Memories:
• Introduction,
• Dynamic Random Access Memory (DRAM)
• Static Random Access Memory (SRAM),
• Nonvolatile Memory,
• Flash Memory,
• Ferroelectric Random Access Memory (FRAM)
(10.1 to 10.6 of TEXT2)
10.1 Introduction
• Design issue
• Area efficiency cost per bit
• Access time speed
• Power consumption
Overview of semiconductor memory types.
A typical memory array organization
10.2. Read-Only Memory (ROM) Circuits
A 4-bit x 4-bit NOR-based ROM array.

• If no active transistor exists at the cross point, the column

voltage is pulled high by the pMOS load device.
• Thus, a logic " 1 "-bit is stored as the absence of an active
transistor, while a logic “0"-bit is stored as the presence of an
active transistor at the crosspoint.
10.2. Read-Only Memory (ROM) Circuits
A 4-bit x 4-bit NOR-based ROM array.

• The read-only memory array can also be seen as a simple

combinational Boolean network which produces a specified output
value for each input combination ,i.e., for each address.
• Thus, storing binary information at a particular address location
can be achieved by the presence or absence of a data path from
the selected row (word line) to the selected column (bit line),
which is equivalent to the presence or absence of a device at that
particular location. In the following, we will examine two different
implementations for MOS ROM arrays.
• Consider first the 4-bit x4-bit memory array shown in Fig. 10.3.
Here, each column consists of a pseudo-nMOS NOR gate driven by
some of the row signals, i.e., the word lines.
A 4-bit x 4-bit NOR-based ROM array.

In actual ROM layout, the array can be initially manufactured with nMOS
transistors at every row-column intersection.
The " 1 "-bits are then realized by omitting the drain or source connection, or the
gate electrode of the corresponding nMOS transistors in the final metallization
step.
A 4-bit x 4-bit NOR-based ROM array.

• Figure 10.5 shows a larger portion of the ROM array, except for the pMOS load
transistors connected to the metal columns.
• Note that only 8 of the 16 nMOS transistors fabricated in this structure are actually
connected to the bit lines via metal-to-diffusion contacts.
• In reality, the metal column lines are laid out directly on top of diffusion columns to
reduce the horizontal dimension of the ROM array.
A 4-bit x 4-bit NOR-based ROM array.

• A different NOR ROM layout implementation is based on deactivation of the nMOS

transistors by raising their threshold voltages through channel implants.
• Figure 10.6shows the circuit diagram of a NOR ROM array in which every two rows of
nMOS transistors share a common ground connection, and every drain diffusion
contact to the metal bit line is shared by two adjacent transistors.
• In this case, all nMOS transistors are already connected to the column lines (bit lines);
therefore, storing a " 1 "-bit at a particular location by omitting the corresponding
drain contact is not possible.
• Instead, the nMOS transistor corresponding to the stored " 1 "-bit can be
deactivated, i.e., permanently turned off, by raising its threshold voltage above the
VOH level through a selective channel implant during fabrication.
A 4-bit x 4-bit NOR-based ROM array.

• Note that in this case, each threshold voltage implant signifies a stored "1"-bit, and all
other (non-implanted) transistors correspond to stored "0"-bits.
• Since each diffusion-to-metal contact in this structure is shared by two adjacent
transistors, the implant-mask ROM layout can yield a higher core density, i.e., a
smaller silicon area per stored bit, compared to the contact mask ROM layout.
A 4-bit x 4-bit NAND-based ROM array.
A 4-bit x 4-bit NAND-based ROM array.
Design of Row and Column Decoders

• Now we will turn our attention to the circuit structures of row and
column address decoders, which select a particular memory location in
the array, based on the binary row and column addresses.
• A row decoder designed to drive a NOR ROM array must, by definition,
select one of the 2 word lines by raising its voltage to VOH.
• consider the simple row address decoder shown in Fig. 10.10, which
decodes a two-bit row address and selects one out of four word lines
by raising its level.
Design of Row and Column Decoders

• A most straightforward implementation of this decoder is another NOR

array, consisting of 4 rows (outputs) and 4 columns (two address bits and
their complements).
• Note that this NOR-based decoder array can be built just like the NOR
ROM array, using the same selective programming approach (Fig. 10.11).
• The ROM array and its row decoder can thus be fabricated as two
adjacent NOR arrays, as shown in Fig. 10.12.
Design of Row and Column Decoders
 Design of Row and Column Decoders

• The column decoder circuitry is designed to select one out of 2M bit lines (columns)
• of the ROM array according to an M-bit column address, and to route the data content
of the selected bit line to the data output.
• A straightforward but costly approach would be to connect an nMOS pass transistor to
each bit-line (column) output, and to selectively drive one out of 2M pass transistors by
using a NOR-based column address decoder, as shown in Fig. 10.14.
• In this arrangement, only one nMOS pass transistor is turned on at a time, depending on
the column address bits applied to the decoder inputs.
• The conducting pass transistor routes the selected column signal to the data output.
Similarly, a number of columns can be chosen at a time, and the selected columns can be
routed to a parallel data output port.
Design of Row and Column Decoders
10.3. Static Read-Write Memory (SRAM) Circuits

• Read-write (R/W) memory circuits are designed to permit the modification

(writing) of data bits to be stored in the memory array, as well as their
retrieval (reading) on demand.
• The memory circuit is said to be static if the stored data can be retained
indefinitely (as long as a sufficient power supply voltage is provided),
without any need for a periodic refresh operation.
• We will examine the circuit structure and the operation of simple SRAM
cells, as well as the peripheral circuits designed to read and write the data.
• The data storage cell, i.e., the 1-bit memory cell in static RAM arrays,
invariably consists of a simple latch circuit with two stable operating points
(states).
• Depending on the preserved state of the two-inverter latch circuit, the data
being held in the memory cell
10.3. Static Read-Write Memory (SRAM) Circuits

• Will be interpreted either as a logic "0" or as a logic " 1."

• To access (read and write) the data contained in the memory
cell via the bit line, we need at least one switch, which is
controlled by the corresponding word line, i.e., the row
address selection signal (Fig. 10.21(a)).
• Usually, two complementary access switches consisting of
nMOS pass transistors are implemented to connect the 1-bit
SRAM cell to the complementary bit lines (columns).
• This can be likened to turning the car steering wheel with
both left and right hands in complementary directions.
 10.3. Static Read-Write Memory (SRAM) Circuits

Figure 10.21. Various configurations of the static RAM cell. (a) Symbolic representation
of the two-inverter latch circuit with access switches. (b) Generic circuit topology of the
MOS static RAM cell. (c) Resistive-load SRAM cell. (d) Depletion-load nMOS SRAM cell. (e)
Full CMOS SRAM cell.
10.3. Static Read-Write Memory (SRAM) Circuits
SRAM Operation Principles
• When the word line (RS) is not selected, i.e., when the
voltage level of line RS is equal to logic "0," the pass
transistors M3 and M4 are turned off.
• The simple latch circuit consisting of two
cross-connected inverters preserves one of its two
stable operating points; hence, data is being held.
• At this point, consider the two columns, C and C. If all
word lines in the SRAM array are inactive, the
relatively large column capacitances are
Now assume that we select the memory cell by raising its word line voltage to
logic"1," hence, the pass transistors M3 and M4 are turned on. Once the
memory cell is selected, four basic operations may be performed on this cell.
Power Consumption
• To estimate the standby power consumption of the static
read-write memory cell, assume that a " 1 -bit is stored in the
cell.
• This means that the driver transistor Ml is turned off, while the
driver transistor M2 is conducting, resulting in V = VOH and V2 =
TheVOL.
standby power dissipation of the resistive SRAM cell shown in
Fig. 10.22 becomes
Full CMOS SRAM Cell
• A low-power SRAM cell may be designed simply by using cross-coupled
CMOS inverters instead of the resistive-load nMOS inverters.
• In this case, the stand-by power consumption of the memory cell will be
limited to the relatively small leakage currents of both CMOS inverters.
• The possible drawback of using CMOS SRAM cells, on the other hand, is that
the cell area tends to increase in order to accommodate the n-well for the
pMOS transistors and the polysilicon contacts.
CMOS SRAM Cell Design Strategy
• The two basic requirements which dictate the (WIL) ratios
are: (a) the data-read operation should not destroy the
stored information in the SRAM cell, and (b) the cell should
allow modification of the stored information during the
data-write phase.
CMOS SRAM Cell Design Strategy
CMOS SRAM Cell Design Strategy
SRAM Write Circuitry
• Here, the nMOS transistors Ml and M2 are used to pull down the two column
voltages, while the transistor M3 completes the conducting path to ground.
• Note that M3 is driven by the column address decoder circuitry, i.e., M3 turns on
only when the corresponding column address is selected.
• The column pull-down transistors, on the other hand, are driven by two
pseudo-complementary control signals, WB and WB.
• The "write-enable" signal W (active low) and the data to be written (DATA) are
used to generate the control signals, as shown in the table in Fig. 10.28.
Fast Sense Amplifiers
Fast Sense Amplifiers
Fast Sense Amplifiers
Dual-Port Static RAM Arrays
Dual-Port Static RAM Arrays
10.4. Dynamic Read-Write Memory (DRAM) Circuits
• The use of a capacitor as the primary storage device generally enables the DRAM
cell to be realized on a much smaller silicon area compared to the typical SRAM
cell.
• Notice that even as the binary data is stored as charge in a capacitor, the DRAM
cell must have Access devices, or switches, which can be activated externally for
"read" and "write“ operations.
• But this requirement does not significantly affect the area advantage over the
SRAM cell, since the cell access circuitry is usually very simple.
• Also, no static power is dissipated for storing charge on the capacitance.
• Consequently, dynamic RAM arrays can achieve higher integration densities than
SRAM arrays.
• Note that a DRAM array requires additional peripheral circuitry for scheduling
and performing the periodic data refresh operations.
• The hardware overhead of the refresh circuitry, however, does not overshadow
the area advantages gained by the small cell size.
10.4. Dynamic Read-Write Memory (DRAM) Circuits
10.4. Dynamic Read-Write Memory (DRAM) Circuits
. Three-transistor DRAM cell

Figure 10.38. Typical voltage waveforms associated

Figure 10.31. Three-transistor DRAM cell with the 3-T DRAM cell during four consecutive
operations: write "1," read "1," write "0," and read
with the pull-up and read/write circuitry.
"O."
precharge cycle

Figure 10.39. Column capacitances C2 and C3

are being charged-up through MP1 and MP2
during the precharge cycle.
DRAM Read Operation
DRAM Write Operation
Asynchronous DRAM Mode(1)
Asynchronous DRAM Mode(2)
Synchronous DRAM Mode
Leakage Currents in DRAM Cells
Refresh Operation
DRAM Input/Output Circuits
DRAM Input/Output Circuits

PMOS pull-up structure NMOS pull-up structure

DRAM Decoder
Voltage Sense Amplifiers
To detect signal difference on data lines

• Popular and good common-mode rejection ratio

• Large area and large power consumption
• High speed, small area and low power
• Precharge signal required operation cannot be
reversed
 Internal Voltage Regulator Circuit

Lowering voltage to reduce power

consumption

V
INT
(internal voltage generator)reduce operating
current
Figure 10.44. (a) Typical one-transistor (1-T) DRAM cell with
its access lines. (b) SEM photograph of a stacked-capacitor
DRAM cell structure.