Memory Design

Lecture 9
  The memory is that part of the computer
where programs and data are stored.
 Without a memory from which the processors can read
and write information, there would be no stored-program
digital computers.

 Bit:
 Smallest unit for computer memory

 Byte
Definition  basic storage unit

 Word:
 a group of 16 bits
 A word refers to the basic data size or bit size that can be
processed by the arithmetic and logic unit of the
processor.
 Also refers to the size of internal ALU registers
 3

 1 or 0 = a bit smallest unit for

measuring memory capacity
 4 bits = 1 nibble
 8 bits = 1 byte basic unit for
measuring memory
Memory  16 bits = 2 bytes = 1 word
Measurement  32 bits = 4 bytes =1 double word
 64 bits = 8 bytes =1 quad word
 A paragraph is a group of
consecutive bytes in memory
 Name Size Number of bytes Comment
Bits 1 1 or 0
Nibble 4 bits
Bytes 1 byte Holds a character. Each character uses 1
byte or 8 bits
Kilobyte 1 kilobyte (KB) 1024 = 210 A kilo means a thousand, approximately
1024

Megabyte 1 megabyte (MB) 10242 = 220 Mega means a million, therefore, 1 MB

=1024 ×1024 =10242= 1 048 576 bytes
Gigabyte 1 gigabyte (GB) 10243= 230 Giga means a billion, therefore, 1 GB =
1024×1024×1024 = 10243 =1.07 ×109 bytes

Computer Terabyte 1 terabyte (TB) 10244= 240 Tera represents a trillion, therefore, 1TB =
1024×1024×1024×1024 = 10244 = 1.1×1012

memory Petabyte 1 petabyte (PB) 10245= 250 1024 TB

Exabyte 1 Exabyte (EB) 10246= 260 1024 PB

Zettabyte 1 Zettabyte (EB) 10247= 270 1024 EB

Yottabyte 1 Yottabyte (YB) 10248= 280 1024 ZB

  The function of the memory unit is to store programs
and data needed by the CPU

 There are two classes of storage, called primary and

secondary.
Memory  The Primary memory is also known as main memory
or RAM
 The Secondary memory aka backing storage/
Auxiliary memory,
  Registers
 Cache
Types of  RAM
memory  Virtual memory
 Secondary memory
  Zero access time (latency)
 Infinite capacity
Ideal Memory ?  Zero cost
 Infinite bandwidth (to support
multiple accesses in parallel)
  Ideal memory’s requirements oppose each other
 Bigger is slower
 Bigger takes longer to determine the location

 Faster is more expensive

Problems  Memory technology: SRAM vs. DRAM vs. Disk vs. Tape

 Higher bandwidth is more expensive

 Need more banks, more ports, higher frequency, or faster
technology
  Memories vary in their design and capacity
and speed of operation
 Computers uses different types of memories
 Depending on their nearness to the CPU,
memories form a hierarchy

Memory
Hierarchy
  This Memory Hierarchy Design is divided into 2 main
types:
Concept of  External Memory or Secondary Memory Comprising
of Magnetic Disk, Optical Disk, Magnetic Tape i.e.
Hierarchical peripheral storage devices which are accessible by the
Memory processor via I/O Module.
 Internal Memory or Primary Memory Comprising of
Organization Main Memory, Cache Memory & CPU registers. Directly
accessible by the processor.
Memory
Hierarchy
Memory
Hierarchy
  If the memory type is closer to the CPU, the faster the
CPU can access the instructions and execute them, the
smaller and more expensive it is

 Each type of memory is limited by speed, size, cost

and position relative to the CPU

Memory
Hierarchy
  Capacity: As we move from top to bottom in the Hierarchy, the
capacity increases.
 Access Time: It is the time interval between the read/write
request and the availability of the data. As we move from top to
bottom in the Hierarchy, the access time increases.
 Performance: Earlier when the computer system was designed
without Memory Hierarchy design, the speed gap increases
Characteristics between the CPU registers and Main Memory due to large
difference in access time. This results in lower performance of the
of Memory system and thus, enhancement was required. This enhancement
was made in the form of Memory Hierarchy Design because of
Hierarchy which the performance of the system increases. One of the most
significant ways to increase system performance is minimizing
how far down the memory hierarchy one has to go to manipulate
data.
 Cost per bit: As we move from bottom to top in the Hierarchy, the
cost per bit increases i.e. Internal Memory is costlier than External
Memory
  Semiconductor memory
 Main memory for storing instructions and data during
program execution
 Data is stored and read many times to and from this type of
memory.
 RAM size is measured in Gigabytes
RAM- Random  Typical computers might have the following RAM size
 Rasberry Pi 512 MB
Access Memory  Smart phone 2 GB
 Laptop 4GB
 RAM can be byte or word addressable i.e. each RAM
location can hold a single byte or two bytes of information
 8086 is byte addressable i.e. the word size is 8 bits
 Each memory location has a unique address
Block Diagram
for a typical
RAM Chip
  CS1 – Chip Select 1
 CS2 – Chip Select 2
 RD- Read
 WR – Write
RAM Chip  AD7- 7- bit address
 Number of memory addresses = 27 = 128
  The word size is the number of bits the CPU can
manipulate at once
Word Size  A 32-bit bit machine can process 32-bits using one
single machine code instruction.
  Random access memory (RAM)
Memory  Sequential access memory (SAM)
Classification
 Direct access memory (DAM)
 Contents addressable memory (CAM)
  Data access time is
independent to the physical
location
 Random access memories are
RAM further classified as
 Read-Write memories
(RAM)
 Read only memories (ROM)
  Form of semiconductor memory used in
PCs and workstations as main memory for
the computer
 Each one-bit memory cell uses a
capacitor for data storage
 Capacitor charge state indicates stored
value
DRAM  Whether the capacitor is charged or
discharged indicates storage of 1 or 0
 Capacitors do not hold charge indefinitely
 Capacitors leak there is need for refresh
the contents of memory periodically
every few seconds (Volatile)
 Need for refresh circuits
  SDRAM: Synchronous DRAM.
 semiconductor memory faster than conventional
DRAM.
 It is synchronised to the clock of the processor and is
capable of keeping two sets of memory addresses open
SDRAM simultaneously. By transferring data alternately from
one set of addresses, and then the other, SDRAM cuts
down on the delays associated with non-synchronous
RAM, which must close one address bank before
opening the next.
  Type of semiconductor memory
 One bit memory cells use bi-stable
memory latches/flip flops for data storage
 Two cross coupled inverters store a
single bit
 4 transistors for storage
SRAM  2 transistors for access
 No need of refresh circuits
 supports faster read and write times than
DRAM (typically 10 ns against 60 ns for
DRAM)
 Is normally used for caches
 CAPACITOR

Capacitor Versus
Transistor
TRANSISTOR
 Parameter SRAM DRAM

Location Located between main memory and CPU Found on the motherboard
external to CPU
Speed Faster because it is on chip memory. Access Slower it is off chip memory
time is less than main memory
Capacity Smaller capacity typically 1MB-16MB Higher capacity (1GB-
16GB)
Cost Expensive Cheap
Application For cache memory (L2 and L3 units) For main memory (DDR#)

SRAM versus Transistors Construction requires 6 transistors for a

single block of memory
Construction requires 1
transistor for a block of

DRAM Density Lower density and rarer (6 transistors per

memory
High density (1 transistor, 1
cell) capacitor per cell)
Manufacturin Use flip flops does not produce electric uses capacitor which
g leakage. produces leakage current and
Manufacturing requires putting capacitor needs power refresh circuitry
and logic together Manufacturing requires
putting capacitor and logic
together

Power Low power consumption uses switches High power consumption

consumption (holds charge)
  semiconductor memory technology used where the
data is written once and then not changed.
 ROM is a flash memory chip that contains a small
amount of non volatile memory
Read Only  Retains contents after computer is switched off
Memory(ROM)  Contains Basic Input Output Software(BIOS) which the
firmware for the motherboard
 BIOS contains bootstrap program which loads the
operating system
ROM chip
  A group of chips, typically 8 or 16, is mounted on a tiny
printed circuit board and sold as a unit. This unit is
called a SIMM (Single Inline Memory Module) or a
DIMM (Dual Inline Memory Module), depending on

Memory whether it has a row of connectors on one side or both

sides of the board.
Packaging and  SIMMs have one edge connector with 72 contacts and
Types transfer 32 bits per clock cycle.
 DIMMs usually have edge connectors with 84 contacts
on each side of the board, for a total of 168 contacts and
transfer 64 bits per clock cycle.
256 –MB SIMM
Chip
  PROM
 EEPROM
Types of ROM  EPROM
 FLASH MEMORY
  Programmed during Manufacturing process
 It is a semiconductor memory which can only have data
written to it once - the data written to it is permanent.

 Manufactured blank and are programmed using a

special PROM programmer
 Typically a PROM will consist of an array of fuse-able
PROM links some of which are "blown" during the
programming process to provide the required data
pattern
 The contents OF EACH MEMORY CIRCUIT ARE
LOCKED BY A FUSE DIODES)

 Prom are permanent storage

  This form of semiconductor memory can be programmed
and then erased at a later time. This is normally achieved
by exposing the silicon to ultraviolet light. To enable this to
happen there is a circular window in the package of the
EPROM to enable the light to reach the silicon of the chip.
When the PROM is in use, this window is normally covered
by a label, especially when the data may need to be
preserved for an extended period.
 The PROM stores its data as a charge on a capacitor. There
EPROM is a charge storage capacitor for each cell and this can be
read repeatedly as required. However it is found that after
many years the charge may leak away and the data may be
lost.
 Nevertheless, this type of semiconductor memory used to
be widely used in applications where a form of ROM was
required, but where the data needed to be changed
periodically, as in a development environment, or where
quantities were low.
  Data can be written to it and it can be erased using an
electrical voltage
 Can be updated by the manufacturer

 This is typically applied to an erase pin on the chip.

 Like other types of PROM, EEPROM retains the contents
EEPROM of the memory even when the power is turned off

 Also like other types of ROM, EEPROM is not as fast as

RAM
 Used in PCs and smart phones as firmware
  NVRAM
 Any memory which does not lose information when power
is turned off
 Includes (Except ROM) conventional RAM with battery
back up such as BIOS memory

Other types of
RAM
  Cheaper variant of EEPROM
 Blocks of bytes are erased at the same time
 Data can be written to it and it can be erased only in blocks,
 data can be read on an individual cell basis.
 To erase and re-programme areas of the chip,
programming voltages at levels that are available within
electronic equipment are used.
 It is non-volatile, and this makes it particularly useful.
FLASH MEMORY  Flash memory is widely used in many applications
including memory cards for digital cameras, mobile
phones, computer memory sticks and many other
applications
 Limited number of write cycles
 Cheaper than SDRAM, more expensive than disk
 Slower than SRAM, faster than disk
  Volatile temporary memory on a storage device
 Created when a computer is running many processes at
once and RAM is low
Virtual Memory
 The OS makes part of the storage drive available to use
as RAM
  Memories consist of a number of cells (or locations)
each of which can store a piece of information.

 Each cell has a number, called its address, by which

programs can refer to it.

Memory  If a memory has n cells, they will have addresses 0 to n

− 1.
Addresses  All cells in a memory contain the same number of bits.
 If a cell consists of k bits, it can hold any one of 2k different
bit combinations. organizations for a 96-bit memory.

 adjacent cells have consecutive addresses

 Three ways of
organizing a 96-
bit memory.
 Computers that use the binary number system
(including octal and hexadecimal notation for binary
numbers) express memory addresses as binary
numbers.
 The number of bits in the address bus determines the
maximum number of directly addressable cells in the
memory and is independent of the number of bits per
cell.
 A memory with 212 cells of 8 bits each and a memory
with 212 cells of 64 bits each need 12-bit addresses.
 If an address bus has m bits, the maximum number of
cells addressable is 2m .
 For example, the size of the address bus used to reference
the memory of Fig. (a) needs to be at least 4 bits in order to
express all the numbers from 0 to 11.
 Fig. (b) and (c), a 3-bit address bus is sufficient
  it is the smallest addressable unit.
 nearly all computer manufacturers have standardized on an
8-bit cell, which is called a byte.
 Bytes are grouped into words.
 A computer with a 32-bit word has 4 bytes/word, whereas a
Cell computer with a 64-bit word has 8 bytes/word.

 The significance of a word is that most instructions operate

on entire words, for example, adding two words together.
 a 32-bit machine will have 32-bit registers and instructions for
manipulating 32-bit words,
 a 64-bit machine will have 64-bit registers and instructions for
manipulating 64-bit words.
  A small and very fast memory which is part of the CPU
or closer to the CPU than RAM

 Its purpose is to make the main memory appear to the

processor to be much faster than it actually is.
 The effectiveness of this approach is based on a property
of computer programs called locality of reference.

 Temporarily hold instructions and data that the CPU is

likely to reuse
Cache Memory
 Control unit automatically checks CPU for instructions
before requesting data from RAM
 Cache is graded as Level 1(L1), Level 2(L2), Level 3(L3)
 Each CPU core has its own L1 cache, but may share L2
and L3 caches
  There are mainly three levels of cache (L1, L2, L3) which
are categorized based on their speed and capacity.
Cache Levels Going from L1 to L3, memory access time and storage
capacity increases
  L1:
 This is the smallest and fastest cache and is placed
close to or alongside of the processor to make data
access faster.
 Level 1 cache is separate for all processors in
multiprocessors machines and this is where requested
data is checked first.
L1  Usually its size is up to 256KB, however, in some
processors like Xeon it can be up to 1 MB.

 Instruction and Data is separate in this cache. However,

this separation depends upon the architecture of the
cache design.
  Between CPU and RAM sometimes into CPU with L1
 This is slower than the L1 cache and greater in size than
L1.
 Its size is up to 8MB.
L2
 Level 2 cache keeps the data that is expected to be
accessed by the processor in coming clocks.
 Level 2 cache is also separate for all cores.
  This is the slowest cache and greatest in size as
compared to other cache memories.

 Level 3 cache is up to 50MB.

 With multicore processors, each core can have
L3 dedicated L1 and L2 cache, but they can share an L3
cache.
 If an L3 cache references an instruction, it is usually
elevated to a higher level of cache.
  Issue?
 In practice after the CPU issues a memory
request, it will not get the word it needs for
many CPU cycles. The slower the memory, the
more cycles the CPU will have to wait.

Cache Memory  Solution

 Combining a small amount of fast memory
Issue with a large amount of slow memory to get the
speed of the fast memory (almost) and the
capacity of the large memory at a moderate
price.
 The small, fast memory is called a cache
  Memory references made in any short time interval
tend to use only a small fraction of the total memory is
called the locality principle and forms the basis for all
caching systems.
locality principle  The general idea is that when a word is referenced, it
and some of its neighbours are brought from the large
slow memory into the cache, so that the next time it is
used, it can be accessed quickly.