Hindawi

Journal of Nanomaterials
Volume 2022, Article ID 3487853, 17 pages
https://doi.org/10.1155/2022/3487853

Research Article
Design and Implementation of ALU Using Graphene Nanoribbon
Field-Effect Transistor and Fin Field-Effect Transistor

D. Rebecca Florance ,1 B. Prabhakar ,2 and Manoj Kumar Mishra 3

1
Research Scholar, Department of Electronics and Communication Engineering, JNTU College of Engineering, Jagtial,
Telangana, India
2
Associate Professor, Department of Electronics and Communication Engineering, JNTU College of Engineering, Jagtial,
Telangana, India
3
Professor, Salale University, Fitche, Ethiopia

Correspondence should be addressed to D. Rebecca Florance; rebeccafl[email protected]

and Manoj Kumar Mishra; [email protected]

Received 18 May 2022; Revised 7 June 2022; Accepted 16 June 2022; Published 1 July 2022

Academic Editor: Samson Jerold Samuel Chelladurai

Copyright © 2022 D. Rebecca Florance et al. This is an open access article distributed under the Creative Commons Attribution
License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is
properly cited.

Arithmetic and logical unit (ALU) are the core operational programmable logic block in microprocessors, microcontrollers, and
real-time-integrated circuits. The conventional ALUs were developed using complementary metal oxide semiconductor (CMOS)
technology, which resulted in excessive power consumptions, path delays, and number of transistors. Therefore, this article
focuses on the design and development of hybrid delay-controlled reconfigurable ALU (DCR-ALU) using field-effect transistor
(FinFET) and graphene nanoribbon field-effect transistor (GnrFET) technologies. Initially, a novel carry output predictable full
adder (COPFA) and carry input selectable full adders (CISFA) are developed using multiplexer selection logic; then, delay-
controlled hybrid adder (DCHA) and delay-controlled hybrid subtractor (DCHS) are developed using these full adders. In
addition, a unified delay-controlled hybrid adder and subtractor (DCHAS) is developed by combining these DCHA and
DCHS. Further, a delay controller array multiplier (DCAM) also developed using DCHA modules. Finally, DCR-ALU is
developed by adopting the DCHAS, DCAM, and logical operations. The obtained simulation results shows that the proposed
nanotechnology-based models outperformed the conventional adders and subtractors in terms of area, power, and delay
reduction.

1. Introduction with an information path high speed model is a research

area to decorate. Through the adder, the speed is constrained
Recent years, the digital circuitry needs the decrease of area according to the time necessity for carry propagation in the
and power by optimizing the time with improving perfor- digital adders [3]. The situations of every bit are created
mance in speed. The fundamental digital circuits consist of successively in a steady progression in an adder basic and
adders and multipliers as their building blocks. Further, proliferate a carry into the following position. Many high-
these are generally utilized as various hardware blocks in performance systems, such as microprocessors, DSP, digital
DSP and ALU frameworks [1]. In DSP, it incorporates communications, and spectrum analysis, rely on ALUs.
refinement and digital filtering like digital communications, The performance of a system is governed by the multiplier’s
spectral analysis, FFT, and DFT. In view of the activity of performance, as it is the system’s most space-consuming and
adder, the power utilization execution relies upon it. In VLSI slowest component. As a result, maximizing the multiplier’s
industry [2], the segments of convenient electronics have [4] speed and area is a crucial design consideration. Since the
quick development for the circuits of low control math. area and speed are opposing restrictions, several methods
The proficient structure of the power and area utilization and designs have been created to provide a better trade-off
2 Journal of Nanomaterials

between the two. Furthermore, due to the scenario of many DCHS is developed by using two complementation addition
DSP applications are aimed at portable, both battery- properties with DCHA as building block.
operated systems and power dissipation are also a significant Then, 4-bit DCHA, DCHS, and DCHAS blocks are
design limitation. The ALUs are the major building block in extended with reconfigurable properties, which formed the
every IC, which is utilized widely in various VLSI systems N-bit implementations of delay-controlled reconfigurable
such as specific application of microprocessors and DSP hybrid adder (DCRHA), delay-controlled reconfigurable
architectures [5]. Further, the ALU performs the logical hybrid subtractor (DCRHS), and delay-controlled reconfi-
operations, additions, and multiplications, respectively. The gurable hybrid adder subtractor (DCRHAS).
key task of addition is adding the two binary numbers; it is In addition, 4-bit DCAM is developed by using DCHA
the basis of several useful functions such as division, multi- modules and extended with N-bit delay-controlled reconfi-
plication, and subtraction and addresses calculation [6], gurable array (DCRAM).
etc. In critical path, adder is a part of most of these systems Finally. DCR-ALU is developed by using DCRHAS,
which regulates the systems’ complete performance. The DCRAM, and logical operations using FinFET and GnrFET
performance enhancing of the ALU cell (the binary adder technologies. The simulation results show that the pro-
building block) is an important goal. Recently, VLSI systems posed models are outperformed in terms of area, power,
are developing with low power and have occurred as and delay reduction as compared to conventional adders
extremely in request due to the development of technologies and subtractors.
in computation and communication of mobile. But there is a Rest of the paper is contributed as follows: Section 2
restricted power offered for the mobile systems. Full adder deals with the related work with problems. Section 3 deals
(FA) is the simple building blocks of various digital VLSI with preliminaries of the proposed models. Section 4 deals
circuits. Some modifications have been done in concern to with the proposed method. Section 5 deals with simulation
its structure from its invention. In submicron [7] and deep results and discussions. Section 6 concludes with future
submicron technologies, the motivation of the VLSI scope.
designers is to reduce the static and dynamic power con-
sumption in VLSI ICs. When aiming about the energy 2. Related Work
efficient arithmetic circuits inside the processors, there is a
need for obtaining an energy efficient ALU architecture. To This section gives the detailed survey of various adders
design an energy efficient ALU, which is to be utilized in developed over the past few years. The survey is mainly
higher-order adders, one of the necessary parameters is the focusing on analysis of hybrid adders. In [9], the authors
reduction in total power consumption. This will increase developed the approximate adders exhibits with slow speed
the switching of the logic level signal in all the internal as of compact design but carry look ahead performed faster
well as external loads of each subcircuits in arithmetic units and consumed more area. Radiation-hardened majority-
which leads to large dynamic power consumption [8]. based magnetic full adder (RHMFA) [10] is designed and
Hence, the reduction in dynamic power consumption is performed in this addition process of increasing speed. In
the most significant factor in improving the energy efficiency analysis of approximate adders, utilizing FinFET shows that
in arithmetic building blocks. The rise in leakage current the speed of the approximate adders is almost double than
inside the discrete devices fabricated in VLSI IC leads to con- the conventional RCA.
siderable increase in static power consumption [9]. In order to In [11], the authors developed the Hybrid FinFET Full
design an energy efficient ALU cell, one has to concentrate in adder (HFFA) and Hybrid FinFET adder (HFA) design for
achieving the reduction in both static and dynamic power con- video and image processing applications. It exhibits the gate
sumption. This is evident with the following discussion on depth in the structure of adder and implemented dual RCA
power dissipation in CMOS-based circuits. with the input 0 and 1, respectively. Further, Imprecise
Recently, FinFET, GnrFET, carbon nanotube FET Minority-Based CNFET Full Adder (IMC-FA) and Impre-
(CntFET), and RibbonFET are widely using in variety cise Minority-Based CNFET Adder (IMCA) work with effi-
applications for area, power, and delay improvement perfor- cient and simple process of significantly modification of
mance. These advanced FET models are developed by mod- gate level and the parameter reduction in conventional
ifying the processing parameters (such as size, thickness, HFFA [12]. Further, IMCA is an optimization process in
temperature, current, voltage levels, materials of fabrication, the constraints of VLSI designs, respectively. To overcome
gate oxidation, source, and drain divisions, introducing extra the area, power, and delay consumption issues in 4-bit, 8-
terminals) of different layers. Thus, this work considered the bit CNTFET Ternary Full adder (CTFA) and CNTFET
FinFET and GnrFET models for development of various Ternary adder (CTA) without utilizing Mux and utilizing
arithmetical operations. The major contributions of this approximate adders is developed in [13] and simulations
work are illustrated as follows: resulted in better performance for modified designs as com-
Initially, modified full adder (MFA) is developed with 10 pared to state of art approaches. The ternary half adder and
transistors using multiplexer selection logics. Then, CISFA 1-trit multiplier architecture have been developed [14] and
and COPFA are developed by changing the carry input evaluated the performances of the design in terms of area,
and carry out operations of MFA. power, and delay.
Further, 4-bit DCHA, DCHS, and DCHAS are devel- In [15], the authors developed the PTL-based subtractor
oped using MFA, CISFA, and COPFA modules, where (PTLS) with the gate-level modifications, which required less
Journal of Nanomaterials 3

gates to perform the operation in the proposed work. It pro- [29] was introduced to develop the Carry Save Multiplier.
vides area reduction and the total power. The result analysis But this method consumes the high computational complex-
shows the better performances of the circuit and faster than ity in terms of delay. In [30], the authors developed the area-
the others. In this way, MTCMOS subtractor (MTCMOSS) efficient FinFET-based approximate multiplier methodology
[16] makes efficient and simple way to process the VLSI with low voltage with least current consumption circuits.
hardware implementations. The mobile industry is growing These were implemented for a current feed operational
rapidly not only because of arithmetic unit but also with EETM and the current conveyor. Then, FinFET-based dis-
the arithmetic units of less power and area. A simple and crete wavelet transform (FDWT) [31] was developed by
efficient modification of gate level makes the reduction in using reversable logic gates. The comparison has revealed
power, area, and delay in Trit Unbalanced Ternary Subtrac- that this method of FinFET design could reduce the area
tor (TUTS) [17]. Based on the modifications of CSLA, the by almost 50% of the smallest area.
performances were compared with other adders. By the In [32], the authors developed high-speed 8-bit ALU
BEC modification instead of MFA [18] chain, the logic (HS-ALU) using 18 nm FinFET technology which is based
converter provides the circuit with slight changes of delay. on the kogge stone additions and Dadda multiplier. It is
The fast process performances of TUTS are utilized for one of the most vividly encountered operations across a
arithmetic functions in data processing processors. majority of the real-time DSP solutions but consumed
In [19], the authors developed the gating-aware energy higher power. Further, N-bit ALU [33] is developed by using
adders and subtractors (GAEAS) for power utilization that 18 nm FinFET technology, which mainly implies function of
has transformation. For the reduction of circuit consump- additions and designs relied the considerable speed as it is
tion, BEC is utilized in the modified quantum adders instead one of the performance metrics and digital circuits with
of CSLA and RCA with increasing the delay slightly. In [20], high-speed performance has always gained significant
the authors proposed the low error efficient approximate importance. This method is suffering with the high compu-
FinFET-based Hybrid Adder/Subtractor Circuit (FHAS), tational complexity. In [34], the authors developed the
which is linear proportional of N delay performed with N 32 nm-FinFET-based 4-bit ALU (FALU-32) developed using
-bit, so highest delay process is performed by these adders. array multipliers, carry save additions. The power consump-
Normally, it provides faster results with more delay process tion in the case of the FALU-32 circuit is to be mitigated
than the other adders. It provided because of large number either for two distinct reasons as to mitigate the heat dissipa-
of logic gates and fan-in. In [21], the authors proposed tion to support significant volumes of functions that are
CNTFET-based adder and subtractor (CNTFET-AS), which integral to handling the IC. Further, sub-10 nm gate
exhibits high speed with compact design but consumes more length-based Schottky-barrier FinFET (SB-FinFET) [35]
area. Also, CNTFET is accessible with low-power multi- was developed to reduce the power consumption problems
pliers. The simulation results shown that it resulted in better presented in basic FinFET technology. Further, 1-bit ALU
performance as compared to the FinFET-based adders [22]. is developed by using SB-FinFET technology; however, this
In [23], the authors developed the multioperative reversible method is suffering with the fabrication issues. Then, hybrid
adder and subtractor (MRAS), which can be used in the pin-transfer torque-magnetic tunnel junction (STT-MTJ)
design of high-performance modules [24] like multiple bit and hybrid tunnel FET (TFET) [36] are developed to reduce
adders, multipliers, multiplexers, subtractors, comparators, the mutual problems presented in conventional GnrFET,
and registers. The advancement in fabrication nanotech- FinFET, and CNTFET technologies. Then, 1-bit magnetic
nology [25] with the shrinking device sizes has allowed ALU (MALU) is developed by using STT-MTJ and TFET
for placement of nearly two billion transistors on Intel’s technologies, where STT-MTJ resulted in reduced area and
advanced processor. delay metrics.
In [26], the authors developed the 14 nm FinFET
technology-based 8-bit Dadda multiplier (FDM) using 3. Preliminaries
approximate 4 : 2 compressors. The carry propagate adders
are designed with a 4 : 2 compressor to reduce the height of The design and development of full adders are critical
the partial product rows. Further, CNTFET-based vedic because they are the fundamental building blocks of all inte-
mathematics processor (CVMP) [27] is developed to reduce grated circuits. Therefore, the design of full adders must be
the power complexities presented in the FDM, which per- done with care because of their importance. Basic CMOS
forms additions, multipliers, multiply and accumulations, technology-based full adder is utilizing the greater energy,
and DWT operations. The maximum height of the partial area, delay, and power consumption. So, the GnrFET and
product was reduced by one unit. This was achieved through FinFET technologies serve as an alternate technology to the
the pipelining of the multiplier by optimization of the array basic CMOS technology, which is characterized by low
reduction stage. In [28], the authors developed the Majority- resource consumption. This work implemented novel three
Based Imprecise Multiplier (MBIM) with 7 nm FinFET. The different types of full adders for performing addition and
MBIM adopted the advanced quantum dot cellular automata subtraction operations. They are MFA with 10 transistors,
for generalization of majority logic formulations. The partial COPFA with 12 transistors, and CISFA with 12 transistors,
product reductions were achieved through the hybrid com- respectively. All the three designs contain equal number of
pressors with majority logic gates. Further, FinFET-based PMOS and NMOS transistors, which allows for the intro-
Energy Efficient Pass Transistor Adiabatic Logic (EEPAL) duction of the equilibrium state in three models, allowing
4 Journal of Nanomaterials

for the control and synchronization of the unbiased

electron-hole pair. Furthermore, this equilibrium condition A
ensures that the ideal power consumption is maintained XOR

MUX21
B
while simultaneously improving energy efficiency. S

3.1. MFA. Figure 1 shows the block diagram of MFA, which NOT
contains two multiplexers for sum and carry out genera-
tions. Here, Cin is applied as selection input to the Cin
MUX21, and it generates the sum output based on data
selection logic between XOR and XNOR outcomes. Finally,
sum output of MFA is generated as follows:

MUX21
Cout
(
A ⊕ B ⊕ C in = A ⊕ B, Cin = 0,
S= ð1Þ
A ⊕ B ⊕ C in = A⨀B, Cin = 1:
Figure 1: Block diagram of MFA.

Further, XNOR of inputs A, B is applied as selection

input to the MUX21-A, and it generates the carry output MUX21-A generates the output as C in . The operation of
based on data selection logic. Finally, carry output of MFA MUX21-A is illustrated as follows:
is generated as follows: (
C in , A = B,
OUTA = ð3Þ
( C ins , A ≠ B:
Cin , ðA⨀BÞ = 0,
C out = ð2Þ
B, ðA⨀BÞ = 1: Then, output of MUX21-A (OUTA ) is applied as selec-
tion input to the MUX21-A, which generates the sum output
based on XOR-XNOR selection logic. Finally, sum of CISFA
Figure 2 shows the FinFET-based transistor level archi- is generated as follows:
tecture of the proposed MFA, which contains five PMOS-
(
FinFETs and five NMOS-FinFETs. Initially, input B is A ⊕ B, OUTA = 0,
applied to the gate terminal of P1 and N1 FinFETs, which S= ð4Þ
functions as inverter and generates the outcome B.
Fur- A⨀B, OUTA = 1:


ther, B and input A are applied to gate terminal of P2
and N2 FinFETs, which functions as XOR gate and gener- Further, XNOR of inputs A, B is applied as selection
ates output as A ⊕ B:. Further, A ⊕ B is also applied to the input to the MUX21-A, and it generates the carry output
gate terminal of P3 and N3 FinFETs, which act as inverter based on data selection logic. Finally, carry output of CISFA
and generates the output as A⨀B. Then, C in is applied as is generated as follows:
input to gate terminal to the gate terminal of P4 and N4 (
FinFETs, which acts as MUX21 with A ⊕ B and A⨀B as OUTA , ðA⨀BÞ = 0,
data inputs, so sum output is generated. Finally, A⨀B Cout = ð5Þ
was generated from MUX21 applied as input to gate ter- B, ðA⨀BÞ = 1:
minal of P5 and N5 FinFETs, which acts as MUX21, so
carry output is generated. Figure 4 shows the FinFET layout of CISFA, which
contains 6 number of PMOS-FinFETs and 6 number of
3.2. CISFA. The major advantage of CISFA is that it has the NMOS-FinFETs. Initially, input B is applied to the gate ter-
potential capability to select the carry inputs. Generally, the minal of P1 and N1 FinFETs, which functions as inverter
complexity of addition process purely depends on carry gen- and generates the outcome B.
Further, B
and input A are
eration and forwarding nature. So, the fast operation of full applied to gate terminal of P2 and N2 FinFETs, which func-
adders can be effectively performed by minimizing the com- tions as XOR gate and generates output as A ⊕ B: In addi-
putations through different carry inputs. The CISFA module tion, A ⊕ B is applied to gate terminal of P3 and N3
considers the selectable extra carry input (C ins ), which is dif- FinFETs, which acts as MUX21-A with C ins and C in as data
ferent from original carry input (Cin ). inputs. Further, A ⊕ B is also applied to the gate terminal of
Figure 3 shows the block diagram of CISFA, which is P4 and N4 FinFETs, which act as inverter and generates the
implemented from the fundamentals of MFA by introducing output as A⨀B. Then, OUTA generated from MUX21-A is
the extra OR gate. Initially, C ins and C in applied as input to applied as input to gate terminal of P5 and N5 FinFETs,
MUX21, which is used to select the two carry inputs. Here, which acts as MUX21-B with A ⊕ B and A⨀B as data
if both inputs A and B are equal, then MUX21-A generates inputs, so sum output is generated. Finally, A⨀B generated
the output as C ins , and if inputs A and B are not equal, then from MUX21-B is applied as input to gate terminal of P6
Journal of Nanomaterials 5

P2 P4
Vdd Vdd Cin
A
A B S

P1
P3
N2 N4
B – A B
B

N1 N3
P5
Gnd
Gnd Cout

N5

Figure 2: FinFET modelling of MFA.

with XOR-AN module. This module generates both XOR

A and AND outputs, where AND output is the temporary
MU X21-B

XOR carry output.

B
S In most scenarios, Cout is generated when two or more
numbers of ones available in input data, so this temporary
NOT carry out will check the availability of ones and generates
Cins the Coutp ,respectively. Figure 6 shows the FinFET layout of
MUX21-A

COPFA, which contains 6 number of PMOS-FinFETs and

6 number of NMOS-FinFETs. It is also acts similar like
Cin MFA with extra AND operation.
MUX21-C

Cout
4. Proposed DCR-ALU Method
ALUs are the basic building in every integrated circuit, and
they decide the performance of various applications. Thus,
the optimal design of adders and subtractors will improve
Figure 3: Block diagram of CISFA. the performance of microprocessors and microcontrollers.
This section deals with the detailed analysis of implementa-
and N6 FinFETs, which acts as MUX21-C, so carry output is tion DCR-ALU, which is developed by using DCRHA,
generated. DCRHS, DCRHAS, and DCRAM, respectively. Further,
these adders and subtractors are developed by using-by-
3.3. COPFA. The major advantage of COPFA is that it using MFA, COPFA, and CISFA modules (mentioned in
predicts two carry outputs such as carry output (Cout ) and Section 3). Figure 7 shows the N-bit implementation of the
predictable carry output (Coutp ). These carry outputs are proposed DCR-ALU, which consumes the low area, power,
used as inputs for the CISFA module, which can be used and delay properties as they are implemented by using
to fast switching of data. Figure 5 shows the block diagram advanced full adders. Here, A, B are N-bit inputs, S is the
of COPFA, which is implemented by replacing XOR gate selection line with three inputs, and OUT is the final ALU
6 Journal of Nanomaterials

OUTA
P2 P5
Vdd A B Vdd
A
S

P1 Cin
P4
N2 N5
B – A B
B
P3
OUTA
N1 N3
P6
Gnd Gnd Cout
N3

Cins
N6

Figure 4: FinFET modelling of CISFA.

The 4-bit DCHA totally contains 44 number of FinFETs.

A A B
The detailed operation of 4-bit DCHA is illustrated as
MUX21-A

XOR-AND follows:
B
S Step 1. Initially, A0, B0 and Cin are applied as input to the
Coutp NOT MFA-1 and it generates S0 , C out1 as output signals.
Step 2. Apply A1, B1 and C out1 variables as inputs to
Cin COPFA, which generates the Cout2 as regular carry out and
C out2p as predicated carry out. Here, C out2p is generated fast
by analyzing the intermediate carries as compared to C out2 .
MUX21-B

Cout Step 3. Apply A2, B2 , Cout2 , and Cout2p variables as inputs

to CISFA, and it generates S2 , C out3 as output signals. This
module has the capacity to generate carry output by select-
ing high-speed input data levels. Based on the accurate
Figure 5: Block diagram of COPFA. sum generation situations, accurate path is selected. Usually,
the RSCP path contains the generalized carry propagations,
output. Further, based on selection combinations, ALU will and HSCP path contains propagation carry from predicted
perform the different operations. Table 1 presents the outcome to selectable input.
detailed operations for each selection combination of the Step 4. Finally, A3, B3 and Cout3 are applied as input to the
proposed DCR-ALU. MFA, and it generates final outputs S3 , C out .
The proposed 4-bit DCHA contains the “reconfiguration
4.1. DCRHA. The delay problems generated in the conven- block,” which is formed by the combination of CISFA and
tional adders are overcome by introducing CISFA-COPFA COPFA modules. This reconfigurable block is used to
combination. The MFA and MUX21 of basic adders are develop the N-bit DCRHA by repeating the reconfiguration
replaced by CISFA-COPFA combination, which signifi- blocks multiple times. Further, the number of reconfigu-
cantly reduces the area, power, and delay as compared to ration blocks is decided by length of N-bit DCRHA.
other approaches. Figure 8 shows the block diagram of For N-bit length of DCRHA, Mð= ðN − 2Þ/2Þ numbers
DCHA. It reduces the problems generated in the SRHA by of reconfiguration blocks are used. Further, the number
employing the high-speed carry propagation (HSCP) and of transistors in the N-bit DCRHA is 20 + 24 ∗ ððN − 2Þ/2Þ,
regular-speed carry propagation (RSCP) paths. Here, HSCP respectively.
is the low delay consumption path, RSCP is the high delay Figure 9 shows the block diagram of N-bit DCRHA, and
consumption path. Further, the DCHA is developed by its operation is illustrated as follows:
replacing the intermediate MFA stages of SRHA with Step 1. Initially, A0, B0 and Cin are applied as input to the
COPFA and CISFA modules. MFA-1, and it generates So , C out1 -based output signals.
Journal of Nanomaterials 7

P2 P5
Vdd Cin
A Vdd
A B S

P1 P4
N2 N5
B – A B
B Gnd

N1 P3 N4
P6
Gnd Coutp
Gnd
Cout

N3
N6

Figure 6: FinFET modelling of COPFA.

Step 3. The process of reconfigurable blocks is repeated

A for other inputs, and the number of reconfigurable blocks
is depending on factor M.
B N-bit DCRHAS
Step 4. Finally, AN−1 , BN−1 , and C outN−1 are applied as
S[0] inputs to the MFA, and it generates final outputs SN−1 , C out .

4.2. DCRHS. This section gives the detailed analysis of

hybrid subtractors, which are developed by performing the
N-bit DCRAM Multiplexer
OUT twos complement addition process. Therefore, there is no
special requirement of full subtractors for performing sub-
traction operation.
Figure 10 shows the block diagram of DCHS, and it is
developed by performing the twos complement operation
N-bit logical on DCHA. The 4-bit DCHS totally contains 52 (= 44 + 8)
operation
number of FinFETs; here 8 extra FinFETs are used for four
inverters. The detailed operation of 4-bit DCHS is illustrated
as follows. Initially, input B is applied to the inverter, which
generates the B
as output. Then, A0, B0 and binary − 1 are
S[0] S[1] S[2] applied as input to the MFA, but it acts as full subtractor
and generates D0 and Brout1 as output signals. Apply A1, B1
Figure 7: Architecture of N-bit DCR-ALU.
and Brout1 variables as inputs to COPFA, which generates
the Brout2 as regular borrow out and Brout2p as predicated
Step 2. Apply A1, B1 and Cout1 variables as inputs to borrow out. Here, Brout2p is generated fast by analyzing the
COPFA, which generates the S1 , Cout2 Cout2p . Apply A2, B2 , intermediate borrows as compared to Brout2 . Apply A2, B2 ,
C out2 , and C out2p variables as inputs to CISFA, and it gener- Brout2 , and Brout2p variables as inputs to CISFA, and it gener-
ates S2 , C out3 as output signals. ates D2 , Brout3 as output signals. Finally, A3, B3 and Brout3 are
8 Journal of Nanomaterials

Table 1: N-bit DCT-ALU operations.

Selection line (S) Output operation Comments

000 OUT = DCRHAS ðA, B, S ½0Þ As S ½0 = 0, DCRHAS acts as DCRHA.
001 OUT = DCRHAS ðA, B, S ½0Þ As S ½0 = 1, DCRHAS acts as DCRHS.
010 OUT = DCRAM ðA, B, S ½0Þ Multiplication
100 OUT = A Buffer
101 OUT = XOR ðA, BÞ EX-OR logical operation
110 OUT = XNOR ðA, BÞ EX-NOR logical operation
110 OUT = AND ðA, BÞ AND logical operation
111 OUT = OR ðA, BÞ OR logical operation

A3 B3 A2 B2 A1 B1 A0 B0

Cout2

MFA CISFA COPFA MFA Cin

Cout Cout3 Cout1
Cout2p
Reconfiguration
block

S3 S0
S2 S1

HSCP
RSCP

Figure 8: Proposed 4-bit DCHA.

AN–1 BN–1 AN–2 BN–2 AN–3 BN–3 A2 B2 A1 B1 A0 B0

CoutN–1

CoutN–2 Cout2
MFA CISFA COPFA CISFA COPFA MFA Cin
Cout CoutN–3 Cout3 Cout1
Cout2 N–2 Cout2p
Reconfiguration Reconfiguration
block-M block

SN–1 SN–2 SN–3 S2 S1 S0

HSCP
RSCP

Figure 9: Proposed N-bit DCRHA.

applied as input to the MFA, and it generates final outputs figurable blocks is repeated for M number of times and
S3 , Brout . generates multiple difference, borrow outputs. Finally,
Figure 11 shows the block diagram of N-bit DCRHS, and
N−1 and C out are applied as input to the MFA and
AN−1, B N−1
its operation is illustrated as follows, initially, A0, B9 and 1 are it generates final outputs DN−1 , Brout .
applied as input to the MFA and it generates D0 , Brout1 based
output signals. Apply A1, B1 and Brout1 variables as inputs to
4.3. DCRHAS. Figure 12 shows the block diagram of 4-bit
COPFA, which generates the D1 , Brout2 Brout2p . Apply A2, B2 , DCHAS, and it is developed by performing the twos comple-
Brout2 , and Brout2p variables as inputs to CISFA, and it ment operation with mode selection properties. Figure 13
generates D2 , Brout3 as output signals. The process of recon- shows the block diagram of N-bit DCRHAS. The DCHAS
Journal of Nanomaterials 9

B3 B2 B1 B0

Inverters

A3 A2 A1 A0

Brout2
Brout3
MFA CISFA COPFA MFA 1
Brout Brout1
Brout2p
Reconfiguration
block

D3 D2 D1 D0
HSCP
RSCP

Figure 10: Proposed 4-bit DCHS

BN–1 BN–2 BN–3 B2 B1 B0

Inverters
AN–1 AN–2 AN–3 A2 A1 A0
BroutN–1

Brout1
BroutN–2 Brout2
MFA CISFA COPFA CISFA COPFA MFA 1
Brout BroutN–3 Brout3
Broutp Brout2p
N–2
Reconfiguration Reconfiguration
block-M block

DN–1 DN–2 DN–3 D2 D1 D0

HSCP
RSCP

Figure 11: Proposed N-bit DCRHS

B3 B2 B1 B0

XOR XOR XOR XOR

A3 A2 A1 A0
CBout3

CBout2

MFA CISFA COPFA MFA Msel

CBout CBout1
CBout2p
Reconfiguration
block

SD3 SD2 SD1 SD0

HSCP
RSCP

Figure 12: Proposed 4-bit DCHAS.

10 Journal of Nanomaterials

BN–1 BN–2 BN–3 B2 B1 B0

XOR XOR XOR XOR XOR XOR

AN–1 AN–2 AN–3 A2 A1 A0

CBoutN–1

CBout1
CBoutN–2 CBout2
MFA CISFA COPFA CISFA COPFA MFA
CBout CBoutN–3 CBout3 Msel
CBoutp CBout2p
N–2
Reconfiguration Reconfiguration
block-M block

SDN–1 SDN–2 SDN–3 SD2 SD1 SD0

HSCP
RSCP

Figure 13: Proposed N-bit DCHAS.

a3 a2 a1 a0

b0

1’b0
FinFET/
GnrFET b1
AND gate
PP03

PP02

PP01
PP00
PP13 PP12 PP11 PP10

Proposed 4-Bit DCRHA

b2

S04 S03 S02 S01 S00

PP23 PP22 PP21 PP20
Proposed 4-Bit DCRHA

b3

S14 S13 S12 S11 S10

PP33 PP32 PP31 PP30
Proposed 4-Bit DCRHA

P7 P6 P5 P4 P3 P2 P1 P0

Figure 14: Architecture of 4-bit DCAM.

contains M sel pin, which is used to select addition and sub- difference output (SD) signal acts as D and carry-borrow
traction operations. Further, if M sel is zero, then DCHAS (CB) output signal acts as Brout .
acts as DCHA, because XOR operation between M sel ,B
(
results output the same as B only. In this case, sum- A + B, M sel = 0,
difference output (SD) signal acts as S and carry-borrow SD = ð6Þ
(CB) output signal acts as C out . In addition, if M sel is one, A − B, M sel = 1:
then DCHAS act as DCHS, because XOR operation between

respectively. This complemented
M sel ,B results output as B, 4.4. DCRAM. This section gives the detailed analysis of delay
output is useful for twos complement-based addition process controlled reconfigurable array multiplier (DCRAM), which
to generate the end difference outcome. In this case, sum- is developed by using DCRHA. Figure 14 shows the
Journal of Nanomaterials 11

Table 2: Operation of 4-bit DCAM.

Operation Comments
a3 a2 a1 a0 Input a
b3 b2 b1 b0 Input b
1’b0 PP03 PP02 PP01 PP00
Partial products generated and inputs to 1st stage 4-bit DCRHA
PP13 PP12 PP11 PP10

S04 S03 S02 S01 S00 Sum generated from first stage 4-bit DCRHA and applied as input to second stage 4-bit
DCRHA
PP23 PP22 PP21 PP20 Partial products

S13 S10 Sum generated from second stage 4-bit DCRHA and applied as input to third stage 4-bit
S14 S12 S11
DCRHA
PP33 PP32 PP31 PP30 Partial products
S24 S23 S22 S21 S20 Sum generated from third stage 4-bit DCRHA
P7 P6 P5 P4 P3 P2 P1 P0 Final product bits

an–1 .. .............. a2 a1 a0
b0

1’b0
FinFET/
GnrFET b1
AND gate

Proposed N-Bit DCRHA

C0 b2

.
.
.
Proposed N-Bit DCRHA
.

bn–1

Proposed N-Bit DCRHA

Cn–1 P2n–1 P2 P1 P0

Figure 15: Architecture of N-bit DCRAM.

architecture of DCAM, which is developed by using FinFET/ of m and n are ranged from 0 to 3, respectively. For an
GnrFET-based AND gates and 4-bit DCRHAs. Initially, instance, PP00 represents the FinFET AND operation
4-bit inputs such as a½3 : 0 = ða3 , a2 , a1 , a0 Þ and b½3 : 0 = between a0 and b0 .Further, these partial products are
ðb3 , b2 , b1 , b0 Þ are applied to AND gates, which generates applied to multistage 4-bit DCRHA, which generates the
the partial products. final multiplier output bits. Table 2 presents the detailed
operation of 4-bit DCAM.
PPmn = FinFETANDðam ,bm Þ : ð7Þ The operation of 4-bit DCAM is extended with N-bits
with reconfigurable properties and generated as N-bit
DCRAM. Figure 15 presents the architecture of N-bit
Here, PPmn represents the partial products, m repre- DCRAM, which is developed by using FinFET/GnrFET-
sents the bit position of input a, and n represents the bit based AND gates and N-bit DCRHAs. Here, inputs a, b are
position of input b. In the scenario of 4-bit DCAM, values ranged from 0 to ðn − 1Þ such as {an−1 , an−2 , ⋯ ⋯ :a2 , a1 , a0 }
12 Journal of Nanomaterials

Table 3: Operation of 4-bit DCRAM.

Operation Comments
an−1 ⋯⋯ a3 a2 a1 a0 Input a
bn−1 ⋯⋯ b3 b2 b1 b0 Input b
1’b0 PP0,n−1 ⋯⋯ PP03 PP02 PP01 PP00
Partial products generated and inputs to 1st stage 4-bit DCRHA
PP1,n−1 PP1,n−1 ⋯⋯ PP12 PP11 PP10

S0,n S0,n−1 S0,n−2 ⋯⋯ S02 S01 S00 Sum generated from first stage 4-bit DCRHA and applied as input to second
stage 4-bit DCRHA
PP2,n−1 PP2,n−2 PP2,n−3 ⋯⋯ PP21 PP20 Partial products
Repeat the process until (N-1) number of addition stages are completed.
P2n−1 P2n−2 P2n−3 ⋯⋯ P3 P2 P1 P0 Final product bits

Table 4: Device parameters for FinFET. 5.1. Performance Evaluation. This work considers the multi-
ple metrics to evaluate the performance of the proposed
Parameter Value models and comparison with state of art approaches. They
FinFET technologies 7 nm, 10 nm, 14 nm, 16 nm, and 20 nm are average power consumption (APC), sum rise delay
Length of the channel (L) 7 nm, 10 nm, 14 nm, 16 nm, and 20 nm (SRD), sum fall delay (SFD), carry output rise delay
Thickness of front/back (CORD), carry output fall delay (COFD), static noise margin
1.2 nm (SNM), total energy consumption (TEC), static power con-
gate oxide
Thickness of the fin (Si) 4 nm sumption (SPC), total current (TC), and propagation delay
(PD). Table 5 compares the 7 nm based FinFET and 22 nm
Height of the fin ðhfin Þ 7 nm, 10 nm, 14 nm, 16 nm, and 20 nm
based GnrFET performances for various proposed modules
Work function 4.5 eV/4.9 eV such as DCHA, DCHS, DCHAS, DCAM, and DCR-ALU.
Power supply (VDD) 1V Further, the FinFET technology resulted in superior perfor-
Channel doping 2 × 1020 cm−3 mance as compared GnrFET technology for all the proposed
models.
Source/drain doping 2 × 1020 cm−3
Table 6 compares the performance of the proposed
CISFA with various state of art models like RHMFA [10],
HFFA [11], IMC-FA [12], CTFA [13], and MFA [18]. From
the simulations, it is observed that the proposed CISFA
and fbn−1 , bn−2 , ⋯ ⋯ :,b2 , b1 , b0 g, respectively. Further, resulted in superior performance, because the CISFA utilizes
develop the partial products using FinFET/GnrFET-based the advanced path selection mechanisms. Further, the con-
AND gates. Here, N-bit DCAM is capable of developing the ventional methods suffering with the more power consump-
N 2 number of partial products. Further, The N-bit DCAM tions due to a greater number of transistors.
contains (N-1) number of N-bit DCRHAs, where the output Table 7 compares the performance of the proposed
of one adder is applied is input to next stage. Then, apply these DCHA with various state of art adders like HFA [11], IMCA
partial products to N-bit DCRHAs and reduce the partial [12], CTA [13], and RCA [18]. From the simulations, it is
products with stage-by-stage multiplication, which resulted observed that the proposed DCHA resulted in superior per-
in final product bits. Table 3 presents the detailed operation formance, because the CPHA utilizes the COPFA-based
of N-bit DCRAM. path forwarding properties. Table 8 compares the perfor-
mance of the proposed DCHS with various state of art sub-
tractors like PTLS [15], MTCMOSS [16], and TUTS [17].
5. Results and Discussion From the simulations, it is observed that the proposed
DCHS resulted in superior performance, because it performs
This section provides a full examination of simulation subtraction using twos complement addition process.
results obtained using a variety of parameters, which Table 9 compares the performance of the proposed DCHAS
may be used to demonstrate the efficiency of the proposed with various state of art combined adders and subtractors
research. On top of that, all of the planned tasks have like GAEAS [19], FHAS [20], CNTFET-AS [21], and
been implemented and simulated, and their parameters MRAS [23]. From the simulations, it is observed that the
have been determined using the HSpice tool on both the proposed DCHAS resulted in superior performance,
FinFET and GnrFET technology platforms. Also included because it performs subtraction using twos complement
is a full analysis of the many simulation parameters that addition process.
were utilized in the design and development of the pro- Table 10 compares the performance of the proposed
posed work using the H-SPICE tool, which is shown in DCAM with various state of art multipliers like FDM [26],
Table 4. MBIM [28], EEPAL [29], and CVMP [27]. From the
 Journal of Nanomaterials

Table 5: FinFET and GnrFET comparisons of the proposed methods.

Method DCHA DCHS DCHAS DCAM DCR-ALU

Technology FinFET-7 nm GnrFET-22 nm FinFET-7 nm GnrFET-22 nm FinFET-7 nm GnrFET-22 nm FinFET-7 nm GnrFET-22 nm FinFET-7 nm GnrFET-22 nm
APC (nw) 2.192 4.14328 2.24344 4.25016 2.3512 4.4568 4.93752 9.35928 7.0771 13.41497
SRD (ns) 15.848 29.9432 16.5576 31.7864 13.3424 25.2336 28.019 52.99056 40.160 75.95314
SFD (ns) 20.024 37.8824 20.828 39.692 27.0656 51.15424 56.837 107.4239 81.467 153.9743
CORD (ps) 1.9776 3.75448 2.0572 3.8508 3.46304 6.545056 7.2723 13.74462 10.423 19.70062
COFD (ps) 15.824 29.8464 16.4584 30.6376 3.3084 6.25356 6.94764 13.13248 9.9582 18.82322
PD (ns) 1.976 3.71928 2.02376 3.77064 13.7424 25.97136 28.859 54.53986 41.364 78.17379
TC (nA) 2.536 4.81552 2.64784 5.00176 9.3608 17.69512 19.657 37.15975 28.176 53.26231
SPC (nw) 2.008 3.38968 2.27424 4.31136 4.32288 8.1824 9.0780 17.18304 13.011 24.62902
TEC (nJ) 0.072 0.11096 0.05296 0.10064 1.64344 3.0616 3.4512 6.42936 4.9467 9.215416
SNM 5.8722 10.6472 5.92344 11.1944 6.24776 11.7864 13.1203 24.75144 18.8057 35.47706
13
14 Journal of Nanomaterials

Table 6: Performance comparison of the proposed CISFA with existing full adders.

Method RHMFA [10] HFFA [11] IMC-FA [12] CTFA [13] MFA [18] CISFA
APC (nw) 12.00003 10.3798 8.384 2.262218 1.714 1.05472
SRD (ns) 45.57444 42.19374 42.02087 41.32643 9.7537 6.00208
SFD (ns) 92.32847 84.65102 84.50273 83.82905 19.785 12.1784
CORD (ps) 71.17313 53.90735 53.51331 10.72597 2.5315 1.54464
COFD (ps) 52.85658 50.23387 46.05195 10.24718 2.4185 0.8308
PD (ns) 57.09781 50.79739 43.00979 42.5649 10.046 5.82336
TC (nA) 41.72174 34.15361 30.00008 29.00142 6.8448 4.17848
SPC (nw) 31.52455 24.90975 21.06001 13.38892 3.16 1.94952
TEC (nJ) 38.33638 31.93173 25.45166 5.089908 1.2013 0.72616
SNM 35.93823 29.27089 29.06582 19.35038 4.567 2.64616

Table 7: Performance comparison of DCHA with existing 4-bit adders.

Method HFA [11] IMCA [12] CTA [13] RCA [18] DCHA
APC (nw) 18.47604 14.92352 4.026748 3.864 2.192
SRD (ns) 75.10486 74.79715 73.56105 27.907 15.848
SFD (ns) 150.6788 150.4149 149.2157 35.268 20.024
CORD (ps) 95.95508 95.25369 19.09223 3.486 1.9776
COFD (ps) 89.41629 81.97247 18.23998 27.897 15.824
PD (ns) 90.41935 76.55743 75.76552 3.457 1.976
TC (nA) 60.79343 53.40014 51.62253 4.555 2.536
SPC (nw) 44.33936 37.48682 23.83228 3.6015 2.008
TEC (nJ) 56.83848 45.30395 9.060036 0.134 0.072
SNM 52.10218 51.73716 34.44368 10.35 5.8722

Table 8: Performance comparison of DCHS with existing 4-bit subtractors.

Method PTLS [15] MTCMOSS [16] TUTS [17] DCHS

APC (nw) 19.21508 15.52046 4.1818 2.24344
SRD (ns) 78.10905 77.78904 76.349 16.5576
SFD (ns) 156.706 156.4315 155.143 20.828
CORD (ps) 99.79328 99.06384 19.8592 2.0572
COFD (ps) 92.99294 85.25137 18.9658 16.4584
PD (ns) 94.03612 79.61973 78.7914 2.02376
TC (nA) 63.22517 55.53615 53.6843 2.64784
SPC (nw) 46.11293 38.98629 24.7857 2.27424
TEC (nJ) 59.11202 47.11611 9.42237 0.05296
SNM 54.18627 53.80665 35.8243 5.92344

simulations, it is observed that the proposed DCAM resulted [32], FALU-32 [34], SB-FinFET [35], and STT-MTJ [36].
in superior performance, because it utilizes the delay con- The conventional ALUs are developed by using basic adders,
troller environment for data transfer from one module to multiplier prototypes, which caused to increase area, delay,
another module. and power consumptions. Further, the proposed DCR-
Table 11 compares the performance of the proposed ALU utilizes delay intensive paths, which caused to improve
DCR-ALU with various existing ALUs such as HS-ALU the performance.
Journal of Nanomaterials 15

Table 9: Performance comparison of DCHAS with existing adders and subtractors.

Method GAEAS [19] FHAS [20] CNTFET-AS [21] MRAS [23] DCHAS
APC (nw) 20.52005 17.74946 14.33664 3.868393 2.3512
SRD (ns) 77.93229 72.1513 71.85569 70.6682 13.3424
SFD (ns) 157.8817 144.7532 144.4997 143.3477 27.0656
CORD (ps) 121.7061 92.18157 91.50776 18.34141 3.46304
COFD (ps) 90.38475 85.89992 78.74883 17.52268 3.3084
PD (ns) 97.63726 86.86354 73.54674 72.78598 13.7424
TC (nA) 71.34418 58.40267 51.30014 49.59243 9.3608
SPC (nw) 53.90698 42.59567 36.01262 22.89505 4.32288
TEC (nJ) 65.55521 54.60326 43.52234 8.703743 1.64344
SNM 61.45437 50.05322 49.70255 33.08915 6.24776

Table 10: Performance comparison of DCAM with existing multipliers.

Method FDM [26] MBIM [28] EEPAL [29] CVMP [27] DCAM
APC (nw) 22.57206 19.52441 15.7703 4.255232 4.93752
SRD (ns) 85.72552 79.36643 79.04126 77.73502 28.019
SFD (ns) 173.6699 159.2285 158.9497 157.6825 56.837
CORD (ps) 133.8767 101.3997 100.6585 20.17555 7.2723
COFD (ps) 99.42323 94.48991 86.62371 19.27495 6.94764
PD (ns) 107.401 95.54989 80.90141 80.06458 28.859
TC (nA) 78.4786 64.24294 56.43015 54.55167 19.657
SPC (nw) 59.29768 46.85524 39.61388 25.18456 9.0780
TEC (nJ) 72.11073 60.06359 47.87457 9.574117 3.4512
SNM 67.59981 55.05854 54.67281 36.39807 13.1203

Table 11: Performance comparison of DCR-ALU with existing ALUs.

Method HS-ALU [32] FALU-32 [34] SB-FinFET [35] STT-MTJ [36] DCR-ALU
APC (nw) 24.62406 21.29935 17.20397 4.642072 7.0771
SRD (ns) 93.51875 86.58156 86.22683 84.80184 40.160
SFD (ns) 189.458 173.7038 173.3996 172.0172 81.467
CORD (ps) 146.0473 110.6179 109.8093 22.00969 10.423
COFD (ps) 108.4617 103.0799 94.4986 21.02722 9.9582
PD (ns) 117.1647 104.2362 88.25609 87.34318 41.364
TC (nA) 85.61302 70.0832 61.56017 59.51092 28.176
SPC (nw) 64.68838 51.1148 43.21514 27.47406 13.011
TEC (nJ) 78.66625 65.52391 52.22681 10.44449 4.9467
SNM 73.74524 60.06386 59.64306 39.70698 18.8057

6. Conclusion paths. In addition, DCAM developed with low area proper-

ties by using DCHA and FinFET/GnrFET technology-based
This article implemented the FinFET and GnrFET AND gates. Moreover, all these DCHA, DCHS, DCHAS,
technology-based DCR-ALU by adopting the DCHA, and DCAM modules are extended with reconfigurable
DCHS, DCHAS, and DCAM modules. Initially, a unified properties, which are formed as N-bit DCRHA, DCRHS,
12 transistor COPFA and CISFA are developed by using DCRHAS, and DCFRAM modules. The simulation results
multiplexer selection logic with low delay paths. Then, demonstrate that the proposed approach outperforms con-
DCHA, DCHS, and DCHAS modules are developed by ventional adders and subtractors and consumed a smaller
using COPFA and CISFA, which has the potential capacity number of transistors, reduced power consumption with
to select the low-speed and high-speed carry propagation path delays. In future, the present work can be extended to
16 Journal of Nanomaterials

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The study was performed as a part of the Employment of on CNFET technology,” computer and knowledge Engineering,
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