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Memory Interface

❖ Memory Devices
❖ Address Decoding
❖ 8088 and 80188 (8-Bit) Memory Interface
❖ 8086, 80186, 80286, and 80386SX (16-Bit)
Memory Interface

Chapter 8
CLO5

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Objectives of Chapter 8
By the end of this chapter, the student will be able to:
❖ Decode the memory address and use the outputs
of the decoder to select various memory
components.
❖ Explain how to interface both RAM and ROM to a
microprocessor.
❖ Interface memory to an 8-, 16-, 32-, and 64-bit

Chapter 8 data bus.

CLO5

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Introduction
❖ Simple or complex, every microprocessor-based
system has a memory system.

❖ Almost all systems contain two main types of memory:

read-only memory (ROM) and random access memory
(RAM) or read/write memory.

❖ This chapter explains how to interface both memory

types to the Intel family of microprocessors.

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Memory Devices
❖ Before attempting to interface memory to the microprocessor, it is
essential to understand the operation of memory components.
❖ In this section, we explain functions of the four common types of
memory:
▪ ROM: Read Only Memory
▪ OTP ROM: One-time programmable ROM (PROM: Programmable ROM
▪ EPROM: Erasable programmable ROM
▪ EEPROM: Electrically erasable programmable ROM
▪ Flash Memory: Extension of EEPROM
▪ SRAM: Static Random Access Memory
▪ DRAM: Dynamic Random Access Memory

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Write Ability / Storage Permanence

❖ Traditional ROM/RAM distinctions
➢ ROM
o read only, bits stored without power
➢ RAM
o read and write, lose stored bits without power
❖ Traditional distinctions blurred
➢ Advanced ROMs can be written to
o e.g., EEPROM
➢ Advanced RAMs can hold bits without power
o e.g., NVRAM
❖ Write ability
➢ Manner and speed a memory can be written
❖ Storage permanence
➢ Ability of memory to hold stored bits after they are written

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Write Ability / Storage Permanence

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Write Ability
o Ranges of write ability
➢ High end
o processor writes to memory simply and quickly
o e.g., RAM
➢ Middle range
o processor writes to memory, but slower
o e.g., FLASH, EEPROM
➢ Lower range
o special equipment, “programmer”, must be used to write to memory
o e.g., EPROM, OTP ROM
➢ Low end
o bits stored only during fabrication
o e.g., Mask-programmed ROM
o In-system programmable memory
➢ Can be written to by a processor in the embedded system using the memory
➢ Memories in high end and middle range of write ability

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Storage Permanence
❖ Range of storage permanence
➢ High end
o essentially never loses bits
o e.g., mask-programmed ROM
➢ Middle range
o holds bits days, months, or years after memory’s power source turned off
o e.g., NVRAM
➢ Lower range
o holds bits as long as power supplied to memory
o e.g., SRAM
➢ Low end
o begins to lose bits almost immediately after written
o e.g., DRAM
❖ Nonvolatile memory
➢ Holds bits after power is no longer supplied
➢ High end and middle range of storage permanence

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ROM: “Read-Only” Memory

❖ Nonvolatile memory
❖ Can be read from but not written to, by a
processor in an embedded system
❖ Traditionally written to, “programmed”,
before inserting to embedded system
2k x N
❖ Uses
➢ Store software program for general-
purpose processor
o program instructions can be one or more
ROM words
➢ Store constant data needed by system
➢ Implement combinational circuit

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Example: 8 x 4 ROM
▪ Horizontal lines = words
▪ Vertical lines = data Internal view
▪ Lines connected only at circles
8 × 4 ROM
▪ Decoder sets word 2’s line to 1 if
address input is 010 enable
word 0
word 1
▪ Data lines Q3 and Q1 are set to 1 3×8 word 2

because there is a “programmed” A0 Decoder word line

A1
connection with word 2’s line A2
▪ Word 2 is not connected with data
lines Q2 and Q0 data line

▪ Output is 1010 programmable

connection wired-OR

Q3 Q2 Q1 Q0

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Mask-programmed ROM

❖ Connections “programmed” at fabrication

▪ set of masks
❖ Lowest write ability
▪ only once
❖ Highest storage permanence
▪ bits never change unless damaged
❖ Typically used for final design of high-volume systems

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OTP ROM: One-time programmable ROM

• Connections “programmed” after manufacture by user

– user provides file of desired contents of ROM
– file input to machine called ROM programmer
– each programmable connection is a fuse
– ROM programmer blows fuses where connections should not exist
• Very low write ability
– typically written only once and requires ROM programmer device
• Very high storage permanence
– bits don’t change unless reconnected to programmer and more fuses
blown
• Commonly used in final products
– cheaper, harder to inadvertently modify

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EPROM: Erasable programmable ROM

• Programmable component is a MOS transistor
– Transistor has “floating” gate surrounded by an insulator
0V
– (a) Negative charges form a channel between source and drain floating gate
storing a logic 1 drain
source
– (b) Large positive voltage at gate causes negative charges to
move out of channel and get trapped in floating gate storing a
logic 0 (a)

– (c) (Erase) Shining UV rays on surface of floating-gate causes

negative charges to return to channel from floating gate
restoring the logic 1
+15V
– (d) An EPROM package showing quartz window through which
UV light can pass (b)
source drain

• Better write ability

– can be erased and reprogrammed thousands of times 5-30 min
• Reduced storage permanence
– program lasts about 10 years but is susceptible to source drain
radiation and electric noise (c)

• Typically used during design development

(d)

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EEPROM: Electrically erasable programmable ROM

• Programmed and erased electronically

– typically by using higher than normal voltage
– can program and erase individual words
• Better write ability
– can be in-system programmable with built-in circuit to provide higher
than normal voltage
• built-in memory controller commonly used to hide details from memory
user
– writes very slow due to erasing and programming
• “busy” pin indicates to processor EEPROM still writing
– can be erased and programmed tens of thousands of times
• Similar storage permanence to EPROM (about 10 years)
• Far more convenient than EPROMs, but more expensive

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Flash Memory
• Extension of EEPROM
– Same floating gate principle
– Same write ability and storage permanence
• Fast erase
– Large blocks of memory erased at once, rather than one word at a
time
– Blocks typically several thousand bytes large
• Writes to single words may be slower
– Entire block must be read, word updated, then entire block written
back
• Used with embedded systems storing large data items in
nonvolatile memory
– e.g., digital cameras, TV set-top boxes, cell phones

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RAM: “Random-access” memory

• Typically volatile memory R/W
External View

– bits are not held without power supply enable 2k × n

Read and Write
• Read and written to easily by embedded system A0
…
Memory

during execution Ak-1

…

• Internal structure more complex than ROM

Qn-1 Q0
– a word consists of several memory cells, each Internal View
storing 1 bit I3 I2 I1 I0

– each input and output data line connects to each 4×4 RAM

cell in its column enable

– RD/WR connected to every cell A0 2×4

A1 Decoder
– when row is enabled by decoder, each cell has Memory
cell
logic that stores input data bit when RD/WR RD/WR To every cell
indicates write or outputs stored bit when rd/wr
Q3 Q2 Q1 Q0
indicates read
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Basic Types of RAM

• SRAM: Static RAM
Memory Cell Internals
– Memory cell uses flip-flop to store bit
SRAM
– Requires 6 transistors
– Holds data as long as power supplied
Data Data
• DRAM: Dynamic RAM
– Memory cell uses MOS transistor and W
capacitor to store bit
– More compact than SRAM
– “Refresh” required due to capacitor leak DRAM
• word’s cells refreshed when read Data
– Typical refresh rate 15.625 microsec. W

– Slower to access than SRAM

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Example:
HM6264 & 27C256 RAM/ROM devices
• Low-cost low-capacity
memory devices 11-13, 15-19 data<7…0>
11-13, 15-19 data<7…0>
2,23,21,24, addr<15...0> 27,26,2,23,21, addr<15...0>
• Commonly used in 8-bit 25, 3-10
22 /OE
24,25, 3-10
22 /OE
microcontroller-based 27 /WE /CS
20
embedded systems 20 /CS1

• First two numeric digits 26 CS2 HM6264

block diagrams
27C256

indicate device type

Device Access Time (ns) Standby Pwr. (mW) Active Pwr. (mW) Vcc Voltage (V)
– RAM: 62 HM6264
27C256
85-100
90
.01
.5
15
100
5
5
– ROM: 27 device characteristics

• Subsequent digits Read operation Write operation

indicate capacity in data data

kilobits addr addr

OE WE
/CS1 /CS1
CS2 CS2
timing diagrams

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Composing Memory
• Memory size needed often differs from size of readily
available memories
• When available memory is larger, simply ignore
unneeded high-order address bits and higher data lines
• When available memory is smaller, compose several
smaller memories into one larger memory
– Connect side-by-side to increase width of words 2x1
Dec
– Connect top to bottom to increase number of words
• added high-order address line selects smaller memory
containing desired word using a decoder
– Combine techniques to increase number and width of words

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Memory Pin Connections

▪ address inputs
▪ data outputs or
input/outputs
▪ some type of selection
input
▪ at least one control input
to select a read or write
operation

A pseudo memory component illustrating the address, data,

and control connections.

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Address Connections
❖ Memory devices have address inputs to select a
memory location within the device.
❖ Almost always labeled from A0 , the least significant
address input, to An
▪ where subscript n can be any value
▪ always labeled as one less than total number of address pins
❖ A memory device with 10 address pins has its address
pins labeled from A0 to A9.

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Address Connections
❖ Memory devices have address inputs to select a
memory location within the device.
❖ The number of address pins on a memory device is
determined by the number of memory locations found
within it.
❖ Today, common memory devices have between 1K
(1024) to 1G (1,073,741,824) memory locations.
❖ A 1K memory device has 10 address pins.
▪ therefore, 10 address inputs are required to select any of its
1024 memory locations

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Address Connections
❖ It takes a 10-bit binary number to select any single
location on a 1024-location device.
▪ 1024 different combinations
▪ if a device has 11 address connections, it has 2048 (2K)
internal memory locations
❖ The number of memory locations can be extrapolated
from the number of pins.

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Data Connections
❖ All memory devices have a set of data outputs or
input/outputs.
▪ today, many devices have bidirectional common I/O pins
▪ data connections are points at which data are entered for
storage or extracted for reading
❖ Data pins on memory devices are labeled D0 through
D7 for an 8-bit-wide memory device.

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Data Connections
❖ An 8-bit-wide memory device is often called a byte-
wide memory.
▪ most devices are currently 8 bits wide,
▪ some are 16 bits, 4 bits, or just 1 bit wide
❖ Catalog listings of memory devices often refer to
memory locations times bits per location.
▪ a memory device with 1K memory locations and 8 bits in each
location is often listed as a 1K x 8 by the manufacturer
❖ Memory devices are often classified according to total
bit capacity.

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Selection Connections
❖ Each memory device has an input that selects or
enables the memory device.
▪ sometimes more than one
❖ This type of input is most often called a chip select
(𝑮𝟐𝑨) chip enable (𝑪𝑬) or simply select (ഥ𝑺) input.
❖ RAM memory generally has at least one or input, and
ROM has at least one
❖ If more than one 𝑪𝑬 connection is present, all must be
activated to read or write data

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Control Connections
❖ All memory devices have some form of control input or
inputs.
▪ ROM usually has one control input, while RAM often has one
or two control inputs
❖ Control input often found on ROM is the output enable
or gate connection, which allows data flow from
output data pins.
❖ The 𝑶𝑬 connection enables and disables a set of three-
state buffers located in the device and must be active
to read data.

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Control Connections
❖ RAM has either one or two control inputs.
▪ if one control input, it is often called R/W
❖ If the RAM has two control inputs, they are usually
labeled 𝑾𝑬 (or 𝑾 ), and 𝑶𝑬 (or 𝑮
ഥ ).
▪ write enable 𝑾𝑬 must be active to perform memory write, and
𝑶𝑬 active to perform a memory read
▪ when the two controls are present, they must never both be
active at the same time
❖ If both inputs are inactive, data are neither written
nor read.
▪ the connections are at their high-impedance state

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ROM Memory
❖ Read-only memory(ROM) permanently stores
programs/data resident to the system.
▪ and must not change when power disconnected
❖ Often called nonvolatile memory, because its contents
do not change even if power is disconnected.
❖ A device we call a ROM is purchased in mass
quantities from a manufacturer.
▪ programmed during fabrication at the factory

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ROM Memory
❖ The EPROM (erasable programmable read-only
memory) is commonly used when software must be
changed often.
❖ An EPROM is programmed in the field on a device
called an EPROM programmer.
❖ Also erasable if exposed to high-intensity ultraviolet
light.
▪ depending on the type of EPROM

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ROM Memory
❖ PROM memory devices are also available, although
they are not as common today.
❖ The PROM (programmable read-only memory) is also
programmed in the field by burning open tiny NI-
chrome or silicon oxide fuses.
❖ Once it is programmed, it cannot be erased.

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ROM Memory
❖ The Figure illustrates the 2716 EPROM, which is
representative of most common EPROMs.
❖ This device contains 11 address inputs and eight data
outputs. The 2716 is a 2K x 8 read-only memory device.
❖ The 27XXX series of the EPROMs includes the following pan
numbers: 2704 (512 x 8), 2708 (1K x 8), 2716 (2K x 8),
2732 (4K x 8), 2764 (8K x 8), 27128 (16K x 8), 27256 (32K
x 8), 27512 (64K x 8), and 271024 (128K x 8).
❖ Each of these parts contains address pins, eight data
connections, one or more chip selection inputs (𝑪𝑬 ), and
an output enable pin (𝑶𝑬 ).

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ROM Memory

The pin-out of the 2716, 2K x 8 EPROM.

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Static RAM (SRAM) Devices

❖ Static RAM memory devices retain data for as long as
DC power is applied.
❖ Because no special action is required to retain data,
these devices are called static memory.
▪ also called volatile memory because they will not retain data
without power
❖ The main difference between ROM and RAM is that
RAM is written under normal operation, whereas ROM
is programmed outside the computer and normally is
only read.

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Static RAM (SRAM) Devices

❖ The figure illustrates the 4016 SRAM,
▪ a 2K x 8 read/write memory
❖ This device is representative of all SRAM devices.
▪ except for the number of address and data connections.
❖ The control inputs of this RAM are slightly different
from those presented earlier.
▪ however the control pins function exactly the same as those
outlined previously

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Static RAM (SRAM) Devices

The pin-out of the TMS4016, 2K x 8 static RAM (SRAM)

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Dynamic RAM (DRAM) Memory

❖ Available up to 256M x 8 (2G bits).
❖ DRAM is essentially the same as SRAM, except that it
retains data for only 2 or 4 ms on an integrated
capacitor.
❖ After 2 or 4 ms, the contents of the DRAM must be
completely rewritten (refreshed).
▪ because the capacitors, which store a logic 1 or logic 0, lose
their charges

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Dynamic RAM (DRAM) Memory

❖ In DRAM, the entire contents are refreshed with 256
reads in a 2-or 4-ms interval.
▪ also occurs during a write, a read, or during a special refresh
cycle
❖ DRAM requires so many address pins that
manufacturers multiplexed address inputs.
❖ The figure illustrates a 256 x 4 DRAM.

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Dynamic RAM (DRAM) Memory

The pin-out of the 256 × 4 dynamic RAM (DRAM).

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Address Decoding
❖ In order to attach a memory device to the
microprocessor, it is necessary to decode the address
sent from the microprocessor.
❖ Decoding makes the memory function at a unique
section or partition of the memory map.
❖ Without an address decoder, only one memory device
can be connected to a microprocessor, which would
make it virtually useless.

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Why Decode Memory

❖ The 8088 has 20 address connections and the 2716
EPROM has 11 connections.
❖ The 8088 sends out a 20-bit memory address whenever
it reads or writes data.
▪ because the 2716 has only 11 address pins, there is a mismatch
that must be corrected
❖ The decoder corrects the mismatch by decoding
address pins that do not connect to the memory
component.

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Simple NAND Gate Decoder

❖ When the 2K x 8 EPROM is used, address connections
A10– A0 of 8088 are connected to address inputs A10–
A0 of the EPROM.
▪ the remaining nine address pins (A19–A11)are connected to a
NAND gate decoder
❖ The decoder selects the EPROM from one of the 2K-
byte sections of the 1M-byte memory system in the
8088 microprocessor.
❖ In this circuit a NAND gate decodes the memory
address, as seen in the following figure.

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Simple NAND Gate Decoder

A simple NAND gate decoder that selects a 2716 EPROM

for memory locationFF800H–FFFFFH.
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Simple NAND Gate Decoder

❖ If the 20-bit binary address, decoded by the NAND
gate, is written so that the leftmost nine bits are 1s and
the rightmost 11 bits are don’t cares (X), the actual
address range of the EPROM can be determined.
▪ a don’t care is a logic 1 or a logic 0, which ever is appropriate
❖ Because of the excessive cost of the NAND gate
decoder and inverters often required, this option
requires an alternate be found.

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Simple NAND Gate Decoder

❖ Example illustrates how the address range for this
EPROM is determined by writing down the externally
decoded address bits (A19-A11) and the address bits
decoded by the EPROM (A10-A0) as don't cares.
❖ As the example illustrates, the don’t cares are first
written as 0s to locate the lowest address and then as
1s to find the highest address. The Example also shows
these binary boundaries as hexadecimal addresses.
Here, the 2K EPROM is decoded at memory address
locations FF800H-FFFFFH.

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Simple NAND Gate Decoder

❖ Notice that this is a 2K-byte section of the memory and
is also located at the reset location for the 8086/8088
(FFFF0H), the most likely place for an EPROM.
❖ Example

1111 1111 1XXX XXXX XXXX

OR
1111 1111 1000 0000 0000 = FF800H
to
1111 1111 1111 1111 1111 = FFFFFH

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The 3-to-8 Line Decoder (74LS138)

❖ One of the more common, although not only, integrated
circuit decoders found in many microprocessor-based
systems is the 74LS138 3-to-8 line decoder.
❖ The truth table shows that only one of the eight
outputs ever goes low at any time. For any
❖ of the decoder’s outputs to go low, the three enable
inputs (𝑮𝟐𝑨, 𝑮𝟐𝑩 , and G1) must all be active.
❖ To be active, the 𝑮𝟐𝑨 and 𝑮𝟐𝑩 inputs must both be low
(logic 0), and G1 must be high (logic 1).

Microprocessors 503431-3
47 Dr. Mohamed Abdelaziz
 College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

The 3-to-8 Line Decoder (74LS138)

❖ Once the 74LS138 is enabled, the address inputs (C, B,
and A) select which output pingoes low. Imagine eight
EPROM 𝑪𝑬 inputs connected to the eight outputs of the
decoder! This is a very powerful device because it
selects eight different memory devices at the same
time.
❖ Even today this device still finds wide application.

Microprocessors 503431-3
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College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

The 3-to-8 Line Decoder (74LS138)

The 74LS138, 3-to-8 line decoder and function table.

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 College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

Sample Decoder Circuit

❖ The outputs of the decoder in Figure, are connected to
eight different 2764 EPROM memory devices.
❖ The decoder selects eight 8K-byte blocks of memory for
a total capacity of 64K bytes.
❖ The fig. show the address range of each memory device
and the common connections to the memory devices.
❖ In this circuit, a three-input NAND gate is connected to
address bits A19–A17.
❖ When all three address inputs are high, the output of
this NAND gate goes low and enables input 𝑮𝟐𝑩 of the
74LS138.
❖ Microprocessors 503431-3
50
Dr. Mohamed Abdelaziz
 College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

Sample Decoder Circuit

❖ Input G1 is connected directly to A16.
❖ In order to enable this decoder, the first four address
connections (A19–A16) must all be high.
❖ Address inputs C, B, and A connect to microprocessor
address pins A15–A13.
❖ These three address inputs determine which output pin
goes low and which EPROM is selected whenever 8088
outputs a memory address within this range to the
memory system.

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 College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

Sample Decoder Circuit

A circuit that uses eight 2764 EPROMs for a 64K x 8 section of memory in an 8088
microprocessor-based system. The addresses selected in this circuit are F0000H-FFFFFH

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 College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

8088 and 80188 (8-bit) MEMORY

INTERFACE
❖ In this section, we examine the memory interface to
both RAM and ROM.
❖ 8088/80188 microprocessors have an 8-bit data bus,
which makes them ideal to connect to common 8-bit
memory devices available.
❖ For the 8088/80188 to function correctly with memory,
however, the system must decode the address to select
a memory component

Microprocessors 503431-3
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 College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

Interfacing EPROM to the 8088

❖ The Figure illustrates an 8088/80188 microprocessor
connected to eight 2732 EPROMs, 4K x 8 memory
devices.
❖ The 2732 has one more address input (All) than the
2716, and twice the memory. The device in this
illustration decodes eight 4K x 8 blocks of memory, for
a total of 32K x 8 bits of the physical address space for
the 8088/80188.

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 College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

Interfacing EPROM to the 8088

❖ Notice that the decoder is selected for a memory address
range that begins at location F8000H and continues through
location FFFFFH—the upper 32K bytes of memory.
❖ This section of memory is an EPROM because FFFF0H is
where the 8088 starts to execute instructions after a
hardware reset. We often call location FFFF0H the cold-start
location.
❖ The software stored in this section of memory would contain
a JMP instruction at location FFFF0H that jumps to location
F8000H so the remainder of the program can execute.

Microprocessors 503431-3
55 Dr. Mohamed Abdelaziz
College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

Interfacing EPROM to the 8088

Eight 2732 EPROMs interfaced to the 8088 microprocessor.

Microprocessors 503431-3
56 Dr. Mohamed Abdelaziz
 College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

Interfacing RAM to the 8088

❖ RAM is a little easier to interface than EPROM because most
RAM memory components do not require wait states.
❖ An ideal section of the memory for the RAM is the very
bottom, which contains vectors for interrupts. Interrupt are
often modified by software packages, so it is rather
important to encode this section of the memory with RAM.
❖ In Figure, 16 62256 32K x 8 static RAMs are interfaced to
the 8088, beginning at memory location 00000H. This circuit
board uses two decoders to select the 16 different RAM
memory components and a third to select the other
decoders for the appropriate memory sections.

Microprocessors 503431-3
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 College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

Interfacing RAM to the 8088

❖ Sixteen 32K RAMs fill memory from location 00000H
through location 7FFFFH, for 512K bytes of memory.
❖ The first decoder (U4) in this circuit selects the other two
decoders. An address beginning with 00 selects decoder U3
and an address that begins with 01 selects decoder U9.
❖ Notice that extra pins remain at the output of decoder U4
for future expansion. These pins allow more 256K x 8 blocks
of RAM, for a total of 1M x 8, simply by adding the RAM and
the additional secondary decoders.

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College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

Data D0 - D7

Address A0 - A14

32 K x 8
SRAM
32 K x 8
WR WR SRAM
32 K x 8
RD OE SRAM
32 K x 8
Y0 CS
A15 A SRAM
32 K x 8
Y1 CS
A16 B SRAM
32 K x 8
Y2 CS SRAM
A17 C 32 K x 8
74138 Y3 CS
3 x 8 SRAM
32 K x 8
Decoder Y4 CS SRAM
G1
Y5 CS
G2A
Y6 CS
G2B
Y7 CS

Y0
A18 A
Y1
A19 B
Y2
C 74138 Y3
3 x 8
Decoder Y4
Vcc G1
Y5
G2A
Y6 32 K x 8
G2B SRAM
Y7 32 K x 8
WR SRAM
32 K x 8
OE SRAM
32 K x 8
Y0 CS
A15 A SRAM
32 K x 8
Y1 CS
A16 B SRAM
32 K x 8
Y2 CS SRAM
A17 C 32 K x 8
74138 Y3 CS
3 x 8 SRAM
32 K x 8
Decoder Y4 CS SRAM
IO/M G1
Y5 CS
G2A
Y6 CS
G2B
Y7 CS

A 512K byte static memory system using 16 62255 SRAMs

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 College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

8086 (16-Bit) Memory Interface

❖ The 8086, 80186, 80286, and 80386SX microprocessors
differ from the 8088/80188 in three ways:
(1) the data bus is 16 bits wide instead of 8 bits wide as on the 8088,
ഥ pin of the 8088 is replaced with an 𝑴/𝑰𝑶 pin, and
(2) the 𝑰𝑶/𝑴
(3) there is a new control signal called bus high enable (𝑩𝑯𝑬 ).
❖ The address bit A0 or 𝑩𝑳𝑬 is also used differently.
❖ 80286/80386SX contains a 24-bit address bus (A23–A0)
instead of A 20-bit address bus (A19–A0) of the
8086/80186.

Microprocessors 503431-3
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 College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

16-Bit Bus Control

❖ The data bus of the 8086, 80186, 80286, and 80386SX is twice as
wide as the bus for the 8088/80188. This wider data bus presents
us with a unique set of problems that have not been encountered
before.
❖ The 8086 must be able to write data to any 16-bit location—or any
8-bit location.
❖ This means that the 16-bit data bus must be divided into two
separate sections (or banks) that are eight bits wide so that the
microprocessor can write to either half (8-bit) or both halves (16-
bit).
❖ The Figure illustrates the two banks of the memory. One bank (low
bank) holds all the even-numbered memory locations, and the
other bank (high bank) holds all the odd-numbered memory
locations.
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 College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

16-Bit Bus Control

❖ –one bank (low bank) holds all even-numbered memory locations
❖ –the other bank (high bank) holds all the odd-numbered memory
locations.

The high (odd) and low (even) 8-bit memory banks of the
8086/80286/80386SX microprocessors.

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 College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

16-Bit Bus Control

❖ The 8086, 80186, 80286, and 80386SX use the signal
(high bank) and the A0 address bit or (Bus low enable) to
select one or both banks of memory used for the data
transfer. The Table depicts the logic levels on these two pins
and the bank or banks selected.
❖ Bank selection is accomplished in two ways:
(1) a separate write signal is developed to select a write to each bank of
the memory, or
(2) separate decoders are used for each bank. As a careful comparison
reveals, the first technique is by far the least costly approach to
memory interface for the 8086, 80186, 80286, and 80386SX
microprocessors.

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College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

16-Bit Bus Control

The high (odd) and low (even) 8-bit memory banks of the
8086 microprocessors.
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College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

16-Bit Bus Control

Memory bank selection using BHE and BLE (A0).

BHE BLE (A0) Function

0 0 Both banks enabled for a 16-bit transfer

0 1 High bank enabled for an 8-bit transfer
1 0 Low bank enabled for an 8-bit transfer
1 1 No banks enabled

Microprocessors 503431-3
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 College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

Separate Bank Decoders

❖ The use of separate bank decoders is often the least
effective way to decode memory addresses for the 8086,
80186, 80286, and 80386SX microprocessors.
❖ This method is sometimes used, but it is difficult to
understand why in most cases. One reason may be to
conserve energy, because only the bank or banks selected
are enabled.
❖ This is not always the case with the separate bank read and
write signals that are discussed later.
❖ The Figure illustrates two 74LS138 decoders used to select
64K RAM memory components for the 80386SX
microprocessor (24-bit address).
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 College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

Separate Bank Decoders

❖ Here, decoder U2 has the pin (A0) attached to , and
decoder U3 has the signal attached to its input.
❖ Because the decoder will not activate until all of its enable
inputs are active, decoder U3 activates only for a 16-bit
operation or an 8-bit operation from the low bank.
❖ Decoder U2 activates for a 16-bit operation or an 8-bit
operation to the high bank. These two decoders and the 16
64K-byte RAMs they control represent a 1M range of the
80386SX memory system. Decoder U1 enables U2 and U3 for
memory address range 000000H-0FFFFFH.

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 College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

Separate Bank Decoders

❖ Notice in Figure that the A0 address pin does not connect to
the memory because it does not exist on the 80386SX
microprocessor.
❖ Also notice that address bus bit position Al is connected to
memory address input A0, A2 is connected to Al, and so
forth. The reason is that A0 from the 8086/80186 (or from
the 80286/80386SX) is already connected to decoder U2
and does not need to be connected again to the memory.
❖ If A0 or is attached to the A0 address pin of memory, every
other memory location in each bank of memory would be
used. This means that half of the memory is wasted if A0 or
is connected to A0.
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College of Computers and Information Technology ‫كلية الحاسبات وتقنية المعلومات‬

Separate bank decoders.

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69 Dr. Mohamed Abdelaziz