Received 23 November 2022; revised 11 December 2022; accepted 21 December 2022.

Date of publication 23 December 2022;

date of current version 22 February 2023. The review of this article was arranged by Editor E. Sangiorgi.
Digital Object Identifier 10.1109/JEDS.2022.3231822

Overview on Latch-Up Prevention in CMOS

Integrated Circuits by Circuit Solutions
MING-DOU KER (Fellow, IEEE), AND ZI-HONG JIANG
Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu 300, Taiwan

CORRESPONDING AUTHOR: M.-D. KER (e-mail: [email protected])

This work was supported in part by the “Center for Neuromodulation Medical Electronics Systems” from The Featured Areas Research Center Program within the Framework of the Higher
Education Sprout Project by the Ministry of Education (MOE), Taiwan, and in part by the National Science and Technology Council (NSTC), Taiwan, under
Contract NSTC 109-2221-E-009-100-MY3, Contract NSTC 111-2321-B-A49-002, and Contract NSTC 110-2622-8-009-017- TP1.

ABSTRACT In CMOS chips, the wider layout rules were traditionally applied to overcome latch-up issues.
However, the chip area with wider layout rules was often enlarged, and in turn the chip cost was also
increased. To effectively improve latch-up immunity without enlarging the chip area, circuit methods
were therefore invented. An overview on circuit methodology used to prevent latch-up issues in CMOS
integrated circuits (ICs) is presented in this article. The circuit solutions, including reducing the I/O pad
trigger current, sensing the trigger current to control the power supply, and restarting the power supply
through an MOS switch to shut off the latch-up current, are overviewed.

INDEX TERMS Latch-up, latch-up prevention, silicon-controlled rectifier (SCR), guard ring, active guard
ring, voltage regulator, over-current detector.

I. INTRODUCTION
The parasitic silicon-controlled-rectifier (SCR) structure in
CMOS integrated circuits had been reported to cause seri-
ous latch-up failures [1], [2], [3], [4]. As shown in Fig. 1(a),
the SCR structure is a 2-terminal device with a four-layer
p-n-p-n path, which consists of two bipolar devices (QPNP
and QNPN ). The equivalent circuit of the latch-up (SCR) path
between the anode and cathode is shown in Fig. 1(b) [5], [6].
Since the collector current of QNPN is also the base current
of QPNP , if the trigger current Itn flows into the base of
QNPN and causes QNPN to enter the amplification work-
ing zone, QPNP will further amplify the collector current
of QNPN , which generates a positive-feedback regenerative FIGURE 1. (a) Four-layer p-n-p-n structure, and (b) the equivalent circuit
mechanism to establish the latch-up state. Similarly, when the of the latch-up (SCR) path from anode to cathode.

trigger current Itp flows into the base of QPNP , the latch-up
path will be triggered into the latch-up state. When a latch-
up path occurs, regardless of whether the trigger current diffusion) of PMOS in an N-well connected to VDD, and
Itn/Itp was removed, the latch-up path does not stop until the source (N+ diffusion) of NMOS in the p-well/p-substrate
the chip burns out. Thus, IC engineers had been advised connected to VSS (GND), the p-n-p-n path forms the par-
to be mindful of latch-up failures during circuit design and asitic latch-up path from VDD to VSS, which is shown
chip layout. in Fig. 2(b). Moreover, the cross-sectional view of the para-
The typical parasitic p-n-p-n path (P+/N-well/P-well/N+) sitic p-n-p-n path inside a CMOS inverter and the equivalent
in the layout of a CMOS inverter drawn with well taps circuit that causes latch-up issues are shown in Figs. 3(a)
(pickups) is shown in Fig. 2(a). With the source (P+ and 3(b), respectively. The typical I–V characteristic of the
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FIGURE 2. (a) Typical layout top view of CMOS inverter with well taps
(pickups), and (b) the parasitic latch-up path in the CMOS inverter.

FIGURE 3. (a) Cross-sectional view of CMOS inverter, and (b) the

equivalent circuit of the latch-up path from VDD to VSS. FIGURE 4. (a) The illustrated I-V characteristics of the parasitic latch-up
path in a CMOS technology. (b) The measured DC I-V characteristics of the
parasitic latch-up path in a CMOS inverter cell drawn with foundry’s design
rules and pickups, fabricated in a 0.18-µm bulk CMOS process.

parasitic latch-up path is illustrated in Fig. 4(a). The mea-

sured DC I-V characteristics of the parasitic latch-up path is illustrated in Fig. 5(b), where the overshooting peak volt-
in a CMOS inverter cell drawn with foundry’s design rules age (Vp) is often 1.5 times of VDD voltage level. With the
and pickups, fabricated in a 0.18-μm bulk CMOS process, is trigger current applied to the I/O pins, or the transient volt-
shown in Fig. 4(b). The holding voltage is only 1.02V mea- age applied to the power pins, the latch-up events may occur
sured at room temperature, even if the pickups (P+ diffusion in the region of I/O cells, or even in the region of internal
in P-well, N+ diffusion in N-well) had been drawn inside the circuits [8], [9], [10], [11], [12], [13], [14], [15], [16].
layout area the CMOS inverter. Once the parasitic latch-up To increase latch-up immunity of CMOS ICs, the typ-
path is triggered, the vertical QPNP and lateral QNPN tran- ical layout skills include increasing the anode and cath-
sistors are kept on due to the positive-feedback regenerative ode spacing, improving the width of the guard rings,
mechanism. Typically, the SCR has a lower holding volt- and adjusting the spacing between guard rings. Also,
age (Vh) of ∼1V in the bulk CMOS technologies, which some process optimizations in CMOS technology had
was often smaller than the VDD of internal circuits. The been implemented [17], [18], [19], [20], [21], [22], which
triggered-on latch-up path will conduct a huge abnormal cur- include trench isolation, SOI (Silicon on Insulator), ret-
rent flowing from the power supply (VDD) to GND, which rograded well, and epitaxy (Epi) wafer, etc. Additional
often burns out the chip. passive guard rings had also been applied [23], [24], [25],
To verify the latch-up immunity of CMOS ICs, the JEDEC [26], [27]. However, even if high latch-up immunity can
Standard for IC Latch-Up Test [7] has been widely used be achieved by implementing the aforementioned meth-
in the IC industry. The I/O cell under latch-up test with ods, they may increase the manufacturing cost or chip
the applied positive or negative trigger current is illustrated area. Therefore, to look for a cost-efficient solution for
in Fig. 5(a). An overshooting or undershooting trigger cur- improving latch-up immunity has been strongly requested
rent of 100 mA is applied to each I/O pin to seek whether by the cost-sensitive consumer IC products. IC designers
any latch-up event occurs in the chip, or not. In addition, were required to save the fabrication cost without uti-
the voltage fast transient on the VDD power supplies may lizing extra mask layers and/or process steps, to reduce
induce latch-up occurrence in CMOS ICs. The latch-up test the layout spacing between the PMOS and NMOS, and
with the voltage-transient trigger applied to the VDD pins even to reduce the width of guard rings. Thus, some

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FIGURE 5. Latch-up test for a CMOS IC with (a) the overshooting or undershooting trigger current at the I/O pad, and (b) the voltage-transient trigger at
the VDD pad.

circuit solutions are invented to effectively improve latch- Section II. In Section III, a novel auto-detector circuit
up immunity of CMOS ICs, without enlarging the chip to sense the trigger current injecting from the I/O cells,
layout. and then to stop latch-up current in the internal circuits
Without additional process modification, the passive guard for latch-up prevention, is presented [31]. Moreover, TLU
rings in layout placement are universally applied for latch- (transient-induced latch-up) is more easy to cause the latch-
up preventions. The devices located at the I/O pads must up occurrence located inside the internal circuit blocks of
be surrounded by double guard rings, as specified by the CMOS ICs [11], [12], [13], [14], [15], [16]. Thus, the power
design rules of foundry [27], to overcome the latch-up issues supply restart method with switching control circuit is used
at the I/O pads. Thus, the latch-up event would not occur to interrupt the latch-up current path from the power line to
in the IO cells, when the I/O cell layout has been drawn the internal circuit blocks [32], [33], [34], [35], [36]. The
with the suitable guard rings. However, in order to save power supply restart to stop the latch-up current by MOS
layout area, the devices of the internal circuits would not be switches is reviewed in Section IV. Comparisons among the
surrounded by guard rings. Only some pickups (P+ diffusion circuit solutions to improve latch-up immunity are discussed
in P-well, N+ diffusion in N-well) are drawn inside the in Section V, and an example of application with the auto-
layout area of internal circuits to provide the correct biases detector circuit in a digital IC is given in Section VI. Finally,
to the P-well and N-well. Therefore, the internal circuits, a conclusion is given in Section VII.
with no guard rings surrounding, are still sensitive to latch-
up issues. As shown in Fig. 5(a), the P+ drain/N-well (N+ II. ACTIVE GUARD RING
drain/P-well) junction in the I/O PMOS (NMOS) device For the traditional latch-up prevention on the I/O cell with
is forward-biased to conduct the positive (negative) trigger guard rings, the guard rings are drawn to fully surround the
current into the substrate. Hence, the passive guard ring may I/O or ESD (electrostatic discharge) devices in layout. Some
not completely absorb the latch-up trigger current. Since a design rules to specify the widths and spacings of guard
part of the trigger current is injected into the p-type substrate rings were often given by the foundries. In addition, the
and flows towards the internal circuit blocks, the parasitic spacing from the I/O cells to the blocks of internal circuits
p-n-p-n path of the internal circuits can be fired to cause must be drawn wider (∼ 50 µm, or even more) in layout to
latch-up event [27]. As a result, the circuit methods of active avoid the latch-up event occurrence in the internal circuits
guard ring were therefore reported to improve the latch-up due to the trigger current applied to the I/O pads [27]. If the
immunity of CMOS ICs [28], [29], [30]. specification of latch-up immunity was requested higher, the
In this article, the active guard ring to improve latch- aforementioned widths and spacings must be drawn further
up immunity by circuit methodology is first reviewed in wider to result in a bigger chip layout. Thus, the concept

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of additional junctions of BJTs (Qn_sen and Qp_sen), a

sensing circuit block, and two large-dimensional ESD protec-
tion transistors (Mpesd and Mnesd). The Qn_sen and Qp_sen
are used to sense and monitor latch-up trigger current levels.
The base terminal of Qn_sen is connected to VSS, the base
terminal of Qp_sen is connected to VDD, and the emitter
terminals of these two BJTs are connected to the I/O pad.
The gate terminal of Mnesd is connected to the collector
of Qp_sen, which is also connected to ground via a poly
resistor RN. The gate terminal Mpesd is connected to the
collector of Qn_sen, which is also connected to VDD via a
poly resistor RP. During the normal circuit operating condi-
FIGURE 6. Concept of “active guard ring” designed to reduce the current
injecting to the internal circuits during latch-up I-tests. tion, the ESD protection transistors (Mpesd and Mnesd) are
kept in the off state.
When a negative trigger current is applied at the I/O pad
during the latch-up I-test, the Qn_sen detects the latch-up
current perturbations and then pulls low the gate of the
Mpesd. Qn_sen can be turned on and produce a sensing
current (In_sen). When In_sen is sufficient to pull down
the gate terminal (QN) of Mpesd, quite a large amount of
compensating current (Icomp) can be produced from VDD
to the I/O pad. So, with the source-to-drain current of Mpesd
(Icomp) increased, the negative trigger current applied at the
I/O pad can be neutralized. Thus, the substrate perturbation
current from the I/O or ESD devices flowing toward the
internal circuits can be decreased during the latch-up negative
I-test.
On the contrary, when a positive trigger current is applied
from an external source during the latch-up I-test, the pad
voltage is pulled over the supply voltage VDD, and Qp_sen
FIGURE 7. Circuit structure of the active guard ring implemented with BJT can be turned on to produce a sensing current (Ip_sen).
junctions [29].
When Ip_sen is sufficient to pull up the gate terminal (QP)
of Mnesd, quite a large amount of extra sink current (Isink)
can be produced by the Mnesd of large device dimension
of “active guard ring” realized by circuit methodology to
to neutralize the positive trigger current applied at the I/O
effectively improve latch-up immunity without enlarging the
pad. Thus, the latch-up immunity of the internal circuits
layout spacings was reported [28], [29], [30].
against the latch-up I-test applied at the I/O pad can be
The concept of “active guard ring” is illustrated in Fig. 6,
significantly improved. The effectiveness of such a circuit
where the sensing circuit is used to detect the current inject-
implementation of active guard ring has been successfully
ing from the I/O or ESD devices during the latch-up I-test
verified in the silicon chip [29].
with positive or negative trigger currents applied at the I/O
pad. Then, some compensation currents (Isink or Icomp) are
B. ACTIVE GUARD RING WITH ADDITIONAL MOS [30]
generated to “neutralize” the trigger current that applied to
The circuit structure of active guard ring implemented
the I/O pad. Finally, the current injecting from the I/O or
with additional MOS transistors is shown in Fig. 8, which
ESD devices toward the internal circuits can be dramatically
includes a sensing circuit block, two large-dimensional ESD
reduced to avoid the latch-up occurrence in the internal cir-
protection transistors (Mpesd and Mnesd), and two resistors
cuits. By using such a circuit solution of “active guard ring”,
(RP and RN) in the sensing circuit. Under normal circuit
the latch-up immunity against latch-up I-test with trigger cur-
operation, the gate voltage (VGP) of PMOS (MPS) is biased
rents applied at the I/O pad can be significantly improved,
to VDD through RP, and the gate voltage (VGN) of NMOS
without enlarging the layout spacing between the I/O cells
(MNS) is biased to ground through RN. So, the ESD pro-
and the internal circuits.
tection transistors (Mpesd and Mnesd), with VGP voltage
level at VDD and VGN voltage level at ground, are kept in
A. ACTIVE GUARD RING WITH BJT JUNCTION [29] the off state.
In Fig. 7, the circuit structure of the active guard ring is Under the latch-up I-test with the positive trigger current
implemented by the additional junctions of bipolar junc- applied to the I/O pad, the pad voltage (Vpad) will be raised
tion transistors (BJTs). The active guard ring is composed higher than VDD. When the Vpad is larger than the gate

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FIGURE 8. Circuit structure of active guard ring implemented with

additional MOS transistors [30].

voltage (VGP) of MPS over a threshold voltage, MPS will

be turned on. As a result, the gate voltage (VGN) of Mnsed
will be pulled up by the channel current (Ip_sen) of MPS,
and the large-dimensional Mnsed will be turned on to con-
duct the positive trigger current from the I/O pad to VSS.
Thus, the latch-up risk is improved by injecting less current
into the substrate.
Under the latch-up I-test with the negative trigger current
applied to the I/O pad, Vpad will be pulled down to a low FIGURE 9. (a) The function block diagram of the auto-detector circuit to
stop the latch-up current, and (b) the control logic in the detector circuit
voltage level below VSS. The MNS will be turned on, once block [31].
the Vpad is lower below a threshold voltage of VGN. The
gate voltage (VGP) of Mpsed will be pulled down by the
channel current (In_sen) of MNS. As a result, the large- The auto-detector circuit to stop the latch-up current for
dimensional Mpesd is turned on to conduct current from latch-up prevention is shown in Fig. 9(a). To detect the
VDD to the I/O pad that compensates the negative trigger injecting holes (electrons) when a positive (negative) trigger
current applied at the I/O pad. Therefore, the latch-up trig- current is applied to the I/O pad during the latch-up I-test,
ger current injecting into the p-substrate toward the internal a long strip of P+ diffusion (N+/ N-well layer) is inserted
circuits can be significantly reduced, and the overall latch-up between the I/O cells and the internal circuit blocks (accom-
immunity can be effectively strengthened. The effectiveness plished by a ring oscillator). The signal at the P1 node is
of such a circuit implementation of active guard ring with the output of the hole detector, which was constructed using
additional MOS transistors has been already proven in the the P+ diffusion and connected to VSS (GND) with a poly
silicon chip [30]. resistor RP of 1 k. The signal at the N1 node is the out-
put of the electron detector, which was made by the N+
III. AUTO-DETECTOR CIRCUIT TO STOP LATCH-UP diffusion in the N-well and connected to VDD through a
The concept of an auto-detector circuit is to sense the poly resistor RN of 1 k. The P1 and N1 signals are sent
trigger current from the I/O pad to control the power sup- to the detector circuit block using the logic gates depicted
ply [31]. Under the latch-up I-test, the latch-up trigger current in Fig. 9(b). The output signal of the detector circuit block
injecting toward the internal circuits can be detected by (SW_DETR) is used to control the gate of a PMOS transistor
adding a hole/electron detector between the I/O cells and (MP3) in the LDO circuit that provides the power supply
the internal circuits. The output of the auto-detector cir- (VDD_OSC) to the internal circuits (ring oscillators). To
cuit is utilized to turn off the LDO (low dropout regulator), control the gate voltage of MP3 (SW_DETR), two inverters
which provides the power supply to the internal circuits. (MP1, MP2, MN1, and MN2) are used to detect the logic
Thus, the latch-up occurrence in the internal circuits can signals at nodes N1 and P1. The logic gate NOR is used
be entirely stopped to prevent burned-out failures inside the to control the logic states N1 and P1, and the EN of MUX
chip. is used to select whether the auto-detector circuit is enabled

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or not. To fully avoid latch-up issues between PMOS and

NMOS in these circuit blocks, all of the devices utilized in
the detector circuit and LDO are well surrounded by guard
rings in the layout.
Under normal circuit operation conditions (no latch-up
trigger current applied at the I/O pad), since the resistor RP
(RN ) is connected to GND (VDD), the voltage at node P1
(N1) is kept at GND (VDD). Thus, the SW_DETR is kept
at VDD by the detector circuit, and the MP3 is kept off. The
LDO will generate a stable regulated voltage to VDD_OSC,
and the internal circuits (ring oscillator) will perform their
normal circuit functions.
Under the latch-up I-test with positive trigger current
applied to the I/O pad, the injecting holes (from the positive
trigger current) towards the ring oscillator (internal circuits)
are detected by the hole detector (a long strip of P+ dif-
fusion placed between the I/O cells and internal circuits), FIGURE 10. The latch-up current detection and recovery circuit [32].
which causes the voltage level at node P1 to be raised.
When the state at P1 is changed from low to high, the state
at SW_DETR (the output of the detector circuit) is switched IV. RESTART POWER SUPPLY TO STOP LATCH-UP
to low. Then, the MP3 will be turned on, and the LDO will CURRENT
be turned off. Due to MP3 being turned on and MP0 being Due to the parasitic latch-up paths in CMOS ICs, tran-
turned off, the LDO circuit stops to generate the power sup- sient trigger noise appears not only in the I/O pad but also
ply to the VDD_OSC of ring oscillator. Without any power in the internal core circuits through the metal connections
supply to VDD_OSC, any current flowing through the latch- of the VDD/GND power lines. When the parasitic latch-
up paths in the internal circuits can be automatically stopped. up path is triggered, the huge current through the latch-up
After the latch-up I-test, no positive trigger current is applied path can cause irreversible damage to the internal circuits.
to the I/O pad (no hole injecting towards the internal cir- However, the latch-up state can be removed if the power
cuits), so the voltage level at node P1 returns to GND. The supply is stopped. By switching the control circuit on power
state of SW_DETR returns to high, and the LDO circuit supply, the over-current detection circuits were invented
restarts working normally to supply voltage to VDD_OSC. to interrupt the current flow of the latch-up path [32],
Finally, the internal circuits return to their normal circuit [33], [34], [35], [36], and therefore to stop the latch-up
functions. current.
When a negative trigger current is applied to the I/O cell
during the latch-up I-test, the injecting electrons (from the A. LATCH-UP DETECTION AND RECOVERY
negative trigger current) towards the internal circuits are CIRCUIT [32], [33]
then detected by the electron detector (N+/ N-well placed The concept of latch-up current detection and recovery cir-
between the I/O cells and internal circuits), which causes the cuit is shown in Fig. 10 [32]. The circuit includes a power
voltage level at node N1 to be pulled down. When the state control switch MP1 (or MN1) and a latch-up detection cir-
at N1 is changed from high to low, the state at SW_DETR cuit, which controls the gate of the switch MP1 (or MN1).
(the output of the detector circuit) is switched to low, causing The internal core power supply VDDI is generated from the
the MP3 to be turned on, and then the MP0 will be turned voltage regulator. When the parasitic latch-up path of the
off. So, the LDO circuit will be turned off. Because there core circuit block is triggered, an extensive dc-current will
is no power supply to the VDD_OSC, any current flowing appear between the VDDI and VSSI. Thus, the large current
through the latch-up paths in the internal circuits can be will cause the power supply voltage (VDD) to drop signif-
automatically stopped. After the latch-up I-test, no negative icantly, which is detected by the latch-up detection circuit.
trigger current is applied to the I/O pad (no hole injecting Then, the switch MP1 (MN1) is turned off by the PMOS
towards the internal circuits), so the voltage level at node (NMOS) bias control to interrupt the latch-up current from
N1 returns to VDD. The state of SW_DETR returns to high, the voltage regulator to the internal circuits, so the latch-up
and the LDO circuit restarts its normal operation to supply state can be removed. Finally, the power supply will be re-
voltage to VDD_OSC. The internal circuits return to their started to support the normal circuit operations in the internal
normal circuit functions. circuits.
With such an innovative circuit solution, the latch-up To realize such a circuit concept, the latch-up prevention
immunity of CMOS ICs can be substantially increased, but circuit which composed of an intended function circuit and a
with a short distance between the I/O cells and the blocks latch-up detection circuit is shown in Fig. 11 [33]. A switch
of internal circuits to save the chip layout area [31]. MN0 with a resistor R1 is connected between the ground

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FIGURE 11. Realization of a latch-up prevention circuit [33].

FIGURE 12. Latch-up current self-stop circuit [34].

terminal and the intended function circuit to prevent latch-up

issues. The latch-up detection circuit, which is composed B. LATCH-UP CURRENT SELF-STOP CIRCUIT [34]
of two inverters (MP1, MP2, MN1, and MN2), MN0, R1, The latch-up current self-stop circuit realized with a MOS
and R2, is used to turn the power on or off of the intended switch and a current mirror detector is shown in Fig. 12 [34].
function circuit. The power-down control signal is the output The circuit consists of a PMOS switch MP1, a diode-
of the latch-up detection circuit, and it decides whether the connected NMOS MN1 with its current mirror pair MN2,
intended function circuitry is enabled or disabled. When the and the circuit (INV and R) used to bias the gate of MP1.
power-down signal has a low value (logical low), the power The current extractor of the internal core circuit is made by
supply for the intended function circuitry operates normally. using MN1 and MN2 NMOS transistors built as a current
In a power-down state with a high value (logical high), the mirror. The resistor R between VDD and the inverter (INV)
power supply for the intended function circuitry is removed input node A is used for the current-voltage converter, which
to stop the latch-up event. provides the feedback current signal to control the gate of
During normal circuit operations, the voltage difference switch MP1 via the INV inverter.
between node VSS and the ground (GND) is small due to the During the normal circuit operation, the voltage drop on
R1 of lower resistance. Therefore, transistor MP1 is turned the resistor R is minimal since the current flowing through
on, and the gates (node A) of the MP2 and MN2 are pulled it is relatively small. The input stage of inverter INV node
to logic “High”, which causes the MN2 to be turned on and A coupled to VDD by the resistor R is biased in the “high”
to pull the power-down signal to a lower voltage level. So, state, which makes the gate of the MP1 transistor biased at a
the power-down signal is logical “Low”, and the intended “low” state. So, the MP1 is turned on, and the power supply
function circuitry is running normally. VDD is passed to the internal core circuit (VDDI). The
When a latch-up issue occurs inside the intended func- internal core circuit can be generally operating to perform
tion circuit, the huge latch-up current conducting through the intended circuit functions.
R1 will cause a greater voltage drop between node VSS and If the parasitic latch-up path inside the internal core circuit
ground (GND). Because the voltage drop exceeds the thresh- was triggered on, a large current will appear on the path from
old voltage of transistor MN1, the MN1 will be turned on VDD to GND through MP1 and MN1. When a huge current
to pull down the voltage level at node A, and then the gate is identified, it will be mapped to MN2 and the resistor R
of the MN0 will be turned off to stop the current flowing by the current mirror. The voltage drop across the resistor
out from the intended function circuit. As transistor MN1 R is greatly increased by the mapped large current. This
is turned on, node A is also pulled low, which causes the large voltage drop makes the state of the INV input node A
MP2 to be turned on and the MN2 to be turned off to pull changing from “high” to “low”, and then the PMOS switch
the power-down signal to logical “High”. The intended func- of MP1 is turned off. When the MP1 is turned off, the huge
tion circuitry will be in a power-down state, so the latch-up latch-up current flowing through the parasitic latch-up path
occurrence can be removed by stopping the current of the in the internal core circuit can be stopped, and the latch-up
latch-up path. occurrence is removed.
After the latch-up condition ends, the voltage level at When the latch-up current is shut off, the voltage drop on
VSS node will be pulled low again due to the resistor R2 the resistor R is decreased to zero, so that the output state of
of some suitable resistance, and then the power-down signal the inverter INV is changed into a “low” state, and then the
goes back to a “low” state, and the intention circuit is turned switch MP1 is re-turned on. Thus, the internal core circuit
back to its normal circuit operation. is auto-reset and back to its normal circuit operation again.

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FIGURE 13. (a) The voltage regulation with latch-up prevention circuit,
and (b) the corresponding latch-up detection circuit [35]. FIGURE 14. The latch-up over-current prevention circuit independent of
power module [36].

C. VOLTAGE REGULATION WITH LATCH-UP PREVENTION

CIRCUIT [35] then transistor MN4 is turned on, which further discharges
The combination of voltage regulation and latch-up pre- node I and increases the rising voltage of output C. The
vention circuit is shown in Fig. 13(a) [35]. The voltage latch-up detection circuit turns off the transistor MP1 and
regulation is composed of an amplifier (AMP), a power tran- turns on the transistor MN1. Then, the MNPWR is turned
sistor MNPWR, and a latch-up detection circuit. The latch-up off to stop the latch-up current in the internal core circuit.
prevention circuit is made up of a latch-up detection circuit,
a switch transistor MP1, and MN1. The output (node C) of D. LATCH-UP OVER-CURRENT PREVENTION CIRCUIT [36]
latch-up detection circuit is used to enable or disable the The latch-up over-current prevention circuit independent of
power transistor (MNPWR) by switching MP1 and MN1. power module is shown in Fig. 14, which consists of a
The corresponding circuit implementation for the latch-up higher-current switch MP1, an equal proportional current
detection circuit is shown in Fig. 13(b), which includes the sensing module, a judging module, and a self-starting mod-
transistors MN2, MP2, MP3, MN3, an RC averaging circuit ule. A higher-current switch MP1 is connected to the power
(R1 and C1), and a feedback transistor MN4. The AMP out- pad (VDD), the chip power manager module, and the internal
put node A is connected to the gate of MN2, whose drain core circuit, while the chip power manager module is con-
is connected to the external power supply voltage VDD1 nected to the self-starting module. The switch MP1 is used
and whose source is connected to the source of two series- to interrupt the latch-up current path from the power line
connected MP2 and MP3. Node M is defined by the coupled VDD to the internal core circuit. The latch-up state can be
sources of transistors MN2 and MP2, which are also con- released and then auto-reset back to normal operation again
nected to the capacitor C2 to stabilize the voltage at node M. by the self-starting module and the judging module.
Node I is connected to the gates of MP3 and MN3, as well An equal proportion current detection module consists
as the RC averaging circuits R1 and C1. of a lower-current switch MP2, an operational amplifier
During normal circuit operation, the voltage regulation (AMP) connected to a negative feedback loop, which is used
provides a constant voltage to the internal core circuit, and to ensure that the drain voltage of higher-current switch
the gate of transistor MP1 is turned on due to the latch-up MP1 and lower-current switch MP2 are identical, and a
detection circuit output (node C) being at a lower voltage. PMOS transistor MP3 is used to control the feedback volt-
The MN1 is turned off, and the power transistor MNPWR age. In addition, the sources of the higher-current switch
is turned on. MP1 and the lower-current switch MP2 are connected to
If the latch-up path inside the internal core circuit was the power supply VDD to ensure that I1 and I2 are pro-
triggered on, a huge latch-up current will flow from VDDI portional, and I1 is the K times of I2, which provides
to GND, and the VDDI is dropped down. The internal power the current sense function of MP1 and MP2 to be enabled
supply voltage VDDI is connected to the input of the detec- synchronously.
tion circuit, and the voltage at node I decreases with a time In the judging module, an equal proportion of output cur-
constant determined by R1 and C1. As the voltage level of rent (I2) is converted to voltage with the drain of transistor
node I falls below that of node M by two threshold volt- MP3 via resistor R1, which is connected to the positive
ages (i.e., the threshold voltage drops of transistors MP2 input terminal of a comparator (COPM). Besides, the neg-
and MP3), the output C rises to a high voltage value, and ative input terminal reference voltage (VREF) is used to

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determine whether the I2 exceeds the pre-set threshold or proposed to improve latch-up immunity. In addition, the auto-
not. The self-starting module is composed of a low-voltage- detector circuit with the corresponding control circuits was
to-high conversion circuit (L to H) and a delay circuit. The invented to detect the latch-up trigger current that injected
output voltage of the self-starting circuit (V_EN) and output toward the internal circuits, and then to stop the power sup-
voltage (VC) of COMP are the input terminals to the logic ply of the internal circuits to avoid the permanent hardware
AND gate in the judging module. The output (Vctrl) of logic failure. The power supply of the internal circuits will be
AND gate is used to control whether the MP1 is enabled or automatically re-supplied when the injected latch-up trigger
disabled. current was disappeared. On the other hand, when the tran-
Under normal conditions, the output current I2 of the equal sient current or voltage was coupled into the internal core
proportion detecting module is converted to a voltage by R, circuits to cause latch-up events inside them, the power sup-
which is less than the reference voltage VREF. Therefore, ply of internal circuits can be reset and re-started by the
the output of COMP (VC) is logic low, the output of the MOS switch to shut down the latch-up current path inside
judgment module is also logic low, and the higher-current the internal circuits. The MOS switches are controlled by
switch MP1 is kept in conduction. the corresponding latch-up detection circuits, which required
When the latch-up issue occurs in the internal core circuit, some additional layout area to implement the switch with
the current I1 flowing to VDDI will be increased signif- acceptable transient and steady-state voltage drops.
icantly. Thus, the output of the equal proportion current In the design of “active guard ring”, with some additional
detecting module incrementally exceeds the default refer- devices directly connected to the I/O pads, a little increase
ence voltage, followed by the corresponding output voltage of capacitive loading from the added devices will be seen
of I2. As a result, the judgment circuit generates the sig- by the signals at the I/O pads. In the circuit solution of
nal (Vctrl) “High” to turn off the switch MP1, and the auto-detector circuit or the method to restart power supply,
current to the power manager for the internal core circuit there was no device of the proposed circuits directly added
will be stopped. The latch-up occurrence in the internal to the I/O pads. Thus, no capacitive loading was seen by
core circuit will be resolved when the power supply to the signals at the I/O pads. The comparisons among various
the power manager is disconnected. After that, the power latch-up prevention by circuit solutions were summarized in
manager module is detected at a low-level voltage by the Table 1.
self-starting circuit. The high-current switch MP1 is turned
on again, the power manager is recovered, and the nor- VI. EXAMPLE OF APPLICATION
mal functional operation of the internal core circuit is To explore the advantage of the proposed auto-detector cir-
restored. cuit [31], a CMOS digital IC with 44 pads is depicted in
Fig. 15, where there are 40 I/O pads, two power pads, and
V. DISCUSSION AND COMPARISON two ground pads. The power and ground pads used for I/O
With the inherent parasitic SCR paths in CMOS technology, cells are usually different from the power and ground pads
the latch-up issue has been one of the main reliability con- used for internal circuits. The auto-detector circuit and LDO
cerns in CMOS IC products. To avoid damage or reliability are supplied with the power (VDDI) and ground (VSSI)
issues from latch-up events in harsh environments, such as pads for internal circuits, and the power of internal circuits
industrial applications or automotive applications, latch-up (logic gates) is supplied by the output of LDO (voltage
prevention must be paid more attention not only in chip lay- regulator). With the I/O cell library provided by foundry,
out phase, but also in the beginning of circuit design phase. each I/O cell has been drawn with a fix cell layout area of
It may be a good way to use the additional process modifi- 60µm x 180µm, including the bonding pad. There are 11
cation provided by the foundry to overcome latch-up issues. pads arranged at each side of the 44-pin CMOS IC, and
But, the corresponding cost of chip fabrication will become the corner cells are applied at the four corners to provide
expensive. Hence, the cost-efficient solution by using circuit the metal connections among the I/O cells located at the
methods was proposed to enhance latch-up immunity in the four sides of the chip layout. Finally, the total chip area
IC industry. of this 44-pin CMOS IC realized in a 0.18-µm 1.8V/3.3V
The devices located at the I/O pads must be surrounded CMOS process with the typical I/O cell library is 1085µm
by double guard rings, as specified by the design rules of x 1085µm, whereas the area for the internal core circuits
foundry, to overcome the latch-up issues at the I/O pads. is 725µm x 725µm. The spacing between the I/O cells and
Thus, the latch-up event would not occur in the IO cells, the internal core circuits is 15 µm, in which the P+ and
when the I/O cell layout has been drawn with the suitable N+ diffusion rings used to detect the latch-up trigger current
guard rings. But, the internal circuits, with no guard rings injecting from the I/O cells are drawn as 2 µm in width,
surrounding the devices, are sensitive to latch-up issues. To and 2 µm spacing between them. These P+ and N+ diffu-
reduce the latch-up trigger current (that applied at the I/O sion rings, which are placed at each side between the I/O
pad with the I/O circuits) injected into the internal core cells and the internal core circuits, are connected together
circuits, the circuit solution of “active guard ring” has been by metal lines to the latch-up auto-detector circuit. Thus,

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TABLE 1. Comparisons among the circuit solutions to improve latch-up immunity.

TABLE 2. Layout area occupied by each block in a CMOS digital ic of

44 pads implemented with auto-detector circuit.

the latch-up trigger current applied to the I/O pads at each

side of the CMOS IC can be detected and sent to the auto-
detector circuit. The output of the auto-detector circuit is
used to shut down the LDO (voltage regulator) which sup-
plies the power to the internal circuits (logic gates). Thus, the
latch-up current in the internal circuits can be fully stopped
to avoid the burned-out failure. When the latch-up trigger
current disappears, the LDO (voltage regulator) will return
back to its normal function to supply the power for internal FIGURE 15. The chip layout to show the application of the proposed
circuits. auto-detector circuit and LDO in a CMOS digital IC with 44 pads, realized
Layout area occupied by each block in a CMOS digi- in a 0.18-µm 1.8V/3.3V CMOS process.
tal IC of 44 pads implemented with auto-detector circuit to
overcome latch-up issue has been listed in Table 2. With
the calculation on the layout area of each block in Fig. 15, the CMOS IC to meet the practical applications in harsh
the area occupied by all I/O cells (including pads), the environments.
internal core circuit (logic gates), the LDO (voltage reg-
ulator), and the auto-detector circuit are 55.83%, 40.5%, VII. CONCLUSION
3.6%, and 0.07%, respectively. Without widely enlarging A comprehensive overview of circuit solutions for latch-up
the spacing between the I/O cells and internal circuits, prevention is presented in this article. The parasitic p-n-p-n
the proposed method with the auto-detector circuit and structure is inherent in the bulk CMOS technology, which
LDO co-operation can perform high latch-up immunity for often caused latchup failure of CMOS ICs during the field

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applications. In the applications with harsh environment, [16] C. C. Yen, M. D. Ker, and T. Y. Chen, “Transient-induced
the overshooting/undershooting noise glitches coupling to latchup in CMOS ICs under electrical fast-transient test,” IEEE
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would be huge. The latchup immunity of CMOS ICs in [17] D. B. Estreich, A. Ochoa, and R. W. Dutton, “An analysis
such harsh applications has been requested with a much of latch-up prevention in CMOS IC’s using an epitaxial-buried
layer process,” in IEDM Tech. Dig., Dec. 1978, pp. 230–234,
higher specification, as compared to that used in the con- doi: 10.1109/IEDM.1978.189394.
sumer electronics. In the scaled-down CMOS technology [18] A. G. Lewis, R. A. Martin, T. Y. Huang, J. Y. Chen, and
with shorter distances between devices in the chip lay- M. Koyanagi, “Latchup performance of retrograde and conventional
n-well CMOS technologies,” IEEE Trans. Electron Devices, vol. 34,
out of CMOS ICs, the latch-up paths would be easily no. 10, pp. 2156–2164, Oct. 1987, doi: 10.1109/T-ED.1987.23211.
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ICs, circuit solutions have been proposed to overcome the [20] S. Voldman et al., “The influence of a silicon dioxide-
latch-up issues, which did not require high costs of uti- filled trench isolation structure and implanted sub-collector on
lizing additional process layer or a wider distance in chip latchup robustness,” in Proc. IRPS, Apr. 2005, pp. 112–120,
doi: 10.1109/RELPHY.2005.1493072.
layout. Latchup prevention in CMOS ICs by circuit solu- [21] S. H. Voldman, “The influence of a novel contacted polysili-
tions is an emerging topic that IC designers shall pay confilled deep trench (DT) biased structure and its voltage bias
attention. state on CMOS latchup,” in Proc. IRPS, Mar. 2006, pp. 151–158,
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[22] J. P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI.
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[23] J. Quincke, “Novel test structures for the investigation of the effi-
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MING-DOU KER (Fellow, IEEE) received the ZI-HONG JIANG received the B.S. degree in
Ph.D. degree from the Institute of Electronics, electronic engineering from the National Taiwan
National Chiao Tung University (NCTU), University of Science and Technology, Taipei,
Hsinchu, Taiwan, in 1993. Taiwan, in 2017. She is currently pursuing the
He is currently a Chair Professor with the Ph.D. degree on the topic of latch-up prevention
Institute of Electronics, National Yang Ming in CMOS ICs with the Institute of Electronics,
Chiao Tung University (NYCU), Hsinchu, where National Yang Ming Chiao Tung University,
he is the Director of the Institute of Pioneer Hsinchu, Taiwan.
Semiconductor Innovation and Biomedical
Electronics Translational Research Center. In the
technical field of reliability and quality design
for microelectronic circuits and systems, he has authored/coauthored
over 610 technical papers in international journals and conferences. He
has proposed many solutions to improve the reliability and quality of
integrated circuits, which have been granted with hundreds of U.S. patents.
He had been invited to teach and/or to consult the reliability and quality
design by hundreds of design houses and semiconductor companies in
the worldwide IC industry. Some of his inventions or designs had been
widely used in the modern IC products and microelectronic systems. His
current research interests include the reliability and quality design for
nanoelectronics and gigascale systems, as well as the circuits and systems
for biomedical applications. He had served as a member of the Technical
Program Committee and the Session Chair of numerous international
conferences for many years, including IEEE Symposium on VLSI Circuits,
IEEE International Solid-State Circuits Conference, IEEE International
Symposium on Circuits and Systems, and IEEE International Reliability
Physic Symposium. He ever served as the Distinguished Lecturer in the
IEEE Circuits and Systems Society form 2006 to 2007 and in the IEEE
Electron Devices Society from 2008 to 2020 and an Associate Editor
of IEEE TRANSACTIONS ON VLSI SYSTEMS, IEEE TRANSACTIONS ON
BIOMEDICAL CIRCUITS AND SYSTEMS, and the Guest Editor for Frontiers
in Neuroscience on the research topic of microelectronic implants for
central and peripheral nervous system. He was the Founding President
of Taiwan ESD Association, the 3rd President of Taiwan Engineering
Medicine Biology Association, and the Vice-President of IEEE Taipei
Section. He is currently serving as the Editor for IEEE TRANSACTION
ON D EVICE AND M ATERIALS R ELIABILITY and IEEE J OURNAL OF
THE E LECTRON D EVICES S OCIETY and the Guest Editor for IEEE
TRANSACTION ON ELECTROMAGNETIC COMPATIBILITY on the special
issue of “Electrostatic Discharge and Immunity—from IC to System.”

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