Example68: First In First Out Memory Circuit

68.1 - Example68: Design and Implement of First In First Out Memory

68.2.1 - Introduction

This example program gives you information about design and implementation
of First In First Out Memory.Design procedure, VHDL code development, simu-
lation, implementation and testing all are explained here.

68.2.2 - Schematic Diagram:

CLOCK

o
o
DATAIN<3> o
Toggle Switches

o
DATAIN<2> o
o DATAOUT<3>

o
DATAIN<1> o
o DATAOUT<2>

o
DATAIN<0> o
o DATAOUT<1>

LED's
DATAOUT<0>

FULL

EMPTY
WRREQ
RDREQ
RESET

Xilinx Application Module

8WAY DIP Switch

Port lines IP1_3, IP2_3, IP3_3 & IP4_3 are connected with the toggle switches
and IP1_2, IP2_2 & IP3_2 are connected with the DIP switch are used to get
status of the 4 bit input vector ‘DATAIN<3> - DATAIN<0>’ from toggle switches
and three input ‘W RREQ’, ‘RDREQ’ & ‘RESET’ from DIP switch.

364
Mini FPGA Evaluation Board User Guide
 Example68: First In First Out Memory Circuit

I/O lines L04P_1, L04N_1, L05P_1, L05N_1, L06P_1 & L06N_1 are used to con-
trol LED’s D1 to D6. Logic ‘1’ on the port line switches on the LED and logic ‘0’
switches off the LED. Bit allocations to drive LED’s are given below.

L04P_1 - Bit0 - LED ‘D1’

L04N_1 - Bit1 - LED ‘D2’
L05P_1 - Bit2 - LED ‘D3’
L05N_1 - Bit3 - LED ‘D4’
L06P_1 - Bit4 - LED ‘D5’
L06N_1 - Bit5 - LED ‘D6’

68.2.3 - Project Creation:

Steps for creating a New Project is same procedure as shown in the FPGA Appli-
cation Module manual.

At the step of Module Definitons, enter the following entity name, architecture
name, port name and direction.
Entity Name : FIFOmem
Architecture Name : behavioral
Port Name Direction
CLOCK in
W RREQ in
RDREQ in
RESET in
DATAIN in
DATAOUT out
FULL inout
EMPTY inout

After finished all steps, your source file template is created and is included into
the project design window refreshed with new design.

In the design window, your VHDL file is listed under the xc3s250e-4tq144 de-
vice heading with name FIFOmem-behavioral (FIFOMemory.vhd). Double click
this VHDL file, a VHDL code is opened with basic template.

365
Mini FPGA Evaluation Board User Guide
 Example68: First In First Out Memory Circuit

Now your application in VHDL code can be entered in the FIFOmem architec-
ture block.

68.2.5 - VHDL Code Development

VHDL Code Flowchart:

Start

Entity Description: Process Decription for FIFO READ :

m, n, positive=4 At rising_edge(clk)
CLOCK, if RESET= '1' then Rdaddr <= 0
RESET,WRREQ,RDREQ,Input,Std_logic Databuffer <= (others => '0')
DATAin, Input, Nbit vector elsif (Rdpulse = '1' and EMPTY = '1') then
DATAout, Output, Nbit vector Databuffer <= Fifo_memory(Rdaddr)
FULL, EMPTY, InOut,std_logic Rdaddr <= (Rdaddr + 1) mod m

Signal Description: Process Decription for FIFO WRITE :

Fifo_memory, Fifo_array At rising_edge(clk)
Wraddr,Rdaddr,Offset,Natural range 0 to (m-1) if RESET = '1' then Wraddr <= 0
Rdpulse, Wrpulse, Q1, Q2, Q3, Q4 Std_logic elsif (Wrpulse = '1' and FULL = '0') then
Databuffer , Bit_vector((n-1) downto 0) Fifo_memory(Wraddr) = To_Bitvector(DATAIN)
clk , std_logic Wraddr <= (Wraddr + 1) mod m

Synchronize Process: Calculate Offset Adrress :

wait until rising_edge(clk) Offset = (Wraddr - Rdaddr) when (Wraddr >
Q1 <= WRREQ Rdaddr)
Q2 <= Q1 else (m - (Rdaddr - Wraddr)) when (Rdaddr >
Q3 <= RDREQ Wraddr)
Q4 <= Q3 else 0;

LED Interface :
EMPTY <= '1' when (Offset = 0) else '0'
Pulse Generation :
FULL <= '1' when (Offset = (m-1)) else '0'
Wrpulse <= Q2 and not(Q1)
DATAOUT <= To_Stdlogicvector(Databuffer)
Rdpulse <= Q4 and not(Q3)
when RDREQ = '0'
else (others => 'Z')

366
Mini FPGA Evaluation Board User Guide
 Example68: First In First Out Memory Circuit

VHDL Code:

entity FIFOmem is
Generic(m, n : Positive := 4); --m is fifo depth, n is fifo width
port(RESET, WRREQ, RDREQ, CLOCK : in Std_logic;
DATAIN : in Std_logic_vector((n-1) downto 0);
DATAOUT : out Std_logic_vector((n-1) downto 0);
FULL, EMPTY : inout Std_logic);
end FIFOmem;

architecture behavioral of FIFOmem is

type Fifo_array is array(0 to (m-1)) of Bit_vector((n-1) downto 0);
signal Fifo_memory : Fifo_array;
signal Wraddr, Rdaddr, Offset : Natural range 0 to (m-1);
signal Rdpulse, Wrpulse, Q1, Q2, Q3, Q4 : Std_logic;
signal Databuffer : Bit_vector((n-1) downto 0);
begin --pulse synchronisers for WRREQ and RDREQ
sync_ffs : process --modified for Symplify to a process
begin
wait until rising_edge(CLOCK);
Q1 <= WRREQ;
Q2 <= Q1;
Q3 <= RDREQ;
Q4 <= Q3;
end process;
--concurrent logic to generate pulses
Wrpulse <= Q2 and not(Q1);
Rdpulse <= Q4 and not(Q3);
Fifo_read : process
begin
wait until rising_edge(CLOCK);
if RESET = '1' then
Rdaddr <= 0;
Databuffer <= (others => '0');
elsif (Rdpulse = '1' and EMPTY = '1') then
Databuffer <= Fifo_memory(Rdaddr);

367
Mini FPGA Evaluation Board User Guide
 Example68: First In First Out Memory Circuit

Rdaddr <= (Rdaddr + 1) mod m;

end if;
end process;

Fifo_write : process
begin
wait until rising_edge(CLOCK);
if RESET = '1' then
Wraddr <= 0;
elsif (Wrpulse = '1' and FULL = '0') then
Fifo_memory(Wraddr) <= To_Bitvector(DATAIN);
Wraddr <= (Wraddr + 1) mod m;
end if;
end process;

Offset <= (Wraddr - Rdaddr) when (Wraddr > Rdaddr)

else (m - (Rdaddr - Wraddr)) when (Rdaddr > Wraddr)
else 0;
EMPTY <= '1' when (Offset = 0) else '0';
FULL <= '1' when (Offset = (m-1)) else '0';
DATAOUT <= To_Stdlogicvector(Databuffer) when RDREQ = '0'
else (others => 'Z');
end behavioral;

68.2.6 - User Constraint File Description:

Pin numbers and constraints of VHDL design, are defined in a separate user constraint
file FIFOmem.ucf.
Port Line allocation:
DATAOUT<3> - DATAOUT<0>, FULL & EMPTY :
Bit0 - L04P_1 - D1
Bit1 - L04N_1 - D2
Bit2 - L05P_1 - D3
Bit3 - L05N_1 - D4
Bit4 - L06P_1 - D5
Bit5 - L06N_1 - D6

368
Mini FPGA Evaluation Board User Guide
 Example68: First In First Out Memory Circuit

DATAIN<3> - DATAIN<0>:
IP1_3(Pin6) - SW1
IP2_3(Pin10) - SW2
IP3_3(Pin12) - SW3
IP4_3(Pin18) - SW4
WRREQ, RDREQ & RESET :
IP1_2(Pin38) - SW1
IP2_2(Pin41) - SW2
IP3_2(Pin69) - SW3

To create a constraint file manually, double click Edit Constraints (Text) command under
User Constraints heading of Process window. Now you can edit the following lines in
plain text editor.

NET "CLOCK" LOC = "P122"| IOSTANDARD = LVTTL;

NET "WRREQ" LOC = "P38" | IOSTANDARD = LVTTL;
NET "RDREQ" LOC = "P41" | IOSTANDARD = LVTTL;
NET "RESET" LOC = "P69" | IOSTANDARD = LVTTL;
NET "DATAIN<3>" LOC = "P6" | IOSTANDARD = LVTTL;
NET "DATAIN<2>" LOC = "P10" | IOSTANDARD = LVTTL;
NET "DATAIN<1>" LOC = "P12" | IOSTANDARD = LVTTL;
NET "DATAIN<0>" LOC = "P18" | IOSTANDARD = LVTTL;
NET"DATAOUT<3>"LOC = "P85"| IOSTANDARD = LVTTL| SLEW = SLOW | DRIVE = 4;
NET"DATAOUT<2>"LOC = "P86"| IOSTANDARD = LVTTL| SLEW = SLOW | DRIVE = 4;
NET"DATAOUT<1>"LOC = "P87"| IOSTANDARD = LVTTL| SLEW = SLOW | DRIVE = 4;
NET"DATAOUT<0>"LOC = "P88"| IOSTANDARD = LVTTL| SLEW = SLOW | DRIVE = 4;
NET"FULL" LOC = "P91" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;
NET "EMPTY" LOC = "P92" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 4;

If you already have constraint file, select Add Copy of Source option of right click popup
menu in Sources window to import existing constraint file.

68.2.7 - Synthesizing, Simulation, Implementation and Programming File Generation:

Follow the same steps for Synthesizing, Simulation, Implementation Process and
Programming File Generation are mentioned in the FPGA Application Module manual.

369
Mini FPGA Evaluation Board User Guide
 Example68: First In First Out Memory Circuit

Note: Before Implementation Process, you must edit VHDL code.

VHDL CODE:
architecture behavioral of FIFOmem is

type Fifo_array is array(0 to (m-1)) of Bit_vector((n-1) downto 0);

signal Fifo_memory : Fifo_array;
signal Wraddr, Rdaddr, Offset : Natural range 0 to (m-1);
signal Rdpulse, Wrpulse, Q1, Q2, Q3, Q4 : Std_logic;
signal Databuffer : Bit_vector((n-1) downto 0);
signal cnt : integer range 0 to 50000000:=0;
signal clk : std_logic;

begin

process(CLOCK)
begin
if CLOCK='1' and CLOCK'event then
if cnt = 50000000 then
cnt<=0;
clk<=not clk;
else
cnt<=cnt+1;
end if;
end if;
end process;
--pulse synchronisers for WRREQ and RDREQ
--modified for Synplify to a process
sync_ffs : process
begin
wait until rising_edge(clk);
Q1 <= WRREQ;
Q2 <= Q1;
Q3 <= RDREQ;
Q4 <= Q3;
end process;
--concurrent logic to generate pulses

370
Mini FPGA Evaluation Board User Guide
 Example68: First In First Out Memory Circuit

Wrpulse <= Q2 and not(Q1);

Rdpulse <= Q4 and not(Q3);
Fifo_read : process
begin
wait until rising_edge(clk);
if RESET = '1' then
Rdaddr <= 0;
Databuffer <= (others => '0');
elsif (Rdpulse = '1' and EMPTY = '1') then
Databuffer <= Fifo_memory(Rdaddr);
Rdaddr <= (Rdaddr + 1) mod m;
end if;
end process;

Fifo_write : process
begin
wait until rising_edge(clk);
if RESET = '1' then
Wraddr <= 0;
elsif (Wrpulse = '1' and FULL = '0') then
Fifo_memory(Wraddr) <= To_Bitvector(DATAIN);
Wraddr <= (Wraddr + 1) mod m;
end if;
end process;

Offset <= (Wraddr - Rdaddr) when (Wraddr > Rdaddr)

else (m - (Rdaddr - Wraddr)) when (Rdaddr > Wraddr)
else 0;
EMPTY <= '1' when (Offset = 0) else '0';
FULL <= '1' when (Offset = (m-1)) else '0';
DATAOUT <= To_Stdlogicvector(Databuffer) when RDREQ = '0'
else (others => 'Z');
end behavioral;

371
Mini FPGA Evaluation Board User Guide
 Example68: First In First Out Memory Circuit

68.2.8 - Programming FPGA:

Connect the USB cable and switch on the power supply. If STAT LED blinks,wait until
blinking is over. Then launch Topview Programmer - Xilinx FPGA application and Select
FPGA in Device Selection window and using Browse button select the FIFOmem.xsvf
file in the filename selection box. Then click Configure button to program FPGA.Now
your application program gets downloaded into FPGA. Status bar displays programming
status. Also DONE LED is switched on to indicate sucessful FPGA configuration.

68.2.9 - Verification:

After configuration FPGA, We find that the FIFO Memory circuit gives us memory space
to write & read operation by first in first out method. Here we use three input signals are
WRREG, RDREQ & RESET. When WRREQ=1 enable the write operation. When
RDREQ=1 enable the read operation. When RESET=1 enable the reset condition.
And two output signals are ‘FULL’ indicates memory space is full and ‘EMPTY’
indicates memory space is empty.

Change the inputs signals in SW1,SW2 & SW3 (DIP switch) and give input datas in
SW1-SW4(toggle switches). Now verify the memory outputs in LED’s D1-D6.

For Example:
sw1 sw2 sw3 sw4 (Toggle switches)
Input data DATAIN<3>-<0> - 1 0 1 0
Input signals ‘WRREQ’ - 1
Input signals ‘RDREQ’ - 0
Input signals ‘RESET’ - 0

Output data DATAOUT<3>-<0> - 1 0 1 0 (LED’s D1 to D4)

Output signals ‘FULL’ - 1 (LED D5)
Output signals ‘EMPTY’ - 0 (LED D6)

The memory outputs are displayed on LED’s D1-D4, D5 & D6.

372
Mini FPGA Evaluation Board User Guide