TABLE OF CONTENTS

NAME OF THE CONTENT PAGE NO

TABLE OF CONTENTS i

LIST OF FIGURES v

LIST OF TABLES viii

CHAPTER 1: INTRODUCTION

1.1. Objective And Motivation 1

1.2 Overview of VLSI Systems 2

1.2.1 Typical Design Flow 3

5
1.3. Organization of the Report

CHAPTER 2: THEORITICAL ASPECTS OF LOW

POWER MULTIPLIER
2.1. Baugh Wooley Multiplier 6

2.2. Estimation of Power In VLSI Circuit 9

2.2.1. Introduction
9
2.2.2. Basic Concepts of Power
10
2.2.3. Approach to Low Level Power Estimation
10

2.2.4 .Approach to High Level Power Estimation 11

2.3. Voltage over Scaling

2.3.1 Introduction 12

2.3.2 Error Tolerant DSP Applications 15

2.3.3Design Approaches for Voltage Over Scaled 15

Systems
2.3.4 Error Analysis in Voltage Over Scaled 16
Systems

i
 2.4. Soft Errors
2.4.1. Introduction 16

2.4.2. Critical Charge 18

2.4.3 Causes of Soft Errors 19

2.4.4 Cosmic Rays Creating Energetic Neutrons And

Protons 20

2.4.5 Thermal Neutrons 21

22
2.4.6 Others

2.4.7 Detecting Soft Errors 23

2.4.8 Correcting Soft Errors 23

2.4.9 Challenges of Technology Scaling 24

2.4.10 Reasons for Increase in Soft Error 25

Failure Rate of Logic Circuits

CHAPTER 3 : DESIGN OF MULTIPLIER BASED ON ANT

ARCHITECTURE

3.1 The RPR Technique 27

3.2 Proposed ANT Multiplier Design Using Fixed-width RPR 27

3.3 Proposed Precise Error Compensation Vector for

Fixed-width RPR 29

CHAPTER 4: SOFTWARE TOOL DESCRIPTION

4.1 Introduction to Verilog 32

4.1.1 Features of Verilog 33

4.1.2 Verilog v/s VHDL 33

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 4.1.3 Verilog Program Structure 33

4.1.4 Design Styles in Verilog 34

4.1.5 Top Down Design 34

4.1.6 Simulation 34

4.1.7 Modelling Styles 35

4.2 Review of Micro Wind 37

4.2.1 Micro Wind 38

4.2.2 Micro Wind Design Flow 42

4.3 Over View of Xilinx ISE 43

4.3.1 Design Flow overview 44

4.4 X-Power Analyzer 47

4.4.1 X-Power Supports the Following Simulators 50

4.4.2 VCD File Generation Using Modelsim 50

CHAPTER 5: IMPLEMENTATION OF ANT BASED

ARCHITECTURE

5.1 Verilog Implementation of ANT Based Multiplier 52

5.1.1 Normal Multiplier Block 52

5.1.2 RPR Block 53

5.1.3 ANT Based Multiplier 54

5.2 Layout Implementation Of ANT Based Multiplier 55

5.2.1 Layout Schematic Diagrams for 4-bit Normal Multiplier 55

5.2.2 Layout Schematic Diagrams for 3-bit ANT Based Multiplier 55

5.2.3 Full Adder Schematic Diagram 56

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 5.2.4 Half Adder Schematic Diagram 56

CHAPTER 6: RESULTS AND DISCUSSION

6.1 Results for Layout Diagrams 57

6.1.1 Layout Diagrams for 4-bit Normal Multiplier 58

6.1.2 Layout Diagrams for 3-bit Multiplier 58

6.1.3 Full Adder Output 58

6.1.4 Half Adder Output 59

6.2 Results for ANT Multiplier 59

6.2.1 Main Block Outputs 59

6.2.2 Truncated Block Outputs 62

6.2.3 ANT Multiplier Output 64

CHAPTER 7: CONCLUSION AND FUTURE ENHANCEMENT 68

REFERENCES 70

APPENDIX 71
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 LIST OF FIGURES

Fig No. Name of the Figure Page No.

1.1 VLSI Design Flow 3

1.2 Y-chart 4

2.1 General 4-bit multiplication 7

2.2 General 8-bit multiplication 8

2.3 Challenges of technology scaling 25

3.2 Proposed ANT architecture with fixed width

28
RPR

4.1 The Micro wind window as it appears at the

39
initialization stage

4.2 Access to basic contact macros 40

4.3 Various contacts 40

4.4 Top menu bar 41

4.5 Micro wind design flow diagram 42

4.6 Xilinx design flow 44

Design flow from logic design to layout

4.7 47
Implementation

4.8 1-bit Binary Multiplication 47

4.9 2-bit binary multiplication 48

4.10 X-power analyzer 51

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5.1 4-bit normal multiplier schematic diagram 55

5.2 55
3-bit ANT multiplier schematic diagram
5.3 56
Full adder schematic diagram
5.4 56
Half adder schematic diagram
6.1 57
4-bit multiplier layout diagram

6.2
4-bit Multiplier power calculations 57

6.3 58
3-bit ANT multiplier layout diagram

6.4 58
3-bit ANT multiplier power calculation
diagram
59
6.5 3-bit normal multiplier RTL schematic diagram

59
6.6 3-bit multiplier technology Schematic diagram

60
6.7 3-bit main block multiplier design summary

6.8 3-bit main block multiplier device utilization

60
summary

6.9 3-bit main block multiplier delay and memory

60
summary
61
6.10 X-power report

61
6.11 3-bit normal multiplication simulation result

6.12 3-bit truncated multiplier RTL schematic 62

diagram

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 6.13 3-bit truncated multiplier technology schematic 62
diagram

6.14 3-bit truncated multiplier design summary 63

6.15 3-bit truncated multiplier device utilization summary 63

6.16 3-bit truncated multiplier delay and memory summary 63

6.17 truncated X-power report 64

6.18 3-bit truncated multiplication simulation result 64

6.19 3-bit ANT multiplier RTL schematic diagram 64

6.20 3-bit ANT multiplier technology schematic diagram 65

6.21 3-bit ANT multiplier design summary 65

6.22 3-bit ANT multiplier device utilization summary 65

6.23 3-bit ANT multiplier delay and memory summary 66

6.24 ANT X-power report 66

6.25 3-bit ANT multiplication simulation result 66

6.26 3-bit ANT multiplication simulation result 67

vii
 LIST OF TABLES

Table No. Name Of the Table Page No.

6.1 Truth table for full adder 58

6.2 Truth Table for half adder 59

viii