EXP.

NO: INSTRUMENTATION AMPLIFIER

AIM:
To construct and test the CMRR (Common Mode Rejection Ratio) of a 3 op-amp
instrumentation amplifier using op-amp IC741.

APPARATUS REQUIRED:

S.NO COMPONENTS / EQUIPMENT RANGE QUANTITY

1. IC 741 03
1KΩ. 06
2. RESISTORS
22KΩ 01
3. DIGITAL TRAINER KIT --- 01
4. SIGNAL GENERATOR (0-3)MHz 02
5. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
6. CONNECTING WIRES --- FEW

PROCEDURE:
1. Select the entire resistor with same value of resistance R. Let RG be the gain varying
resistor with different values of resistance. For simplicity, let RG be a constant value.
2. Connect the circuit as shown in the circuit diagram.
3. Give the input V1 & V2 to the non-inverting terminals of first & second
Op-amp respectively.
4. By varying the value of RG, measure the output voltage for common mode and
differential mode operation. Since RG is selected as constant value, provide different input
value of V1 & V2.
5. Calculate the differential mode gain Ad and common mode gain Ac to calculate the
Ad
CMRR as CMRR=20 log .
Ac
CIRCUIT DIAGRAM:

+15v

+IC 741
Rf=1K

+15v
R2=1K
-15v
R1=1K
-
IC 741

RG=22K +
R1=1K
V1 -15v
R2=1K

+15v R1=1K
-
IC 741

+ 3 +
V2
-15v

TABULATION:

COMMON MODE GAIN CALCULATION - AC

RG V1 V2 Vo AC = V0/
S.No
(KΩ) (Volts) (Volts) (Volts) [(V1+V2)/2]

1.

2.

3.

4.

5.
 DIFFERENTIAL MODE GAIN - AD & CMRR CALCULATION.

CMRR =
V1 V2 Vo Ad= V0 / A
S.No RG (KΩ)
(Volts) (Volts) (Volts) [V1 -V2] 20 log ( d )(dB)
Ac
1.
2.

3.

4.

5.

RESULT:
Thus a 3 op-amp instrumentation amplifier was constructed and CMRR is tested
using op-amp IC 741.
EXP.NO: ACTIVE LOW PASS, HIGH PASS AND BAND PASS FILTER
USING OP-AMP

AIM:
To design an Active Low Pass, High Pass and Band Pass Filter using op-amp and to test
their performance

APPARATUS REQUIRED:

S.NO COMPONENTS / EQUIPMENT RANGE QUANTITY

1. IC 741 --- 02
1.5 KΩ 02
2. RESISTORS 10KΩ 01
22KΩ 04
3. CAPACITORS 0.1μf, 0.01μf 01
4. DIGITAL TRAINER KIT --- 01
5. SIGNAL GENERATOR (0-3)MHz 01
6. CATHODE RAY OSCILLOSCOPE (0-30)MHz 01
7. CONNECTING WIRES --- FEW

DESIGN PROCEDURE: (ACTIVE HPF):

Design a HPF at cutoff frequency fL of 1KHZ & P.B gain of 2. Follow the same procedure
as LPF & interchange the R & C position with capacitor first & resistor in parallel to capacitor
where the other end connected to ground.
Af ( f / f L )
In high pass filter Theoretical gain is given as Vo =

Vin
2
1 +( f / f )

PROCEDURE - (LPF & HPF):

1. Connect the circuit as shown in the circuit diagram.

2. Select the corresponding cut-off frequency (higher or lower) and determine the value of
C & R. select the value of R1 & Rf depending on desired passband gain Af..
3. Apply a constant voltage input sinusoidal signal to the non-inverting terminal of op-amp.
4. Tabulate the output voltage Vo with respect to different values of input frequency.
5. Calculate passband gain and plot the graph of frequency versus voltage gain & check the
graph to get approximately the same characteristic as shown in the model graph.
LOWPASS FILTER:-
CIRCUIT DIAGRAM:-
R1=22K R f=22K

+15v
2 - 7
Signal 6
Generator 1.5K

3 + 4
+ +
RL=10K
Vin ~ 0.1uf
-15v
CRO
-

TABULATION:
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No (dB)
(Hz) (Volts)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
MODEL GRAPH:
CIRCUIT DIAGRAM - (HIGH PASS FILTER):-
R1=22K R f=22K

+15v
2 7
Signal 0.1μf
-
Generator IC 741
6
3 + 4
+ +
RL=10K
Vin ~ 1.5K -15v
CRO
-

TABULATION:
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No (dB)
(Hz) (Volts)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

MODEL GRAPH:
CIRCUIT DIAGRAM: (BANDPASS FILTER)
R1=22K Rf=22K

R1=22K Rf=22K
+15v
+15v

2 7
2 7
-
- IC 741

Signal C=0.1uf
Generator
IC 741
6
3 + 4
6
R=1.5K
+ 3 + 4 +

-15v CRO
Vin ~ -15v
C=0.01uf
RL=10K -
R=1.5K
-

First Order High Pass Filter First Order Low Pass Filter

TABULATION:

Frequency Output Voltage Gain = 20 log (V0 /Vin)

S.No (dB)
(Hz) (Volts)
1
2
3
4
5
6
7
8
 MODEL GRAPH:

PROCEDURE:
1. Select the lower and higher cut-off frequency and calculate the value of R & C for the
given frequencies.
2. Design for LPF & HPF separately and then combine the circuit by first placing the HPF
followed by a LPF (i.e.) HPF in series with LPF.
3. Connect the circuit as shown in the circuit diagram.
4. Apply a constant voltage input sinusoidal signal to the non-inverting terminal of op-amp.
5. Tabulate the output voltage Vo with respect to different values of input frequency.
6. Calculate passband gain and plot the graph of frequency versus voltage gain & check the
graph to get approximately the same characteristic as shown in the model graph.
DESIGN PROCEDURE - (ACTIVE BPF):-
Design a BPF to pass a band of 1 KHz to 10 KHz with a passband gain of 4.
1. Select the highest cut-off frequency of LPF as fH = 10 KHz and the lowest cut-off
frequency of HPF as fL = 1 KHz.
2. Design the HPF first by taking fL = 1KHz. Assume the value of C < 1μf.
Let C = 0.1μf.
3. Calculate R from the expression.
1 1
fL = Therefore R1 =
2π RC C2πfL C

1
R= ;
2π (1KHz)(0.1X10 6 )

R = 1.59KΩ ≈ R=1.5KΩ
 4. Then design the LPF by taking fH = 10KHz. Assume the value of C < 1μf. Let C =
0.01μf.
1
5. Calculate R from the expression fH = ; Therefore R = 1
2 π RC C2πf

R = 1.59KΩ ≈ R=1.5KΩ

6. Calculate the values of Rf & R1 with the use of pass band gain.
Overall P.B gain of BPF = 4 = 2 (HPF) X 2 (LPF

DESIGN PROCEDURE (ACTIVE LPF):

Design a LPF at cutoff frequency fH of 1KHz with a passband gain of 2.

1. Choose the given value of fH = 1KHz.
2. Select the value of C < 1μf
1
3. Assume C = 0.1μf. Calculate R from fH =
2 πR C
1
R=
C.2πf

R = 1.5KΩ C = 0.1μf

4. Determine the value of R1 & Rf from pass band gain of the filter.

Af = 1 +Rf / R.1

5. Calculate the practical gain

Gain (dB)=20log (Vo/Vin);

RESULT:
Thus an Active Lowpass, High pass and Band Pass Filters are designed and tested using
op-amp IC 741.
 PLL CHARACTERISTICS AND FREQUENCY
EXP.NO:
MULTIPLIER USING PLL

AIM:
To design & test the characteristics of PLL and to construct and test frequency multiplier
using PLL IC565.

APPARATUS REQUIRED:

S.NO COMPONENTS / EQUIPMENT VALUE QUANTITY

1 IC 565 --- 01
2 IC 555 --- 01

3 RESISTORS 12KΩ, 54.5 KΩ, 6.8K Each one

0.01μF 4
CAPACITORS
4
0.1 μf, 10μf, 1 μf EACH 01

5 DIGITAL TRAINER KIT --- 01

6 REGULATED POWER SUPPLY (0 -30V), 1A 1

7 CATHODE RAY OSCILLOSCOPE (0 – 30MHz) 1

8 CONNECTING WIRES --- FEW

 PLL as Frequency Multiplier – Circuit diagram

(a) : Input
(b) : PLL output under locked conditions without 555
(c) : Output at pin4 of 565 with 555 connected in the feedback
THEORY:
The frequency divider is inserted between the VCO and the phase comparator of PLL.
Since the output of the divider is locked to the input frequency fIN , the VCO is actually running
at a multiple of the input frequency .The desired amount of multiplication can be obtained by
selecting a proper divide– by – N network ,where N is an integer. To obtain the output frequency
fOUT =2fIN, N = 2 is chosen. One must determine the input frequency range and then adjust the free
running frequency fOUT of the VCO by means of R1 and C1 so that the output frequency of the
divider is midway within the predetermined input frequency range. The output of the VCO now
should be 2fIN . The output of the VCO should be adjusted by varying potentiometer R1 . A small
capacitor is connected between pin7 and pin8 to eliminate possible oscillations. Also, capacitor C2
should be large enough to stabilize the VCO frequency.

SAMPLE READINGS:

PARAMETER INPUT OUTPUT

Amplitude (Vp-p)

Frequency (KHz)

PROCEDURE:-
1. The circuit is connected as per the circuit diagram.
2. Apply a square wave input to the pin2 of the 565
3. Observe the output at pin4 of 565 under locked condition.
4. Give the output of 565 to the pin2 of 555 IC.
5. Observe the output of 555 at pin3.
6. Now give the output of 555 as feedback to the pin5 of the 565.
7. Observe the frequency of output signal fo at pin4 of 565 IC.
8. Plot the waveforms in graph.

RESULT:
Thus the PLL characteristics are designed and tested and Frequency multiplier using IC
565 is constructed and tested.
 EXP.NO: R-2R LADDER TYPE D- A CONVERTER USING OP-AMP

AIM:

To design a 4-bit R-2R ladder type DAC using OP-AMP.

APPARATUS REQUIRED:

S.NO COMPONENTS / EQUIPMENT VALUE QUANTITY

1 IC 741 --- 01
2 RESISTOR 22K, 10K 05, 04

3 DIGITAL MULTIMETER METER

4 DIGITAL TRAINER KIT --- 01

5 REGULATED POWER SUPPLY (0 -30V), 1A 1

6 CATHODE RAY OSCILLOSCOPE (0 – 30MHz) 1

7 CONNECTING WIRES --- FEW

THEORY:

In R-2R ladder network only two values of resistors are required. Consider 4
bit DAC, where switch position d1, d2, d3, d4 corresponding to binary words.

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. The inputs are given through b0, b1, b2, b3.
3. The inputs are given from (0-15)V and observe the outputs in voltmeter.
4. The graph is drawn.
CIRCUIT DIAGRAM:

TABULATION:

Equivalent Binary Practical Theoretical

Decimal Voltage Voltage
(V) (V)
b3 b2 b1 b0
DESIGN PROCEDURE:

Vo = -Rf (b3/2R + b2/4R + b1/8R + b0/16R)Vref

Rf = R

Vo = -Vref (b3/2 + b2/4 + b1/8 + b0/16)

Assume R = 10K

2R = 22K

RESULT:

Thus the 4-bit R-2R ladder type DAC is designed and its outputs are verified.