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Cinterion® LGA DevKit
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User Guide

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Cinterion® LGA DevKit User Guide Page 2 of 36

User Guide: Cinterion® LGA DevKit

Version: 03

Date: 2020-05-29

DocId: lga_devkit_ug_v03

Status: Public / Released

GENERAL NOTE
THIS DOCUMENT CONTAINS INFORMATION ON THALES DIS AIS DEUTSCHLAND GMBH
(“THALES”) PRODUCTS. THALES RESERVES THE RIGHT TO MAKE CHANGES TO THE PROD-
UCTS DESCRIBED HEREIN. THE SPECIFICATIONS IN THIS DOCUMENT ARE SUBJECT TO
CHANGE AT THE DISCRETION OF THALES. THE PRODUCT AND THIS DOCUMENT ARE PRO-
VIDED ON AN "AS IS" BASIS ONLY AND MAY CONTAIN DEFICIENCIES OR INADEQUACIES.
THALES DOES NOT ASSUME ANY LIABILITY FOR INFORMATION PROVIDED IN THE DOCUMENT
OR ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT DESCRIBED HEREIN.

THALES GRANTS A NON-EXCLUSIVE RIGHT TO USE THE DOCUMENT. THE RECIPIENT SHALL
NOT COPY, MODIFY, DISCLOSE OR REPRODUCE THE DOCUMENT EXCEPT AS SPECIFICALLY
AUTHORIZED BY THALES.

Copyright © 2020, THALES DIS AIS Deutschland GmbH

Trademark Notice
Thales, the Thales logo, are trademarks and service marks of Thales and are registered in certain coun-
tries. Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in
the United States and/or other countries. All other registered trademarks or trademarks mentioned in this
document are property of their respective owners.

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Contents
36

Contents

1 Introduction ................................................................................................................. 5
1.1 Feature and Benefits.......................................................................................... 5
1.2 Supported Products ........................................................................................... 6
1.3 Package Content ............................................................................................... 7

2 Quickstart .................................................................................................................... 9
2.1 Mounting the LGA DevKit Socket ...................................................................... 9

3 LGA DevKit Overview ............................................................................................... 10

3.1 Top and Underside View.................................................................................. 10
3.2 Block Diagram.................................................................................................. 11

4 LGA DevKit Interfaces .............................................................................................. 12

4.1 USB.................................................................................................................. 12
4.2 SIM................................................................................................................... 12
4.3 Pin Headers ..................................................................................................... 13
4.3.1 Default Configuration .......................................................................... 13
4.4 ON Button: Module Start and Power Down ..................................................... 14
4.5 RST Button: Module Reset .............................................................................. 14
4.6 ASC0 Switch: Module UART Interface Selection............................................. 14
4.7 PWR Switch: Power Source Selection............................................................. 14
4.8 Free Level Shifters........................................................................................... 15
4.9 LEDs ................................................................................................................ 15
4.10 Patch Field ....................................................................................................... 15
4.11 RF Antenna...................................................................................................... 16
4.12 Power Supply................................................................................................... 17
4.12.1 Supply Current Measurement ............................................................. 17
4.12.2 External Reference Supply ................................................................. 18

5 General Characteristics............................................................................................ 19

6 Operating the LGA DevKit with a DSB .................................................................... 20

6.1 LGA DevKit on DSB-Mini ................................................................................. 20
6.2 LGA DevKit on DSB75..................................................................................... 21

7 Module Specific Configuration Settings ................................................................. 22

7.1 BGS1 and BGS2 Operation ............................................................................. 22
7.2 BGS12 Operation............................................................................................. 22
7.3 EMS31 Operation ............................................................................................ 22
7.4 ENS22 Operation............................................................................................. 23

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Contents
36

8 Document Information.............................................................................................. 24
8.1 Revision History ............................................................................................... 24
8.2 Related Documents ......................................................................................... 24
8.3 Safety Precaution Notes .................................................................................. 25
8.4 Regulatory Compliance Information................................................................. 25

9 Appendix.................................................................................................................... 26
9.1 LGA DevKit SM................................................................................................ 26
9.1.1 Placement ........................................................................................... 26
9.1.2 Schematics ......................................................................................... 27
9.2 LGA DevKit L ................................................................................................... 30
9.2.1 Placement ........................................................................................... 30
9.2.2 Schematics ......................................................................................... 31
9.3 Errata/Troubleshooting .................................................................................... 34

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1 Introduction
35

1 Introduction

The Cinterion® LGA DevKit is designed as a generic development adapter for Cinterion® LGA
modules. With the LGA DevKit it is no longer necessary to connect the Cinterion® evaluation
modules to an adapter for test and development purposes.

The LGA DevKit may operate stand-alone without the need of any further tools or devices, or
it can be operated with a port extender, for instance the DSB75 or DSB-Mini as an adapter be-
tween the module and further external applications.

The LGA DevKit is available in two variants:

• SM supports the complete industrial platform modules
• L supports most of the industrial plus platform modules

Either one of the LGA DevKit variant (SM or L) needs to be ordered together with the LGA
DevKit socket, leaving the option to reuse the socket for the other LGA DevKit variant.

1.1 Feature and Benefits

• LGA DevKit socket supports four different module footprints with different LGA pad counts
for industrial/industrial plus platform modules:
With LGA DevKit SM: LGA106, LGA114, and LGA120
With LGA DevKit L: LGA156
• Future proof, ready for new, upcoming modules
• Stand-alone: Get the LGA module up and running without additional tooling
• Supports DSB75/DSB-Mini as port extender
• UART via USB VCP, and/or native USB communication
• Direct module signal access with complete interruption for deep level investigation
• Real module current consumption measurement, no additional leakage current
• Powered via USB or external devices (e.g., DSB75/DSB-Mini)
• Adjustable module supply level 2.8...4.5V
• VEXT self-adjustment for level shifter reference level
• Further supported interfaces: SPS, SIM2, ASC1, Audio, GPIO, GNSS
• Error detection: Wrong or wrongly oriented modules, as well as shorts on module, prevent-
ing damages
• Clear & easy concept for usage and signaling
• Cost minimized: LGA DevKit socket usable for both LGA DevKit versions (SM and L)
• QR code scanning leads users to all the information necessary for usage

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1.2 Supported Products
35

1.2 Supported Products

The following table lists modules that are supported by the LGA DevKit variants SM and L, de-
pending on the module’s pad count (i.e., module’s footprint).

Table 1: Supported products

LGA DevKit SM LGA DevKit L
S (LGA 106, LGA 114) M (LGA 120) L (LGA 156)

m
BGS12 BGS8 PDS5
BGS2 EHS6 PDS6
BGS5 EHS8 PLS62-W

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EHS5 ELS61 PLS8
ELS31 ELS81
EMS31
Cinterion® ENS22
EXS62
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EXS82
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1.3 Package Content
35

1.3 Package Content

The following packages are available for the LGA DevKits. Normally an LGA DevKit SM or L
would be used with the LGA DevKit socket SML:

• Cinterion® LGA DevKit SM (Ordering number: L30960-N0111-A100)

- Base PCB for the industrial platform modules
- USB and SMA cable
- An ultra-wideband high efficiency antenna
- A bag of jumpers ~25pcs
- A quick start guide
• Cinterion® LGA DevKit L (Ordering number: L30960-N0112-A100)
- Base PCB for the industrial plus platform modules
- USB and SMA cable
- An ultra-wideband high efficiency antenna
- A bag of jumpers ~25pcs
- A quick start guide
• Cinterion® LGA DevKit socket SML (Ordering number: L30960-N0110-A100)
- The needle socket fitting on both PCB versions SM and L
- Screws, fixing frames, retention lid

Figure 1 shows the LGA DevKit package contents, whereas Figure 2 shows how the LGA
DevKit socket SML can be used for both LGA DevKit variants S and M.

USB cable
Quick Start
Guide

LGA DevKit
(SM or L)
Jumpers

Antenna

SMA cable

Figure 1: LGA DevKit SM package content

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1.3 Package Content
35

Cinterion® LGA DevKit socket SML

(L30960-N0110-A100)

Cinterion® LGA DevKit SM Cinterion® LGA DevKit L

(L30960-N0111-A100) (L30960-N0112-A100)

SM L

LGA120 LGA106 LGA156

LGA114

Figure 2: LGA DevKit socket SML with LGA DevKit variants SM and L

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2 Quickstart
35

2 Quickstart

Please complete the following steps to quickly get started with your LGA DevKit.

• Mount the LGA DevKit socket onto the LGA DevKit (for details see Section 2.1).
• Insert the fixing frame and then the module into the socket and close the retention lid by
pressing it down and turning it clockwise.
• Connect the provided antenna to the SMA connector named "MAIN".
• Check that the jumpers are set to their default delivery positions.
• Connect your host PC to either the USB or the USB VCP connector (depending on the mod-
ule). In case of USB VCP connections, install FT232R drivers.
• Set the switches PWR & ASC0 at the DevKit's lower right corner to "USB". Now, the green
"PWR" LED lights up.
• Shortly press the ON button to start the module. Now, the white "ON" LED lights up

The red "ERROR" LED may indicate issues that should be corrected. For de-
tails see Section 4.9.

Note: By scanning the QR code at the underside of the LGA DevKit you will also
find further information, videos and available drivers.

2.1 Mounting the LGA DevKit Socket

Before operating, the socket has to be mounted onto the LGA DevKit
with 4 screws. Scanning the QR code on the DevKit's underside and/
or the quick start guide will lead you to the DevKit's web home where
you find a short introduction and video on how to do this.

The white printing on the DevKit shows how the socket shall be orien-
tated and mounted. You can quickly adapt to different module foot-
prints by using dedicated fixing frames. All contacts have low-
resistivity needles.

Note: The module's thermal encapsulation inside the socket increases the thermal resistance
(Rth). Thus, you need to be aware that the board temperature may rise quite quickly until au-
tomatic thermal shutdown takes effect, especially at higher environmental temperatures or high
radio output power.

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3 LGA DevKit Overview
35

3 LGA DevKit Overview

3.1 Top and Underside View

Figure 3 and Figure 4 show the top and underside view of the of the LGA DevKit SM variant.

Please note that both SM and L variants of the LGA DevKit are identical - except or the MAIN
and DIV antenna connectors that are interchanged, and the footprint indicators showing the dif-
ferent LGA module footprints.

Error LED Configurable & interruptible signals

Activity LED

USB VCP & PWR

Current test Adjustable

supply
USB & PWR

Supply mode

MAIN*

DIV*

Channel select Activity LEDs GPS Footprint indicator**

* = MAIN and DIV antenna connectors are interchanged with the LGA DevKit L variant
** = Footprint indicator shows LGA156 footprint with the LGA DevKit L variant

Figure 3: LGA DevKit SM top view

DSB interface

VCP FTDI

PWR circuit PWR buffer

CTRL & Error det.

SIM Module footprint ex. GND Patch field

Figure 4: LGA DevKit SM underside view

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3.2 Block Diagram
35

3.2 Block Diagram

Native Micro
USB Data
USB
Left side: Right side:
Module Pins Peripherals Combinded
Powering

RF Main/ DRX On board Module Signals

GPS ASC0 Micro
Antenna Sim USB
Connector
Connector Connector

m
Jumper

Module Signals
Status LEDS

GPS
PWR Signal Jumpers
Antenna

SIM

ASC0
Switch
Signal

.co
ASC0 FTDI
Auto Adjust
Serial – USB
Cinterion® Industrial Multifootprint Levelshifter
Bridge

Power
80 Pin
ASC0 Signal
DSB75 / DSB
Mini
Connector
RST Module
Button
BTN Signals

SIM2
es
ON
Button

Power
BTN

MCU control unit Power

Footprint
detection LDO &
Protection
uid

Power Switch
Error detection Jumper
LED Capacitor Bank
Jumper
Start module
Adjust BATT+
control Jumper
PWR
-g

User Interface/
Logical Block Signaling Power Block Controlling Module
Connectors

Figure 5: LGA DevKit block diagram

all

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4 LGA DevKit Interfaces
35

4 LGA DevKit Interfaces

4.1 USB
The LGA DevKit comes with two USB interfaces supporting power supply and serial commu-
nication. You may choose to setup communication via a module's USB port and/or a module's
UART (ASC0) port via FTDI232R VCP.

• Both USB ports can be used in parallel while power is sourced from both ports.
• The native USB power is isolated from the VCP USB power by a diode, meaning that the
VCP USB power does not feedback to the native USB power, but vice versa. This should
be taken into account when supplying the LGA DevKit from different USB power sources,
depending on the voltage levels there could be a power feedback from native USB to VCP
USB.
• In case of marginal USB power supply both USB ports should be used to improve power
capabilities.

Note: The modem's USB driver can be downloaded from the LGA DevKit's web page that can
be reached by scanning the QR code.

4.2 SIM
On the LGA DevKit's underside you find a SIM card holder that is con-
nected to the module's regular SIM interface lines, except for the
CCIN line where the (default) jumper needs to be set for CCIN at the
CONTROL pin headers (see Section 4.3). However, some modules
come with an additional SIM interface. This can be accessed in con-
junction with a DSB75/DSB-Mini (as port extender) to support dual
SIMs - with the DSB75/DSB-Mini serving as the second SIM interface.

Some Cinterion® modules require additional components at the SIM

interface, for instance pull-up resistors managed by the DevKit's con-
trol logic. These can be overridden by setting a switch on the DevKit's
underside - see Figure 6. For modules requiring a CCIO pull up resis-
tor this switch should be set to "CCIO PULLUP" (see Section 7.3).
Figure 6: SIM settings

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4.3 Pin Headers
35

4.3 Pin Headers

The pin headers at the top side can be used to setup connections between modules and pos-
sible on board peripherals. Thus, pin headers having signal names at their left side only, name-
ly the pin headers AUDIO, CONTROL, ASC0_A, ASC0_B, DAI, ASC1, GPIO, and PWR, can
be bridged by jumpers. All of these pin headers have the module's signal name on their left side
(marked yellow in Figure 7), whereas the right side corresponds to peripherals like level shifters
or the DSB connector (marked green in Figure 7).

• Placing a jumper connects a line through a level shifter to the associated pin at the 2x40 pin
connector at the underside of the LGA DevKit (and thus to a connected DSB75/DSB-Mini).
See also Figure 5.
• Not placing a jumper leaves a module signal open.

External periphery can also be connected to all accessible module signals directly. When con-
necting other external periphery to the pin headers pay attention not to violate the maximum
module ratings.

Figure 7: Pin headers

4.3.1 Default Configuration

Figure 8 shows the factory default jumper and switch positioning.
Control & ASC0

3x Jumper

USB USB

Figure 8: Default jumper and switch configuration

Please also verify that the SIM switch at the underside is set to default "CCIO Pullup disabled".

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4.4 ON Button: Module Start and Power Down
35

4.4 ON Button: Module Start and Power Down

Pushing the ON button shortly (i.e., <0.5s), the LGA DevKit starts up and initially analyses the
mounted module orientation and type. In case both are recognized and correct, the module is
started using specific start pulses. The white LED indicates the module’s VEXT state as high.

Also, it is possible to start up the module by toggling DTR on the DSB75/DSB-Mini RS232 con-
nector.

Pushing the ON button for more than 2s shuts down the LGA DevKit's power supply, and the
module's power supply is interrupted regardless of its current state.

4.5 RST Button: Module Reset

Pushing the RST button pulls down a module's EMERG-RST/OFF signal, thus forcing it into
reset or off state. Please note that this functionality is only available if the (default) jumper is set
for EMERG_RST at the CONTROL pin block (see Section 4.3).

4.6 ASC0 Switch: Module UART Interface Selection

The "ASC0" switch selects the module's UART communication interface either via USB VCP
(FTDI232R) or via "RS232" D-Sub interface on the DSB75/DSB-Mini.

Changing this from "USB" to "RS232" during operation resets the FTDI VCP bridge in order to
release the signal lines, thus leading to a USB VCP disconnect on the host PC side.

4.7 PWR Switch: Power Source Selection

The "PWR" switch selects the preferred power source, both sources can be connected at the
same time, but do not supply the LGA DevKit in parallel.

When "USB" is set, both LGA DevKit USB ports will contribute to the overall power supply with
a connected DSB75/DSB-Mini having to be powered separately. Setting "EXT", the power is
supplied from the DSB75/DSB-Mini interface.

Please note that there is a dedicated power supply for the GPS antenna. To use this, the two
pins at the GPS_PWR field will have to be soldered and connected by jumper.

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4.8 Free Level Shifters
35

4.8 Free Level Shifters

The LGA DevKit provides 8 free level shifters, with 4 placed & connected at the patch field on
the underside, and 4 connected to the pin header "LEVELSHIFTER". The level shifters on the
pin header are referenced to the module's Vext, and Vref that by default corresponds to 3V or
to "REF IN" if connected (see Section 4.12.2).

These level shifters can be used to shift signals that are not available at the DSB connector.

4.9 LEDs
The LGA DevKit LEDs have the following meaning:

LED Meaning
RED Blinking continuously: Module is inserted wrongly oriented, not powered, turn by 180°
Blinking 2 times: No module inserted, not powered
Blinking 3 times: A module not supported by footprint is inserted, not powered, change
module
Lighting: Overcurrent detected in module power pass, change module, restart LGA
DevKit's power supply
GREEN Module TXD0 activity, low active
GREEN Sufficient supply level, but not switched on
PWR
AMBER Module RXD0 activity, low active
BLUE Module state GPIO5 / LED (if a jumper is set for GPIO5 at the GPIO pin headers)
WHITE ON Module started, V180/300 is at high level (if the (default) jumper is set for VEXT at the
CONTROL block)
WHITE USB TX/RX activity on USB VCP

4.10 Patch Field

A small patch field is available at the LGA DevKit's under-
side. If required, you can add simple components (LED,
Transistors etc.) here. All module signals, except USB and
RF are accessible at the underside by the labeled pads.

4 level shifters are accessible close to the patch field as

well with the reference Vext and Vref. The Vref related lev-
el shifter connections can also be accessed via four addi-
tional pads at the left underside of the LGA DevKit where
additional pins may be soldered.

Attention: The warranty may be lost if the patch field is sol-

dered.
Figure 9: Patch field

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4.11 RF Antenna
35

4.11 RF Antenna
The LGA DevKit supports three antenna interfaces. The two SMA connectors "MAIN" and
"DRX" are used for radio transmission. The GNSS interface is supported by an U.FL connector
named "GPS".

All antenna interfaces have additional ESD protection implemented.

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Figure 10: S11 MAIN antenna input return loss transmit Figure 11: S21 MAIN antenna insertion loss transmit
direction (with socket) direction (with socket)
uid

The LGA DevKit package includes a broad band high efficiency PCB antenna that can be used
with the DevKit for all radio band combinations.
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Figure 12: S12 MAIN antenna insertion loss receive Figure 13: Antenna S11
direction (with socket)

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4.12 Power Supply
35

4.12 Power Supply

The LGA DevKit can be supplied through one or two USB ports that should be in the range of
5V +-5%, and/or externally by the DSB75/DSB-Mini. The modules supply level can be adjusted
in the range between 2.8…4.8V by setting the variable resistor at the DevKit's top side. The
DevKit power supply path is short protected with ~2A. In case of overcurrent the power path
will be interrupted and the red LED lights up until the power has been reset.

As a recommendation the LGA DevKit should be supplied with 5V/1A over one or two USB
ports. The onboard bypass capacitors should buffer enough energy to support short 2G peak
currents up to 2.5A.

4.12.1 Supply Current Measurement

The LGA DevKit supports three methods to measure the current consumption of the inserted
module.

• Measure the voltage across the on board 100 mOhm shunt resistor
• Measure the current by a current meter
• Power the module by an external power supply e.g. power analyzer

All options require a jumper placed on the 4th "BB" and 5th "RF" row for connecting baseband
and radio. Those two jumpers also allow to measure the current separately for the BB and RF
path.

Figure 14: Supply current measurements

Note: When measuring with a current meter, the meter’s internal resistance may cause a high
voltage drop, forcing the module to shut down. This can be avoided by measuring the voltage
cross the shunt. The current option is suitable for specialist power meter supplies, whereas the
voltage option is suitable for common voltage meters.

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4.12 Power Supply
35

4.12.2 External Reference Supply

To drive/operate the LGA DevKit's interfaces at certain voltage levels, an external reference
voltage may be connected. By default, i.e., without an external reference voltage connected,
the interface operates at 3V to meet the DSB75/DSB-Mini requirements. But if it is required to
operate the interface at another voltage, an external source in the range between 1.2V...5V can
be connected to "REF IN" and "GND" as shown in Figure 15.

Figure 15: External reference supply and pin header for free level shifter

Please note that this jumper should not be set when the LGA DevKit is connected to a DSB.

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5 General Characteristics
35

5 General Characteristics

The following table lists absolute maximum ratings for the LGA DevKit. Please note that viola-
tion of these limits may cause permanent damage to the LGA DevKit.

Table 2: Absolute maximum ratings

Parameter Min Max Unit
Voltage on USB ports -0.3 5.5 V
Voltage on DSB port -0.3 5.5 V
Voltage on signal pin header, depending on used module -0.3 2.1 V
Current signal pin header, depending on used module -10 +10 mA
Voltage on external reference -0.3 6 V
Socket single contact continues current 2 A

The following table lists recommended operating and environmental conditions for the LGA
DevKit.

Table 3: Operating and environmental conditions

Parameter Min Max Unit
Recommended operating condition 0 45 °C
Storage temperature 0 85 °C
Supply voltage on USB port 4.75 5.25 V
Supply current capability on USB port 1 A
Socket single contact resistance (Rev1) 80 120 mOhm
Socket single contact resistance (Rev1.1) 25 35 mOhm
Socket spring life cycle 100,000

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6 Operating the LGA DevKit with a DSB
35

6 Operating the LGA DevKit with a DSB

6.1 LGA DevKit on DSB-Mini

The LGA DevKit supports a 2x40pin connector at its underside, compatible to the DSB75/DSB-
Mini. A DSB may be a port extender for an RS232 interface, a second SIM or an analog audio
interface. When operating the LGA DevKit with a DSB the following settings can be adjusted.
• Use the "PWR" switch to select the power source. If you select "EXT", the DevKit expects
the power on the DSB connector. If you select "USB", the DevKit is powered by its USB
ports, and the DSB expects a separated power source.
• Use the "ASC0" switch to select the first UART. If you select "RS232", the modules ASC0
is conducted to the DSB and can be accessed on the D-SUB connector. If you select "USB"
the UART can be accessed via USB VCP port
Note that the USB VCP bridge will be in reset state while "RS232" is activated. As a conse-
quence the interface is de-enumerated on host side.
Also note that in order to reliably switch between the USB VCP bridge and the RS232 inter-
face, the DSB Mini requires an additional 47k pull up resistor. See red box in Figure 16 for
placement.

Figure 16: LGA DevKit on DSB-Mini

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6.2 LGA DevKit on DSB75
35

6.2 LGA DevKit on DSB75

To operate the LGA DevKit with the DSB75 please complete the following steps:

• Mount the LGA DevKit onto the DSB75.

• Insert the module.
• Set "PWR" and "ASC0".
• Check if all jumpers are placed at the pin header: CONTROL, ASC0_A and PWR
• Connect the host PC to DSB75 via Sub-D.

m
• Connect power to DSB75 and if needed to the LGA DevKit.
• Press the ON button (or the DSB75 IGT button).

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Figure 17: LGA DevKit on DSB75

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7 Module Specific Configuration Settings
35

7 Module Specific Configuration Settings

The following sections describe specific settings that must be taken into account for certain
modules.

7.1 BGS1 and BGS2 Operation

BGS2 requires a reference voltage for the I/O domain at VDIG (pad 10 of the LGA106 foot-
print). Therefore please connect IO25 and VEXT via a jumper.

7.2 BGS12 Operation

For a proper start of BGS12 a connection between the module’s ON signal (in Control block)
and VREF (in level shifter block) is required.

7.3 EMS31 Operation

EMS31-V requires a pull up resistor for the SIM interface that is not automatically detected as
with other modules. In order to activate the SIM pull up please use the SIM switch setting on
the LGA DevKit’s underside as described in Section 4.2.

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7.4 ENS22 Operation
35

7.4 ENS22 Operation

To make sure that firmware updates are performed without interruption, the default jumper at
"VEXT" at the "CONTROL" pin header must be removed. Instead, this jumper needs to be
placed at the "LEVELSHIFTER" pin header to connect "VEXT_B" and "VREF".

Also, with ENS22 the white ON LED blinks only very shortly, and about 3.5 seconds before the
module actually starts up.

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Cinterion® LGA DevKit User Guide Page 24 of 36

8 Document Information
35

8 Document Information

8.1 Revision History

Preceding document: "Cinterion® LGA DevKit User Guide" v02
New document: "Cinterion® LGA DevKit User Guide" v03

Chapter What is new

6.1 Added note regarding additional pull up resistor on DSB Mini.
7.4 Added remark on ENS22 jumper settings required for firmware updates.
9 Added placement and schematics for LGA DevKit L.

Preceding document: "Cinterion® LGA DevKit User Guide" v01

New document: "Cinterion® LGA DevKit User Guide" v02

Chapter What is new

Throughout Revised and updated document.
document

New document: "Cinterion® LGA DevKit User Guide" v01

Chapter What is new

--- Initial document setup.

8.2 Related Documents

[1] Hardware Interface Description for your Thales module
[2] AT Command Set for your Thales module

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Cinterion® LGA DevKit User Guide Page 25 of 36

8.3 Safety Precaution Notes
35

8.3 Safety Precaution Notes

The common safety precautions that apply to mobile phones must also be observed at all times
when using this LGA DevKit. Failure to comply with these precautions violates safety stan-
dards. Thales assumes no liability for customer’s failure to comply with these precautions.

The following is a non-extensive list of the mobile phone and LGA DevKit usage restrictions:

Pacemaker patients are advised to keep their hand-held mobile away from the pacemaker
while it is on.
Mobile phones must be switched off before boarding an aircraft.

Mobile phones may not be operated in the presence of flammable gases or fumes

Interference can occur if mobile phones are used close to TV sets, radios, computers or inad-
equately shielded equipment
Do not use your mobile while driving a vehicle

You should never rely solely upon any wireless device for essential communications, for exam-
ple for emergency calls

The power supply connected to the LGA DevKit shall be in compliance with the SELV require-
ments defined in EN 60950-1.

8.4 Regulatory Compliance Information

The Cinterion® LGA DevKit is intended for evaluation and development purposes only, and
should therefore only be used in a (laboratory) test environment. The device is not CE ap-
proved, and has not been authorized as required by the rules of the FCC. All persons handling
the Cinterion® LGA DevKit must be properly trained in electronics and observe good engineer-
ing practice standards.

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9 Appendix
35

9 Appendix

9.1 LGA DevKit SM

9.1.1 Placement

m
CON14 CON7 CON9 CON10 CON13 CON11 CON12
LED2

.co
CON18

LED6

JP3
C36 C35

R26
P1

CON17
es
CON2

JP2 C40 L3 C41

C42
L1
C43
JP4 JP6
JP8
C38

C37

C56
CON3

C55
uid

C45
L2
C44
CON16 CON15

LED9 BTN1 BTN2

CON1

S3 S2 LED4 LED5 LED3 LED1

Top view

U$1
-g

C32 R51
C52 R7 C53 D2 C14 R69 R70 R73 R61 R71 R1 R65 R68 R64 R15 R2 T3 R6 C23 R24
R50
C18 C58 R59
R72 R66 R67 R25
T16 IC8 T2 C22
R14 C28 C27 C24 R83
IC6 IC18 IC17 IC5 IC2 IC16 IC14 IC15 C30 R89
C29 C26 C25 R49 T11 R85
C34
-

IC20 R37
C20 C15 C33 C31 R63 L28 R54 D3
R27
IC7 L32
IC1

T6 C9 T17 R36 R39

R38 C21 C46 C47
IC4 L30
R29 T7 R30 R52
JP1
T10 T13 C5
TP8 1
C8 L29L35 L33L34L31
C50 T14
+

R18 C19
all

C51 R17 R102 R47 R48

R75 R55
-

C7 R22
C48 R53
T5
R56
R35 C2 C6 C16 R104
U$4 R60 R32 R20
IC10 T12 T9
R34 R86
+

D1 R31
C17R21
R43 R44
R40
R42 R45 R57
IC21 C67 R41
C69 C57 IC99
TP7 7
C70 C71 C68
C62 C59 R28
+

C77 R101 D5 R82

S1 R103
IC19
C78
R88
R62
C4 C3 C39
R87 R4 C60 C64
R96 T15 R98
IC11 R97
R46
-

C61 C63 C12 C10 C13 C11

C76 C75 R100
IC9 R23 IC3
R3 C66 C65
R76 R77 CON8
R5 IC22
T1
TP1 0

TP5
TP4

R79 R78
R81

R80 LED7
R58
TP6

JP7

R95 U$3
R94
T8 R84 C1 R8R10R9
R93
R99 C72
R92R91 R16
R90 R12 T4
R13 R33 R19
C73
R11 C74

Underside view

Figure 18: Top and underside placements (LGA DevKit SM)

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9.1 LGA DevKit SM
35

9.1.2 Schematics

A MODULE1
B C D U$2
E F G H
EHS5/6/8, ELS61, BGS2/5 Custom Dual Design EHS5/6/8, ELS61, BGS2/5 Custom Dual Design SMA + U.FL CONNECTORS
INDUSTRIAL FOOTPRINT
VUSB_MODULE U.FL-R-SMT(01)_np
200R
CON15

RF
233/44 233/44
VUSB/[2] R58 VUSB VUSB_MODULE VUSB

USB
228
45 236 18pF C41 18pF C40
USB_DP_TINY_LGA/[2] USB_DP_LGA106/114 HSIC_DATA HSIC_DATA/NC ANT_GPS_PWR/NC ANT_GPS_PWR/[2] ANT_MAIN HSIC_DATA
46 59 237
USB_DM_TINY_LGA/[2] USB_DN_LGA106/114 RF_OUT ANT_MAIN HSIC_STRB HSIC_STRB/NC GND

GND
22nH
L3
234 56
USB_DP_BIG_LGA/[2] USB_DP_LGA120 GND/ANT_DRX ANT_DRX GND

USB
5

RF
235 224/35 28 229/40
USB_DM_BIG_LGA/[2] USB_DN_LGA120 ANT_GPS/NC ANT_GPS I2CCLK/[2] I2CLCK GPIO4/FST_SHDN/NC GPIO4/[3]

I2C
HSIC_DATA
HSIC_STRB
236

237
HSIC_DATA/NC
HSIC_STRB/NC
ANT_GPS_PWR/NC
228
ANT_GPS_PWR/[2] I2CDAT/[2]
27
I2CDAT GPIO5/LED/NC
GPIO6/PWM2/NC
239/39

240/38
GPIO5/[3]
GPIO6/[3]
CON2
5
73251-1150
VSIM
20
VSIM GPIO7/PWM1/NC
241/37
GPIO7/[3] GND
28 229/40 216/17 242/36 CON16
I2CCLK/[2] I2CLCK GPIO4/FST_SHDN/NC GPIO4/[3] CCRST CCRST GPIO8/COUNTER/NC GPIO8/[3]

I2C
27 239/39 21 95 18pF C43 18pF C42
I2CDAT/[2] I2CDAT GPIO5/LED/NC GPIO5/[3] CCCLK CCCLK SDIO1 PAD95 ANT_DRX HSIC_STRB

SIM
GPIO
240/38 218/19
GPIO6/PWM2/NC GPIO6/[3] CCIO CCIO GND

GND
22nH
L1
20 241/37 217/18 222
VSIM VSIM GPIO7/PWM1/NC 242/36
GPIO7/[3] CCIN/[3] CCIN GPIO11/NC GPIO11 GND
216/17 221
CCRST CCRST GPIO8/COUNTER/NC GPIO8/[3] GPIO12/NC GPIO12
21 95 220
CCCLK CCCLK SDIO1 PAD95 GPIO13/NC GPIO13

SIM
GPIO
218/19 246 219 CON3
CCIO CCIO PAD246 CC2_VCC GPIO14/NC GPIO14 73251-1150
CCIN/[3]
217/18
CCIN GPIO11/NC
222
GPIO11 SPI_MISO
249
CC2_RST/SPI_MISO GPIO15/NC
244
GPIO15 GND

SIM2
221 247 35 CON1 U.FL-R-SMT(01)_np
GPIO12/NC GPIO12 PAD247 CC2_CLK GPIO25/NC GPIO25
220 248 206/7 18pF C45 18pF C44
GPIO13/NC GPIO13 SPI_CLK CC2_IO/SPI_CLK ADC1/NC ADC1/[3] ANT_GPS
246 219 106
PAD246 CC2_VCC GPIO14/NC GPIO14 SPI_MOSI SPI/MOSI

22nH
L2
249 244 243/1
SPI_MISO CC2_RST/SPI_MISO GPIO15/NC GPIO15 VMIC VMIC/[3] U.FL-R-SMT(01)

SIM2
247 35 207/8 65
PAD247 CC2_CLK GPIO25/NC GPIO25 ON_MODULE/[3] ON MICP1/SPI_CS2 MICP1/[3]

AUDIO
248 206/7 215/16 66
SPI_CLK CC2_IO/SPI_CLK ADC1/NC ADC1/[3] VDDLP VDDLP MICN1/SPI_CS1 MICN1/[3]
106 79 202/3
SPI_MOSI SPI/MOSI NC/AUTO_ON EPP1 EPP1/[3]

4
243/1 33 201/2
VMIC EMG_RST EPN1
VMIC/[3] EMG_RST/[3] EPN1/[3]
4

CONTROL
ON_MODULE/[3]
207/8
ON MICP1/SPI_CS2
65
MICP1/[3] VEXT_MODULE/[3]
209/10
V180/VDIG RSV/AGND/GND
64
AGND/[3] GND
AUDIO

215/16 66 22
VDDLP VDDLP MICN1/SPI_CS1 MICN1/[3] VCORE/[3] VCORE/V285
79 202/3 72 26
NC/AUTO_ON EPP1 EPP1/[3] AUTO_ON AUTO_ON/NC GPIO23/SCLK SCLKDAI/[3]
33 201/2 24
EMG_RST/[3] EMG_RST EPN1 EPN1/[3] GPIO22/TFSDAI FSDAI/[3]

I2S
CONTROL

VEXT_MODULE/[3]
209/10

22
V180/VDIG RSV/AGND/GND
64
AGND/[3] GPIO21/RXDDAI
25

23
RXDAI/[3] FREE GPIO/PINS PINHEADER
VCORE/[3] VCORE/V285 GPIO20/TXDDAI TXDAI/[3]
72 26
AUTO_ON AUTO_ON/NC GPIO23/SCLK SCLKDAI/[3]
24 29 JP4
GPIO22/TFSDAI FSDAI/[3] GPIO17/TXD1/MISO TXD1/[3]
GND

I2S

1 2

ASC1
25 30
GPIO21/RXDDAI RXDAI/[3] GPIO16/RXD1/MOSI RXD1/[3] GPIO15 GPIO14
47uF

47uF

47uF

47uF

23 53 31 3 4
GPIO20/TXDDAI TXDAI/[3] BATT+_RF/[2] BATT+_RF/BATT+_BGS5_EMS31/BATT+_BB_ELS31
GPIO18/RTS1 RTS1/[3] VDDLP GPIO13
204 32 5 6
BATT+_BB/[2] BATT+_BB GPIO19/CTS1/SPI_C CTS1/[3] AUTO_ON GPIO12
7 8
C38

C37

C36

C35

29 5
GPIO17/TXD1/MISO TXD1/[3] BATT+_BB2 BATT+_BB/BATT+_BGS5_EMS31/BATT_RF_ELS31 GPIO25 VEXT_MODULE/[3]
9 10
ASC1

30 212/13
GPIO16/RXD1/MOSI RXD1/[3] TXD0 TXD0/[3] V480/[2] GPIO11
53 31 210/11 11 12
BATT+_RF/[2] BATT+_RF/BATT+_BGS5_EMS31/BATT+_BB_ELS31
GPIO18/RTS1 RTS1/[3] RXD0 RXD0/[3] GND/[2] EXTERN_REFERENCE/[2]
204 32 214/15
BATT+_BB/[2] BATT+_BB GPIO19/CTS1/SPI_C CTS1/[3] RTS0 RTS0/[3]
2x6_HEAD_SMD

ASC0
5 211/12
BATT+_BB2 BATT+_BB/BATT+_BGS5_EMS31/BATT_RF_ELS31 CTS0 CTS0/[3]
212/13 67 232/43
TXD0 TXD0/[3] DNU67 DNU GPIO1/DTR0 DTR0/[3]
GND

_np 43x 210/11 68 230/41

TP75 GND RXD0 RXD0/[3] DNU68 DNU GPIO3/DSR0/SPI_CLK DSR0/[3]
238 214/15 69 231/42
GND_DETECT RTS0 DNU GPIO2/DCD0
3
BIG_LGA_DETECT/[2]
54
RTS0/[3] DNU69 DCD0/[3]
JP8 3
ASC0

211/12 70 213/14
TWIST_DETECT TWIST_DETECT CTS0 CTS0/[3] DNU70 DNU GPIO24/RING0 RING0/[3]

BATT+_BB/[2]
_np 67 232/43 71 1 2
TP66 DNU67 DNU GPIO1/DTR0 DTR0/[3] DNU71 DNU PAD246 SPI_CLK
68 230/41 73 93 3 4
DNU68 DNU GPIO3/DSR0/SPI_CLK DSR0/[3] DNU73 DNU POWER DNU CCIN2/[3] PAD247 SPI_MISO
69 231/42 74 94 5 6
DNU69 DNU GPIO2/DCD0 DCD0/[3] DNU74 DNU DNU CCCLK2/[3] PAD95 SPI_MOSI
70 213/14 75 7 8
_np

LED7

DNU70 DNU GPIO24/RING0 RING0/[3] DNU75 DNU V480/[2] GND/[2]

71 76 96
DNU71 DNU DNU76 DNU DNU CCIO2/[3]
DNU73
73
DNU POWER DNU
93
CCIN2/[3] DNU77
77
DNU DNU
97
CCVCC2/[3] 2x4_HEAD_SMD
74 94 78 104
DNU74 DNU DNU CCCLK2/[3] DNU78 DNU DNU DNU104
75 80 105
R31
DNU75 DNU DNU79 DNU DNU DNU105
0R

GND DNU76 76
DNU DNU
96
CCIO2/[3] DNU83
83
DNU DNU
226
DNU226
77 97 87 251
DNU77 DNU DNU CCVCC2/[3] DNU87 DNU DNU CCRST2/[3] NX3008PBKS
78 104 91 98
DNU78 DNU DNU DNU104 DNU91 DNU DNU DNU98
_np T15A
INDUSTRIAL FOOTPRINT BOTTOM PATCHFIELD
BATT+_BB2

80 105
DNU79 DNU DNU DNU105
4 83 226
DNU DNU DNU226
3 87 251
DNU DNU CCRST2/[3]
2 91 98
EHSX_PATCH_FIELD_np
DNU DNU DNU98
1 BATT+/[2]
IC11 >A=
A 4k7
JP1 _np _np _np
ATMEGA_3V_LDO/[2]
1
VIN VOUT
5 +3V/[3] R103 SIMPU_E_OD
2

GND
TP4 TP5 TP6
_np SIM HOLDER >B=

2
_np

100nF
IC9A B
GND

TP10 3k3 4k7

3

VLMG1300-GS08 220R
S1

R99
R23 R62 EN SSSS8_11101 R96
25 15 100k CON8
RESET@UC /RST_PCIN14_C6 SCK_PCIN5_B5

NX3008PBKS
T15B
TP77
14 2 4

C78
_np

100nF
MISO_PCIN4_B4 GND BP CCCLK CCCLK

10nF
TP78
13 1 2 _np
MOSI_PCIN3_B3 1 2 +3V/[3] CCVCC VSIM
MICROCONTROLLER + ON CIRCUIT + RST

TP79
12 3 4 LP2985AIM5-3.0

LED9
_np
SS_OC1B_PCIN2_B2 0R
R5 ON_BUTTON 3 4 CCIO CCIO TP80
11 5 6 GNDGND

C76

C77
_np
OC1A_PCIN1_B1 1k5
R3 ON/[3] RESET@UC 5 6 CCRST CCRST
10
ICP1_CLKO_PCIN0_B0 0R
R100 CCGND GND/[2]
5 GND

220nF
XTAL1_TOSC1_PCIN6_B6 +3V/[3]

10pF

10pF
GNDGND

1nF
CON6 CCDET1 VEXT_BUFF/[2]
R87
R88
R4

TP58 _np T17A

_np
NX3008NBKS
CCDET2 R46 CCIN_X100/[3]
5

C10

C11

C12

C13
TP56
0R

GND
_np

4
0475532001
VDDLP
47k
47k
2k7

6
XTAL2_TOSC2_PCIN7_B7
24
EMERG_RST_X100/[3]

ADC5_SCL_PCIN13_C5 PHS8_CCCLK2_GND
ON_BUTTON

23
ADC4_SDA_PCIN12_C4 PHS8_CCIO1
22
+3V/[3]

ADC3_PCIN11_C3 R97
CDBQR70

D5

21 2k7
ADC2_PCIN10_C2 TWIST_DETECT
Datum Name
ADC1_PCIN9_C1
20 VUSB_MODULE
Vers.: Blatt:
19 Bear.
ADC0_PCIN8_C0

1
VCC VCC
Gepr. 1
47k
R101

16

17 9
3

AIN1_PCI23_D7
100nF

AREF R28 EN_BATT+/[2]

8
KSC701J LFS

KSC701J LFS

AIN0_OC0A_PCI22_D6 0R MOD_ON_DET/[3]
ATMEGA88PA-MMH

ATMEGA88PA-MMH

7 IC9B IC9C
C56

C55

T1_OC0B_PCI21_D5 LED_EN/[2]
2 BG:
BTN2

BTN1
C75

XCK_T0_PCI20_D4 IGT_X100/[3]
1 GND
1u

1u

INT1_OC2B_PCIN19_D3 SIMPU_E_OD
LGA DevKit S+M
4

18

28 GND GND
INT0_PCIN18_D2 E_VEXT-PD/[2]
27 TP57
TXD_PCIN17_D1 _np R98 +3V/[3]
26 TP61
47k_np
RXD_PCIN16_D0 _np
GND GND GND
ATMEGA88PA-MMH Änderung Datum Nam. Ers. f.: Ers. d.:
A B C D E F G H

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9.1 LGA DevKit SM
35

A B C D E F G H
IC4
LDO BATT+ GPS PWR TC1014-3.0VCT713 LDO +3V
BATT+: 2.8V - 4.86V TP68
EXTERN_REFERENCE/[1]
_np
V480 1 5
BATT+/[1] VIN VOUT
3*2 5

ANT_GPS_PWR/[1]
1x2_HEAD

JP3
_np
IN OUT BATT+/[3] T14A
ISL80103 TP81
3

1uF

1uF

2
1
_np
SD
IC10 TP64
2 TP65
LDO_OUT/[3] EN_BATT+/[1] EN/UVLO NX3008PBKS

33pF_np
_np
9*2 1*2 1 6 2 4

C8

C7
IN OUT DVDT FLT ERROR_LED_OD GND BP V480/[1]

2.2uF
15pF
8*2 7
5 X100.BATT+ ILM

470pF
GND
2.2uF

7 3 T14B
5

C57
12k7
R17
EN FB

1k3
R57
GND

R104
IC20

330R
C19

C50

C51

R38

R27
R14

47k

47k
6 4 1 5
C17

_np

C9
4*2
SS PB 0R_np Place Jumper between VIN VOUT VREF/[3]
3

100nF

100nF
V480/[1] 1 & 2 to power GPS
5*2

1uF

1uF
T6 EN

3
_np DMP2021UFDF-7
TP67 bridge FET control with R14

1*5
2 4

C21

C20

C14

C18
T5A

1*5
44WR10KLFTB User Option: NX3008NBKS
GND BP
P1
5 GND_DETECT_DSB/[3] R29
T7B
DMP2021UFDF-7

10nF
BC847

4
LP2985AIM5-3.0

DISCHARGE_BATT+/[1]
R75 T16 4k7
3 USB SUPPLY DIODE
RED

VLMS1300-GS08

LED6
5k_np

4*2

C15
D3 PMEG2020EPK,315
Place R75 for fixed VOUT
2k74
R18

if P1 is not placed T7A

_np TP63
R30

T13
TP62 _np BC847
4k7

180R
R63
1*5 4*2

R52
VUSB/[1] VUSB_FTDI

47k

R102
DMP2021UFDF-7
C5
SSSS811101

2k2
560R
R85
T11A

33pF_np

3
BC857
1uF_np

100nF
ATMEGA_3V_LDO/[1]
BC857
BAT

4
A

ERROR_LED_OD
4
S3 5V

S3 T11B
D1 PMEG2020EPK,315 If the DevKit is used as DSB Adapter then the LDO is enabled for a fixed 3V referencce.

100k

47k
R25

R22
>A=

>B=

C53

C52
T8A
V480/[1] X100.BATT+/[3] LED_EN/[1] R95 If the DevKit is used standalone then the reference is also sourced from +3V or from extern reference
GND
BC847
PMEG2020EPK,315 D2 4k7
47k R7
R21 470k_np RX & TX LEDs V480/[1] V480/[1]

680R
R13
R11
2k7
USB <-> UART Bridge: FTDI IN RUSH CURRENT PROTECTION
IC1

VLMW1300-GS08

VLMB1300-GS08
R54
19 30 L28
33R
100nF

V480/[1] VCC TXD BLM15HG601SN1 TXD0_X100/[3]

1 2 L29 ON/OFF STATUS

LED1

LED3
VREF/[3] VCCIO RXD BLM15HG601SN1 RXD0_X100/[3] V480/[3]
RTS
32 L30
BLM15HG601SN1 RTS0_X100/[3] DMP2021UFDF-7
WHITE SD_CLK(GPIO5)_X100/[3] LIGHT
18 8 L31
BLUE
C23

FTDI_RESET/[3] RESET CTS BLM15HG601SN1 CTS0_X100/[3] T10

_np 31 L32 4*2 1*5
TP76 DTR BLM15HG601SN1 DTR0_X100/[3] VUSB_FTDI
27 6 L33
P$8*2
P$6*2

OSCI DSR BLM15HG601SN1 DSR0_X100/[3]

28 7 L34 T8B T4A

R53

R55
OSCO DCD DCD0_X100/[3] VEXT_BUFF/[1] R93 R16

47k
1M
BLM15HG601SN1 BC847 BC847

3
3 L35
4k7 4k7
RI RING0_X100/[3]
3

47k

47k
0.1R

0.1R

0.1R

0.1R

0.1R

0.1R

0.1R

0.1R
BLM15HG601SN1
ZX62D-B-5PA8(30)

R47

R48

R40

R41

R42

R43

R44

R45

R94

R91
P$1 VUSB_FTDI
3 VCC
P$2 FTDI.USB.D- 22
680R VLMW1300-GS08

6
D- CBUS0 R6
P$3 FTDI.USB.D+ 21 LED2 T5B
D+ CBUS1 NX3008NBKS
GND_MODUL_LED
P$4 16 10 LED White 2

470uF

470uF

470uF

470uF

470uF

470uF

470uF

470uF
3V3OUT CBUS2
CON18

ID FTD.3V3 V480/[1] V480/[1]

1
P$5 11

1uF
TP69
GND CBUS3 _np
14 9

R56
FTDI.USB.D+ USBDP CBUS4

1M
P$11
P$10

C46

C47

C2

C4

C3

C6

C16

C39
15

330R

330R
C48

R19

R33
FTDI.USB.D- USBDM
26
TEST
100nF

24
GND
4*2

VLMG1300-GS08

VLMO1300-GS08
GND
17 GNDGND GND
C22

GND
20 GND RX TX

LED4

LED5
GND
GREEN SOFT
FT232RQ ORANGE

220k

220k
R86

R20

R60

R34
47k

47k
VEXT BUFFER

C73

C74
T9A T12A

BATT+/[1]
BC847 BC847

1uF

1uF
USB MULTIPLEXER
2 RXD0_X100/[3] R32
T9B
TXD0_X100/[3] R35
T12B

2
GND
47k
R8

BC847 BC847
C1 100nF C30 100nF
P$8*2
P$6*2

10k 10k
R9 V480/[3]
VCC

5
0R 0R_np GND_MODUL_LED
GND
ZX62D-B-5PA8(30)

P$1 VUSB/[1] 1 IC7

VCC R84 OE VCC R10 BATT+/[3] VEXT_JUMPER/[3]
D- P$2 BOARD.D- 0R 4
BIG_LGA_DETECT/[1] SEL R36 VEXT_BUFF/[3]
470k
R37

D+ P$3 BOARD.D+ 3 0R

0R_np
R92
P$4 TLV6741 T4B

1nF C34

C31
HSD1+ D+
CON17

ID USB_DP_BIG_LGA/[1] BOARD.D+ VEXT_BUFF/[1] R12

2

1k
BC847

R39
P$5 GND
GND USB_DM_BIG_LGA/[1] HSD1- D- BOARD.D- 4k7

47k
R90
100nF_np
6
P$11
P$10

USB_DP_TINY_LGA/[1] HSD2+ T17B

2 NX3008NBKS
USB_DM_TINY_LGA/[1] HSD2- GND E_VEXT-PD/[1]
1

GND
GND

CURRENT MEASUREMENT I2C LEVELSHIFTER Datum Name

R26
Vers.: Blatt:
JP2
0.1R Bear.
1 BATT+/[1]
TP72 1
3
2
4
PLACE JUMPER
VEXT_BUFF/[1] VREF/[3] VEXT_BUFF/[1] VREF/[3]
Gepr. 1
PLACE VOLTMETER
5 6
R76

R77

R78

R79

PLACE AMETER
4k7

4k7

4k7

4k7

7 8 TP71
BATT+_BB/[1]
BG:
9 10 TP70
5

2x5_HEAD_SMD
BATT+_RF/[1]
I2CCLK/[1] R80
0R
4
T1A
3 I2C_CLK_LS/[3] I2CDAT/[1] R81
0R
1

T1B
6 I2C_DAT_LS/[3] LGA DevKit S+M
NX3008NBKS NX3008NBKS
Änderung Datum Nam. Ers. f.: Ers. d.:
A B C D E F G H

t lga_devkit_ug_v03 2020-05-29
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Cinterion® LGA DevKit User Guide Page 29 of 36

9.1 LGA DevKit SM
35

A B C D E F G H
LEVEL SHIFTER ASC0.1 PINHEADER 80 PIN INTERFACE
IC14 CON7 Control EEPROM
1 8 1 2
VREF/[2] VCC-A VCC-B VEXT_BUFF/[2] ON/[1] ON_MODULE/[1]
2 7 3 4
100nF B1

100nF
RXD0_X100/[2] A1 RXD0@LS EMERG_RST_X100/[1] EMG_RST/[1]

GND
GND
3 6 5 6 1 2
CTS0_X100/[2] A2 B2 CTS0@LS VEXT_JUMPER/[2] VEXT_MODULE/[1] GND GND

TP54
_np
5 4 7 8 3 4
DIR L H
GND CCIN_X100/[1] CCIN/[1] DAC_OUT_X100 DAC_OUT ADC1_IN ADC1_IN_X100
5 6 1 4
C25

C24
_np
PWR_IND PWR_IND ADC2_IN ADC2_IN_X100 SCL VCC +3V/[1]

GND
TP52
74LVCH2T45GT 7 8 3
5 GND
1
IC15
8
@LS = LEVELSHIFTER 2x4_HEAD_SMD
CON9
1 2
ASC0.1
TP_ENV_X100
RXD2_GPIO9_X100
9
11
TP_ENV
RXD2_GPIO9
GND
TXD2_GPIO10
10
12
TXD2_GPIO10_X100
_np
TP53

5
SDA
2
5
TP55
VCC-A VCC-B RXD0@LS RXD0/[1] SPICS_X100 SPICS SD_WP(GPIO8) SD_WP(GPIO8)_X100 NC VSS _np
2 7 3 4 13 14
TXD0_X100/[2] A1 B1 TXD0@LS CTS0@LS CTS0/[1] SD_3_X100 SD_3(GPIO4) SPIDI SPIDI_X100
3 6 5 6 15 16 GND
RTS0_X100/[2] A2 B2 RTS0@LS TXD0@LS TXD0/[1] SD_2_X100 SD_2(GPIO3) SD_DET(GPIO7) SD_DET(GPIO7)_X100
5 4 GND 7 8 17 18
DIR L H
GND RTS0@LS RTS0/[1] SD_1_X100 SD_1(GPIO2) SD_CMD(GPIO6) SD_CMD(GPIO6)_X100
19 20
74LVCH2T45GT
SD_0_X100 SD_0(GPIO1) SD_CLK(GPIO5) SD_CLK(GPIO5)_X100/[2]
2x4_HEAD_SMD 21 22
I2CDAT_X100 I2CDAT I2CCLK I2CCLK_X100 0R
GND GND CON10 ASC0.2 23 24 C67 33pF
IC2 ASC0.2
USB_DP VUSB_IN R15 V480/[2] VMIC/[1] AGND/[1]
1 2 25 26
DTR0@LS DTR0/[1] USB_DN USC5 USC5_X100
1 8 3 4 27 28 C68 33pF
VREF/[2] VCC-A VCC-B VEXT_BUFF/[2] DCD0@LS DCD0/[1] VSENSE ISENSE MICP1/[1]
2 7 5 6 29 30

R82
100nF

100nF
DCD0_X100/[2] A1 B1 DCD0@LS DSR0@LS DSR0/[1] VMIC_X100 VMIC USC6 USC6_X100
0R

0R
3 6 7 8 31 32 C69 33pF
DSR0_X100/[2] A2 B2 DSR0@LS RING0@LS RING0/[1] EPN2_X100 EPN2 CCCLK R64
0R CCCLK2/[1] MICN1/[1]
5 4 33 34
DIR L H
GND EPP2_X100 EPP2 VSIM R67
0R CCVCC2/[1]
2x4_HEAD_SMD 35 36
C26

C27
C70 33pF
EPP1_X100 EPP1 CCIO R68
0R CCIO2/[1] EPP1/[1]
74LVCH2T45GT CON11 ASC1 EPN1_X100
37
EPN1 CCRST
38 R66
0R CCRST2/[1]
IC16 1 2 39 40 C71 33pF GND
TXDDAI CTS1@LS CTS1/[1] MICN2_X100 MICN2 CCIN R65 CCIN2/[1] EPN1/[1]

GND
1 8 3 4 41 42
VCC-A VCC-B RTS1@LS R70 RTS1/[1] MICP2_X100 MICP2 CCGND
2 7 100R 5 6 43 44
RING0_X100/[2] A1 B1 RING0@LS RXD1@LS RXD1/[1] MICP1_X100 MICP1 USC4 USC4_X100
3 6 7 8 45 46
4 USC0_X100
5
A2
DIR L H
B2
GND
4
USC0@LS
GND
TXD1@LS R69
100R
2x4_HEAD_SMD
TXD1/[1] MICN1_X100
AGND_X100
47
49
MICN1
AGND
USC3
USC2
48
50
USC3_X100
USC2_X100 4
IGT_X100/[1] IGT USC1 USC1_X100
74LVCH2T45GT CON12 GPIO EMERG_RST_X100/[1]
51
EMERG_RST USC0
52 USC0_X100
GND GND GND 1 2 53 54
IC5 DAI SD_3_X100
3 4
GPIO4/[1] DCD0_X100/[2]
55
DCD0 BATTEMP
56
SD_CLK(GPIO5)_X100/[2] GPIO5/[1] CTS1_X100 CTS1 SYNC SYNC_X100
1 8 5 6 57 58
VREF/[2] VCC-A VCC-B VEXT_BUFF/[2] SD_CMD(GPIO6)_X100 GPIO6/[1] CTS0_X100/[2] CTS0 RXD1 RXD1_X100
2 7 7 8 59 60
100nF

100nF
DTR0_X100/[2] A1 B1 DTR0@LS SD_DET(GPIO7)_X100 GPIO7/[1] RTS1_X100 RTS1 RXD0 RXD0_X100/[2]
3 6 9 10 61 62
USC1_X100 A2 B2 USC1@LS SD_WP(GPIO8)_X100 GPIO8/[1] DTR0_X100/[2] DTR0 TXD1 TXD1_X100
5 4 11 12 63 64
RXDDAI DIR L H
GND I2CDAT_X100 I2CDAT/[2] RTS0_X100/[2] RTS0 TXD0 TXD0_X100/[2]
13 14 65 66
C29

C28

74LVCH2T45GT
I2CCLK_X100 I2CCLK/[2]
CDBQR70
DSR0_X100/[2] DSR0 VDDLP
15 16 67 68
ADC1_IN_X100 ADC1/[1] D4 RING0_X100/[2] RING0 VCHARGE

BC847
IC17 69 70
VEXT CHARGEGATE

T3A
0R_np
GND 1 8 2x8_HEAD_SMD 71 72
VCC-A VCC-B X100.BATT+/[2] BATT+ GND R2 FTDI_RESET/[2]
2 7 73 74
FS USC2_X100 A1 B1 USC2@LS BATT+ GND 10k
SCLK USC3_X100
3
A2 B2
6 USC3@LS
CON13 DAI 75
BATT+ GND
76 R83 LDO_OUT/[2]
_np 5 4 1 2 77 78
TP59 DIR L H
GND USC3@LS R72 SCLKDAI/[1] BATT+ GND
_np 100R 3 4 79 GND 80
TP60
74LVCH2T45GT
USC2@LS R73 FSDAI/[1] BATT+ GND_DETECT_DSB/[2] MOD_ON_DET/[1]
USC1@LS 100R
R71
5 6 RXDAI/[1] If DevKit is used as
4k7
GND

GND GND 7 8
ASC1 100R U$1 DSB Adapter this pin is low

3
R61

1
IC6
8
USC0@LS

2x4_HEAD_SMD
TXDAI/[1]
T27A1132-80SSG0PBNA01RTC GND VEXT_BUFF/[2]
47k
R89
T3B
BC847
3
VREF/[2] VCC-A VCC-B VEXT_BUFF/[2] 0R
2 7
B1
100nF

100nF

RXD1_X100 A1 RXD1@LS SYNC_X100 R1 SD_CLK(GPIO5)_X100/[2]

CTS1_X100
3
A2 B2
6 CTS1@LS
CON14 AUDIO2
5 4 1 2 GND
DIR L H
GND AGND_X100 AGND/[1]
3 4
C33

C32

MICP1_X100 MICP1/[1]
74LVCH2T45GT 5 6
MICN1_X100 MICN1/[1]
GND IC18
VMIC_X100
7 8 VMIC/[1]
1 8 9 10 FREE LEVELSHIFTER PATCHFIELD POWER INDICATION CICUIT
VCC-A VCC-B EPN1_X100 EPN1/[1]
2 7 11 12
TXD1_X100 A1 B1 TXD1@LS EPP1_X100 EPP1/[1] BATT+/[2]
3 6
RTS1_X100 A2 B2 RTS1@LS
5 4 2x6_HEAD_SMD
DIR GND

GND
L H

GND
C60 100nF C64 100nF

470k
R51
74LVCH2T45GT GND IC3
GND GND 1 8
VEXT_BUFF/[2] VCC-A VCC-B VREF/[2]

GND
2 7
TP47 A1 B1 BATT+/[2]
100nF_np C58
PWR_IND
FREE LEVELSHIFTER PINHEADER 3 6
TP37 A2 B2 TP48
S2 5 4
DIR L H
GND
T2A
VEXT_BUFF/[2] R49
2 GND
GND

GND

74LVCH2T45GT BC847
C63 100nF C62 100nF

V480/[2]
GND
1
IC21
8 _np VCC
47k
2

5
VEXT_BUFF/[2] VCC-A VCC-B VREF/[2] TP42
GND 2 7 4 1 IC8
1uF
R24

1LS_IN_A1 A1 B1 1LS_OUT_B1 VCORE/[1]

47k

0R
R59
>A= 3 6 GND 3 4 T2B
A = ENABLE FTDI ONBOARD 1LS_IN_A2 A2 B2 1LS_OUT_B2 R50

GND
GND
BC847
5 4 2 3
C72

C66 100nF C65 100nF 47k_np

DIR L H
GND TLV6741_np
>B= IC22 1
FTDI_RESET/[2] B = ENABLE RS232/LEVELSHIFTER*

2
S2 74LVCH2T45GT GND 1 8 GND
SSSS811101
VEXT_BUFF/[2] VCC-A VCC-B VREF/[2]
GND 2
A1 B1
7 JP7
*The equivalent switch on DSB Mini
TP45 3 6
A2 B2
GND
GND

must be set to RS232 C59 100nF C61 100nF TP43 5 4

DIR L
GND
H

IC19
1 8 74LVCH2T45GT GND TP44
PATCHFIELD TP73 VEXT_BUFF/[2] VCC-A VCC-B VREF/[2]
2 7 TP46
GND
TP49 TP51 TP50 TP1 TP3 TP2 2LS_OUT_A1 A1 B1 2LS_IN_B1
3 6
2LS_OUT_A2 A2 B2 2LS_IN_B2
5 4
DIR L H
GND
TP83 TP82 TP74
VREF/[2] VEXT_BUFF/[2] 74LVCH2T45GT Datum Name Vers.: Blatt:
GND GND Bear.
JP6
1 TP100 TP39 TP38 TP41 TP40 TP36 TP33 TP30 TP27 TP24 TP21 TP13 TP9
VEXT_BUFF/[2]
1
3
2
4
VREF/[2]
Gepr. 1
1LS_IN_A2 1LS_OUT_B2
1LS_IN_A1
5 6 1LS_OUT_B1
TP35 TP32 TP29 TP26 TP23 TP20 TP14 TP8 7 8 BG:
2LS_OUT_A2 2LS_IN_B2
9 10
GND
TP18 TP17 TP16 TP12 TP11
TP34 TP31 TP28 TP25 TP22 TP19 TP15 TP7
2LS_OUT_A1
I2C_CLK_LS/[2]
11 12
2LS_IN_B1
I2C_DAT_LS/[2] LGA DevKit S+M
2x6_HEAD_SMD
Änderung Datum Nam. Ers. f.: Ers. d.:
A B C D E F G H

t lga_devkit_ug_v03 2020-05-29
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Cinterion® LGA DevKit User Guide Page 30 of 36

9.2 LGA DevKit L
35

9.2 LGA DevKit L

9.2.1 Placement

LED2
CON14 CON7 CON9 CON10 CON13 CON11 CON12

CON18

LED6
LGA_MODULE JP3
R26
P1

CON17
CON2

JP2 C40L3 C41

L2 C45
C44

L1 JP4 JP6
JP8
C42 C43 CON1
C38

C37

C56
CON3

C55

LED9 C35C36 BTN1 BTN2

S3 S2 LED4 LED5 LED3 LED1

Top view

U$1

C32
C52 C53 D2 C14 R69R70 R73 R61 R71 R65 R68 R64 R15 R2 T3 R6 C23
R24
C18
R72 R66 R67 C22 R25
T16 R14 C28 C27 C24 R83
IC6 IC18 C29 IC17 IC5 C26 IC2 IC16 C25 IC14 IC15 C30 R89
T11 R85
C34
-

IC20 C20C15 C33 R37

- IC1

C31 R63 L28 R54 D3

R27
T6 R38 C21 C9 C46 T17 R36 IC7 R39 L32
IC4 C47 L30
R29 T7 R30 R52 T10 T13 C5
TP81 C8 L29
L35
L33
L34L31
C19C50 C51
+

R18 T14 R47 R48

R17 R102 R75 R55
-

C7 R22
C48 T5 R53
C2 C6 C16 R56 R104
U$4 R35 R60 R32 R20
IC10 T12 T9
R34 R86
+

R21D1
C17
R43 R44
LED7

LED8
R31 R40
R42 R45R57
IC21 R41

JP1 R82 C57IC99

C62C59
TP77 C67 R28
D5C68
+

C77 R101
C78
R88
C71

C69
C4 C3 C39
C70

IC19 R62
R87R4 C60 C64
R98
R46 C12C10 C13 C11 IC11 R97
C61C63
-

C76 C75

R76
R77 CON8
IC9

R5
PATCHFIELD IC3
C66 C65
IC22
T1
TP10

TP5

R79 R78
TP4

R81
R80
R3
TP6

JP7
R58

R95
R94
T8
R93 R99
C72
R92
R91
R16
R90
R12 T4
R13 R33 R19
R1

C73
R11 C74

Underside view
Figure 19: Top and underside placements (LGA DevKit L)

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Cinterion® LGA DevKit User Guide Page 31 of 36

9.2 LGA DevKit L
35

9.2.2 Schematics
A B C D E F G H
LGA_MODULE PATCHFIELD_BOTTOM SMA + U.FL CONNECTORS
PLS8/PHS8/AGS2/PDS8 Dual Design PLS8/PHS8/AGS2/PDS8 Dual Design

18pF C41 18pF C40

VUSB_MODULE ANT_DRX
200R N5 A12 N5
VUSB/[2] R58 VUSB1 ANT_DRX_MIMO/ANT_DRX/DNU/NC ANT_DRX VUSB_MODULE VUSB1 GND

L3
22nH

GND
P4 E1
BOARD.D+ USB_DP ANT_GNSS ANT_GPS GND

USB

USB
CON17 ZX62D-B-5PA8(30)

RF

RF
P5 K1
P$8*2
P$6*2

BOARD.D- USB_DN ANT_MAIN/ANT_W GSM ANT_MAIN

GPIO4/[3]
H14
GPIO4/WAKE/FST_SHDN ANT_GNSS_DC
VGNSS
D5

K16
ANT_GPS_PWR/[2]
VGNSS
GPIO4/[3]
H14
GPIO4/WAKE/FST_SHDN
VGNSS
K16
VGNSS
CON2
5
73251-1150
VCC
P$1 VUSB/[2]
P$2 PLS62 PLS62

m
K15 J14 K15 J14
D- BOARD.D- VSIM CCVCC GPIO15 GPIO1/GPS_1PPS/DNU GPIO1 VSIM CCVCC GPIO15 GPIO1/GPS_1PPS/DNU GPIO1
P$3 L14 J15 L14 J15 18pF C43 18pF C42
D+ BOARD.D+ CCRST CCRST1 GPIO14 GPIO2/DNU/NC GPIO2 CCRST CCRST1 GPIO14 GPIO2/DNU/NC GPIO2 ANT_MAIN
P$4 L15 J16 L15 J16
ID CCCLK CCCLK1 GPIO13 GPIO3/DNU/NC GPIO3 CCCLK CCCLK1 GPIO13 GPIO3/DNU/NC GPIO3 GND

SIM

SIM

L1
22nH

GND
P$5 K14 H15 K14 H15
GND CCIO CCIO1 GPIO12 STATUS GPIO5/DNU GPIO5/[3] CCIO CCIO1 GPIO12 STATUS GPIO5/DNU GPIO5/[3] GND

GPIO

GPIO
M14 H16 M14 H16
CCIN/[3] CCIN1 GPIO6/LC_IND GPIO6/[3] CCIN/[3] CCIN1 GPIO6/LC_IND GPIO6/[3]
P$11
P$10

G14 G14
GPIO7/DNU GPIO7/[3] GPIO7/DNU GPIO7/[3]
L6 G15 L6 G15 CON3
CCVCC2/[3] CCVCC2/DNU/NC GPIO8/DNU/NC G16
GPIO8/[3] CCVCC2/[3] CCVCC2/DNU/NC GPIO8/DNU/NC G16
GPIO8/[3] 73251-1150
E13 E13
CCRST2/[3] CCRST2/GND/NC GPIO11 GPIO9/DNU GPIO9 CCRST2/[3] CCRST2/GND/NC GPIO11 GPIO9/DNU GPIO9

SIM2

SIM2
D14 F16 D14 F16 CON1
CCCLK2/[3] CCCLK2/GND/NC GPIO25 GPIO10/DNU GPIO10 CCCLK2/[3] CCCLK2/GND/NC GPIO25 GPIO10/DNU GPIO10
E12 E12 18pF C45 18pF C44
PWR_IND_X100/[3] CCIO2/[3] CCIO2/GND/NC CCIO2/[3] CCIO2/GND/NC ANT_GPS
D12 M13 D12 M13
CCIN2/[3] CCIN2/GND/NC ADC1/DNU ADC1/[3] CCIN2/[3] CCIN2/GND/NC ADC1/DNU ADC1/[3]

L2
22nH
ADC

ADC
M12 M12
ONLY PLS8 ADC2/DNU/NC ADC2 ONLY PLS8 ADC2/DNU/NC ADC2 U.FL-R-SMT(01)
R3
0R

M15 M11 M15 M11

VDDLP VDDLP1 ONLY PLS8 ADC3/DNU ADC3 VDDLP VDDLP1 ONLY PLS8 ADC3/DNU ADC3
N14

CONTROL
N14

CONTROL
EMG_RST1 EMG_RST1

.co
EMG_RST/[3] EMG_RST/[3]
M4 C14 M4 C14
PWR_IND POW ER_IND VMIC/DNU VMIC/[3] PWR_IND POW ER_IND VMIC/DNU VMIC/[3]

4
M5 D15 M5 D15
VEXT/V180 MICP1/DNU VEXT/V180 MICP1/DNU
VEXT_MODULE/[3] MICP1/[3] VEXT_MODULE/[3] MICP1/[3]
4

AUDIO

AUDIO
IGT_MODULE/[3]
L16
IGT MICN1/DNU
D16
MICN1/[3] IGT_MODULE/[3]
L16
IGT MICN1/DNU
D16
MICN1/[3] GND
B14 E15 B14 E15
STATUS/[2] STATUS EPP1/DNU EPP1/[3] STATUS/[2] STATUS EPP1/DNU EPP1/[3]
E16 E16
EPN1/DNU EPN1/[3] EPN1/DNU EPN1/[3]
F15 C15 F15 C15
I2CDAT/[2] I2CDAT/DNU I2C GND/AGND/DNU AGND/[3] I2CDAT/[2] I2CDAT/DNU GND/AGND/DNU AGND/[3]

I2C
I2CCLK/[2]
F14
I2CCLK/DNU
M7 PCM_IN
I2CCLK/[2]
F14
I2CCLK/DNU
M7 PCM_IN
FREE GPIO/PINS PINHEADER
DIN/I2S_DIN RXDAI/[3] DIN/I2S_DIN RXDAI/[3]
A4 M8 PCM_CLK A4 M8 PCM_CLK
PCM

PCM
BATT+_RF/[2] R31 BATT+_W CDMA BCLK/I2S_SCLKIN SCLKDAI/[3] BATT+_WCDMA BATT+_W CDMA BCLK/I2S_SCLKIN SCLKDAI/[3]
0R
B3 ONLY PDS5/PDS6/PDS8 M9 PCM_FSC B3 ONLY PDS5/PDS6/PDS8 M9 PCM_FSC JP4
BATT+_WCDMA BATT+_W CDMA FSC/I2S_W SIN FSDAI/[3] BATT+_W CDMA FSC/I2S_W SIN FSDAI/[3]
N13 M10 PCM_OUT N13 M10 PCM_OUT 1 2
BATT+_BB/[2] BATT+ BB DOUT TXDAI/[3] BATT+_BB/[2] BATT+ BB DOUT TXDAI/[3] GPIO1 GPIO2
P13 P13 3 4
BATT+ BB BATT+ BB SIM_SWITCH GPIO3
N3 ONLY PLS8 N6 CTS1/IO19 N3 ONLY PLS8 N6 CTS1/IO19 5 6
BATT+_RF/[2] BATT+_RF/BATT+_GSM I2S_SCLKOUT/SPI_CS/DNU CTS1/[3] BATT+_RF/[2] BATT+_RF/BATT+_GSM I2S_SCLKOUT/SPI_CS/DNU CTS1/[3] VDDLP GPIO9
N4 N7 RTS1/IO18 N4 N7 RTS1/IO18 7 8
BATT+_RF/BATT+_GSM I2S_W SOUT/SPI_CLK/DNU BATT+_RF/BATT+_GSM I2S_W SOUT/SPI_CLK/DNU
GND

RTS1/[3] RTS1/[3] VGNSS VEXT_MODULE/[3]

I2S

I2S
69x P6 RXD1/IO16 P6 RXD1/IO16 9 10
GND1 MCLK/I2S_MCLKOUT/SPI_MOSI RXD1/[3] MCLK/I2S_MCLKOUT/SPI_MOSI RXD1/[3] V480/[2] GPIO10
A9 P7 TXD1/IO17 P7 TXD1/IO17 11 12
TWIST_DETECT GND2/TW IST_DETECT I2S_DOUT/SPI_MISO/DNU TXD1/[3] I2S_DOUT/SPI_MISO/DNU TXD1/[3] GND/[2] EXTERN_REFERENCE/[2]
_np A7 A7
DNU TP66 DNU DNU DNU
DNU1
C12
DNU1 TXD0
P12
TXD0/[3] DNU1
C12
DNU1 TXD0
P12
TXD0/[3] 2x6_HEAD_SMD
C13 P11 C13 P11
DNU2 DNU2 RXD0 RXD0/[3] DNU2 DNU2 RXD0 RXD0/[3]
D13 N10 D13 N10
_np

LED7

DNU3 DNU3 RTS0 RTS0/[3] DNU3 DNU3 RTS0 RTS0/[3]

POWER

POWER
ASC0

ASC0
E14 N8 E14 N8
DNU4 CTS0 DNU4 CTS0
BATT+_BB/[2] DNU4 CTS0/[3] DNU4 CTS0/[3]
3
3 TX_ACT
F13
DNU5
es DTR0
P8
DTR0/[3] TX_ACT
F13
DNU5 DTR0
P8
DTR0/[3]
JP8
1 2
C35
C36

G4 P9 G4 P9
DNU6 DNU6 DSR0 DSR0/[3] DNU6 DNU6 DSR0 DSR0/[3] ADC2 RTS1/[3] SPI_CLK
G13 N9 G13 N9 3 4
DNU7 DNU7 DCD0 DCD0/[3] DNU7 DNU7 DCD0 DCD0/[3] ADC3 TXD1/[3] SPI_MISO
GND DNU8 5 6
47uF
47uF

H13 P10 H13 P10

DNU8 RING0 RING0/[3] DNU8 DNU8 RING0 RING0/[3] PWR_IND_X100/[3] RXD1/[3] SPI_MOSI
K12 K12 7 8
DNU9 DNU9 DNU9 DNU9 V480/[2] GND/[2]
K13 K13
ANT_SWITCH DNU10 ANT_SWITCH DNU10
SIM_SWITCH
L5
DNU11 SIM_SWITCH
L5
DNU11 2x4_HEAD_SMD
GND DNU12
L7
DNU12 DNU12
L7
DNU12
L8 L8 _np
DNU13 DNU13

GND
BATT+_RF/[2] DNU13 DNU13
L9 GND L9 4 _np
DNU14 DNU14 DNU14 DNU14 GND/[2] TP75
3
C37
C38

L10 L10
DNU15 DNU15 DNU15 DNU15 SIM_SWITCH
L11 L11 2
DNU16 DNU16 DNU16 DNU16 ANT_SWITCH
1
47uF
47uF

L12 L12
LED8

DNU17 DNU17 DNU17 DNU17 TX_ACT

_np

L13 L13
DNU18 DNU18 DNU18 DNU18
DNU19
N12
DNU19 DNU19
N12
DNU19 JP1
E5
INDUSTRIAL_DETECT1 GND3/INDUSTRIAL_DETECT1
GND INDUSTRIAL_DETECT2 J4
GND4/INDUSTRIAL_DETECT2 GND3/TW IST_DETECT2 TWIST_DETECT2
uid
A5
IC11
_np _np _np 1 5
ATMEGA_3V_LDO/[2] VIN VOUT +3V/[3]
2 _np
TP4 TP5 TP6
SIM HOLDER
2

100nF
TP10 IC9A 3

VLMG1300-GS08 220R
R99
R62 EN
25 15 100k CON8
RESET@UC /RST_PCIN14_C6 SCK_PCIN5_B5 TP77
14 2 4

C78
_np
MICROCONTROLLER + ON CIRCUIT + RST

100nF
MISO_PCIN4_B4 GND BP CCCLK CCCLK

10nF
TP78
13 1 2 _np
MOSI_PCIN3_B3 1 2 +3V/[3] CCVCC VSIM TP79
12 3 4 LP2985AIM5-3.0

LED9
_np
SS_OC1B_PCIN2_B2 0R
R5 ON_BUTTON 3 4 CCIO CCIO TP80
11 5 6 GND GND

C76

C77
_np
OC1A_PCIN1_B1 IGT/[3] RESET@UC 5 6 CCRST CCRST
10
ICP1_CLKO_PCIN0_B0 CCGND GND/[2]

10pF_np

10pF_np
5 GND

220nF
XTAL1_TOSC1_PCIN6_B6

GND
+3V/[3]
GNDGND

1nF
CON6 CCDET1
R87
R88
R4

GND _np T17A

NX3008NBKS
CCDET2 R46 CCIN_X100/[3]
5

C10

C12

C13
C11
0R

GND
TP58 LDO_OUT/[2]

4
0475532001
47k
47k
2k7

6
XTAL2_TOSC2_PCIN7_B7
EMERG_RST_X100/[3]

24
DISCHARGE_BATT+/[2]

ADC5_SCL_PCIN13_C5 INDUSTRIAL_DETECT1 PLS8: NOT SUPPORTED

ON_BUTTON

23
ADC4_SDA_PCIN12_C4 INDUSTRIAL_DETECT2 VDDLP
22
+3V/[3]

ADC3_PCIN11_C3 R97 VUSB_MODULE

CDBQR70

D5

21 0R
ADC2_PCIN10_C2 TWIST_DETECT
Datum Name
ADC1_PCIN9_C1
20 TWIST_DETECT2
Vers.: Blatt:
19 Bear. 01.04.2019 DO
ADC0_PCIN8_C0
-g

B1 1
1
VCC VCC
Gepr. 1
47k
R101

16

17 9
3

100nF

AREF AIN1_PCI23_D7 R28 EN_BATT+/[2]

8
KSC701J LFS

KSC701J LFS

AIN0_OC0A_PCI22_D6 0R MOD_ON_DET/[3]
ATMEGA88PA-MMH

ATMEGA88PA-MMH

7 IC9B IC9C
C56

C55

T1_OC0B_PCI21_D5 LED_EN/[2]
BG:
BTN2

BTN1

2
C75

XCK_T0_PCI20_D4 IGT_X100/[3]
1 GND
1u

1u

INT1_OC2B_PCIN19_D3 SIMPU_E_OD
LGA DevKit L
4

18

28 GND GND
INT0_PCIN18_D2 E_VEXT-PD/[2]
27 TP57
TXD_PCIN17_D1 _np R98 +3V/[3]
26 TP61
47k_np
RXD_PCIN16_D0 _np
GND GND GND
ATMEGA88PA-MMH Änderung Datum Nam. Ers. f.: Ers. d.:
A B C D E F G H
all

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Cinterion® LGA DevKit User Guide Page 32 of 36

9.2 LGA DevKit L
35

A B C D E F G H
IC4
LDO BATT+ LS GPS PWR TC1014-3.0VCT713 LDO +3V
BATT+: 2.8V - 4.86V TP68
EXTERN_REFERENCE/[1]
_np
V480 1 5
BATT+ VIN VOUT
3*2 5

ANT_GPS_PWR/[1]
JP3
T14A

1x2_HEAD
_np
IN OUT BATT+
ISL80103 TP81
3

1uF

1uF

2
1
_np
SD
IC10 TP64
2 TP65
LDO_OUT/[3] EN_BATT+/[1] EN/UVLO NX3008PBKS

33pF_np
_np
9*2 1*2 1 6 2 4

C8

C7
IN OUT DVDT FLT ERROR_LED_OD GND BP V480/[1]

2.2uF
15pF
8*2 7
5 X100.BATT+

470pF
GND ILM
2.2uF

7 3 T14B
5

C57
12k7
R17
EN FB

1k3
GND

R57

R104
IC20

330R
C19

C50

C51

R38

R27
R14

47k

47k
6 4 1 5
C17

_np

C9
4*2
SS PB 0R_np VIN VOUT VREF/[3]
Place Jumper between
3

100nF

100nF
V480/[1] 1 & 2 to power GPS
5*2
3

1uF

1uF
T6 EN

3
_np DMP2021UFDF-7
bridge FET control with R14

1*5
TP67
2 4

C21

C20

C14

C18
T5A

1*5
44WR10KLFTB User Option: NX3008NBKS
GND BP
P1
5 GND_DETECT_DSB/[3] R29
T7B
DMP2021UFDF-7

10nF
BC847

4
LP2985AIM5-3.0

DISCHARGE_BATT+/[1]
R75 T16 4k7
3 USB SUPPLY DIODE
RED

VLMS1300-GS08

LED6
5k_np

4*2

C15
D3 PMEG2020EPK,315
Place R75 for fixed VOUT
2k74
R18

if P1 is not placed T7A

_np TP63
R30

T13
TP62 _np BC847
4k7

180R
R63
1*5 4*2

R52
VUSB/[1] VUSB_FTDI

47k

R102
DMP2021UFDF-7
C5
SSSS811101

2k2
560R
R85
T11A

33pF_np

3
BC857

C53 1uF_np

100nF
ATMEGA_3V_LDO/[1]
BC857
BAT

4
A

B
ERROR_LED_OD
4
S3 5V

S3 T11B
D1 PMEG2020EPK,315 If the DevKit is used as DSB Adapter then the LDO is enabled for a fixed 3V referencce.

100k

47k
R25

R22
>A=

>B=

C52
T8A
V480/[1] X100.BATT+/[3] LED_EN/[1] R95 If the DevKit is used standalone then the reference is also sourced from +3V or from extern reference

GND
BC847
PMEG2020EPK,315 D2 4k7
47k
R21 RX & TX LEDs V480/[1] V480/[1]

680R
R13
R11
2k7
USB <-> UART Bridge: FTDI IN RUSH CURRENT PROTECTION
SD_CLK(GPIO5)_X100/[3]

VLMW1300-GS08

VLMB1300-GS08
R54
33R
ON/OFF STATUS

LED1

LED3
V480/[3]

0R
R1
DMP2021UFDF-7
WHITE LIGHT
T10 BLUE
VUSB_FTDI
4*2 1*5 BATT+

T8B T4A

R53

R55
IC1 VEXT_BUFF/[3] R93 STATUS/[1] R16

47k
1M
BC847 BC847

3
4k7 4k7
3

47k

47k
0.1R

0.1R

0.1R

0.1R

0.1R

0.1R

0.1R

0.1R
R47

R48

R40

R41

R42

R43

R44

R45

R94

R91
19 30 L28

3
100nF

V480/[1] VCC TXD BLM15HG601SN1 TXD0_X100/[3]

1 2 L29

6
VREF/[3] VCCIO RXD BLM15HG601SN1 RXD0_X100/[3]
32 L30
T5B
RTS BLM15HG601SN1 RTS0_X100/[3]
NX3008NBKS
GND_MODUL_LED
18 8 L31 2
C23

470uF

470uF

470uF

470uF

470uF

470uF

470uF

470uF
FTDI_RESET/[3] RESET CTS BLM15HG601SN1 CTS0_X100/[3] V480/[1] V480/[1]

1
31 L32

1uF
_np
TP76 DTR BLM15HG601SN1 DTR0_X100/[3]
27 6 L33
P$8*2
P$6*2

R56
OSCI DSR DSR0_X100/[3]

1M
BLM15HG601SN1

C46

C47

C39
C2

C4

C3

C16
C6
28 7

330R

330R
L34

C48

R19

R33
OSCO DCD BLM15HG601SN1 DCD0_X100/[3]
3 L35
RI RING0_X100/[3]
ZX62D-B-5PA8(30)

BLM15HG601SN1
VCC P$1 VUSB_FTDI 680R VLMW1300-GS08
P$2 FTDI.USB.D- 22

VLMG1300-GS08

VLMO1300-GS08
D- CBUS0 R6
P$3 FTDI.USB.D+ 21 LED2 GNDGND GND
D+ CBUS1
P$4 16 10 LED White GND RX TX

LED4

LED5
CON18

ID FTD.3V3 3V3OUT CBUS2

GND P$5 CBUS3
11 TP69
_np
GREEN SOFT
14 9 ORANGE

220k

220k
R86

R20

R60

R34
FTDI.USB.D+ USBDP CBUS4

47k

47k
P$11
P$10

15 VEXT BUFFER
FTDI.USB.D- USBDM
26

C73

C74
100nF

TEST
24 T9A T12A
GND BC847 BC847
4*2

BATT+

1uF

1uF
GND
17
C22

GND
2 GND
20
C30 100nF
RXD0_X100/[3] R32
10k
T9B
BC847 TXD0_X100/[3] R35
10k
T12B
BC847
2
FT232RQ
VCC

5
GND_MODUL_LED
VEXT_JUMPER/[3]
1 IC7
4 R36 VEXT_BUFF/[3]
470k
R37

3 0R

0R_np
R92
TLV6741 T4B

C34

C31
2 VEXT_BUFF/[3] R12

1k
BC847

R39
GND
4k7

47k
R90
1nF

100nF_np
6

T17B
2 NX3008NBKS
E_VEXT-PD/[1]
1

GND

CURRENT MEASUREMENT I2C LEVELSHIFTER Datum Name

R26 Vers.: Blatt:
JP2
0.1R Bear. 01.04.2019 DO
B1 2
1 BATT+
T P72
1
3
2
4
PLACE JUMPER
VEXT_BUFF/[3] VREF/[3] VEXT_BUFF/[3] VREF/[3]
Gepr. 1
4k7_np

4k7_np

PLACE VOLTMETER Remove R80 & R81

5 6
R76

R77

R78

R79

PLACE AMETER for ultra low current

4k7

4k7

7 8 T P71
BATT+_RF/[1] measurements BG:
9 10 T P70
5

2x5_HEAD_SMD
BATT+_BB/[1]
I2CCLK/[1] R80
0R
4
T1A
3 I2C_CLK_LS/[3] I2CDAT/[1] R81
0R
1

T1B
6 I2C_DAT_LS/[3] LGA DevKit L
NX3008NBKS NX3008NBKS
Änderung Datum Nam. Ers. f.: Ers. d.:
A B C D E F G H

t lga_devkit_ug_v03 2020-05-29
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Cinterion® LGA DevKit User Guide Page 33 of 36

9.2 LGA DevKit L
35

A B C D E F G H
LEVEL SHIFTER ASC0.1 PINHEADER 80 PIN INTERFACE
IC14 CON7 Control
1 8 1 2
VREF/[2] VCC-A VCC-B VEXT_BUFF/[2] IGT/[1] IGT_MODULE/[1]
2 7 3 4

100nF

100nF
A1 B1

GND
RXD0_X100/[2] RXD0@LS EMERG_RST_X100/[1] EMG_RST/[1]

GND
3 6 5 6 1 2
CTS0_X100/[2] A2 B2 CTS0@LS VEXT_JUMPER/[2] VEXT_MODULE/[1] GND GND
5 4 7 8 3 4
DIR L
GND
H
CCIN_X100/[1] CCIN/[1] DAC_OUT_X100 DAC_OUT ADC1_IN ADC1_IN_X100
C25 5 6

C24
PW R_IND ADC2_IN

GND
PWR_IND_X100/[1] ADC2_IN_X100
74LVCH2T45GT 7 8
5 GND
1
IC15
8
@LS = LEVELSHIFTER 2x4_HEAD_SMD
CON9
1 2
ASC0.1
TP_ENV_X100
RXD2_GPIO9_X100
9
11
TP_ENV
RXD2_GPIO9
GND
TXD2_GPIO10
10
12
TXD2_GPIO10_X100 5
VCC-A VCC-B RXD0@LS RXD0/[1] SPICS_X100 SPICS SD_W P(GPIO8) SD_WP(GPIO8)_X100
2 7 3 4 13 14
TXD0_X100/[2] A1 B1 TXD0@LS CTS0@LS CTS0/[1] SD_3_X100 SD_3(GPIO4) SPIDI SPIDI_X100
3 6 5 6 15 16
RTS0_X100/[2] A2 B2 RTS0@LS TXD0@LS TXD0/[1] SD_2_X100 SD_2(GPIO3) SD_DET(GPIO7) SD_DET(GPIO7)_X100
5 4 GND 7 8 17 18
DIR L
GND
H
RTS0@LS RTS0/[1] SD_1_X100 SD_1(GPIO2) SD_CMD(GPIO6) SD_CMD(GPIO6)_X100
19 20
74LVCH2T45GT
SD_0_X100 SD_0(GPIO1) SD_CLK(GPIO5) SD_CLK(GPIO5)_X100/[2]
2x4_HEAD_SMD 21 22
I2CDAT_X100 I2CDAT I2CCLK I2CCLK_X100 0R
GND
ASC0.2 GND CON10 ASC0.2 23
USB_DP VUSB_IN
24 R15 V480/[2]
IC2 1 2 25 26
DTR0@LS DTR0/[1] USB_DN USC5 USC5_X100
1 8 3 4 27 28
VREF/[2] VCC-A VCC-B VEXT_BUFF/[2] DCD0@LS DCD0/[1] VSENSE ISENSE
2 7 5 6 29 30
100nF

100nF
DCD0_X100/[2] A1 B1 DCD0@LS DSR0@LS DSR0/[1] VMIC_X100 VMIC USC6 USC6_X100
0R
3 6 7 8 31 32
DSR0_X100/[2] A2 B2 DSR0@LS RING0@LS RING0/[1] EPN2_X100 EPN2 CCCLK R64
0R CCCLK2/[1]
5 4 33 34
DIR L
GND
H
EPP2_X100 EPP2 VSIM R67
0R CCVCC2/[1]
2x4_HEAD_SMD 35 36
C26

C27
EPP1_X100 EPP1 CCIO R68
0R CCIO2/[1]
74LVCH2T45GT CON11 ASC1 EPN1_X100
37
EPN1 CCRST
38 R66
0R CCRST2/[1]
IC16 1 2 39 40
MICN2 CCIN

GND
TXDDAI CTS1@LS CTS1/[1] MICN2_X100 R65 CCIN2/[1]
1 8 3 4 41 42
VCC-A VCC-B RTS1@LS R70 RTS1/[1] MICP2_X100 MICP2 CCGND
2 7 100R 5 6 43 44
RING0_X100/[2] A1 B1 RING0@LS RXD1@LS RXD1/[1] MICP1_X100 MICP1 USC4 USC4_X100
3 6 7 8 45 46
4 USC0_X100
5
A2
DIR L
B2
GND
H
4
USC0@LS
GND
TXD1@LS R69
100R
2x4_HEAD_SMD
TXD1/[1] MICN1_X100
AGND_X100
47
49
MICN1
AGND
USC3
USC2
48
50
USC3_X100
USC2_X100 4
IGT_X100/[1] IGT USC1 USC1_X100
74LVCH2T45GT CON12 GPIO EMERG_RST_X100/[1]
51
EMERG_RST USC0
52 USC0_X100
GND GND GND 1 2 53 54
IC5 DAI SD_3_X100
3 4
GPIO4/[1] DCD0_X100/[2]
55
DCD0 BATTEMP
56
SD_CLK(GPIO5)_X100/[2] GPIO5/[1] CTS1_X100 CTS1 SYNC SYNC_X100
1 8 5 6 57 58
VREF/[2] VCC-A VCC-B VEXT_BUFF/[2] SD_CMD(GPIO6)_X100 GPIO6/[1] CTS0_X100/[2] CTS0 RXD1 RXD1_X100
2 7 7 8 59 60
100nF

100nF
DTR0_X100/[2] A1 B1 DTR0@LS SD_DET(GPIO7)_X100 GPIO7/[1] RTS1_X100 RTS1 RXD0 RXD0_X100/[2]
3 6 9 10 61 62
USC1_X100 A2 B2 USC1@LS SD_WP(GPIO8)_X100 GPIO8/[1] DTR0_X100/[2] DTR0 TXD1 TXD1_X100
5 4 11 12 63 64
RXDDAI DIR L
GND
H
I2CDAT_X100 I2CDAT/[2] RTS0_X100/[2] RTS0 TXD0 TXD0_X100/[2]
13 14 65 66
C29

C28
74LVCH2T45GT
I2CCLK_X100 I2CCLK/[2]
CDBQR70
DSR0_X100/[2] DSR0 VDDLP
15 16 67 68
ADC1_IN_X100 ADC1/[1] D4 RING0_X100/[2] RING0 VCHARGE

BC847
IC17 69 70
VEXT CHARGEGATE

T3A
0R_np
GND 1 8 2x8_HEAD_SMD 71 72
VCC-A VCC-B X100.BATT+/[2] BATT+ GND R2 FTDI_RESET/[2]
2 7 73 74
FS USC2_X100 A1 B1 USC2@LS BATT+ GND 10k
SCLK USC3_X100
3
A2 B2
6 USC3@LS
CON13 DAI VEXT_BUFF/[2]
75
BATT+ GND
76 R83 LDO_OUT/[2]
_np 5 4 1 2 77 78
TP59 DIR L
GND
H
USC3@LS R72 SCLKDAI/[1] BATT+ GND
_np 100R 3 4 79 GND 80
TP60
74LVCH2T45GT
USC2@LS R73 FSDAI/[1] BATT+ GND_DETECT_DSB/[2]
USC1@LS 100R
R71
5 6 RXDAI/[1] If DevKit is used as MOD_ON_DET/[1]
4k7
GND

GND GND 7 8
ASC1 100R U$1 DSB Adapter this pin is low

3
R61

1
IC6
8
USC0@LS

2x4_HEAD_SMD
TXDAI/[1]
T27A1132-80SSG0PBNA01RTC GND 47k
T3B
3
VREF/[2] VCC-A VCC-B VEXT_BUFF/[2] VEXT_BUFF/[2] R89 BC847
2 7
100nF

100nF

RXD1_X100 A1 B1 RXD1@LS
CTS1_X100
3
A2 B2
6 CTS1@LS
CON14 AUDIO2
5 4 1 2
DIR L
GND
H
AGND_X100 AGND/[1]
3 4 GND
C33

C32

MICP1_X100 MICP1/[1]
74LVCH2T45GT 5 6
MICN1_X100 MICN1/[1]
GND IC18
VMIC_X100
7 8 VMIC/[1]
1 8 9 10 FREE LEVELSHIFTER PATCHFIELD EEPROM
VCC-A VCC-B EPN1_X100 EPN1/[1]
2 7 11 12
TXD1_X100 A1 B1 TXD1@LS EPP1_X100 EPP1/[1]
3 6
RTS1_X100 A2 B2 RTS1@LS
5 4 2x6_HEAD_SMD
DIR GND

GND

TP54
L H

GND

_np
C60 100nF C64 100nF
74LVCH2T45GT GND IC3 _np 1 4
TP52 SCL VCC +3V/[1]
GND GND 1 8 _np 3
VEXT_BUFF/[2] VCC-A VCC-B VREF/[2] TP53 SDA
2 7
TP47 A1 B1
FREE LEVELSHIFTER PINHEADER 3 6 5 2 TP55
TP37 A2 B2 TP48 NC VSS _np
S2 5 4
DIR GNDL H

GND

GND
2
GND

GND

C63 100nF C62 100nF 74LVCH2T45GT

V480/[2]
GND
1
IC21
8 _np
2
VEXT_BUFF/[2] VCC-A VCC-B VREF/[2] TP42
GND 2 7 4
1uF
R24

1LS_IN_A1 A1 B1 1LS_OUT_B1
47k

>A= 3 6 GND 3 C67 33pF

A = ENABLE FTDI ONBOARD A2 B2

GND
1LS_IN_A2 1LS_OUT_B2 VMIC/[1] AGND/[1]

GND
5 4 2
C72

C66 100nF C65 100nF

DIR GND L H

>B= IC22 1 C68 33pF

FTDI_RESET/[2] B = ENABLE RS232/LEVELSHIFTER* 74LVCH2T45GT
MICP1/[1]
S2 GND 1 8

R82
VEXT_BUFF/[2] VCC-A VCC-B VREF/[2]

0R
SSSS811101 2 7 JP7
GND A1 B1 MICN1/[1]
C69 33pF
*The equivalent switch on DSB Mini
TP45 3 6
A2 B2
GND
GND

must be set to RS232 C59 100nF C61 100nF TP43 5 4 C70 33pF
DIR GND
L H
EPP1/[1]
IC19
1 8 74LVCH2T45GT GNDTP44 C71 33pF GND
PATCHFIELD TP73 VEXT_BUFF/[2] VCC-A VCC-B VREF/[2] EPN1/[1]
2 7 TP46
TP49 TP51 TP50 TP1 TP3 TP2 2LS_OUT_A1 A1 B1 2LS_IN_B1
3 6
2LS_OUT_A2 A2 B2 2LS_IN_B2
5 4
DIR GND L H

TP84
TP83 TP56
TP82 TP74
VREF/[2] VEXT_BUFF/[2] 74LVCH2T45GT Datum Name Vers.: Blatt:
GND GND Bear. 01.04.2019 DO
TP90 JP6
B1 3
1 TP86
TP100 TP39 TP38 TP41 TP87
TP40 TP36 TP33TP88
TP89
TP30 TP91
TP27 TP24 TP21 TP13 TP9
VEXT_BUFF/[2]
1
3
2
4
VREF/[2]
Gepr. 1
1LS_IN_A2 1LS_OUT_B2
1LS_IN_A1
5 6 1LS_OUT_B1
TP35 TP32 TP29 TP26 TP23 TP20 TP14 TP8 7 8 BG:
2LS_OUT_A2 2LS_IN_B2
9 10

TP85
TP18
GND
TP17 TP16 TP12 TP11
TP34 TP31 TP28 TP25 TP22 TP19 TP15 TP7
2LS_OUT_A1
I2C_CLK_LS/[2]
11 12
2LS_IN_B1
I2C_DAT_LS/[2] LGA DevKit L
2x6_HEAD_SMD
Änderung Datum Nam. Ers. f.: Ers. d.:
A B C D E F G H

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Cinterion® LGA DevKit User Guide Page 34 of 36

9.3 Errata/Troubleshooting
35

9.3 Errata/Troubleshooting
PCB22/23 with DSB-Mini as Expander Board - ON LED
With the LGA DevKit version B22/23 - built in smaller quantities - a current back feeding causes
a constantly glowing WHITE ON LED. There is no impact in functionality.

PCB B22 Module Rotation Detecting Limited

The LGA DevKit's PCB revision B22 - built in a smaller quantity - has a limited rotation detect-
ing. If the DevKit is powered by native USB and the module is inserted upside down, the error
detecting is limited and may allow drawing a limited current (max 20mA) into pad#11/212. The
module may get damaged. This limitation is fixed in B24.

PCB B22 Footprint Detection Limited

The LGA DevKit's PCB revision B22 - built in a smaller quantity - has a limited footprint detec-
tion. Modules with bold lettering "QUALCOMM" (e.g., EXS81) or wrongly positioned RohS sym-
bol (e.g., ELS61/81) on the module's underside, might be detected as a wrong footprint and will
therefore not be powered-up. This limitation has been improved in conjunction with the socket’s
module footprint.

PCB B22 Error LED/ TXD0 LED

The LGA DevKit's PCB revision B22 has a softly glowing error LED. Also, when no module is
inserted the TXD0 LED glows softly. This optical defect is fixed in B24.

PCB B22 Marking

With the LGA DevKit's PCB revision B22 the following markings are swapped:
• DAT and CLK at the GPIO pin headers
• IO13 and VDLP at the FREE GPIOS pin headers

RF Path Matching
The LGA DevKit socket characteristics were improved with regard to module supply path re-
sistance and RF characteristics. There is a smaller quantity built without these improvements.

Socket (old) Socket (new) Improved spring contacts

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Cinterion® LGA DevKit User Guide Page 35 of 36

9.3 Errata/Troubleshooting
35

The old LGA DevKit socket has a decreased RF matching that is improved with the new socket.
The below Figure 20 and Figure 21 shows measurements with the old LGA DevKit socket re-
garding the S11 DevKit's MAIN antenna module RF path as well as the S21 DevKit's MAIN an-
tenna RF path loss. Measurement results for the new LGA DevKit socket are shown above in
Section 4.11.

Figure 20: S11 MAIN antenna input return loss transmit Figure 21: S21 MAIN antenna insertion loss transmit
direction (with old socket) direction (with old socket)

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