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Lab Manual 3 Common Emitter Amplifier

The document outlines an experiment on the Common Emitter Amplifier using LTspice, focusing on drawing input and output characteristics, transient and AC analysis, and comparing theoretical and experimental values. It explains the theory behind transistor operation, including NPN and PNP configurations, biasing circuits, and frequency response. The document also includes circuit diagrams, observation tables, and concludes with viva questions related to BJT applications and biasing stability.

Uploaded by

Rupendra kumar
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
20 views

Lab Manual 3 Common Emitter Amplifier

The document outlines an experiment on the Common Emitter Amplifier using LTspice, focusing on drawing input and output characteristics, transient and AC analysis, and comparing theoretical and experimental values. It explains the theory behind transistor operation, including NPN and PNP configurations, biasing circuits, and frequency response. The document also includes circuit diagrams, observation tables, and concludes with viva questions related to BJT applications and biasing stability.

Uploaded by

Rupendra kumar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Experiment No 3

Common Emitter Amplifier Manual on LTspice

Aim:

Common Emitter

1) To draw the input and output characteristics of transistor connected in CE


configuration
2) Transient analysis of CE amplifier in self-biasing
3) AC analysis of the circuit to find the band width
4) Compare the theoretical and experimental values
5) Plot the DC load line and Q point

Theory: Transistors

• The input and output circuits is the main feature of transistor action because the
transistors amplifying properties come from the consequent control which the
Base exerts upon the Collector to Emitter current.
• Base is the control through which less amount of current flows which is amplified
in collector side that’s why it is called current controlled device.
• The Input impedance is low, and output impedance is high

Region Emitter Base Collector


Doping High Low Moderate
Concentration

NPN Transistor:

• NPN Transistor it is the movement of negative current carriers (electrons) through


the Base region
PNP Transistor:

• All the polarities for a PNP transistor are reversed which means that it “sinks”
current into its Base. The main difference between the two types of transistors is
that holes are the more important carriers for PNP transistors.

BJT Configuration:

Configuration Input Node Output Node Ground


Common Base E C B
Common Emitter B C E
Common Collector B E C
Configuration Amplification Output Current
Factors (𝜶, 𝜷, 𝜸)

𝐼𝑐
𝛼=
Common 𝐼𝐸 𝐼𝐶 = 𝛼𝐼𝐸 + 𝐼𝐶𝐵𝑂
Base 𝐼𝐸 = 𝐼𝐵 + 𝐼𝐶 + 𝐼𝐶𝐵𝑂

𝐼𝑐
𝛽=
Common 𝐼𝐵 𝐼𝐶 = 𝛽𝐼𝐵 + 𝐼𝐶𝐸𝑂
Emitter 𝛽 𝐼𝐶𝐸𝑂 = (1 + 𝛽)𝐼𝐶𝐵𝑂
𝛼=
1+𝛽

𝐼𝐸
𝛾=
Common 𝐼𝐵 𝐼𝐸 = (1 + 𝛽)𝐼𝐵 + (1 + 𝛽)𝐼𝐶𝐵𝑂
Collector 1
𝛾 =1+𝛽 =
1−𝛼

𝐼𝐶𝐵𝑂 Collector to base leakage current

𝐼𝐶𝐸𝑂 Collector to emitter leakage current

𝑰𝑩 = 𝟐% 𝒐𝒇𝑰𝑬 𝜶 range: 0 to 1

𝑰𝑪 = 𝟗𝟖% 𝒐𝒇 𝑰𝑬 𝜷 range: 20 to 500

Self-Biasing Circuit (Voltage Divider Circuit):

𝑅2 𝑅1 𝑅2 𝑉𝑐𝑐 − 𝑉𝐶𝐸 𝑉𝑇 − 𝑉𝐵𝐸


𝑉𝑇 = 𝑉 , 𝑅𝐵 = 𝑅𝑇 = , 𝐼𝑐 = , 𝐼𝐸 =
𝑅2 + 𝑅1 𝑐𝑐 𝑅1 + 𝑅2 𝑅𝐶 + 𝑅𝐸 𝑅𝐸 + 𝑇
𝑅
𝛽+1
Different biasing circuits and DC Load line:

Biasing Circuit design 𝑰𝒄 DC Load line


calculation
• Point A
When 𝐼𝑐 = 0,
Fixed 𝑉𝑐𝑐 − 𝑉𝐶𝐸 𝑉𝐶𝐸𝑚𝑎𝑥 = 𝑉𝐶𝐶
𝐼𝑐 =
Biasing 𝑅𝐶
• Point B
When 𝑉𝐶𝐸 = 0 =>
𝐼𝐶 = 𝑉𝐶𝐶 /𝑅𝐶

• Point A
𝑉𝐶𝐶 − (𝐼𝐶 + 𝐼𝐵 )𝑅𝐶 When 𝐼𝑐 = 0 =>
Collector −𝑉𝐶𝐸 = 0 𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐵 𝑅𝐶
to Base • Point B
Biasing  𝑉𝐶𝐸 = 𝑉𝐶𝐶 − (𝐼𝐶 + When 𝑉𝐶𝐸 = 0
𝐼𝐵 )𝑅𝐶 𝑉 −𝐼 𝑅
 𝐼𝑐 = 𝐶𝐶 𝑅 𝐵 𝐶
𝐶

• Point A
When 𝐼𝑐 = 0,
Voltage 𝑉𝑐𝑐 − 𝑉𝐶𝐸 𝑉𝐶𝐸𝑚𝑎𝑥 = 𝑉𝐶𝐶
𝐼𝑐 =
Divider 𝑅𝐶 + 𝑅𝐸
Biasing (calculated on the • Point B
previous page) When 𝑉𝐶𝐸 = 0 =>
𝑉𝐶𝐶
𝐼𝐶 =
𝑅𝐶 + 𝑅𝐸

We can draw the DC load line


using point A and B calculated
above. We need to find the Q
point such as it is not affected
by saturation region ( 𝐼𝐶 axis) or
by cut-off region (𝑉𝐶𝐸 axis).
Common Emitter Amplifier Working:

i) Biasing Circuit/ Voltage


Divider

The resistances R1, R2, and RE used to


form the voltage biasing and
stabilization circuit. The biasing circuit
needs to establish a proper operating
Q-point otherwise, a part of the
negative half cycle of the signal may be
cut-off in the output.

ii) Input Capacitor (C1)

The capacitor C1 is used to couple the signal to the base terminal of the BJT. If it is not
there, the signal source resistance, Rs will come across R2, and hence, it will change the
bias. C1 allows only the AC signal to flow but isolates the signal source from R2

iii) Emitter Bypass Capacitor (C2)

An Emitter bypass capacitor CE is used parallel with RE to provide a low reactance path
to the amplified AC signal. If it is not used, then the amplified AC signal following through
RE will cause a voltage drop across it, thereby dropping the output voltage.

iv) Coupling Capacitor (C3)

The coupling capacitor C3 couples one stage of amplification to the next stage. This
technique used to isolate the DC bias settings of the two coupled circuits.

CE Amplifier Frequency Response

The voltage gain of a CE amplifier varies with signal frequency. It is because the reactance
of the capacitors in the circuit changes with signal frequency and hence affects the
output voltage. The curve drawn between voltage gain and the signal frequency of an
amplifier is known as frequency response. The figure below shows the frequency
response of a typical CE amplifier.
From the above graph, we observe that the voltage gain drops off at low (< fL) and high (>
fH) frequencies, whereas it is constant over the mid-frequency range (fL to fH).

At Low Frequencies (< fL) The reactance of coupling capacitor C2 is relatively high and
hence a very small part of the signal will pass from the amplifier stage to the load.

Moreover, CE cannot shunt the RE effectively because of its large reactance at low
frequencies. These two factors cause a drop off voltage gain at low frequencies.

At High Frequencies (> fH) The reactance of coupling capacitor C2 is very small and it
behaves as a short circuit. This increases the loading effect of the amplifier stage and
serves to reduce the voltage gain.

Moreover, at high frequencies, the capacitive reactance of base-emitters junction is low


which increases the base current. This frequency reduces the current amplification
factor β. Due to these two reasons, the voltage gain drops off at a high frequency.

At Mid Frequencies (fL to fH) The voltage gain of the amplifier is constant. The effect of
the coupling capacitor C2 in this frequency range is such as maintaining a constant
voltage gain. Thus, as the frequency increases in this range, the reactance of coupling
capacitor (CC) decreases, which tends to increase the gain.

However, at the same time, lower reactance means higher almost cancel each other,
resulting in a uniform fair at mid-frequency.

We can observe the frequency response of any amplifier circuit is the difference in its
performance through changes within the input signal’s frequency because it shows the
frequency bands where the output remains fairly stable. The circuit bandwidth can be
defined as the frequency range either small or big among fH & fL

So, from this, we can decide the voltage gain for any sinusoidal input in a given range of
frequency. The frequency response of a logarithmic presentation is the Bode diagram.
Most of the audio amplifiers have a flat frequency response that ranges from 20 Hz – 20
kHz. For an audio amplifier, the frequency range is known as Bandwidth.

Frequency points like fL & fH are related to the lower corner & the upper corner of the
amplifier which are the gain falls of the circuits at high as well as low frequencies. These
frequency points are also known as decibel points. So the BW can be defined as

BW = fH– fL

The dB (decibel) is 1/10th of a B (bel), is a familiar non-linear unit to measure gain & is
defined like 20log10(A). Here ‘A’ is the decimal gain which is plotted over the y-axis.

The maximum output can be obtained through the zero decibels which communicate
toward a magnitude function of unity otherwise it occurs once Vout = Vin when there is
no reduction at this frequency level, so
VOUT/VIN = 1, so 20log(1) = 0dB

We can notice from the above graph, the output at the two cut-off frequency points will
decrease from 0dB to -3dB & continues to drop at a fixed rate. This reduction within gain
is known commonly as the roll-off section of the frequency response curve. In all basic
filter and amplifier circuits, this roll-off rate can be defined as 20dB/decade, which is
equal to a 6dB/octave rate. So, the order of the circuit is multiplied with these values.

These -3dB cut-off frequency points will describe the frequency where the o/p gain can
be decreased to 70 % of its utmost value. After that, we can properly say that the
frequency point is also the frequency at which the gain of the system has reduced to 0.7
of its utmost value.

Circuit Diagram:

1) Common Emitter DC Characteristics:

Input characteristics 𝐼𝐵 vs 𝑉𝐵𝐸 Output characteristics 𝐼𝐶 vs 𝑉𝐶𝐸

2) CE Transient analysis:
3) CE AC Analysis:

Observation and calculation table:

Parameters Theoretical Value Experimental Value


𝜷 294
𝜶
𝑽𝑻
𝑹𝑻
𝑰𝑩
𝑰𝑪
𝑰𝑬
𝑽𝑪𝑬
𝑨𝑽 = 𝑽𝒐𝒖𝒕 /𝑽𝒊𝒏
Band Width calculation
(𝑩𝑾 = 𝒇𝒉 − 𝒇𝑳 )

Results and conclusion:


1)

Viva Questions:

1) Applications of BJT
2) Which biasing circuit is more stable ?
3) What is saturation region, cut-off region, active region and breakdown region?

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