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Lab Manual

The document provides a step-by-step guide for simulating logic circuits using Quartus-II software, starting from project creation to design and simulation. It includes instructions for designing a logic diagram, inserting gate symbols, connecting wires, and configuring input vectors. Finally, it outlines the process for compiling the design, generating a netlist, and simulating the design to verify the output against expected results.

Uploaded by

Anika Tasnim Islam
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
2 views

Lab Manual

The document provides a step-by-step guide for simulating logic circuits using Quartus-II software, starting from project creation to design and simulation. It includes instructions for designing a logic diagram, inserting gate symbols, connecting wires, and configuring input vectors. Finally, it outlines the process for compiling the design, generating a netlist, and simulating the design to verify the output against expected results.

Uploaded by

Anika Tasnim Islam
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Schematic simulation of Logic Circuits

1. Open the Quartus-II software.


2. Create Project.
Click File →New project Wizard → Next. Change working directory to your own
directory. Write name of the Project. Click Finish.
3. Design Logic Diagram:
Click File→New→Block Diagram/Schematic File→OK. Design Window will appear.

Click Symbol Tool icon for inserting gate symbols. For inserting logic gates of
Figure 1, expand Libraries, then primitive, then logic; and then select or2(two input OR
Gate) as needed. Click OK. The cursor symbol will show the gate symbol. By moving the
cursor position, place the gate symbol in a suitable location of the design window and
insert the symbol by clicking the mouse. Press ESC key to disappear the gate symbol
from the cursor.

Figure:1
For insert input pins(input) and output pin (output), expand Libraries, then primitives, the
pin; and then insert the pins as needed. Double click on the names of the input and output
pins and change there names according to Figure 2.

Figure 2
Connect wires using Orthogonal Node tool icon . Click on Orthogonal node tool icon. Place
the cursor at the start location of the wire and then drag the cursor to the end location of the wire
while pressing the left button of the mouse. Release the mouse button. Then set the pin names by
double clicking on the input pins and output pin. And then save it by pressing Ctrl+S.
The drawn schematic circuit for a 2 input OG gate will look like Figure:3.

Figure: 3
4. Simulate the design:
Determine simulation mode. Click Assignment→Settings. Choose Simulation mode
and change it to Functional. Click OK. Figure 4.

Figure: 4
5. Compile the design. Click Processing→Start Compilation. Compilation message will
appear. Example: Your compilation was successful(5 warnings).

6. Create input vector waveform. Click File → New → Vector Waveform File →
OK(Figure:5). Vector input window will appear.

Figure: 5
Now, Right click on Figure: 6 side on the screen.

Figure: 6
After right click, click insert → insert Node or Bus → Node Finder(Figure: 7).

Figure: 7
Then Select pins(all) then click List.(Figure 8).

Figure: 8

All the node list will appear. Click and all the pins will appear in the right side too. Now
click OK → Ok. Input and output signal lines will appear in the window. (Figure:9)
Figure:9
7. Configure Grid. Click Edit → End Time → 40 ns → OK.
8. Fit the waveform in the window. Right click on the window. Click Zoom → Fit in
window.

Now, Right click on 0 , option window will appear, click value →


clock. Change every us/ps to ns and set period value as 20 ns.
Repeat the same for 1 and set period value as 40 ns.
Now, Save.
The input vector file look like Figure: 10.
Figure: 10

9. Generate Netlist. Click Processing → Generate Functional Simulation Netlist. Netlist


generation message will appear. Example: Functional simulation netlist generation was
successful. Click OK.
10. Simulate Design. Click Processing → Start Simulation → OK.
The simulation output will look like Figure 11. Verify the simulation result with expected output
of the circuit calculated by yourself.
Figure 11 is in the next page.
Figure: 11

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