DEPARTMENT OF ELECTRONICS AND

COMMUNICATIONS ENGINEERING

RECORD NOTEBOOK

VLSI LABORATORY

NAME:
REGISTER NUMBER:
BRANCH:

SEMESTER:

ANNA UNIVERSITY REGIONAL CAMPUS MADURAI,

KEELAKUILKUDI - 625019
 ANNA UNIVERSITY REGIONAL CAMPUS

KEELAKUILKUDI

MADURAI-625019

BONAFIDE CERTIFICATE

It is hereby certified that this is the bonafide record of work done by

____________________________ of Fifth semester, BE Department of
Electronics and Communication Engineering in EC-3552 EC-3561 VLSI
laboratory.

Staff-In-Charge HOD

Submitted for held on _____________ at Anna university regional campus

Madurai.

Register Number:

Internal Examiner External Examiner

 INDEX
S. No Date Experiment Pg. No Marks Signature

1 Simulation of basic logic gates 1

2 Simulation of flip flops 13

Simulation of 8-bit ripple carry

3 21
adder

4 Simulation of multiplier 25

Simulation of Finite state

5 29
machines

Simulation of Universal shift

6 37
register

Simulation of synchronous
7 43
up/down counter

Simulation of asynchronous
8 49
up/down counter

Design and simulation of CMOS

9 51
gates and generation of layouts

Design and simulation of

10 61
inverting amplifier

Design and simulation of

11 65
common source amplifier

Design and simulation of

12 69
common drain amplifier

Design and simulation of five

13 73
transistor differential amplifier
 Exp. No: 01
SIMULATION OF BASIC LOGIC GATES
Date:

AIM:
To write a Verilog program for basic logic gates to synthesize and simulate using Xilinx
software tool.

TOOLS REQUIRED:
Software: 1. Xilinx ISE Design Suite 14.7

THEORY:
1. AND GATE:
An AND gate is a digital logic gate with two or more inputs and one output
that performs logical conjunction. The output of an AND gate is true only
when all of the inputs are true. If one or more of an AND gate's inputs are
false, then the output of the AND gate is false.
2. OR GATE:
An OR gate is a digital logic gate with two or more inputs and one output that
performs logical disjunction. The output of an OR gate is true when one or
more of its inputs are true. If all of an OR gate's inputs are false, then the
output of the OR gate is false
3. NOT GATE:
A NOT gate, often called an inverter, is a nice digital logic gate to start with
because it has only a single input with simple behaviour. A NOT gate
performs logical negation on its input. In other words, if the input is true, then
the output will be false. Similarly, a false input results in a true output
4. NAND GATE:
A NAND gate (sometimes referred to by its extended name, Negated AND
gate) is a digital logic gate with two or more inputs and one output with
behaviour that is the opposite of an AND gate. The output of a NAND gate is
true when one or more, but not all, of its inputs are false. If all of a NAND
gate's inputs are true, then the output of the NAND gate is false.
5. NOR GATE:
A NOR gate (sometimes referred to by its extended name, Negated OR gate) is
a digital logic gate with two or more inputs and one output with behaviour that
is the opposite of an OR gate. The output of a NOR gate is true when all of its
inputs are false. If one or more of a NOR gate's inputs are true, then the output
of the NOR gate is false.

1
Truth Tables:

1. AND Gate:

Equation Symbol Truth Table

A B Y

0 0 0

Y=a&b 0 1 0

1 0 0

1 1 1

2. OR Gate

Equation Symbol Truth Table

A B Y

0 0 0

Y= a|b 0 1 1

1 0 1

1 1 1

3. NOT Gate:

Equation Symbol Truth Table

A Y

Y=~a 0 1

1 0

2
 6. EX-OR GATE (XOR):
An XOR gate (sometimes referred to by its extended name, Exclusive OR
gate) is a digital logic gate with two or more inputs and one output that
performs exclusive disjunction. The output of an XOR gate is true only when
exactly one of its inputs is true. If both of an XOR gate's inputs are false, or if
both of its inputs are true, then the output of the XOR gate is false

PROCEDURE:
1. Click on the Xilinx ISE Design Suite 14.7 or Xilinx Project navigator icon on the
desktop of PC.
2. Write the Verilog code by choosing HDL as top-level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by
double clicking on the synthesis in the process window.
4. Perform the functional simulation using Xilinx ISE simulator.
5. The output can be observed by using ISIM Simulator
PROGRAMS:
DATAFLOW BEHAVIOURAL STRUCTURAL
NOT GATE
module notgate(a,y); module notgate (a,y); module notgate (a,y) ;
input a; input a; input a;
output y; output y; output y;
assign y= ~a; always @(a) not(y,a);
endmodule begin endmodule
y=~a;
end
endmodule
AND GATE
module andgate(a,b,y); module andgate(a,b,y); module andgate(a,b,y);
input a,b; input a,b; input a,b;
output y; output y; output y;
assign y=(a&b); always @(a,b) and(y,a,b);
endmodule begin endmodule
y=a&b;
end
endmodule
OR GATE
module orgate(a,b,y); module orgate(a,b,y); module orgate(a,b,y);
inpput a,b; input a,b; input a,b;
output y; output y; output y;
assign y=(a|b); always @(a,b) or(y,a,b);
endmodule begin endmodule
y=a|b;
end
endmodule

3
4. Nand Gate:

Equation Symbol Truth Table

A B Y

0 0 1

Y=~(a&b) 0 1 1

1 0 1

1 1 0

5. NOR Gate:

Equation Symbol Truth Table

A B Y

0 0 1

Y=~(a|b) 0 1 0

1 0 0

1 1 0

6. XOR Gate:

Equation Symbol Truth Table

A B Y

0 0 0

Y=a^b 0 1 1

1 0 1

1 1 0

4
DATAFLOW BEHAVIOURAL STRUCTURAL
NOR GATE
module norgate(a,b,y); module norgate(a,b,y); module norgate(a,b,y);
inpput a,b; input a,b; input a,b;
output y; output y; output y;
assign y=~(a|b); always @(a,b) nor(y,a,b);
endmodule begin endmodule
y=~(a|b);
end
endmodule
NAND GATE
module nandgate(a,b,y); module nandgate(a,b,y); module nandgate(a,b,y);
input a,b; input a,b; input a,b;
output y; output y; output y;
assign y=~(a&b); always @(a,b) nand(y,a,b);
endmodule begin endmodule
y=~(a&b);
end
endmodule
XOR GATE
module xorgate(a,b,y); module xnorgate(a,b,y); module xnorgate(a,b,y);
input a,b; input a,b; input a,b;
output y; output y; output y;
assign y=(a^b); always @(a,b) xnor(y,a,b);
endmodule begin endmodule
y=~(a^b);
end
endmodule

5
1. AND Gate

2. OR Gate

6
7
3. NOT Gate

4. NAND Gate

8
9
5. NOR Gate

6. XOR Gate

10
RESULT:
Hence, all the logic gates were simulated in Xilinx ISE through HDL

11
12
 Exp. No: 02
SIMULATION OF FLIP-FLOPS
Date:

AIM:
To write a Verilog program for all flip flops to synthesize and simulate using Xilinx software
tool.

TOOLS REQUIRED:
Software: 1. Xilinx ISE Design Suite 14.7

THEORY:
1. D Flip-Flop:
The D (Data) flip-flop is a widely used type of flip-flop. It has a D (data) input and a
clock input and outputs Q and not-Q. On each rising edge of the clock, the output Q
takes the value that was at the D input at the time of the rising edge.
2. JK Flip-Flop:
The JK flip-flop is another common type of flip-flop. The JK flip-flop has two inputs,
traditionally labelled J and K. If the J and K inputs are both high at the clock edge, the
Q output is toggled to its opposite state. If they are both low, the output state remains
the same.
3. SR Flip-Flop:
The SR (Set-Reset) flip-flop is the most fundamental type. It has two inputs, called set
and reset, and two outputs, Q and not-Q. The output Q is true if and only if the input S
has been true after the last time R was true.
4. T Flip-Flop:
The T (Toggle) flip-flop is a single input version of the JK flip-flop. It changes state
(“toggles”) whenever the input is high. If the T input is low, the T flip-flop holds the
previous value.

PROGRAMS:
1. D flipflop
module dff (input wire d, input wire clk, output wire q, output wire nq);
wire d_nand_out, clk_nand_out, q_nand_out, nq_nand_out;
nand(d_nand_out, d, clk);
nand(clk_nand_out, nq, clk);
nand(q, d_nand_out, nq_nand_out);
nand(nq, clk_nand_out, q_nand_out);
endmodule

13
LOGIC DIAGRAM:
1. D-flipflop

2. JK flipflop

3. SR flipflop

4. T flipflop

14
2. JK flipflop
module jkff (input wire j, input wire k, input wire clk, output wire q, output wire nq);
wire j_nand_out, k_nand_out, clk_nand_out, q_nand_out, nq_nand_out;

nand(j_nand_out, j, nq);
nand(k_nand_out, k, q);
nand(clk_nand_out, j_nand_out, k_nand_out);
nand(q, clk_nand_out, nq_nand_out);
nand(nq, clk_nand_out, q_nand_out);
endmodule

3. SR flipflop
module srff (input wire s, input wire r, output wire q, output wire nq);
wire s_nand_out, r_nand_out;
nand(s_nand_out, s, nq);
nand(r_nand_out, r, q);
nand(q, s_nand_out, r_nand_out);
nand(nq, r_nand_out, s_nand_out);
endmodule

4. T flipflop
module tff (input wire t, input wire clk, output wire q, output wire nq);
wire t_nand_out, clk_nand_out, q_nand_out, nq_nand_out;
nand(t_nand_out, t, nq);
nand(clk_nand_out, t, q);
nand(q, t_nand_out, nq_nand_out);
nand(nq, clk_nand_out, q_nand_out);
endmodule

15
1. D-flipflop

2. JK flipflop

16
17
3. SR flipflop

4. T flipflop

18
RESULT:
Hence all flipflops were synthesized and simulated using Xilinx simulator.

19
20
 Exp. No: 03
SIMULATION OF 8 BIT RIPLLE CARRY ADDER
Date:

AIM:
To write a Verilog program for 8-bit ripple carry adder to synthesize and simulate using
Xilinx software tool.

TOOLS REQUIRED:
Software: 1. Xilinx ISE Design Suite 14.7

THEORY:
When you add large numbers carefully together the addition is done digit by digit. In
the illustration, two 8 –digit binary numbers are being added. The top row contains the first
number and the second row the other. Working from the right-hand side, there can be no 'carry'
to add to the sum of the first two digits, so a half adder is sufficient. But for the second and
subsequent pairs of digits, full adders must be use (any carry' is indicated by a f below the
adder). The output will be an 8-bit and if the carry is formed that will be shown in cout output
value.

PROCEDURE:
1. Click on the Xilinx ISE Design Suite 14.7 or Xilinx Project navigator icon on the
desktop of PC.
2. Write the Verilog code by choosing HDL as top-level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by
double clicking on the synthesis in the process window.
4. Perform the functional simulation using Xilinx ISE simulator.
5. The output can be observed by using ISIM Simulator.
PROGRAM:
module half_adder(a,b,sum,carry);
input a,b;
output sum,carry;
xor(sum,a,b);
and(carry,a,b);
endmodule

module full_adder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire w1,w2,w3;
half_adder ha1(a,b,w1,w2);
half_adder ha2(c,w1,sum,w3);

21
LOGIC DESIGN:

TRUTH TABLE:
A B Cin sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

SIMULATION:

22
or(carry,w2,w3);
endmodule

module rippleadder(a, b, cin, sum, cout);

input [7:0] a,b;
input cin;
output [7:0]sum;
output cout;
wire [6:0] c;
full_adder a1(a[0],b[0],cin,sum[0],c[0]);
full_adder a2(a[1],b[1],c[0],sum[1],c[1]);
full_adder a3(a[2],b[2],c[1],sum[2],c[2]);
full_adder a4(a[3],b[3],c[2],sum[3],c[3]);
full_adder a5(a[4],b[4],c[3],sum[4],c[4]);
full_adder a6(a[5],b[5],c[4],sum[5],c[5]);
full_adder a7(a[6],b[6],c[5],sum[6],c[6]);
full_adder a8(a[7],b[7],c[6],sum[7],cout);
endmodule

RESULT:
Hence, 8 bit ripple adder has been implemented in Xilinx simulator and is simulated.

23
24
 EXP.NO: 04
SIMULATION OF MULTIPLIER
DATE:

AIM:
To write a Verilog program for 8-bit multiplier and to synthesize, simulate it using Xilinx
software

TOOLS REQUIRED:
1. Xilinx ISE Design Suite 14.7

THEORY:
Multiplication of two elements in the polynomial basis can be accomplished in the
normal way of multiplication, but there are a number of ways to speed up multiplication,
especially in hardware. In this type the multiplication can done parallel counter and it Is
generated carry. The multiplication is independent of the carry so we can perform N number
of multiplication independent of carry.

PROCEDURE:
1. Click on the Xilinx ISE Design Suite 14.7or Xilinx Project navigator icon on the
desktop of
2. The pc.
3. Write the Verilog code by choosing HDL as top level source module.
4. Check syntax, view RTL schematic and note the device utilization summary by
double
5. Clicking on the synthesis in the process window.
6. Perform the functional simulation using Xilinx ISE simulator.
7. The output can be observed by using ISIM Simulator.

25
1. 8 – bit multiplier

26
PROGRAM:
module 8_bit multiplier (p, x, y):
input [7:0] x, y;
Output [15:0] p;
reg [15:0] a;
integer x ;
always@ (x, y);
begin
a=x;
p=0;
for (i=0;i<8;i+=1)
begin
if (y[i])
p= p+a;
a=a<=<1;
end
end
end module.

RESULT:
Hence a 8 bit multiplier was implemented through Xilinx simulator.

27
28
 Exp. No: 05
SIMULATION OF FINITE STATE MACHINES
Date:

AIM:
To analyse, synthesize and simulate state machines using Xilinx simulation tool

TOOLS REQUIRED:
1. Xilinx ISE Design Suite 14.7

THEORY:
MEALY MODEL:

Analysis describes what a given circuit will do under certain operating conditions.
The behavior of a clocked sequential circuit is determined from the inputs, the outputs, and the
state of its flip-flops. The outputs and the next state are both a function of the inputs and the
present state. The analysis of a sequential circuit consists of obtaining a table or a diagram for
the time sequence of inputs, outputs, and internal states. It is also possible to write Boolean
expressions that describe the behavior of the sequential circuit. These expressions must include
the necessary time sequence, either directly or indirectly. A logic diagram is recognized as a
clocked sequential circuit if it includes flip-flops with clock inputs. The flipflops may be of
any type, and the logic diagram may or may not include combinational logic gates. State
Equations: The behavior of a clocked sequential circuit can be described algebraically by
means of state equations. A state equation (also called a transition equation) specifies the next
state as a function of the present state and inputs. Consider the sequential circuit shown in Fig.
1. It acts as a 0-detector by asserting its output when a 0 is detected in a stream of 1s.

A(t + 1) = A(t)x(t) + B(t)x(t) ; B(t + 1) = A’(t)x(t); y(t) = [A(t) + B(t)]x’(t)

A state equation is an algebraic expression that specifies the condition for a flip-flop state
transition. The left side of the equation, with (t + 1), denotes the next state of the flip-flop one
clock edge later. The right side of the equation is a Boolean expression that specifies the present
state and input conditions that make the next state equal to 1. Since all the variables in the
Boolean expressions are a function of the present state, we can omit the designation ( t ) after
each variable for convenience and can express the state equations in the more compact form

A(t + 1) =Ax + Bx ; B(t + 1) =A’x ; y = Ax’+ Bx’ .

29
LOGIC DIAGRAM:

30
 STATE TABLE:

The time sequence of inputs, outputs, and flip-flop states can be enumerated in a state
table (sometimes called a transition table). The table consists of four sections labeled
present state, input, next state, and output . The present-state section shows the states of
flip-flops A and B at any given time t. The input section gives a value of x for each possible
present state. The next-state section shows the states of the flipflops one clock cycle later,
at time t + 1. The output section gives the value of y at time t for each present state and
input condition. State table for the above Circuit diagram .

MOORE MODEL:
STATE TABLE:
The time sequence of inputs, outputs, and flip-flop states can be enumerated in a
state table (sometimes called a transition table). The table consists of four sections labeled
present state, input, next state, and output . The present-state section shows the states of flip-
flops A and B at any given time t. The input section gives a value of x for each possible present
state. The next-state section shows the states of the flipflops one clock cycle later, at time t +
1. The output section gives the value of y at time t for each present state and input condition

PROGRAM:
MEALY MODEL:
module Mealy_model(y, x, clk, reset);
input x,clk,reset;
output reg y;
reg [1:0] state, next_state;
parameter S0 = 2'b00, S1 = 2'b01,
S2 = 2'b10, S3 = 2'b11;
always @ ( posedge clk) if (reset
== 0) state <= S0;
else state <= next_state; always @
(state, x) case (state)
S0: if (x) next_state = S1; else next_state = S0;
S1: if (x) next_state = S3; else next_state = S0;
S2: if (x) next_state = S2;
else next_state = S0;

31
LOGIC DIAGRAM:

Present State Input Next State Flip- Flop

Inputs
A B x A B JA KA JB KB

0 0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 0 1
0 1 0 1 1 1 1 1 0
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1

1 1 1 1 1 1 0 0 0

32
 S3: if (x) next_state = S2;
else next_state = S0;
endcase
always @ (state, x) case
(state) S0: y = 0;
S1, S2, S3: y = ~x;
endcase
endmodule

MOORE MODEL:
module Moore_Model(y, x, clk, reset);
input x,clk,reset;
output [1:0]y;
reg [1:0] state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11; 0
always @ (posedge clk)
if (reset == 0) state <= S0;
else case (state)
S0: if (x) state <= S0; else state <= S1;
S1: if (x) state <= S2; else state <= S3;
S2: if (x) state <= S2; else state <= S3;
S3: if (x) state <= S3;
else state <= S0;
endcase
assign y=state; endmodule

33
1. Mealy model

2. Moore model

34
RESULT:
Hence, finite state machines were simulated through Xilinx simulator.

35
36
 Exp. No: 06
SIMULATION OF UNIVERSAL SHIFT REGISTER
Date:

AIM:
To synthesise and simulate universal shift register in Xilinx simulator using HDL.

TOOLS REQUIRED:
1. Xilinx ISE Design Suite 14.7

THEORY:
A Unidirectional shift register is a register that can capable of transferring data in only one
direction. Whereas the register that is capable of transferring data in both left and right direction
is called a bidirectional shift register. Now let we have a register which can capable to transfer
data in both the shift-right and shift-left, along with the necessary input and output terminals
for parallel transfer, then it is called a shift register with parallel load or universal shift register.
A shift-right control to enable the shift-right operation and the serial input and output lines
associated with the shift-right.
A shift-left control to enable the shift-left operation and the serial input and output lines
associated with the shift-left.
A parallel-load control to enable a parallel transfer and the n input lines associated with the
parallel transfer.
n parallel output lines.
A clear control to clear the register to 0.
A CLK input for clock pulses to synchronize all operations.
A control state that leaves the information in the register unchanged even though clock
pulses are continuously applied.

PROCEDURE:
1. Click on the Xilinx ISE Design Suite 14.7or Xilinx Project navigator icon on the
desktop of the pc.
2. Write the Verilog code by choosing HDL as top-level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by
double
4. Clicking on the synthesis in the process window.
5. Perform the functional simulation using Xilinx ISE simulator.
6. The output can be observed by using ISIM Simulator.

37
LOGIC DIAGRAM:

TRUTH TABLE:
S0 S1 Register Operation
0 0 No Changes
0 1 Shift Right
1 0 Shift Left
1 1 Parallel load

38
PROGRAMS:
module universal shift(a,s,clk,p);
input [3:0]a;
input [1:0]s;
input clk;
output reg [3:0]p;
initial p<=4'b0110;
always@(posedge clk)
begin
case (s)
2'b00:
begin
p[3]<=p[3];
p[2]<=p[2];
p[1]<=p[1];
p[0]<=p[0];
end
2'b01:
begin
p[3]<=p[0];
p[2]<=p[3];
p[1]<=p[2];
p[0]<=p[1];
end
2'b10:
begin
p[0]<=p[3];
p[1]<=p[0];
p[2]<=p[1];
p[3]<=p[2];
end
2'b11:
begin
p[0]<=a[0];
p[1]<=a[1];
p[2]<=a[2];
p[3]<=a[3];
end
endcase
end
endmodule

39
SIMULATION:

40
RESULT:
Hence, Universal shift register has been synthesized and simulated in Xilinx simulator.

41
42
 Exp. No: 07
SIMULATION OF SYNCHRONOUS UP/DOWN COUNTER
Date:

AIM:
To analyse, synthesize and simulate state machines using Xilinx simulation tool

TOOLS REQUIRED:
1. Xilinx ISE Design Suite 14.7

THEORY:

A Synchronous Up/Down Counter is a type of counter that has the ability to count in both
directions, either up or down, based on a control input. It falls under the category of
synchronous counters, where all the flip-flops are clocked together at the same time. The design
of such a counter is similar to a synchronous counter, but it requires additional combinational
logic for the mode control input. The mode control input, often denoted as ‘M’, decides the
counting direction. When M=0, the counter performs up counting, and when M=1, the counter
performs down counting. The synchronous counter follows a predetermined sequence of states
in response to the common clock signal, advancing one state for each pulse. This type of
counter is used not only for counting but also for phase signal generation, clock division, and
initiation of a process. It is an essential component in any complex digital system design.

PROCEDURE:
1. Click on the Xilinx ISE Design Suite 14.7or Xilinx Project navigator icon on the
desktop of the pc.
2. Write the Verilog code by choosing HDL as top-level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by
double
4. Clicking on the synthesis in the process window.
5. Perform the functional simulation using Xilinx ISE simulator.
6. The output can be observed by using ISIM Simulator.

PROGRAM:
module UpDownCounter(input wire clk, input wire rst, input wire up_down, output reg [3:0] count);
always @(posedge clk or posedge rst) begin
if (rst) begin
Upcount <= 4'b0000;
Downcount<=4’b1111;
end else begin
if (up_down) begin

Upcount <= Upcount + 1;

43
1. Synchronous Up/Down Counter

44
end else begin
Downcount <= Downcount - 1;
end
end
end
endmodule

RESULT:
Hence a synchronous Up Down counter was implemented using HDL and simulated.

45
46
 Exp. No: 08
SIMULATION OF ASYNCHRONOUS UP/DOWN COUNTER
Date:

AIM:
To analyse, synthesize and simulate state machines using Xilinx simulation tool

TOOLS REQUIRED:
1. Xilinx ISE Design Suite 14.7

THEORY:

An asynchronous up/down counter, also known as a ripple counter, is a type of counter where
the output of one flip-flop serves as the clock input for the next flip-flop. This means that the
flip-flops are not clocked simultaneously, which makes the circuit simpler but slower. In an
asynchronous up/down counter, a mode control input (say M) is used to select between up and
down counting. When M = 0, it performs up counting, and when M = 1, it performs down
counting. A combinational circuit is required between each pair of flip-flops to decide whether
to do up or down counting. For example, in a 2-bit asynchronous up counter, two flip-flops are
connected in series, and the output of one flip-flop acts as the clock for the second flip-flop. The
state of the second flip-flop will change only when the output of the first flip-flop is logic 1
and a falling edge occurs. This counter can generate 4 different unique states and is known as
a divide by 4 circuit or mod 4 ripple counter. In a 2-bit asynchronous down counter, the
complemented output state (i.e., Q’) of the previous flip-flop is fed as the clock to the next flip-
flop, and the counter performs down counting. The asynchronous up/down counter is used
more than separate up or down counters because it can perform both up and down counting by
changing the Mode control input.

PROCEDURE:
1. Click on the Xilinx ISE Design Suite 14.7or Xilinx Project navigator icon on the
desktop of the pc.
2. Write the Verilog code by choosing HDL as top-level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by
double
4. Clicking on the synthesis in the process window.
5. Perform the functional simulation using Xilinx ISE simulator.
6. The output can be observed by using ISIM Simulator.

47
1. Asynchronous up/down counter

48
PROGRAM:
module UpDownAsyncCounter(input wire clk, input wire rst, input wire up_down, output reg [3:0]);
always @(posedge clk or posedge rst) begin
if (rst) begin
count <= 4'b0000;
end else begin
if (up_down) begin
count <= count + 1;
end else begin
count <= count - 1;
end
end
end
endmodule

RESULT:
Hence, an asynchronous up down counter has been simulated by synthesising it from HDL.

49
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 Exp. No: 09 DESIGN AND SIMULATION OF CMOS GATES AND
Date: GENERATE LAYOUT

AIM:
To design and simulate CMOS basic gates and generate layout.

TOOLS REQUIRED:
1. Microwind
2. DSCH2

THEORY:
1. NOT GATE:
A NOT gate, often called an inverter, is a nice digital logic gate to start with
because it has only a single input with simple behaviour. A NOT gate
performs logical negation on its input. In other words, if the input is true, then
the output will be false. Similarly, a false input results in a true output
2. NAND GATE:
A NAND gate (sometimes referred to by its extended name, Negated AND
gate) is a digital logic gate with two or more inputs and one output with
behaviour that is the opposite of an AND gate. The output of a NAND gate is
true when one or more, but not all, of its inputs are false. If all of a NAND
gate's inputs are true, then the output of the NAND gate is false.
3. NOR GATE:
A NOR gate (sometimes referred to by its extended name, Negated OR gate) is
a digital logic gate with two or more inputs and one output with behaviour that
is the opposite of an OR gate. The output of a NOR gate is true when all of its
inputs are false. If one or more of a NOR gate's inputs are true, then the output
of the NOR gate is false.

PROCEDURE:
1. Design the CMOS logic of the digital circuit in DSCH3.
2. Save the schematics at a desirable location.
3. Go to files and then select “Make Verilog File.”
4. Open Microwind select “Compile Verilog file” in “Compile” option at the menu bar.
5. Select the Verilog file and select compile.
6. Now simulate with desirable inputs.

51
DSCH3 DIAGRAMS:
1. Not Gate:

2. NAND Gate:

3. NOR Gate:

52
53
LAYOUT DESIGN:
1. NOT Gate:

2. NAND Gate:

54
55
 3. NOR Gate:

SIMULATION:
1. Not Gate:

56
57
2. NAND Gate:

3. NOR Gate:

58
RESULT:
Hence, CMOS implementation of basic gates has been achieved and the layout for each of
them was designed.

59
60
 Exp. No: 10
DESIGN AND SIMULATION OF CMOS INVERTING AMPLIFIER
Date:

AIM:
To design and simulate CMOS inverting amplifier.

TOOLS REQUIRED:
1. Microwind
2. DSCH2

THEORY:

A CMOS inverting amplifier, also viewed as a high gain amplifier, consists of one PMOS
device, M1, and one NMOS device, M2. The CMOS fabrication process is designed such that
the threshold voltage, VTH, of the NMOS and PMOS devices are roughly equal, i.e.,
complementary. Most CMOS amplifiers fit naturally into the transconductance amplifier
category as they have large input resistance and fairly large output resistance. If the load
resistance is high, the CMOS transconductance amplifier is essentially a voltage amplifier.

PROCEDURE:
1. Design the CMOS logic of the digital circuit in DSCH3.
2. Save the schematics at a desirable location.
3. Go to files and then select “Make Verilog File.”
4. Open Microwind select “Compile Verilog file” in “Compile” option at the menu bar.
5. Select the Verilog file and select compile.
6. Now simulate with desirable inputs.

61
CMOS DESIGN:

SIMULATION RESULTS:

62
RESULT:
Hence, CMOS inverting amplifier has been designed and simulated.

63
64
 Exp. No: 11 DESIGN AND SIMULATION OF COMMON SOURCE
Date: AMPLIFIER

AIM:
To design and simulate CMOS inverting amplifier.

TOOLS REQUIRED:
3. Microwind
4. DSCH2

THEORY:

A Common Source Amplifier is a type of amplifier where the source terminal of the Metal
Oxide Field Effect Transistor (MOSFET) serves as the common terminal for the input and
output. The input signal is applied at the gate terminal and the output voltage is amplified and
obtained across the resistor at the load in the drain terminal. The Common Source Amplifier
circuit is most widely used because it can produce high input and output impedance, and its
performance is high. It is also known as a voltage amplifier or a transconductance amplifier.
The circuit diagram of the common source amplifier with N-channel MOSFET along with the
coupling and biasing capability is shown in the source. The design of a common source
amplifier with MOSFET is the same as the Class A amplifier using BJT (Bipolar Junction
transistor). The common source MOSFET amplifier consists of 3 terminals: source, gate, and
drain. The source terminal is where the majority of the carriers required for the device
enters. The drain terminal is where the majority of the carriers in the channel leaves. The gate
terminal controls the conductivity of the channel.

PROCEDURE:
1. Design the CMOS logic of the digital circuit in DSCH3.
2. Save the schematics at a desirable location.
3. Go to files and then select “Make Verilog File.”
4. Open Microwind select “Compile Verilog file” in “Compile” option at the menu bar.
5. Select the Verilog file and select compile.
6. Now simulate with desirable inputs.

65
CMOS DESIGN:

SIMULATION:

66
RESULT:
Hence, common source amplifier has been designed and simulated.

67
68
 Exp. No: 12
DESIGN AND SIMULATION OF COMMON DRAIN AMPLIFIER
Date:

AIM:
To design and simulate CMOS inverting amplifier.

TOOLS REQUIRED:
5. Microwind
6. DSCH2

THEORY:

A MOSFET common drain amplifier, also known as a source follower, uses a MOSFET as the
active device. In this configuration, the drain terminal is at AC ground. The input is applied
between the gate and drain terminals, while the output is measured between the source and
drain terminal. Since the drain terminal is common between the input and output side, it is
known as a Common Drain Amplifier.
The Common Drain Amplifier has the following characteristics:

1. High Input Impedance

2. Low Output Impedance
3. Sub-unity voltage gain

Since the output at the source terminal is following the input signal, it is also known as a Source
Follower. Because of its low output impedance, it is used as a buffer for driving the low output
impedance load. Often in multistage amplifiers, while driving low impedance load, the source
follower is used as an output stage.

PROCEDURE:
1. Design the CMOS logic of the digital circuit in DSCH3.
2. Save the schematics at a desirable location.
3. Go to files and then select “Make Verilog File.”
4. Open Microwind select “Compile Verilog file” in “Compile” option at the menu bar.
5. Select the Verilog file and select compile.
6. Now simulate with desirable inputs.

69
CMOS DESIGN:

SIMULATION:

70
RESULT:
Hence, common drain amplifier has been designed and simulated.

71
72
 Exp. No: 13 DESIGN AND SIMULATION OF 5 – TRANSISTOR
Date: DIFFERENTIAL AMPLIFIER

AIM:
To design and simulate 5-transistor differential amplifier.

TOOLS REQUIRED:
7. Microwind
8. DSCH2

THEORY:

A differential amplifier is a type of electronic amplifier that amplifies the difference between
two input voltages but suppresses any voltage common to the two inputs. It is an analog circuit
with two inputs and one output in which the output is ideally proportional to the difference
between the two inputs. Differential amplifiers are found in many circuits that utilize series
negative feedback (op-amp subtractor, active loads, etc.), where one of the inputs is applied to
the inverting input terminal and the other to the non-inverting input terminal. If you’re referring
to a specific 5-transistor differential amplifier circuit, I would need more details. There are
many ways to construct a differential amplifier using five transistors, and the exact
configuration can vary depending on the specific requirements of the circuit. For example,
additional transistors might be used for current mirrors, active loads, or push-pull output stages.

PROCEDURE:
1. Design the CMOS logic of the digital circuit in DSCH3.
2. Save the schematics at a desirable location.
3. Go to files and then select “Make Verilog File.”
4. Open Microwind select “Compile Verilog file” in “Compile” option at the menu bar.
5. Select the Verilog file and select compile.
6. Now simulate with desirable inputs.

73
CMOS DESIGN:

SIMULATION:

74
RESULT:
Hence, 5 transistor differential amplifier has been implemented and simulated.

75