UNIT-6

Basic Processing Unit

Basic Fundamental concepts – Register Transfer – Arithmetic and logical operation –

Fetching a word from memory - Execution of a complete instruction -Hardwired control -
Micro programmed control : micro instructions, microprogram sequencing , Wide Branching,
microprogram with next address field

Part A Q&A

1. What are the basic operations performed by the

processor?
The primary function of a processor unit is to execute sequence of instructions stored in a
memory, which is external to the processor unit.

2. Explain MDR and MAR.

The data and address lines of the external memory bus connected
to the internal processor bus via the memory data register, MDR,
and the memory address register, MAR, respectively. Register MDR
has two inputs and two outputs. Data may be loaded into MDR
either from the memory bus or from the internal processor bus. The
data stored in MDR may be placed on either bus. The input of MAR
is connected to the internal bus, and its output is connected to the
external bus.

3. Name two special purpose registers.

Index register
Stack pointer

4. Define data path.

The registers, the ALU, and the interconnecting bus are collectively
referred to as the data path.

5. Describe the two control signals used for register transfer.

For each register, two control signals are used to place the contents
of that register on the bus or to load data on the bus into the
register. The input and output of register Ri are connected to the
bus via switches controlled by the signals Ri in and Riout, respectively.
When Riin is set to 1, the data on the bus are loaded into Ri.
Similarly, when Riout is set to 1, the contents of register Ri are placed
on the bus. While Riout is equal to 0, the bus can be used for
transferring data from other registers.

6. Define processor clock.

Processor clock is defined as the time periods in which all operations
and data transfers with in the processor take place.
7. What is known as multiphase clocking.
When edge-triggered flip flops are not used, two or more clock
signals may be needed to guarantee proper transfer of data. This is
known as multiphase clocking.

8. Define MFC.
To accommodate the variability in response time, the processor
waits until it receives an indication that the requested read
operation has been completed. The control signal used for this
purpose is known as Memory-Function-Completed (MFC).
9. What is WMFC.
WMFC is the control signal that causes the processor’s control
circuitry to wait for the arrival of the MFC signal.

10. What is mean by branch instruction.

A branch instruction is an instruction which replaces the contents
of the PC with the branch target address. This address is usually
obtained by adding an offset X, which is given in the branch
instruction, to the updated value of the PC. The location following a
branch instruction is called a branch delay slot.

11. Define register file.

All general purpose registers are combined into a single block called
the register file.

12. What are the two approaches used for generating the
control signals in proper sequence?
Hardwired control
Microprogrammed control

13. What are the factors determine the control signals?

1.Contents of the control step counter
2.Contents of the instruction register
3.Contents of the condition code flags
4.External input signals, such as MFC and interrupt requests

14. Explain hardwired control.

The control hardwire can be viewed as a state machine that
changes from one state to another in every clock cycle, depending
on the contents of the instruction register, the condition codes, and
the external inputs. The outputs of the state machine are the control
signals. The sequence of operations carried out by this machine is
determined by the wiring of the logic elements, hence the name
“hardwired”.

15. What are the features of the hardwired control.

 A controller that uses this approach can operate at high speed. It
has little flexibility and the complexity of the instruction set it can
implement is limited.

16. What is microprogrammed control?

Microprogrammed control is a scheme in which control signals are
generated by a program similar to machine language programs.

17. What is control word?

A control word is a word whose individual bits represent the various
control signals.

18. Define microroutine and microinstruction.

A sequence of control words corresponding to the control sequence
of a machine instruction constitutes the microroutine for that
instruction, and the individual control words in this microroutine are
referred to as microinstructions.

19. What is control store?

The microroutines for all instructions in the instruction set of a
computer are stored in a special memory called the control store.

20. What is the drawback of assigning one bit position to

each control signal?
Assigning individual bits to each control signal results in long
microinstructions because the number of required signals is usually
large. Moreover, only a few bits are set to 1in any given
microinstruction, which means the available bit space is poorly
used.

21. Name some register output control signals.

Pcout, MDRout, Zout, Offsetout, R0out, R1out, R2out, R3out, and TEMPout
22. What is vertical organization and horizontal
organization?
Highly encoded schemes that use compact codes to specify only a
small number of control functions in each microinstruction are
referred to as a vertical organization. On the other hand, the
minimally encoded scheme in which many resources can be
controlled with a single microinstruction is called a horizontal
organization.

23. Compare vertical organization and horizontal organization.

Vertical organization Horizontal organization

Highly encoded schemes Minimally encoded schemes

Specify only a small number of Many resources can be

control signals. controlled.
 Operating speed is high. Operating speed is low.

Ability to express a high degree of Limited ability to express parallel

parallelism microoperations

24. Explain bit-O-Ring technique.

The micro program shows that branches are not always made to a
single branch address. This is a direct consequence of combining
simple micro routines by sharing common parts. Consider an
example in the microprogram sequencing. At this point, it is
necessary to chose between actions required by direct and indirect
addressing modes. If the indirect mode is specified in the
instruction, then the microinstruction in the location 170 is
performed to fetch the operand from the memory. If the direct mode
is specified, this fetch must be bypassed by branching immediately
to location 171. The most efficient way to bypass microinstruction
170 is to have the preceding branch microinstructions specify the
address 170 and then use an OR gate to change the least significant
bit of this address to 1if the direct addressing mode is involved.
This is known as the bit-Oring technique for modifying branch
addresses.

25. What is the drawback of microprogrammed control?

It leads to a slower operating speed because of the time it takes to
fetch microinstructions from the control store.

26. . What are the differences between hardwired and

micro programmed control units?
Part B Q & A
1. With the neat sketch explain the processor organization
Some fundamental concepts
The primary function of a processor unit is to execute sequence of instructions stored in a
memory, which is external to the processor unit.
The sequence of operations involved in processing an instruction constitutes an
instruction cycle,which can be subdivided into 3 major phases:

1. Fetch cycle
2. Decode cycle
3. Execute cycle

To perform fetch, decode and execute cycles the processor unit has to perform set of operations
called micro-operations.
Single bus organization of processor unit shows how the building blocks of processor unit are
organised and how they are interconnected.
They can be organised in a variety of ways, in which the arithmetic and logic unit and all
processor registers are connected through a single common bus.
It also shows the external memory bus connected to memory address(MAR) and data
register(MDR).
Singl

The registers Y,Z and Temp are used only by the processor unit for temporary storage during the
execution of some instructions.
These registers are never used for storing data generated by one instruction for later use by
another instruction.
The programmer cannot access these registers.
The IR and the instruction decoder are integral parts of the control circuitry in the processing
unit.
All other registers and the ALU are used for storing and manipulating data.
The data registers, ALU and the interconnecting bus is referred to as data path.
Register R0 through R(n-1) are the processor registers.
The number and use of these register vary considerably from processor to processor.
These registers include general purpose registers and special purpose registers such as stack
pointer, index registers and pointers.
These are 2 options provided for A input of the ALU.
The multiplexer(MUX) is used to select one of the two inputs.
It selects either output of Y register or a constant number as an A input for the ALU according
to the status of the select input.
It selects output of Y when select input is 1 (select Y) and it selects a constant number when
select input is 0(select C) as an input A for the multiplier.
The constant number is used to increment the contents of program counter.
For the execution of various instructions processor has to perform one or more of the
following basic operations:

a) Transfer a word of data from one processor register to the another or to the ALU.
b) perform the arithmetic or logic operations on the data from the processor registers and store the
result in a processor register.
c) Fetch a word of data from specified memory location and load them into a processor register.
d) Store a word of data from a processor register into a specified memory location.

2. Describe the control signals used in fetching a word from

memory and storing a word in memory.

To fetch a word of data from memory the processor gives the address of the memory location
where the data is stored on the address bus and activates the Read operation.
The processor loads the required address in MAR, whose output is connected to the
address lines of the memory bus.
At the same time processor sends the Read signal of memory control bus to indicate the
Read operation.
When the requested data is received from the memory its stored into the MDR, from
where it can be transferred to other processor registers.
Storing a word in memory
To write a word in memory location processor has to load the address of the desired memory
location in the MAR, load the data to be written in memory, in MDR and activate write operation.
Assume that we have to execute instruction Move(R2), R1.
This instruction copies the contents of register R1 into the memory whose location is specified
by the contents of register R2.
The actions needed to execute this instruction are as follows:
a) MAR [R2]
b) MDR [R1]
c) Activate the control signal to perform the write operation.

The various control signals which are necessary to activate to perform given actions in each step.
a) R2out, MARin
b) R1out, MDRinP
c) MARout, MDRoutM,Write

 The MDR register has 4 control signals:

MDRinP & MDRoutP control the connection to the internal processor data bus and signals MDRinM
& MDRoutM control the connection to the memory Data bus.
 MAR register has 2 control signals.

Signal MARin controls the connection to the internal processor address bus and signal MARout
controls the connection to the memory address bus.
 Control signals read and write from the processor controls the operation Read and Write
respectively.

 The address of the memory word to be read word from that location to the register R3,.
 It can be indicated by instruction MOVE R3,(R2).

The actions needed to execute this instruction are as follows:

a) MAR [R2]
b) Activate the control signal to perform the Read operation
c) Load MDR from the memory bus
d) R3 [MDR]

Various control signals which are necessary to activate to perform given actions in each step:
a) R2out, MARin
b) MARout, MDRinM, Read
c) MDRoutP,R3in

3. Explain the complete instruction execution.

Let us find the complete control sequence for execution of the instruction Add R 1,(R2) for
the single bus processor.
o This instruction adds the contents of register R 1 and the contents of memory location
specified by register R2 and stores results in the register R1.
o To execute bus instruction it is necessary to perform following actions:
1. Fetch the instruction
2. Fetch the operand from memory location pointed by R2.
3. Perform the addition
4. Store the results in R1.

The sequence of control steps required to perform these operations for the single bus
architecture are as follows;
1.PCout, MARin Yin, select C, Add, Zin
2. Zout, PCin, MARout , MARinM, Read
3. MDRout P,MARin
4. R2out , MARin
5. R2out , Yin,MARout , MARinM, Read
6. MDRout P, select Y, Add, Zin
7. Zout, R1in
(i) Step1, the instruction fetch operation is initiated by loading the controls of the PC into
the MAR.
PC contents are also loaded into register Y and added constant number by activating
select C input of multiplexer and add input of the ALU.
By activating Zin signal result is stored in the register Z

(ii) Step2 , the contents of register Z are transferred to pc register by activating Z out and
pcin signal.
This completes the PC increment operation and PC will now point to next instruction,
In the same step (step2), MARout , MDR inM and Read signals are activated.
Due to MARout signal , memory gets the address and after receiving read signal and
activation of MDR in M Signal ,it loads the contents of specified location into MDR
register.

(iii) Step 3 contents of MDR register are transferred to the instruction register(IR) of the
processor.
The step 1 through 3 constitute the instruction fetch phase.
At the beginning of step 4, the instruction decoder interprets the contents of the IR.
This enables the control circuitry to activate the control signals for steps 4 through 7,
which constitute the execution phase.

(iv) Step 4, the contents of register R 2 are transferred to register MAR by activating R 2out
and MAR in signals.

EXECUTION OF A COMPLETE INSTRUCTION

Let us find the complete control sequence for execution of the instruction Add R 1,(R2) for
the single bus processor.
o This instruction adds the contents of register R 1 and the contents of memory location
specified by register R2 and stores results in the register R1.
o To execute bus instruction it is necessary to perform following actions:
1. Fetch the instruction
2. Fetch the operand from memory location pointed by R2.
3. Perform the addition
4. Store the results in R1.

The sequence of control steps required to perform these operations for the single bus
architecture are as follows;
1.PCout, MARin Yin, select C, Add, Zin
2. Zout, PCin, MARout , MARinM, Read
3. MDRout P,MARin
4. R2out , MARin
5. R2out , Yin,MARout , MARinM, Read
6. MDRout P, select Y, Add, Zin
7. Zout, R1in
(i) Step1, the instruction fetch operation is initiated by loading the controls of the PC into
the MAR.
PC contents are also loaded into register Y and added constant number by activating
select C input of multiplexer and add input of the ALU.
By activating Zin signal result is stored in the register Z

(ii) Step2 , the contents of register Z are transferred to pc register by activating Z out and
pcin signal.
This completes the PC increment operation and PC will now point to next instruction,
In the same step (step2), MARout , MDR inM and Read signals are activated.
Due to MARout signal , memory gets the address and after receiving read signal and
activation of MDR in M Signal ,it loads the contents of specified location into MDR
register.

(iii) Step 3 contents of MDR register are transferred to the instruction register(IR) of the
processor.
The step 1 through 3 constitute the instruction fetch phase.
At the beginning of step 4, the instruction decoder interprets the contents of the IR.
This enables the control circuitry to activate the control signals for steps 4 through 7,
which constitute the execution phase.

(iv) Step 4, the contents of register R2 are transferred to register MAR by activating R 2out
and MAR in signals.

(v) Step 5, the contents of register R 1 are transferred to register Y by activating R 1out and
Yin signals. In the same step, MARout, MDRinM and Read signals are activated.
Due to MARout signal, memory gets the address and after receiving read signal and
activation of MDRinM signal it loads the contents of specified location into MDR register.

(vi) Step 6 MDRoutP, select Y, Add and Z in signals are activated to perform addition of
contents of register Y and the contents of MDR. The result is stored in the register Z.
(vii) Step 7, the contents of register Z are transferred to register R 1 by activating Zout and
R1in signals.
Branch Instruction
The branch instruction loads the branch target address in PC so that PC will fetch the next
instruction from the branch target address.
The branch target address is usually obtained by adding the offset in the contents of PC.
The offset is specified within the instruction.
The control sequence for unconditional branch instruction is as follows:
 1. PCout, MARin, Yin, SelectC, Add, Zin
2. Zout, PCin, MARout, MDRinM, Read
3. MDRoutP,IRin
4. PCout,Yin
5. Offset_field_Of_IRout,SelectY,Add,Zin
6. Zout,PCin
First 3 steps are same as in the previous example.
Step 4: The contents of PC are transferred to register Y by activating PC out and Yin
signals.
Step 5: The contents of PC and the offset field of IR register are added and result is saved
in register Z by activating corresponding signals.
Step 6: The contents of register Z are transferred to PC by activating Z out and PC in signals

4. Draw and explain typical hardware control unit.

The control units use fixed logic circuits to interpret instructions and generate control signals
from them.
The fixed logic circuit block includes combinational circuit that generates the required
control outputs for decoding and encoding functions.
 Instruction decoder
It decodes the instruction loaded in the IR.
If IR is an 8 bit register then instruction decoder generates 28(256 lines); one for each
instruction.
According to code in the IR, only one line amongst all output lines of decoder goes
high (set to 1 and all other lines are set to 0).
Step decoder
It provides a separate signal line for each step, or time slot, in a control sequence.
Encoder
It gets in the input from instruction decoder, step decoder, external inputs and
condition codes.
It uses all these inputs to generate the individual control signals.
After execution of each instruction end signal is generated this resets control step
counter and make it ready for generation of control step for next instruction.
The encoder circuit implements the following logic function to generate Yin
Yin = T1 + T5 . Add + T . BRANCH+…
The Yin signal is asserted during time interval T1 for all instructions, during T5 for an
ADD instruction, during T4 for an unconditional branch instruction, and so on.
As another example, the logic function to generate Zout signal can given by
Zout = T2 + T7 . ADD + T6 . BRANCH +….
The Zout signal is asserted during time interval T2 of all instructions, during T7 for an
ADD instruction, during T6 for an unconditional branch instruction, and so on.

5. Draw and explain about micro program control unit.

Every instruction in a processor is implemented by a sequence of one or more sets of
concurrent micro operations.
Each micro operation is associated with a specific set of control lines which, when
activated, causes that micro operation to take place.
Since the number of instructions and control lines is often in the hundreds, the complexity
of hardwired control unit is very high.
Thus, it is costly and difficult to design. The hardwired control unit is relatively inflexible
because it is difficult to change the design, if one wishes to correct design error or modify
the instruction set.
Microprogramming is a method of control unit design in which the control signal memory
CM.
The control signals to be activated at any time are specified by a microinstruction, which
is fetched from CM.
A sequence of one or more micro operations designed to control specific operation, such
as addition, multiplication is called a micro program.

The micro programs for all instructions are stored in the control memory.
The address where these microinstructions are stored in CM is generated by microprogram
sequencer/microprogram controller.
The microprogram sequencer generates the address for microinstruction according to the
instruction stored in the IR.
The microprogrammed control unit,
- control memory
- control address register
- micro instruction register
- microprogram sequencer

The components of control unit work together as follows:

The control address register holds the address of the next microinstruction to be read.
When address is available in control address register, the sequencer issues READ command to
the control memory.
After issue of READ command, the word from the addressed location is read into the
microinstruction register.
Now the content of the micro instruction register generates control signals and next address
information for the sequencer.
The sequencer loads a new address into the control address register based on the next address
information.

Advantages of Microprogrammed control

It simplifies the design of control unit. Thus it is both, cheaper and less error phrone
implement.
Control functions are implemented in software rather than hardware.
The design process is orderly and systematic
More flexible, can be changed to accommodate new system specifications or to correct the
design errors quickly and cheaply.
Complex function such as floating point arithmetic can be realized efficiently.

Disadvantages
A microprogrammed control unit is somewhat slower than the hardwired control unit, because
time is required to access the microinstructions from CM.
The flexibility is achieved at some extra hardware cost due to the control memory and its
access circuitry.

6. Write short notes on micro instruction

A simple way to structure microinstructions is to assign one bit position to each control
signal required in the CPU.
Grouping of control signals
Grouping technique is used to reduce the number of bits in the microinstruction.
Gating signals: IN and OUT signals
Control signals: Read,Write, clear A, Set carry in, continue operation, end, etc.
ALU signals: Add, Sub,etc;
There are 46 signals and hence each microinstruction will have 46 bits.
It is not at all necessary to use all 46 bits for every microinstruction because by using
grouping of control signals we minimize number of bits for microinstruction.

Way to reduce number of bits microinstruction:

Most signals are not needed simultaneously.
Many signals are mutually exclusive

e.g. only one function of ALU can be activated at a time.

A source for data transfers must be unique which means that it should not be possible to get the
contents of two different registers on to the bus at the same time.
Read and Write signals to the memory cannot be activated simultaneously.
 7. Describe the Microprogram Sequencing with the neat flow
chart diagram.

Microprogram sequencing
The task of microprogram sequencing is done by microprogram sequencer.
2 important factors must be considered while designing the microprogram sequencer:
a) The size of the microinstruction
b) The address generation time.

The size of the microinstruction should be minimum so that the size of control memory required
to store microinstructions is also less.
This reduces the cost of control memory.
With less address generation time, microinstruction can be executed in less time resulting better
throughout.
During execution of a microprogram the address of the next microinstruction to be executed has 3
sources:
i. Determined by instruction register
ii. Next sequential address
iii. Branch

Microinstructions can be shared using microinstruction branching.

Consider instruction ADD src, Rdst.
The instruction adds the source operand to the contents of register Rdst and places the sum in
Rdst, the destination register.

Let us assume that the source operand can be specified in the following addressing modes:
a) Indexed
b) Autoincrement
c) Autodecrement
d) Register indirect
e) Register direct

Each box in the flowchart corresponds to a microinstruction that controls the transfers and
operations indicated within the box.
The microinstruction is located at the address indicated by the number above the upper right-hand
corner of the box.
During the execution of the microinstruction, the branching takes place at point A.
The branching address is determined by the addressing mode used in the instruction.
Techniques for modification or generation of branch addresses
i. Bit-ORing
The branch address is determined by ORing particular bit or bits with the current address of
microinstruction.
Eg: If the current address is 170 and branch address is 172 then the branch address can be
generated by ORing 02(bit 1), with the current address.
i. Using condition variables

It is used to modify the contents CM address register directly, thus eliminating whole or in part
the need for branch addresses in μμμμμμmicroinstructions.
Eg: Let the condition variable CY indicate occurance of CY = 1, and no carry when CY = 0.
Suppose that we want to execute a SKIP_ON_CARRY microinstruction.
It can be done by logically connecting CY to the count enable input of μpc at on appropriate point
in the microinstruction cycle.
It allows the overflow condition increment μpc an extra time, thus performing the desired skip
operation.
8. Explain the Microinstructions with Next-Address
Field.
 The microprogram we discussed requires several
branch microinstructions, which perform no useful
operation in the datapath.
 A powerful alternative approach is to include an
address field as a part of every microinstruction to
indicate the location of the next microinstruction to
be fetched.
 Pros: separate branch microinstructions are virtually
eliminated; few limitations in assigning addresses to
microinstructions.
 Cons: additional bits for the address field (around
1/6)
IR

External Condition
Inputs codes

Decoding circuits

AR

Control store

Next address I R

Microinstruction decoder

Control signals

Figure 7.22. Microinstruction-sequencing organization.


 Microinstruction

F0 F1 F2 F3

F0 (8 bits) F1 (3 bits) F2 (3 bits) F3 (3 bits)

Address of next 000: No transfer 000: No transfer 000: No transfer

microinstruction 001: PCout 001: PCin 001: MARin
010: MDRout 010: IRin 010: MDRin
011: Zout 011: Zin 011: TEMPin
100: Rsrcout 100: Rsrcin 100: Yin
101: Rdstout 101: Rdstin
110: TEMP out

F4 F5 F6 F7

F4 (4 bits) F5 (2 bits) F6 (1 bit) F7 (1 bit)

0000: Add 00: No action 0: SelectY 0: No action

0001: Sub 01: Read 1: Select4 1: WMFC
10: Write
1111: XOR

F8 F9 F10

F8 (1 bit) F9 (1 bit) F10 (1 bit)

0: NextAdrs 0: No action 0: No action

1: InstDec 1: ORmode 1: ORindsrc

Figure 7.23. Format for microinstructions in the example of Section 7.5.3.

