ISSN (Online) 2321 – 2004

ISSN (Print) 2321 – 5526

INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN ELECTRICAL, ELECTRONICS, INSTRUMENTATION AND CONTROL ENGINEERING
Vol. 1, Issue 5, August 2013

VLSI Implementation of Pipelined FIR Filter

Aarti Sharma1, Sanjay Kumar2
Department of ECE, Thapar University, Patiala, Punjab, India 1
Department of ECE, Thapar University, Patiala, Punjab, India2

Abstract: This paper proposes to optimize the system speed with minimal cost and hardware by making use of pipelining
approach in the designing of FIR filter. The non- pipelined and pipelined FIR filter has been designed using Hardware
Description Language (HDL) and a comparative study of both the filter designs using Radix-4 & Radix-8 has been done.
The design synthesis and power analysis are carried out using Xilinx ISE 13.1and Synopsis tool, respectively. The concept
of pipelining has been incorporated that results in reducing the delay of the FIR filter, thereby enhancing the speed and
reducing the power dissipation as compared to the non-pipelined techniques. Simulation validates the results.

Keywords: FIR filter, Booth multiplier, Pipelining, Non-pipelining, Kaiser Window.

I. INTRODUCTION
In signal processing, the filter is used to remove some describes the technique used to optimize the FIR filters.
unwanted component or feature from a signal thereby Synthesis results and simulation results are presented in
improving the quality of signal. It alters the amplitude and/ section VI and section VII respectively. Concluding remarks
or phase characteristics of a signal in a desired manner with are given in the final section.
respect to frequency. The primary function of filter are – to
confine a signal into a prescribed frequency band, to II. FINITE IMPULSE RESPONSE FILTER
decompose a signal into two or more sub-bands, to modify Finite impulse response (FIR) filters are a class of digital
the frequency spectrum of a signal and to model the input- filters that have a finite impulse response and are among one
output relationship of a system. Filters are extensively used of the primary types of filter used in DSP and
in signal processing and communication system in communication system [3]. They do not have any feedback
applications like noise reduction, echo cancellation, image and therefore if excited by impulse response, the ouput will
enchancement, speech and waveform synthesis etc. invariably become zero. The input- output relationship of
There are two main kind of filter: analog and digital filter. FIR filter is given by (1)
Analog filter has analog signal at both its input & output and
𝑁−1
are made up from components such as resistors, capacitors 𝑦 𝑛 = 𝑘=0 𝑝(𝑘) 𝑥(𝑛 − 𝑘) (1)
and op amps to produce the required filtering effect. Such
filters are fast and simple to realize but are little stable, where, p(k), k = 0,1,2,3……N-1 are the impulse response
sensitive to temperature variations and expensive to realize coefficients of the filter. N is the filter length that is number
in large amounts. Digital filter on the other hand uses digital of coefficients.
processor to perform numerical calculations on sampled
values of the signal and eliminate the problems associated III. BOOTH MULTIPLIER
with their classical analog counterparts, thus are preferably Multipliers are the basic building block in DSP,
used in place of analog filter [1]. Broadly, digital filters are microprocessors and other applications. The system’s
classified as: Finite Impulse Response (FIR) and Infinite performance is entirely dependent upon the multipliers
Impulse Response (IIR) filter. FIR filters have linear phase, because they have large area, long latency and consume
stability, fewer finite precision errors, and efficient considerable power hence there is a need to design high
implementation hence preferred over IIR filter [2]. This speed, low power consumption, regular and less area
paper discusses the design and implementation of a non- multipliers. The speed of the multipliers can be increased by
pipelined and pipelined FIR filter using both the encoding reducing the number of partial products. Parallel multipliers
schemes for multipliers – Radix-4 and Radix-8. are fastest among all multipliers. Booth multipliers are the
The remainder of the paper proceeds as follows: parallel multipliers that operate on signed operands in two’s
Section II describes the brief summary of FIR filter theory complement form and have high performance, low power
and section III presents the algorithm used to design the consumption and does not suffer from bad regularity [5].
multiplier which is the basic block of FIR filter structure. This paper presents an efficient implementation of high
Section IV briefly explains FIR filter design and Section V speed parallel multipliers using both the encoding schemes
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INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN ELECTRICAL, ELECTRONICS, INSTRUMENTATION AND CONTROL ENGINEERING
Vol. 1, Issue 5, August 2013

Radix–4 and Radix-8 which are further used in the designing Multiply by zero means the multiplicand is multiplied by
of FIR filter. Radix-4 and Radix-8 reduces the number of “0”. Multiply by “1” means the product still remains the
partial products to n/2 and n/3 respectively where n is the same as the multiplicand value. Multiply by “-1” means that
length of the multiplier. The number of partial products can the product is the two’s complement form of the
be further reduced by using higher radices but the multiplicand. Multiply by “-2” is to shift left one bit the
disadvantage is that we need to generate more multiples of two’s complement of the multiplicand value and multiply by
multiplicand. Radix-4 booth recoding encodes the “2” means just shift left the multiplicand by one place.
multipliers bits into [-2, 2]. Multiplier bits are grouped into Multiplying the multiplicand by “3” is equivalent to (2X+X)
the block of three such that each block overlaps the previous addition of multiplicand and left shifted multiplicand by one
block by one bit. The overlapping keeps track off what was digit. Multiply by “-3” means addition of two’s complement
happened in the last block as the MSB of the block act as of multiplicand and shift left one bit the two’s compliment
sign bit. For each group of three bits a partial product is of the multiplicand value. Multiply by “4” means shift left
generated according to the recoding scheme as shown in the multiplicand by two place. Multiply by “-4” means shift
Table I. The same procedure is true for radix-8 but the left the two’s complement of multiplicand by two places.
difference is here the multipliers bits are grouped into block
of four bits and encodes the multiplier bits into [-4,4]
according to the encoding table as shown in Table II. Finally IV. FIR FILTER DESIGN
a regular carry select adder has been used to add all the In this paper, an FIR filter has been designed using Kaiser
partial products [6]. window technique with the help of MATLAB Filter Design
and Analysis tool box (FDA) as shown in Fig. 1 and the
Table I Radix-4 Recoding Scheme
coefficients are directly imported to the VHDL file. The
Multiplier Bits Recoding Operation input, output and coefficients are represented in fixed point
on Multiplicand, X notation and are quantized to 16 bits. The Kaiser window
𝒀𝒊+1 𝒀𝒊 𝒀𝒊−𝟏
has a adjustable parameter α which optimize the main-lobe
0 0 0 0 width and direct control over stop-band attenuation can be
0 0 1 +1X achieved thereby sustaining optimality and flexibility. The
0 1 0 +1X direct form realization of FIR filter and magnitude response
0 1 1 +2X are shown in Fig. 2 and Fig. 3 respectively. The design
1 0 0 -2X parameters or specification are as follows
1 0 1 -1X
1 1 0 -1X 1. Stop-band attenuation = 40 dB
1 1 1 0 2. Pass-band ripple = 0.01 dB
3. Transition width = 500 Hz
Table II Radix-8 Recoding Scheme 4. Sampling frequency = 10 kHz
5. Ideal cut-off frequency = 1200 Hz
Multiplier Bits Recoding
Operation on
𝒀𝒊+2 𝒀𝒊+1 𝒀𝒊 𝒀𝒊−𝟏 Multiplicand,
X
0 0 0 0 0
0 0 0 1 +1X
0 0 1 0 +1X
0 0 1 1 +2X
0 1 0 0 +2X
0 1 0 1 +3X
0 1 1 0 +3X
0 1 1 1 +4X
1 0 0 0 -4X
1 0 0 1 -3X
1 0 1 0 -3X
1 0 1 1 -2X
1 1 0 0 -2X
1 1 0 1 -1X
1 1 1 0 -1X
Fig. 1 FIR digital low-pass filter parameters.
1 1 1 1 0
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INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN ELECTRICAL, ELECTRONICS, INSTRUMENTATION AND CONTROL ENGINEERING
Vol. 1, Issue 5, August 2013

Due to pipelining the critical path has been reduced from

𝑇𝑀 + 70𝑇𝐴 to 𝑇𝑀 + 𝑇𝐴 where, 𝑇𝑀 is the time required for
multiplication operation and 𝑇𝐴 is the time required for
addition operation.

VI. SYNTHESIS RESULTS

Table III Synthesis Report of Non-pipelined FIR Filter.
LOGIC NON- PIPELINED
𝑻𝑴 + 𝟕𝟎𝑻𝑨 ULTILISATION PIPELINED FIR FILTER
FIR FILTER
Fig. 2 Seventy-one tap non-pipelined FIR structure. Number of Slice 1,186/29,504 2,298/29,504
Flip Flop
Four Input LUTs 14,665/29,504 8,698/29,504
Number of Occupied 8,393/14,752 5.004/14,752
Slices
Total Number of 14,917/29504 8,906/29,504
Four Input Slices
Number Of Bonded 51/250 51/250
IOBs
Average Fanout 2.55 2.75
Memory Usuage 891980 900608
(Kb)
Fig. 3 FIR digital low-pass filter magnitude response
Table IV Synthesis report of pipelined FIR filter
V. PIPELINING
Pipelining is an implementation technique in which multiple LOGIC NON- PIPELINED
instructions are overlapped in execution and results in speed ULTILISATION PIPELINED FIR
enhancement for the critical path in most of the DSP system, FIR FILTER
microprocessors etc. It can either increase the clock speed or FILTER
Number of Slice Flip 1,186/29,504 2,299/29,504
reduce the power consumption at the same speed in a DSP
Flop
system. The total execution time for each individual Four Input LUTs 19,687/29,504 11,412/29,504
instruction is not altered by pipelining. It does not accelerate Number of Occupied 11.304/14,752 6,714/14,752
instruction execution time but it does accelerate program Slices
execution time by increasing the number of instruction Total Number of 20,037/29504 11,716/29,504
finished per cycle [2]. Four Input Slices
In pipelining any operation along the critical path is broken Number of Bonded 51/250 51/250
into smaller and quicker operation with registers between the IOBs
levels in order to get a smaller critical path or increase in the Average Fanout 2.65 2.78
operating frequency which leads to higher throughput [7]. Memory Usuage(Kb) 1076364 1080268
The pipelined structure of the proposed FIR filter design is
shown in Fig. 4.

𝑻𝑴 + 𝑻𝑨

Fig. 4 Seventy-one tap pipelined FIR structure. Fig.5 Top Level Circuit Diagram of Low-pass Filter

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INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN ELECTRICAL, ELECTRONICS, INSTRUMENTATION AND CONTROL ENGINEERING
Vol. 1, Issue 5, August 2013

Fig. 9 Simulation of pipelined FIR filter using Radix-4 multiplier.

Fig. 6 Delay and Power analysis of FIR filter using Radix-4 multiplier.

Fig. 10 Simulation of non-pipelined FIR filter using Radix-8

Fig. 7 Delay and Power analysis of FIR filter using Radix-8 multiplier.

VII. Simulation Results

Fig. 11 Simulation of Pipelined FIR Filter Using Radix-8

VIII. CONCLUSIONS
The design of non-pipelined and pipelined FIR filter using
Fig. 8 Simulation of non-pipelined FIR filter using Radix-4 multiplier. both the encoding schemes – Radix-4 and Radix-8 has been
accomplished via Hardware Description Language and
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INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN ELECTRICAL, ELECTRONICS, INSTRUMENTATION AND CONTROL ENGINEERING
Vol. 1, Issue 5, August 2013

synthesized on XILINX ISE Software (Xilinx ISE 13.1

version) for Spartan 3E FGPA (Field Gate Programmable
Array) family (XC3S1600E). Synthesis reports are shown in
Table III and Table IV. The Fig. 6 demonstrates that the
pipelined technique enhances the speed and reduces delay
from 157.413 ns to 26.892 ns i.e., 82.9 % in pipelined FIR
filter designed using Radix-4 multiplier as compared to non-
pipelined technique. On the other hand, delay has been
reduced from 149.386 ns to 26.934 ns i.e. 81.97 % in
pipelined FIR filter designed using Radix-8 multiplier as
compared to non-pipelined technique as shown in Fig. 7.
Power analysis shows that the dynamic power has been
reduced by the same amount from 106.7415 mW to 60.3062
mW i.e., 43.50 % due to pipelining technique in both the
designing of FIR filters as shown in Fig. 6 and Fig. 7.
Simulation waveforms are shown in Fig. 8 – Fig. 11. The top
RTL level symbol of proposed FIR filter is shown in Fig. 5.
As all the structures are implemented using VHDL language,
they can be ported to any FPGA family.

ACKNOWLEDGEMENT
The author would like to thank Mr. Sanjay Kumar for his
complete guidance and entire VLSI department for their
support.

REFERENCES

[1]. N. Parijatha, K.R.A. Hinduja and A.C. Shaker, “FPGA Optimized Low
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[2]. R. Kaur, A. Raman, Member, IACSIT, H. Singh and J. Malhotra,
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[3]. B. Rashidi, B. Rashidi and M. Pourormazd, “Design and
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[4]. E. Ifeachor and B. Jervis, “Finite impulse response (FIR) filter design”
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