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 Computer Architecture

and Organization

d be (From 8085 to Core2Duo and beyond) y ond)

Subrata Ghoshal

Professor and Head, Information Technology Department

Sikkim Manipal Institute of Technology, Sikkim

Delhi • Chennai • Chandigarh

Editor–Acquisitions: Sachin Saxena

The circuits, software routines, schematics and ideas presented in this book are purely for academic

purpose. The author and the publisher have made their best efforts in preparing this book. Neither the

publisher nor the author offer any warranty for the accuracy or completeness of any information.

All registered trademarks belong to respective organizations.

Copyright © 2011 Dorling Kindersley (India) Pvt. Ltd

This book is sold subject to the condition that it shall not, by way of trade or otherwise, be lent, resold,

hired out, or otherwise circulated without the publisher’s prior written consent in any form of binding

or cover other than that in which it is published and without a similar condition including this condition

being imposed on the subsequent purchaser and without limiting the rights under copyright reserved

above, no part of this publication may be reproduced, stored in or introduced into a retrieval system,

or transmitted in any form or by any means (electronic, mechanical, photocopying, recording or other-

wise), without the prior written permission of both the copyright owner and the publisher of this book.

ISBN 978-81-317-6155-7

First Impression

Published by Dorling Kindersley (India) Pvt. Ltd, licensees of Pearson Education in South Asia.

Head Of ce: 7th Floor, Knowledge Boulevard, A-8(A), Sector 62, Noida 201 309, UP, India.

Registered Of ce: 11 Community Centre, Panchsheel Park, New Delhi 110 017, India.

Compositor: Glyph International Pvt. Ltd.

Printer: India Binding House.

 To my wife

Rita

and my daughter

Bulbul

who are still tolerating me even after my fifth book.

 Brief Contents

Cha pter 1 Introduction 1

Cha pter 2 O ver view of Computer 14

Cha pter 3 Funda menta ls of Digi ta l L ogic Circui ts 28

Cha pter 4 C omputer Ar i th me tic 58

Cha pter 5 Proces s or B a s ic s 94

Cha pter 6 Ins tr uction S et a nd As s embly L a n gua ge

Progra mming 14 9

Cha pter 7 The Memor y Sys tem 19 8

Cha pter 8 Input/ Output Orga niza tion 23 7

 Cha pter 9 Microprogra mming a n d Microa rchi tec tu re 267

Ch a pter 10 C ontrol U ni t Opera tion 30 1

Ch a pter 11 Opera ting Sys tem 3 45

Ch a pter 12 Pipel ining 3 67

Ch a pter 13 Pa ra l lel Proce s s ing a nd Super-S ca la r

Opera tion 391

Ch a pter 14 Embedded Sys tems 411

Ch a pter 15 C omputer Per iphe ra ls 43 0

Appendix-A Number Sys tems 44 2

Appendix-B SPARC a nd Ul tra -SPARC 4 49

vi Brief Contents

Appendix-C Pow er PC 46 3

Appendix-D Intel Core2Du o 475

Appendix- E MIPS R4000 49 4

Appendix-F Proj ect B a nk 51 0

 Contents

Preface xxv

Acknowledgements xxvi

About the Author xxvii

1. Introduction 1
Chapter Objectives 1

1.1 Introduction 1

1.1.1 Difference Between Architecture and Organization 2

1.1.2 Essential Architectural Features of a Computer 3

1.2 Historical Background 3

1.2.1 Mechanical Computers (Calculators) 3

1.2.2 First Generation (Vacuum Tubes) 4

1.2.3 Second Generation (Transistors) 6

1.2.4 Third Generation (Integrated Circuits) 6

1.2.5 Fourth Generation (VLSI) 7

1.3 Classification 8

1.3.1 Embedded Systems 8

1.3.2 Personal Computers (PCs) 9

1.3.3 Work Stations 9

1.3.4 Servers 9

1.3.5 Mainframes 10

1.3.6 Looking Forward 10

Summary 11

Points to Remember 11

Review Questions 12

2. Overview of Computer 14
Chapter Objectives 14

2.1 Basic Structure of Computer Hardware 14

2.2 Fundamental Units 15

2.2.1 HDD and SMPS 16

2.2.2 Motherboard 16

2.3 Basic Operational Concepts 18

2.3.1 Processor Clock 18

2.3.2 Program Counter 18

viii Contents

2.3.3 Instruction Fetch 19

2.3.4 Instruction Decode 19

2.3.5 Instruction Execute 20

2.3.6 Program Flow Control 21

2.4 Bus Structure 21

2.4.1 Internal Bus 21

2.4.2 External Bus 22

2.5 Building Blocks of a Computer 22

2.5.1 Digital Logic 22

2.5.2 Microarchitecture 23

2.5.3 Operating System 24

2.5.4 User’s Program 24

Summary 24

Points to Remember 24

Review Questions 25

3. Fundamentals of Digital Logic Circuits 28

Chapter Objectives 28

3.1 Introduction 28

3.1.1 Background 29

3.1.2 Scope 29

3.2 Boolean Algebra 29

3.2.1 Boolean Operators 30

3.2.2 Truth Table 31

3.2.3 Boolean Identities 32

3.3 Logic Gates 32

3.3.1 Common Logic Gates 33

3.3.2 Universal Gates 34

3.4 Combinational Circuits 35

3.4.1 Decoder 36

3.4.2 Multiplexer 37

3.5 Arithmetic Circuits 38

3.5.1 Half Adder 38

3.5.2 Full Adder 39

3.5.3 n-Bit Adder 39

3.6 Sequential Circuits 40

3.6.1 Clock Signal 40

3.6.2 Basic Latch 41

3.6.3 S-R Latch 42

Contents ix

3.6.4 Clocked S-R Flip-Flop 43

3.6.5 D Flip-Flop 44

3.6.6 J-K Flip-Flop 44

3.6.7 T Flip-Flop 45

3.7 Registers and Counters 45

3.7.1 Registers 46

3.7.2 Counters 46
3.8 Memory Circuits 47
 3.9 Solved Examples 48

Summary 54

Points to Remember 55

Review Questions 55

4. Computer Arithmetic 58
Chapter Objectives 58

4.1 Introduction 58

4.2 Addition and Subtraction 59

4.2.1 Two’s Complement Representation 59

4.2.2 Purpose of Two’s Complement 60

4.2.3 Sign Representation 60

4.2.4 Signed Addition and Subtraction 62

4.3 Multiplication Algorithms 63

4.3.1 Paper and Pencil Method 63

4.3.2 Method of Repeated Additions 64

4.4 Booth’s Algorithm 64

4.4.1 Arithmetic Right-shift 64

4.4.2 Locations and Counters 64

4.4.3 Details of Shift Operation 66

4.4.4 Algorithm and Flowchart 66

4.4.5 Solved Example 4.1 67

4.4.6 Solved Example 4.2 69

4.4.7 Solved Example 4.3 70

4.4.8 Solved Example 4.4 71

4.4.9 Multiplication with Signed Integers 72

4.5 Division Algorithms 72

4.5.1 Paper and Pencil Method 72

4.6 Division of Signed Integers 73

4.6.1 Locations and Counters 73

4.6.2 One-bit Left-shift 74

x Contents

4.6.3 Algorithm for Division of Signed Integers 74

4.6.4 Solved Example 4.5 74

4.6.5 Solved Example 4.6 76

4.7 Floating-point Number Representation 77

4.7.1 Signed-magnitude Representation 77

4.7.2 Solved Example 4.7 78

4.7.3 Scientific Representation 78

4.7.4 Biasing the Exponent 79

4.7.5 Normalizing the Mantissa 80

4.7.6 Range of Numbers 82

4.7.7 Accuracy 84

4.7.8 IEEE 754 Format 85

4.8 Floating-point Arithmetic and Unit Operations 85

4.8.1 Floating-point Unit Operations 86

4.8.2 Exponent Overflow or Underflow 86

4.8.3 Mantissa Overflow or Underflow 87

4.8.4 Floating-point Addition and Subtraction 87

4.8.5 Floating-point Multiplication 88

4.8.6 Floating-point Division 89

4.8.7 Guard Bits 90

 4.9 Pipelined ALU 90

Summary 91

Points to Remember 91

Review Questions 92

5. Processor Basics 94
Chapter Objectives 94

5.1 Introduction 94

5.2 Processor Architecture and Organization 94

5.2.1 Internal Architecture 95

5.2.2 Basic Function 95

5.2.3 Peripheral Devices and External Communication 96

5.2.4 Address Bus and Addressing 97

5.2.5 Data Bus and Data Flow Control 97

5.2.6 Control Bus 98

5.3 Processor Operation 99

5.3.1 Instruction Cycle 99

5.3.2 Instruction Fetch 100

5.3.3 Instruction Decode 101

Contents xi

5.3.4 Instruction Execute 101

5.3.5 Machine Cycle and T-states 101

5.3.6 Timings, Control and Response 102

5.4 Register Set 102

5.4.1 Status Register 103

5.4.2 Accumulator 104

5.4.3 Program Counter 104

5.4.4 Stack Pointer 104

5.4.5 General Purpose Registers 104

5.5 Stack Organization 104

5.5.1 Stack as Storage Area 104

5.5.2 Subroutines and Stack 105

5.6 Interrupts 106

5.6.1 Interrupt Service Routine (ISR) 106

5.6.2 Vectored and Non-vectored Interrupts 106

5.6.3 Enabling, Disabling and Masking of Interrupts 106

5.7 Intel 8085 Microprocessor 107

5.7.1 Pins and External Signals 107

5.7.2 Internal Architecture 107

5.7.3 Register Set 109

5.7.4 System Clock 110

5.7.5 System Reset 110

5.7.6 Instruction Set 110

5.7.7 Program Memory and Stack Area 111

5.7.8 Interrupts 111

5.7.9 Timing Diagrams 112

5.7.10 Special Features 113

5.8 Intel 8086 Microprocessor 113

5.8.1 Pins and External Signals 113

5.8.2 Internal Architecture and Registers 115

5.8.3 Memory Segmentation 117

5.8.4 Memory Bank Addressing 119

5.8.5 System Clock 121

 5.8.6 System Reset 121

5.8.7 Instruction Set 121

5.8.8 Stack 122

5.8.9 Interrupts 122

5.8.10 Timing Diagrams 123

5.8.11 Special Features 124

xii Contents

5.9 Intel 8051 Microcontroller 124

5.9.1 Pins and External Signals 125

5.9.2 Internal Architecture 125

5.9.3 Register Set 126

5.9.4 System Clock 127

5.9.5 System Reset 128

5.9.6 Instruction Set 128

5.9.7 Stack 128

5.9.8 Interrupts 128

5.9.9 Special Features 129

5.10 RISC and CISC Processors 129

5.10.1 Introduction of RISC Processors 129

5.10.2 Simple and Reduced Number of Instructions 131

5.10.3 Lesser Addressing Modes 131

5.10.4 Uniform Instruction Format 131

5.10.5 More Registers 131

5.10.6 Pipeline Architecture 131

5.10.7 Conclusion 132

5.11 Intel 80386 Processor 132

5.11.1 External Signals 132

5.11.2 Internal Architecture and Registers 134

5.11.3 Memory Handling 136

5.11.4 Timing Diagram 137

5.11.5 Special Features 138

5.12 Intel Pentium 4 Processor 138

5.12.1 RISC-like CISC Design 139

5.12.2 Internal Architecture 141

5.12.3 Register Set 143

Summary 144

Points to Remember 146

Review Questions 146

6. Instruction Set and Assembly Language

Programming 149
Chapter Objectives 149

6.1 Introduction 149

6.2 High Level, Assembly and Machine Language 150

6.2.1 High Level Language 150

6.2.2 Assembly Language 151

6.2.3 Machine Language 151

 Contents xiii

6.3 Functions and Characteristics of Instructions 152

6.3.1 Data Move Type 152

6.3.2 Arithmetic and Logical Type 153

6.3.3 Program Flow Control Type 153

6.4 Addressing Modes 155

6.4.1 Immediate 156

6.4.2 Direct 157

6.4.3 Register Direct 157

6.4.4 Register Indirect 158

6.4.5 Relative 159

6.4.6 Implicit 159

6.4.7 Indexed 160

6.5 Instruction Formats and Fields 161

6.5.1 Role of Processor 162

6.5.2 Role of Instruction Set 162

6.5.3 Relation of Format and Field 163

6.6 8085 Instruction Set 163

6.6.1 Format and Fields 164

6.6.2 Discussions 167

6.7 8086 Instruction Set 168

6.7.1 Format and Fields 170

6.7.2 Discussions 172

6.8 8051 Instruction Set 172

6.8.1 Format and Fields 173

6.8.2 Discussions 174

6.9 Assembly Language Programming 174

6.9.1 Why Assembly Language Programming? 175

6.9.2 Assembly Language Program Format 176

6.9.3 Assembler Directives 177

6.9.4 Data Transfer and Manipulations 178

6.9.5 Loops and Loop Control 178

6.9.6 Program Branching 179

6.9.7 Subroutine Calls 179

6.10 Assembler 179

6.10.1 Two-pass Assembler 180

6.10.2 One-pass Assembler 180

6.10.3 Editor, Loader, Linker and Debugger 181

6.10.4 Macro 181

xiv Contents

6.11 Intel 80386 Processor 182

6.11.1 80386 Instruction Set 182

6.11.2 Special Features 183

6.12 Intel Pentium 4 Processor 184

6.13 Solved Example 184

Summary 194
Points to Remember 195
Review Questions 195

7. The Memory System 198

Chapter Objectives 198

7.1 Introduction 198

7.2 Memory Classification 198

7.2.1 Read Only Memory (ROM) 200

7.2.2 Read/Write Memory (RAM) 200

7.3 Memory Characteristics and Hierarchy 201

7.3.1 Access Time 201

7.3.2 Cost of Storage per Bit 202

7.3.3 Affordable Convenient Size 202

7.3.4 Memory Hierarchy 202

7.4 Cache Memory 204

7.4.1 Background of Cache Introduction 204

7.4.2 The Idea of Cache 206

7.4.3 How Does Cache Work? 206

7.4.4 Classification of Cache 207

7.4.5 Levels of Cache 207

7.4.6 Cache in Intel Processors 207

7.4.7 Cache Hit and Hit Rate 208

7.4.8 Storing Results in Cache 208

7.4.9 Direct Mapped Cache 209

7.4.10 Solved Examples 211

7.4.11 Set Associative Cache 213

7.4.12 Fully Associative Cache 214

7.4.13 Replacement Algorithms 214

7.5 Main Memory 215

7.5.1 Dynamic RAM (DRAM) 215

7.5.2 DRAM Refreshing 216

Contents xv

7.6 Secondary Memory 216

7.6.1 Hard Disc 216

7.6.2 Optical Disc 217

7.6.3 Magnetic Tape 218

7.7 Virtual Memory 218

7.7.1 Overlay 218

7.7.2 How Virtual Memory Works? 219

7.7.3 Paging in Virtual Memory 219

7.7.4 Virtual Memory in Intel Processors 220

7.8 Memory Management 221

7.8.1 DMA 221

7.8.2 Steps for a File Reading Operation using DMA 223

7.9 Intel 80386 Memory Organization 224

7.9.1 Physical and Logical Address 224

7.9.2 Selector-descriptor Tables 225

7.9.3 Protection in Multi-tasking Environment 226

7.9.4 Paging and Page Tables of 80386 227

7.10 Pentium 4 Memory Organization 228

7.10.1 Pentium 4 Data Types 229

7.11 Memory Decoding 229

7.11.1 Principle of Decoding 230
 7.11.2 Types of Decoder 231

7.11.3 Common Issues of Memory Decoding 231

Summary 233

Points to Remember 234

Review Questions 235

8. Input/Output Organization 237

Chapter Objectives 237

8.1 Introduction 237

8.2 Basic Input/Output Structure of Computers 238

8.2.1 Interfacing and Communication Techniques 238

8.2.2 Classification of Communication 240

8.3 Asynchronous Data Communication 240

8.3.1 Examples of Asynchronous Communication 240

8.4 Serial and Parallel Communications 241

8.4.1 Format of Serial Data Transfer 242

8.4.2 USART 242

8.4.3 Intel 8251 USART 243

xvi Contents

8.5 Programmed I/O (Polling) 244

8.5.1 Sending Data Out 244

8.5.2 Receiving Data In 245

8.5.3 Intel 8255 PPI 245

8.6 Interrupt Driven I/O 246

8.6.1 Strobed Input Mode 246

8.6.2 Strobed Output Mode 247

8.6.3 Bidirectional Data Transfer Mode 248

8.6.4 Advantage of Interrupt Driven I/O 248

8.7 Interrupt Controller (8259) 249

8.7.1 8259 Without Cascading 250

8.7.2 8259 with Cascading 250

8.8 DMA 251

8.8.1 Intel 8237 DMA Controller 251

8.9 Device Drivers 253

8.10 Standard I/O Interfaces (Buses) 254

8.10.1 Genesis of Interfacing Buses 255

8.10.2 Universal Serial Bus (USB) 256

8.10.3 Small Computer System Interface (SCSI) 259

8.10.4 GPIB/HPIB/IEEE488 260

8.10.5 VME Bus 261

8.10.6 Multibus 261

8.11 Bus Arbitration 261

8.12 I/O Processor 262

8.13 Solved Example 263

Summary 263

Points to Remember 264

Review Questions 264

9. Microprogramming and Microarchitecture 267

Chapter Objectives 267

9.1 Introduction 267

9.1.1 Latching Data Available Within a Register 267

 9.1.2 Data Flow Control from or to a Register 268

9.1.3 Need of Data Path Design 268

9.2 Problem of Allowing Data-flow 268

9.2.1 What is Expected? 268

9.2.2 Visualizing Data-flow and Registers 269

9.2.3 Data Path Design 269

Contents xvii

9.2.4 Control Signal Requirements 271

9.2.5 Control Signals for Four General Purpose Registers (R0–R3) 272

9.2.6 Control Signals for Accumulator 273

9.2.7 Need of Microinstructions 274

9.2.8 Microinstructions for the Example Problem 275

9.3 Instruction Cycles of a Processor 277

9.4 Hardwired Control 278

9.4.1 Working of Hardwired Control 278

9.4.2 Advantages of Hardwired Control 279

9.4.3 Disadvantages of Hardwired Control 279

9.5 Programmed Control 280

9.5.1 Working of Programmed Control 280

9.5.2 Advantages of Programmed Control 280

9.5.3 Disadvantages of Programmed Control 280

9.6 Sequencing and Execution of Microinstructions 281

9.6.1 Example 1 (Load Accumulator by RO) 281

9.6.2 Example 2 (Save Accumulator in RO) 282

9.6.3 Example 3 (Add Accumulator with RO) 282

9.7 Solved Example 283

9.8 Utilizing System Clock 288

9.9 Processor Data Path Design 291

9.9.1 One Data Path (C-Bus) 292

9.9.2 Two Data Paths (B-Bus and C-Bus) 294

9.9.3 Three Data Paths (A-Bus, B-Bus and C-Bus) 295

9.10 Solved Example 295

Summary 297

Points to Remember 297

Review Questions 298

10. Control Unit Operation 301

Chapter Objectives 301

10.1 Introduction 301

10.2 Control Unit (CU) 302

10.3 Micro-operations 303

10.3.1 Fetch Cycle 303

10.3.2 Indirect Cycle (Operand Fetch) 307

10.3.3 Execute Cycle 308

10.3.4 Interrupt Cycle 308

10.3.5 Instruction Cycle 309

xviii Contents

10.4 Control of the Processor 310

10.4.1 Controlling System 310

10.4.2 Internal Data Paths 311

10.4.3 Latching Signals 314

10.5 Hardware Implementation 315

10.6 Solved Examples 316

10.6.1 Example 1 (Using C-Bus) 316

10.6.2 Example 2 (Using C-Bus and B-Bus) 322

10.6.3 Example 3 (Alternate Solution Using C-Bus and B-Bus) 329

10.6.4 Example 4 (ALU Operation Using 1-Bus and 3-Bus) 330

10.6.5 Example 5 (Interrupt Handling) 332

10.6.6 Example 6 (Subroutine Call) 334

Summary 341

Points to Remember 342

Review Questions 342

11. Operating System 345

Chapter Objectives 345

11.1 Introduction 345

11.1.1 Why OS? 345

11.1.2 What is an OS? 346

11.1.3 Evolution of OS 347

11.1.4 Purpose of OS 347

11.2 Process and Its Control 347

11.2.1 Multi-tasking Environment 348

11.2.2 Life-cycle of a Process 348

11.2.3 Process Control Block (PCB) 349

11.2.4 Movements of a Process 350

11.3 Scheduling Issues 350

11.3.1 CPU-bound and I/O-bound Processes 350

11.3.2 Common Types of Scheduling 351

11.3.3 Efficiency of a Scheduling 351

11.3.4 Non–pre-emptive SJF 352

11.3.5 Pre-emptive SJF 353

11.3.6 First-Come-First-Served or FCFS 354

11.3.7 Round Robin 354

11.3.8 Non–pre-emptive Priority 355

11.3.9 Pre-emptive Priority 356

11.3.10 Process Switching 357

Contents xix

11.4 Threads 358

11.5 Semaphores 359

11.5.1 Need of Semaphore 359

11.5.2 Critical Section 360

11.6 Memory Management Issues 362

11.6.1 Swapping 362

11.6.2 Contiguous Memory 362

 11.6.3 Paging 363

Summary 363

Points to Remember 364

Review Questions 365

12. Pipelining 367

Chapter Objectives 367

12.1 Introduction 367

12.2 Some Basic Concepts 368

12.2.1 Pipeline Strategy 369

12.2.2 Multi-stage Pipeline 370

12.2.3 Efficiency of a Pipeline 370

12.3 Pipeline Performance 372

12.3.1 Stalling 372

12.3.2 Types of Hazards 374

12.4 Data Hazards 375

12.4.1 Data Dependency 375

12.4.2 Solution by Software Method 375

12.4.3 Solution by Hardware Method 376

12.4.4 I/O Wait 377

12.5 Instruction Hazards 377

12.5.1 Cache-miss 377

12.5.2 Conditional Branch Instructions 377

12.6 Structural Hazards 379

12.7 Controls and Data Paths 381

12.8 Pentium 4 Pipeline 383

12.8.1 Why RISC-like-CISC 383

12.8.2 Out-of-order Execution 384

12.8.3 Register Renaming 385

12.8.4 Speculative Execution 385

12.8.5 Stages of P4 Pipeline 385

xx Contents

Summary 387

Points to Remember 388

Review Questions 388

13. Parallel Processing and Super-Scalar

Operation 391
Chapter Objectives 391

13.1 Introduction 391

13.2 Parallel Processing 392

13.2.1 Flynn’s Classifications 392

13.2.2 Structure of Multiprocessors 393

13.2.3 I/O Modules 394

13.3 Network Topologies 394

13.3.1 Crossbar 394

13.3.2 Hypercube 395

13.3.3 Mesh 396

13.3.4 Tree 397

13.3.5 Multi-stage 397

13.3.6 Ring 398

13.3.7 Single Bus 399

 13.3.8 Mixed Topology 400

13.4 Program Parallelism 400

13.4.1 Dividing into Subprograms 400

13.4.2 Shared Variables and Critical Sections 401

13.4.3 Cache Coherence 402

13.5 Super-scalar Operation 402

13.6 Array Processor 404

13.7 Vector Processor 405

13.8 Fault Tolerant Computing 406

Summary 407

Points to Remember 408

Review Questions 408

14. Embedded Systems 411

Chapter Objectives 411

14.1 Introduction 411

14.2 Types and Classifications 412

14.2.1 Processing Power 412

Contents xxi

14.2.2 Power Supply 412

14.2.3 Life-span or Usage 413

14.2.4 Wireless 413

14.2.5 Instrumentation 413

14.2.6 Medical 413

14.2.7 Real-time Systems 414

14.2.8 Networking 414

14.2.9 Analog Processing 414

14.3 Architecture of Microcontrollers 414

14.3.1 General Architecture 415

14.4 Architecture of Atmel AVR 416

14.4.1 Pins and Signals 416

14.4.2 AVR Core 417

14.4.3 Oscillator and Watchdog Timer 417

14.4.4 Memory Blocks 417

14.4.5 Status Register (SREG) 420

14.4.6 Stack Pointer and System Stack 420

14.4.7 Power Saving Features 421

14.4.8 System Reset 421

14.5 Organizational Issues 422

14.5.1 DC Characteristics of Port Pins 422

14.5.2 Power Consumption and Saving 423

14.6 Design Issues 423

14.6.1 Device Selection 423

14.6.2 Communication 424

14.6.3 Power Optimizing 425

14.6.4 Compactness 425

14.6.5 Cost-effectiveness 425

14.6.6 Robustness 425

14.6.7 Compatibility 425

14.7 Example of Embedded System 426

14.7.1 User Requirements 426

14.7.2 System Specifications 426

 Summary 427

Points to Remember 428

Review Questions 428

xxii Contents

15. Computer Peripherals 430

Chapter Objectives 430

15.1 Introduction 430

15.2 Keyboard 430

15.2.1 Keyboard Basics 431

15.2.2 Multiple Key Scanning and Two-dimensional Matrix 431

15.2.3 Keyboard as an Embedded System 432

15.3 Mouse 433

15.3.1 Opto-mechanical Mouse 433

15.3.2 Optical Mouse 433

15.3.3 Mouse as an Embedded System 434

15.4 Printers 434

15.4.1 Dot-matrix Printer 435

15.4.2 Inkjet Printer 436

15.4.3 Laser Printer 437

15.4.4 Color Printing 437

15.5 Display 437

15.5.1 CRT Display 437

15.5.2 Flat Panel Display 438

15.6 Touch pads 438

Summary 439

Points to Remember 439

Review Questions 440

Appendix-A. Number Systems 442

Objectives 442

A.1 Introduction 442

A.2 Decimal Numbers 442

A.3 Binary Numbers 443

A.4 Hexadecimal Numbers 443

A.5 Octal Numbers 444

A.6 Conversion Techniques 444

A.6.1 Decimal to Binary 445

A.6.2 Binary to Decimal 446

A.6.3 Binary to Hexadecimal 446

A.6.4 Hexadecimal to Binary 446

Summary 446

Points to Remember 447

Review Questions 447

 Contents xxiii

Appendix-B. SPARC and UltraSPARC 449

Objectives 449

B.1 Introduction 449

B.2 Background 449

B.2.1 RISC Characteristics 450

B.2.2 Design History 450

B.3 Functional Overview 450

B.4 SPARC and UltraSPARC Register Set 451

B.4.1 Special Features 452

B.5 Internal Architecture 453

B.6 Pipelining 454

B.7 Instruction Format 455

B.8 Instruction Set 456

Summary 459

Points to Remember 460

Review Questions 460

Appendix-C. Power PC 463

Objectives 463

C.1 Introduction 463

C.2 Background 463

C.3 Internal Architecture 464

C.4 Register Set of Power PC 465

C.5 Power PC Instruction Set 467

C.6 Pipeline of Power PC 470

C.6.1 Branch Processing by Power PC 471

C.7 Data Types of Power PC 472

Summary 472

Points to Remember 472

Review Questions 473

Appendix-D. Intel Core2Duo 475

Objectives 475

D.1 Difference Between Dual Core and Core2Duo 475

D.2 Salient Features of Core2Duo 476

D.3 A Few Important Signals 477

D.4 Low-power States and Power Management 479

D.5 Internal Architecture 481

D.6 Instruction Set 482

xxiv Contents

Summary 491

Points to Remember 492

Review Questions 492

Appendix-E. MIPS R4000 494

Objectives 494

E.1 Introduction 494

E.2 General Architecture 495
 E.3 External Signals 496

E.4 Internal Architecture 497

E.5 Register Set 499

E.6 MIPS R-Series Instruction Set 499

E.7 Instruction Format 503

E.8 Pipeline 504

E.9 Memory Management 505

E.10 Exception Processing of MIPS R4000 506

Summary 507

Points to Remember 507

Review Questions 507

Appendix-F. Project Bank 510

Answers for Target the Correct Option 522

Glossary 524

Acronyms 533

Bibliography 535

Index 537
 Preface

Introducing another title within the numerous titles in the well-established area of Computer Architec-

ture and Organization may be considered a counter-productive effort; especially, when there are well-

reputed and most respected authors in this eld. For the last 15 years or so, I myself am one of the best

admirers of these authors and their titles. Therefore, I must explain wherefrom I gather the courage to

start working on such a manuscript.

During classroom interactions with my students, I did observe that no single book covers the existing

syllabi followed by different Indian universities in the area of Computer Architecture and Organization.

The second and an even more important observation is that a larger section of our students are unable

to follow the description and these descriptions need to be narrated at their own understanding level.

I must, therefore admit that I followed these well-established textbooks myself and converted their nar-

ration to tune to the frequency of our students. To put it in simple words, they feel uncomfortable with

Core2Duo architecture but remains comfortable with 8085- or 8086-related discussions.

My efforts to help my students would have remained con ned within my lecture notes, had there

been no invasion from a totally unexpected source. It was Thomas Mathew Rajesh of PearsonEducation

(India), who, one ne afternoon, suggested the idea of developing a manuscript on Computer Archi-

tecture and Organization, especially for our students. Very soon I found that Sachin Saxena of Pearson

India also joined Thomas and I was not able to sustain the pressure of 2:1 ratio. I started working on

the manuscript when I was in Pune and nished it when I shifted to Sikkim. It took a very long time in

referring to many existing reference materials and to maintain accuracy at various phases.

I frankly admit that this book is written for the majority of students of our country, whom I know

well, as I had the privilege to teach and interact with many students at various places of India and

who were at various levels of their learning abilities. I hope that I know, by now, what they can digest

easily and what they can digest with certain dif culties. That is the reason for adopting a simple and

easy-to-understand classroom language, placing diagrams and tables at appropriate places, present-

ing full-length solved examples on complex topics like ALU design or instruction set design, and also

concluding with a summary followed by points to remember. The set of exercises at the end of every

chapter includes three types of questions. Ten are multiple choice types with answers given at the end

of the book. Ten are easy to solve and their answers would be found within each chapters. The last 10

questions are a little thought-provoking type and need some contemplation on the subject matter. A

glossary and acronyms would help interested readers to quickly get the relevant information. All com-

ments and criticism related to this book would be thankfully acknowledged by me. I may be reached at

[email protected].

SUBRATA GHOSHAL
 Acknowledgements

I sincerely thank Brig. (Dr) S. S. Pabla, (Vice Chancellor, Sikkim Manipal University) and Brig. (Dr)

S. N. Mishra, (Pro-Vice Chancellor, Sikkim Manipal University and Director, Sikkim Manipal Insti-

tute of Technology) for their constant encouragement and support extended towards preparation of the

manuscript.

I must acknowledge my ever helpful colleagues of the IT department of Sikkim Manipal Institute of

Technology (SMIT). My special thanks to Ashish Datta for his photography and to Subhajit Kar for his

help in various phases during the preparation of the manuscript.

I remember all my students, including Sonam Palden Barphungpa, who helped me in various ways

for the preparation of the manuscript, some through their open-hearted criticism and some by giving

meaningful suggestions. Amitabha Biswas, Manager, MACINTEL Solutions, is gratefully acknowl-

edged for allowing me to reproduce the photograph of Apple-Mac Workstation.

I thank the whole team at Pearson India, especially Thomas Mathew Rajesh, Sachin Saxena and

Gaurav Jain, for their ef cient way of handling this project.

I am grateful to my wife Rita and my daughter Bulbul for their immense patience and cooperation

during the preparatory stages of the manuscript. It is surprising that they are still happily tolerating me

even after my fth book.

S UBRATA GHOSHAL
 About the Author

Professor Subrata Ghoshal is a Ph.D. from Indian Institute of

Technology Bombay and is presently the Head of Information

Technology department of Sikkim Manipal Institute of Technol-

ogy, Sikkim. Earlier, he was associated with premier academic

institutions of India, like BITS, Pilani; IIIT, Pune; STCET, Kol-

kata, etc. and has more than 20 years of teaching experience.

Starting in 1982 with EC1030, a third generation computer ac-

cepting Hollerith punch-cards, Professor Ghoshal has worked

with various types of computers, like BBC Micro, Hewlett

Packard series 9000, TDC, ZX-Spectrum, VAX and so on, and

had the privilege of keenly observing the developments of com-

puters during the last three decades.

Professor Ghoshal is the inventor of the rst Indian chess-playing laptop, namely Inchess Chessputer

with ELO rating 2000+, for which he owns the copyright. His invention was highly appreciated by

eminent people like Mr Viswanathan Anand. For a long period, he was the expert committee member

of CSIR, New Delhi. He has delivered lectures on invitation on various topics at different engineering

institutes of India, located at places like Jaipur, Pune, Hyderabad, Coimbatore, Chennai, Nagpur, etc.

He has authored several text books and technical papers and guided several Ph.D. and M.Tech. stu-

dents. He is an expert in small system design, specially hard real time systems, where he effectively uses

his expertise in assembly language programming. He has successfully completed many consultancy

projects and his areas of academic interest and expertise include robotics, arti cial intelligence and

embedded systems.
 1

Introduction

This chapter introduces the computer as a machine and discusses about its brief history

of evolution and some of its salient features. After completion of this chapter, the reader

would know about

R Generation-wise salient features of computers

CHAPTER OBJECTIVES

R Classi cation of present-day computers and their application areas.

1.1 INTRODUCTION
In the very early days of computers, common people had an illusion about its capabilities, that it can

do anything and everything (as if, it can perform any miracle like: the Indian Rope Trick!). Of course,

these false notions about computers were observed only in those people who were quite far away from

the real application areas of the machine.

However, even among a few present-day people, the general awareness about the overall work-

ing mechanism of computer is not very clear, although these people may be observed using their own

laptops. They use touch pads or pen drives without the knowledge of how these units function.

Knowledge of computer architecture and organization is essential to those who belong to Computer

Science or Information Technology streams. However, this does not indicate that others should not peep

into these secrets. A computer is a tool for general purpose and any one using it (or may use it) should

know about its basic working mechanism. The subject, which deals with these details, is known as

Computer Architecture and Organization.

2 Computer Architecture and Organization

T HO
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Do not be surprised if you overhear two naïve persons discussing about computer architecture

and organization in the following manner:

Person 1 : What is this organization about?

Person 2 : It decides about the layout pattern of the keys on the keyboard.
 Person 1 : And what is the architecture?

Person 2 : Design of the chassis of the system.

1.1.1 Difference Between Architecture and Organization

At this juncture, it is expected that these three terms, namely, computer, architecture and organization,

should be de ned. In a straightforward manner, this may be done by presenting the simplest de nitions

without jumping into any controversy. A

computer may be taken as an electronic instrument capable

of very high speed numerical calculations and carry out some speci c control operations, completely

depending on the software, which it would be executing. Computer architecture deals with broad or

overall design issues related with it, whilecomputer organizationmeans the electronic implementation

(or details) of the architectural modules. Therefore, a computer cannot be a substitute for hot pancake,

computer architecture does not mean how the manufacturer’s logo is printed on the laptop or computer

organization does not imply what should be the layout of a QWERT keyboard.

To elaborate the difference between computer architecture and computer organization, we may con-

sider a simple example. Let us assume that for a new computer, ongoing with its design and development

stages and yet to be manufactured and marketed, its designers consider about the provision of its exter-

nal bus to offer the facility for its user to interface some external devices. The type of such a bus and its

signal details are nalized from the architectural considerations. However, whether there should be any

external pull-up resistors, or noise-reduction capacitors or buffers for that bus, would be an organizational

issue. Broadly speaking, reduced instruction set computing (RISC) and complex instruction set comput-

ing (CISC), pipeline, multiple instruction, multiple data stream (MIMD) and single instruction, multiple

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This discussion reminds me the following conversation between two persons regarding the

difference between architecture and organization.

–‘Can you please draw a clear demarcation line between architecture and organization?’

–‘No. I can only place at either side if someone draws a line.’

–‘That would also do.’

–‘But someone should first draw a line without any thickness.’

 Introduction 3

Figure 1.1 Schematic representation of a computer

data stream (SIMD) and so on are architectural issues. On the other hand, memory, input/output (I/O)

and control unit (CU) are organizational issues. Finally, if we observe the computer evolution closely,

it may be concluded that there is a grey area between architecture and organization whose width is

steadily increasing due to rapid development of latest technology. In other words, in certain cases (e.g.,

data path design), the domains of architecture and organization overlap each other.

1.1.2 Essential Architectural Features of a Computer

Essential architectural modules of any computer, in general, are represented through Figure 1.1. All arith-

metic and logical operations are performed by the arithmetic-logic unit (ALU) and we would design one

such ALU in Chapter 3. The CU is responsible to carry out all control operations, which we would study

thoroughly in Chapter 10. Modern day processors are a combination of ALU and CU, to be discussed in

Chapters 5 and 6. The storage unit (commonly designated as memory) helps to store information in the

form of data and instructions and would be covered in Chapter 7. Finally, the Input–Output module in-

terfaces with the external world and with the remaining support devices, are the main topics of Chapter 8.

If we study carefully, we shall nd that the architecture of computers has not changed much. This

may be proved by comparing a latest personal computer (PC) or workstation with one of the earliest

computer in operation. However, its organization had undergone very rapid and substantial change (and

is still changing). This demands a lookback to its past and a brief discussion about the history or evolu-

tion of computers.

1.2 HISTORICAL BACKGROUND

The present generation of computer users (may be referred as laptoppers) have very limited idea about

the salient features of computers used about 30 or 40 years before. The present author had the privilege

to use such a system during the years 1982 and 1983, which accepted programs (only FORTRAN was

available and allowed at that time) in the form of punched cards and can only be run by batch process-

ing (through its operator). However, believe it or not, they were the improved versions of their earlier

incarnations, as described below. A time-line of these improvements is represented through Figure 1.2.

1.2.1 Mechanical Computers (Calculators)

The rst effort to fabricate a mechanical calculating machine was made by the famous European scien-

tist, Pascal, as back as 1642. That mechanical device was only capable of addition and subtraction and

may be considered as the rst step towards automatic computing. A few years later, famous German

mathematician, Leibniz, fabricated an improved version of this mechanical calculator, which could also

perform multiplication and division.

4 Computer Architecture and Organization

Figure
Time-line
1.2 of improvements in computers

About 150 years later, in early nineteenth century, contribution came from Charles Babbage, a

professor of mathematics, who planned two computers: Differential engine and Analytical engine. The

overall architecture of his analytical engine was very much similar to our modern computers. Unfortu-

nately, he was not able to prepare any working model of either of his designs, due to various reasons.

1.2.2 First Generation (Vacuum Tubes)

Whatever we have discussed so far may not be designated as true computers in a strict sense, as all those

were mechanical devices and not electronic machines. The real era of (electronic) computers began with

the introduction of vacuum tubes, and these computers are now designated as rst-generation comput-

ers. The era of these rst-generation computers may be taken approximately between 1945 and 1955.

Electronic numerical integrator and computer (ENIAC) was one of the pioneers in this series and

was introduced around 1946. It was made with vacuum tubes and relays having multi-position manual

switches and jumper cables for connecting with different sockets. Its volume was large, weight was

huge and power consumption was substantial with respect to present-day PCs and laptops. To have a

rough idea for the purpose of comparison, it may be suf cient to indicate that it occupied about 150 m 2

of oor area, weighing about 30 tons and consumed near about 140 kW of power. Fabricated with more

than 18,000 vacuum tubes, its original purpose was to help the US military to prepare the trajectory

tables for their artillery. Although for its delay in completion it was never used for that purpose, how-

ever, it was successful in creating awareness and generating interest in the development and usage of

similar electronic computing machines and may be accepted as the pioneer.

T HO
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Surprisingly, nowhere the name of Leonardo Da Vinci was mentioned related to any contribu-

tion in computing or computers. It is difficult to believe that the person, who had made original

contributions in so many diverse fields of science and engineering, did not pay any attention to

automated computing.

Introduction 5

Figure
Schematic
1.3 of the IAS computer

Surprisingly, ENIAC depended on decimal representation rather than binary representation. To rep-

resent a digit of, e.g., a decimal integer, ENIAC depended on a group of 10 vacuum tubes, each one

representing a decimal number between zero and nine. Out of these 10 vacuum tubes of the group, only

one must be on, representing that number and others must be off.

Next important landmark, in that era, was the contribution from John Von (pronounced as fon and

not as bhon) Neumann, working at the Institute for Advanced Studies of Princeton Institute – the IAS

machine. It is interesting to note that the basic architecture used in his machine is still being followed in

most of the modern computers. His design contained ve basic modules (Figure 1.3), namely

R Memory
R Arithmetic-logic unit
 R Control unit

R Input

R Output

As we know, in present day computers, the ALU and the CU are merged together forming the

microprocessor or simply processor. The reader may compare Figure 1.3 with Figure 1.1 and form his/

her own impression.

In the case of ENIAC, the method of altering or changing any program was a laborious job. Von

Neumann, along with Alan Turing, developed the improved scheme of storing the executable program

in the memory of the computer, ushering a new era of computer architecture. The IAS machine was

commissioned around 1952.

It might be interesting to readers that the present computer giant, IBM, did show very little interest

in these computing machines, like ENIAC. However, as late as in 1953, IBM offered its rst computer,

TH
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In early days, they were known as microprocessor. However, with their rapid growth in their

capabilities, nowadays, they are designated simply as processor.

6 Computer Architecture and Organization

namely 701. This was a 36-bit word machine with 2,048 words of memory. At some later date, IBM

introduced 704 with improved computing power, having a memory size of 4,096 words.

1.2.3 Second Generation (Transistors)

After the invention of transistors from Bell Labs in 1947, all vacuum tubes of computers were quickly

replaced by these transistors making their size smaller and increasing their ef ciency as well. These

transistorized computers are designated as second-generation computers, which lasted roughly for the

subsequent 10 years, that is, from 1955 to 1965.

Programmed data processor-1 (PDP-1), from digital equipment corporation (DEC), may be taken

as one of the milestones during this period. PDP-1 may be designated as the rst minicomputer, which

was available in the market. With its 512 ⫻ 512 pixels display screen, its memory was composed of

4,096 locations, each location of the size of 18-bits. Although its speed of instruction execution was

only 2,00,000 instructions per second, which was about half of the then fastest computer from IBM,

that is, IBM 7090, PDP-1 succeeded in securing a place in the computer market because of its cheaper

price tag.

A few years later, the successor of PDP-1, namely PDP-8 came into market. This was a 12-bit machine

from DEC with an improved performance. Omnibus was the major contribution of PDP-8, which

interconnected, for the rst time in the history of computers, the processor with all its peripherals. With a

lower price tag than PDP-1, PDP-8 was able to establish itself as the leader of minicomputers in the world

market. DEC continued with its PDP series and presented PDP-11, which is described in Section 1.2.4.

Meanwhile, IBM continued improvements of its 700 and 7000 series computers, which dominated

the computer market. This version was designated as 7090, which, at a later stage, was improved to

7094. From the fact le, we nd that 7094 was a 36-bit word machine offering 32,536 words of core

memory. Another smaller machine from IBM, namely 1401, became very popular to those who were

less interested about number crunching but more interested in record keeping.

Almost at the end of this era, in 1964, we encountered another superb machine, called 6600 from

Control Data Corporation (CDC), whose designer was Cray, another computer genius. This machine,

6600, was much faster than IBM’s 7094, because Cray implemented parallel processing with multiple

processors. At a later date an improved version of 6600, designated as 7600, was available. CDC and

Cray continued further improvements and innovations to launch the famous computer at that time,

namely Cray-1.

1.2.4 Third Generation (Integrated Circuits)

Meanwhile, after the introduction of transistors, the silicon industry started growing rapidly resulting in

integration of more and more transistors and other discrete components (like resistors and capacitors)

in a single chip. Initially, the number of discrete components was lesser and the process was designated
as small scale integration (SSI). As the time elapsed, more and more components were incorporated
 within a single chip and the designation changed to large scale integration (LSI) and very large scale
integration (VLSI).
In the early 1960s, Gordon Moore, co-founder of Intel Corporation, observed and commented that

the number of transistors within the same wafer area becomes double every year, which is now referred as

the famousMoore’s law. Moore predicted that the trend would remain stable for some time. However, it is

interesting to note that the trend remains unchanged even till today (Figure 1.4). This indicates that, without

changing the wafer-size, more and more complex functions may be accommodated within the ICs.

Introduction 7

Figure 1.4 Increase of number of transistors/IC and timeline of microprocessors

Improved versions of computers, fabricated with these SSI and LSI chips are designated as third-

generation computers. The throughput of these machines increased and the price became lesser so that

it started percolating to larger number of end-users. As far as the time scale is concerned, these third-

generation computers lasted between 1965 and 1985.

Two important machines of this era are IBM System/360, the mainframe family from IBM, and

PDP-8, the minicomputer from DEC. As a leader of computer manufacturers, introduction of System/

360 may be taken as a very bold decision from IBM. So far it had been marketing two popular machines,

serial I/O processor 1401 and giant number cruncher 7094. However, they were widely different in their

con gurations and operations including programming. In System/360, IBM merged together these two

machines to offer a single product line with upgradeable features so that, depending upon the growing

need of any customer, a suitable model of System/360 may be adopted. Thus, what was offered was

not a single machine but a family of machines. System/360 offered different models, e.g., Model 30,

Model 40, Model 50, Model 65 and Model 75.

As mentioned in Section 1.2.3, DEC introduced PDP-11, the 16-bit machine with byte-oriented

memory and word-oriented registers. It was highly appreciated and used in universities, and DEC con-

tinued to be the market leader of minicomputers.

1.2.5 Fourth Generation (VLSI)

Finally, we are ushered into the era of VLSI chips and became habituated with the usage of PCs, which

are marketed with still more improved ef ciency at a reduced factory price. All these were possible

because one the then smaller organization, Intel, introduced its rst microprocessor (Intel 4004) in

the early 1970s. The success of this resulted in a series from Intel and its 8-bit microprocessor – 8080

offered powerful features, suf cient enough to dream about small PCs.

One such unit was Apple (Apple, Apple II, Apple Macintosh) and another one was TRS-Radio

Shack. A third one wasBBC MICRO. All these were immensely popular and widely used at their times.
 8 Computer Architecture and Organization

Meanwhile, observing the success of these smaller units, IBM launched, in 1981, its now famous IBM

PC, with Intel 8088 (a truncated version of Intel 8086) as its driving force, which became a legend.

Meanwhile, operating system started gaining its own importance and a little known company, named

Microsoft, started contributing in this area, starting with MS DOS. The rapid growth and popularity of

these two organizations, namely Intel and Microsoft, is now well-known to all. As on one hand, the mar-

ket started receiving more and more powerful microprocessors, e.g., 80186, 286, 386, 486 andPentium

series followed by Core 2 Duo, on the other hand, it received more powerful operating systems like

OS/2 and Windows (several versions).

Another side of this technological advancement was re ected throughmicrocontrollers, the so-called

computer in a single chip. While microprocessors needed support devices to become a functional sys-

tem, microcontrollers, on the other hand, were designed for standalone operations. All these resulted

in a variety of computers for different applications, which we shall discuss in the following sections.

1.3 CLASSIFICATION
Like all other items, computers may be classi ed in different ways depending upon various attributes,

e.g., price, performance, power consumption and so on, to name a few. However, in this section

we classify these machines according to their usage (Figure 1.5). In this classi cation, we are not

including very small and very large computers. This very small variety may be located in devices like

smart cards and very large variety are designated as supercomputers. Supercomputers are very large

computers in the form of memory space and operating speed. They are, generally, used for number

crunching and simulation studies in bigger organizations, like business houses or universities. If we

do not include these two ends of the spectrum, then we may classify the rest in one of the following

categories.

1.3.1 Embedded Systems

Starting with our mobile handsets, these embedded systems we can locate almost every corner around

us, e.g., ipods, automatic weighing machines, digital cameras, robots and so on. They are essentially

controlled by some type of microcontrollers, which are, as already indicated before, single-chip com-

puters and contain all necessary hardware and software to run the system for which it is programmed.

These tiny computers are generally not capable of executing any user program, which our PCs

can. However, they are capable of running the system designated around them. In most of the cases,

they are battery or solar cell operated, consuming extremely less power. Their memory size and

speed of execution are also at lower levels. Yet, they are essentially computers as they can compute

electronically.

Figure
The1.5
computer spectrum

Introduction 9

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Computers available in mobile handsets may be designated as nail-tops or finger-tops to fit

with other available ‘tops’. Maybe in the near future we would be using nerve-tops or tip-tops!
1.3.2 Personal Computers (PCs)
Desktops, laptops, palmtops and all other tops belong to this category. Essentially, they are capable of

executing user’s software as they are equipped with some type of operating system (Windows or Linux

in most of the cases). Inside these PCs, we would be able to locate some microprocessor (or proces-

sor), which are more powerful and interfaced with larger size of memory than the previously described

embedded systems. Price-wise, also, they are more expensive than the embedded systems and consume

more electrical power to be functional.

Personal computers are characterized by their ability for extensive user-interaction, which is not

offered by other larger computers, e.g., servers, mainframes or supercomputers. This user-interaction is

not limited to interactive video games but also extended to program development, spread sheets, graphi-

cal editing and also word processing. However, essentially these PCs are single user systems.

1.3.3 Work Stations

Similar to PCs, work stations are also single user systems. However, they are more powerful with faster

processors, larger memory area, better graphics handling capability and, above all, they may be net-

worked, allowing restricted access to other users of the network.

1.3.4 Servers
Servers are not much different from PCs, excepting that their disc space, memory size and network-

communication speed vary. Generally, they are equipped with multiple processors for faster response

against requests of data communication. Like PCs, they also have a particular OS. Figure 1.6 shows

some of the internal features of Apple Mac server, including four disc-drive modules, RAM-cards and

its mother board.

Figure
Apple
1.6Mac. server (Courtesy: Macintel Solutions)

10 Computer Architecture and Organization

1.3.5 Mainframes
These computers have enormous amount of storage space in the form of discs and magnetic tapes

and much more I/O lines than normal computers or servers. They are generally used where very large

amount of data storage is required. Their size is also proportionately larger than other computers and

need special housing or larger rooms. Data sets are transacted in both ways to or from various locations

that may be thousands of kilometers away.

1.3.6 Looking Forward

This book is made up of 15 chapters and 6 appendices. In this chapter, we have been introduced to com-

puters, its evolution and certain classi cations. In the next chapter, i.e., Chapter 2, we take an overview

of computers using a top–down approach and discuss about some very essential hardware and software

requirements for it. We start with its external features and then move inside towards the motherboard

and then towards the processor, which has the main control over the entire system.

In Chapter 3, we discuss quickly about the essential concepts of digital logic, which are directly

related with computer hardware. All basic building blocks of computer, i.e., logic gates, ip- ops, reg-

isters, clocks, data ow control, ALU design and so on are discussed in this chapter. Note that whatever

hardware features discussed in this chapter offers a direct bearing to the CU design of the processor.

As all computers are basically meant for number crunching, representation and processing of num-

bers in various form play the most important role in computer design. Chapter 4 deals with computer

arithmetic, and all fundamental arithmetic operations of a computer are explained in this chapter. The

need for various instructions and operations are initiated in this chapter.
Microprocessors or processors are the heart of all computers and their basics are explained in
Chapter 5. Discussions were initiated as general discussions followed by examples from speci c pro-
cessors from Intel. Keeping in mind the expectations of students, examples are taken from Intel 8085,
8086, 8051 microprocessors and microcontroller. Thereafter, two of more advanced processors from

Intel, namely 80386 and Pentium 4 were used as example cases. This chapter concentrates on hardware

aspects of processors dealing with its internal architecture, register set, external signals, interrupts,

external memory interfacing and addressing techniques and related timing diagrams. Two major schools

of processor architecture designs, namely RISC and CISC are explained in this chapter with related

discussions on strengths and weaknesses of each branch of design considerations.

In Chapter 6, the discussions continued for the same set of processors, taking up the software issues

generated from the instruction set of these processors. As assembly language instruction set forms the

backbone of all processors, detailed discussions are presented on these issues with suf cient examples.

One of the important aspects of computer architecture, i.e., the instruction format, is explained here with

a complete solved example of instruction set design.

Memory units are essential for all computers and various memory related issues were discussed in

Chapter 7. It includes main and secondary memory, cache memory, virtual memory and so on. Access-

ing main memory directly is a frequently used technique by some peripheral devices. For this purpose,

DMA technique is explained in details in this chapter. Cache directory also plays another important role

in memory management and elaborated with suf cient details.

Chapter 8 deals with basic I/O organization of computers, including various types of bus structures.

Both polled as well as interrupt driven mode of I/O were explained using 8255 as an example device. Some

widely adopted bus architectures, e.g., USB, SCSI, HPIB and so on, are also explained in this chapter.

Next two chapters, Chapters 9 and 10 are very closely related. Chapter 9 introduces the microprogram-

ming and microarchitecture concepts, which are the fundamentals for the control operation of processors.
 Introduction 11

It deals with data path design and data ow control concepts and introduces the need of micro-operations for

a processor. The next chapter, Chapter 10, uses these concepts for the CU design of processors. In both these

chapters, several example cases are presented for easier understanding of the basic concepts.

The OS is one of the fundamental modules of computers and its essential features are introduced

in Chapter 11. Concept of a process, various scheduling issues and the need for critical section and its

handling through semaphores are introduced in this chapter.

The next two chapters, Chapters 12 and 13, are devoted for essential architectural features of all

modern processors, namely pipeline architecture and parallel processing. Pipeline architecture speeds

up the execution process and is adopted in all modern processors, which is the theme of Chapter 12.

Several common techniques like out-of-order execution, register renaming and speculative execution

are discussed in this chapter. In Chapter 13, the theme is superscalar architecture, which allows a pro-

cessor to execute multiple instructions simultaneously. Some details of Intel’s Pentium 4 processor are

presented as example cases in these two chapters.

As embedded systems are ooding the market and is considered as an integral part of computer systems,

Chapter 14 is devoted for some initial discussions on this topic. As an example for these issues, Atmel

Corporation’s AVR microcontroller (ATmega8) is taken up in this chapter. Internal and functional details of

some selected peripheral devices, commonly used with any computer system are discussed in Chapter 15.

Appendix A discusses some essential features of the number systems. In the following four appendi-

ces, architectural and organizational issues of four advanced processors are discussed. These processors

are SPARC and UltraSPARC from SUN Microsystems, Power PC from AIM, Core2Duo from Intel and

R4000 from MIPS Corporation. Except Intel’s Core2Duo, the remaining three processors are excellent

examples for pure RISC architecture. A project bank is given in Appendix F to conclude the discussions

with some exercises.

SUMMARY
Computers are electronic machines capable of number crunching and control operations, executing

them through the instructions of the software. Historically, they are categorized as rst, second, third

and fourth-generation computers, depending upon their essential electronic parts being vacuum tubes,

transistors, integrated circuits and VLSI chips, respectively. ENIAC was the rst electronic computer

followed by IBM 700 and 7000 series, PDP series, IBM System/360 series, Cray-1, Apple series, IBM

PC and so on. Considering their size, capabilities and usages, they may be classi ed as embedded sys-

tems, PCs, work stations, servers and mainframe.

Embedded system, generally, does not support any user program and runs mostly on battery power.

PCs are for user-interactive services while work stations provide better computing power than PCs.

Servers have larger disc space and memory, offering high speed data communication. Mainframes are

for massive record keeping and huge I/O processing at faster speed.

POINTS TO REMEMBER
R Computer architecture deals with overall design issues of a computer, while computer organization

deals with its electronic details for implementing these architectural issues.

R Computer organization has undergone much more transformation against time with respect to the

changes incorporated in computer architecture.

 12 Computer Architecture and Organization

QUICKSAND CORNER
I still remember when I was asked to write my that any program must be a general one and I should

rst high level language program by my teacher, use variables in place of 7 and 5 and add steps to

he said ‘Now write a program to add two integers, read those variables from keyboard as inputs.

like seven and ve’. Using pencil and paper I had The moral of the story is: Just like a program

been able to utilize my newly acquired program- must be capable in dealing with any type of data

ming skill in form of the following instructions: set and not a dedicated one, similarly a computer

must be able to execute any user program and

SUM = 7 + 5
should be a general purpose machine. Just by
PRINT SUM
observing at a keyboard and CRT terminal, the
END reader should not mistake the unit as a computer.

It might be innocent-looking input and monitoring

Immediately understanding my unique program-
devices for a rolling display sign board!!
ming knowledge my teacher patiently explained

REVIEW QUESTIONS

Target the Correct Option

1. Who was the rst person to invent mechanical 6. What was the major contribution of PDP-8?

calculating machine? (a) 12-bit memory (c) Omnibus

(a) Babbage (c) Von Neumann (b) parallel processing (d) none of these

(b) Pascal (d) none of these

7. System/360 from IBM was the rst one to

2. Who invented differential engine? offer

(a) Babbage (c) Von Neumann (a) different models (c) GUI

(b) Pascal (d) none of these (b) Intel processors (d) none of these

3. What was the original purpose of fabrication 8. Microcontrollers contain inside the chip

of ENIAC? (a) solar cells (c) multiple CPUs

(a) Commercial (c) Military (b) complete computer (d) none of these

(b) Academic (d) none of these

9. Personal computers are characterized for their

4. The rst computer from IBM was made capability of performing excellent

with (a) number crunching (c) networking

(a) vacuum tubes (c) ICs (b) high speed I/O (d) none of these

(b) transistors (d) none of these

10. Mainframes computers are characterized for

5. PDP-1 computer was manufactured by their massive

(a) IBM (c) CDC (a) storage space (c) printers

(b) DEC (d) none of these (b) graphics terminals (d) none of these

Introduction 13

Find in Few Seconds

1. De ne computer architecture and computer changes with respect to time? What may be

organization. the reason for this?

2. What was the limitation of the rst mechani- 7. How does a workstation differ from a per-

cal calculating machine? sonal computer?

3. How the number system was represented in 8. Which organization introduced 4004 micro-
ENIAC? processor? When was it introduced?
 4. What was the specialty of the IAS machine? 9. What was the major problem of ENIAC
and who did solve it resulting in IAS
5. What are the differences between a super
computer?
computer and a mainframe?

10. What is Moore’s law? What do you think

6. Out of computer architecture and computer
about its validity?
organization, which one has undergone more

Spend Some Time Here

1. Why was IBM initially reluctant to enter the 6. How earlier computers performed without

computer market? any operating system?

2. Which invention, according to you, created 7. How many embedded systems you can iden-

more impact in computer industry, Transistors tify around you in your daily life? Prepare a

or Integrated circuits? Justify your answer. list of those embedded systems.

3. Which factor is more responsible for enhanc- 8. What is meant by smart cards?

ing the speed of modern computers?

9. Why 6600 was faster than IBM 7094?

4. Prepare a list of microprocessors/processors

10. What do you imagine about computers after
used in different computers. How many of
50 or 100 years from now?
these processors are known to you?

5. Name a few operating systems known to you.

How many of these operating systems were

used by you?
2

Overview of Computer

This chapter presents a broad introduction about computers. After completion of this chapter,

the reader would know about

CHAPTER OBJECTIVE

R Basic structure of computer hardware with its fundamental units

R General operational concepts of a computer

R Bus structure

R A few important modules inside a computer.

2.1 BASIC STRUCTURE OF COMPUTER HARDWARE

The external appearance of modern PCs is simple, attractive and well-known to all of us. It must have

a keyboard for instruction input—sometimes a mouse for quicker actions. The display unit is the most

prominent one, where we generally look for the output. In some cases, there may be a printer attached

with it, resting quietly at one corner. If it is not a laptop, then we can expect to nd a separate chassis,

housing the system, the source and destination of most of the interconnecting cables.

TH
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Because of BlueTooth and other Wi-Fi facilities, the number of these interconnecting cables

is decreasing nowadays. Wi-Fi is already available for internet connection and BlueTooth for

the mouse. In the near future, all other essential peripheral devices would also be interfaced

through wireless communications, eliminating the need of these interconnecting cables, for

which the chassis had been famous so far.

 Overview of Computer 15

We may come across a workstation in some designer’s of ce (or in residence), which might have

a larger display unit of higher resolution. There may be some additional peripheral devices attached

with the workstation, like a scanner or a digitizer or an XY-plotter. As we know, a scanner is capable

of generating a digital image of any drawing/photograph/text. Digitizer, on the other hand, echoes the

co-ordinate of the present position of the stylus in digital form. An XY-plotter is capable of producing

drawing on paper, using colour pens as per the commands transferred to it.

When one visits a chemical factory or any other factory, we may nd that the PC is attached with a suspi-

cious looking box from which plenty of wires are distributed to some unknown destinations. After a polite

query, we may be enlightened that the box is a multi-channel analog to digital converter (ADC), necessary to

monitor various operations of the plant or a digital to analog converter (DAC) for some control operations.

If we get a chance to see a mainframe of some bank (during its working hours and by prior permis-

sion from the authority), inevitably, our immediate attention would be drawn to the array of large, circu-

lar magnetic tape drives, which are mostly stationary but sometimes rotating in irregular fashion. The

appearance of the mainframe may not be as impressive as these dynamic units.

ADC/DAC

Figure 2.1 A computer system with some peripheral devices

In this so-calledconducted tour, we may come across many external devices, which are interfaced with

the computer to cater to various demands (Figure 2.1). Computer is a tool for general purpose, which may

be upgraded to suit some particular purpose of the user. If we are interested to know how this computer

functions, we need to locate and study its fundamental units, which we are about to discuss now.

2.2 FUNDAMENTAL UNITS

Let us assume that we have opened the chassis of an IBM PC. What do we nd inside? A big printed

circuit board (PCB) called the motherboard, and a few individual boxes (Figure 2.2). These boxes are

16 Computer Architecture and Organization

Figure 2.2 Some internal features of a computer

switching mode power supply (SMPS), hard disc drive (HDD) and optical disc drive (ODD). We also

discover a lot of wires and cable connections connecting from one unexpected corner with another.

2.2.1 HDD and SMPS

The HDD, as we know, is meant for storing data or program. They are called secondary memory and is

generally used as mass storage devices. The SMPS can be ignored at present, as its only duty is to cater

to various power requirements for the computer. Therefore, what remains is the motherboard, which

carries out the real functions of the computer.

2.2.2 Motherboard
At a rst glance, the motherboard may be taken as an extremely complicated hardware assembly. De nitely,

it contains plenty of discrete components of various sizes and shapes (Figure 2.3). However, its heart is

the processor or central processing unit (CPU), which, depending upon the model of the PC, may be of

various types. If it is the rst IBM PC, you may expect Intel 8088 in its 40 pin dual in-line package (DIP).

For an advanced one, like PC/AT, you would get a 386 processor. In more advanced models, you would

be able to locate a Pentium processor. In Chapter 5, we shall have a detailed discussion about this CPU.

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Opening the chassis of a working PC is not recommended, in general. It should be done by a

professional expert. Any discarded old PC may be opened. But remember to disconnect its

power supply, if it is operational and wait for at least 15 minutes. Its display unit must be

disconnected before any such investigations are carried out. Never try to open the display unit

of a computer. Neither should you venture to open an SMPS. This might be lethal.

Overview of Computer 17

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We have encountered two terms, main memory (primary memory) and secondary memory. The

most important point is, program residing in the main memory may be directly executed by the

processor. However, program residing in secondary memory must be loaded to main memory for its

execution. No processor is able to directly execute any program residing in secondary memory.

Another point we should keep in mind is that the time required by the CPU for data com-

munication with secondary memory is much more than that required for communication with

main memory.

Next important item is the main memory. Within the motherboard, we may locate two types of

memory, RAM and ROM; both belonging to the class of primary memory or main memory. In Chapter 7,

we shall have a detailed discussion about the memory system. However, at this stage, we shall only

point out that the ROM, which is a non-volatile memory, is necessary to accommodate the starting-up

software for the computer. The RAM, generally in the form of a RAM-card in present generation PCs

and in the form of array of ICs on the motherboard itself for old IBM PCs, is provided for all other

temporary storage during its operational stage.

Figure 2.3 Some details of a computer’s motherboard

Other important devices, scattered around the motherboard are interrupt controller, universal syn-

chronous asynchronous receiver transmitter (USART), programmable peripheral interface (PPI), timers

and counters, to name a few. The remaining major devices are hard disc controller, bus buffers and bus

drivers, graphics adopters and so on. Finally, we must mention the array of large plug-in sockets, where

extra service cards may be plugged-in to enhance the capability of the machine. Essentially, these sock-

ets offer the system bus, which we shall discuss shortly. The major question to be answered at this stage
 18 Computer Architecture and Organization

is, how so many devices function properly and concurrently? For that, we have to investigate the basic

operational concepts of a computer.

2.3 BASIC OPERATIONAL CONCEPTS

What is the duty of any computer when it is operational? As a matter of fact, there are two duties, as follows:

RExecute the software by fetching instructions from memory.

R Look for any external signal and react accordingly.

Both these duties are entrusted upon and carried out by the microprocessor (or processor), which is

the central controller of the whole system. The second part deals with eventual external interrupts or

other input signals, e.g., from keyboard or mouse, which will be discussed later. However, the major

duty of the processor is to run (or execute) the software, and this program execution is done continu-

ously until the computer is switched off. The question is how this execution is done? Several steps are

to be combined together to respond to this question. The following sections describe these steps.

2.3.1 Processor Clock

The heart of any processor is its clock, which starts almost the moment a computer is switched on (powered).

This clock is a simple digital signal producing on and off states alternately, at equal time intervals, as shown

in Figure 2.4. In this diagram, the X-axis indicates time and the Y-axis represent DC voltage. This oscillating

phenomenon generates two different edges of the clock signal, rising edge (positive edge) and falling edge

(negative edge). In Chapter 3, it would be explained how these edges or transitions may be used to increment

or decrement any binary counter. Presently, let us assume that the clock signal is capable of running this phe-

nomenon. Which counter is affected by this process? The answer is–the Program Counter.

Figure
Processor
2.4 clock

2.3.2 Program Counter

Inside every processor, there is a binary counter, known as Program Counter (popularly known as PC).
The width (number of bits accommodated) of this counter varies from processor to processor. However,
its basic operation is identical in all cases. With every falling edge (or rising edge, depending upon the
processor) of the clock signal, this counter is incremented by one.

TH
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Believe it or not, this simple looking clock signal of Figure 2.4 is the basic driving force for all types

of computers available on the earth. Stop this signal and not a single computer would function.

Overview of Computer 19

What purpose does this incrementing serve? Well, the content of the PC, the group of bits, is
immediately sent out to the memory area (main memory). This bunch of signals, which moves out from

the PC to the memory is known as address signal. What is its function? After reaching the memory section,

depending upon the pattern of the signal generated by combinations of 1s and 0s of different bits, it targets

one unique memory location. The content of that memory location is then brought within the processor. This

process is known as memory reading, and this is illustrated in Figure 2.5. In this diagram, the thick arrow

from the PC, representing multiple address signals, is directed to the memory, represented by the rectangle at

the right. Inside this memory unit, there are various address spaces (known as locations) and every address
space contains some data. To obtain or read any data, its address along with a memory-read command is
 necessary. It is the duty of the CPU to generate the read-memory command, which is designated as a control
signal. After receiving the address and read command, the memory unit releases the related data through the

data path, as shown by the thick arrow at bottom of the diagram. Note that the thick arrows indicate multiple

signals or a bunch of signals while the thin single-lined arrow indicates only one signal, like read-memory.

Figure 2.5 Reading from memory

2.3.3 Instruction Fetch

If we now assume that the original content of the PC was that address of memory, which contains the

executable program, then the memory reading by the above-mentioned process must be to fetch an

instruction of the program, and the procedure is known as instruction fetch. After completion of this

instruction fetch, the binary content of the memory location (instruction byte) is available within the

processor itself. It is needless to mention that in the next clock cycle the PC would be incremented by

one and the whole process would be repeated, as we shall see a little later.

2.3.4 Instruction Decode

Now the processor becomes busy with the instruction byte, freshly fetched from the memory, to

understand what it is all about. After all, for every instruction, the processor must do something special

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The direct relation between the total number of instructions offered by the processor and the

time required to decode had resulted in two different processor types—reduced instruction

set computer (RISC) and complex instruction set computer (CISC). We shall deal with this

topic in Chapter 5.

20 Computer Architecture and Organization

as per that instruction. This concept of understanding

‘ the instruction’ is also known as decoding the

instruction or instruction decode. The more the total number of instructions offered by the processor,

the more complex would be this instruction decoding unit. At a later chapter, we shall be familiar with

the microprogramming and other techniques for instruction decoding and its execution.

2.3.5 Instruction Execute

From the instruction decoding module, after the processor knows what to do, it immediately starts to

carry out the order. This execution may be of various types, depending upon the instruction and the

processor, like

R Fetch an operand from memory or

R Add two registers.

Whatever be the job, once it is executed, the procedure, which started with the increment of

the PC, becomes complete. The cycle of incrementing PC and so on. is repeated, as shown in

Figure 2.6.
Figure 2.6 Major functions of a processor

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In earlier processors, fetching, decoding and executing occupied different time slots. In modern

processors, they overlap each other, which is known as pipelining. In other words, during

decoding or execution stage, some instruction fetch is carried out simultaneously. In Chapter 12,

we shall discuss about pipelining.

Discovering Diverse Content Through
Random Scribd Documents
opinione fu difesa dal Bianchi, coadiuvato nella parte archeologica
dal Prof. Lorenzo Re, i quali basarono la loro tesi:
1º Sulle regolarità dei pozzi, donde, dissero, uscivano le gabbie che
racchiudevano le belve.
2º Sul fatto che il podio era munito di «macchine versatili, reti e denti
lunghissimi sporgenti sull’arena» [825].
3º Sul passo di Erodiano [826], nel quale leggesi: ἀναῤῥιπτέιν
(sursum mittere, sursum iacere).
Il Bianchi prevenne l’obiezione che gli si potea facilmente rivolgere,
ricordandogli le naumachie narrateci da Suetonio e da Dione; e,
disprezzando soverchiamente e con poca equità la fama storica del
secondo, asserì che una sola naumachia ebbe luogo nell’Anfiteatro
Flavio; quella cioè che si diè ai tempi di Domiziano; ed aggiunse che,
anche ammettendo altri combattimenti navali, questi non
osterebbero alla sua opinione, imperocchè, dice, quattro piedi
d’acqua possono sostenere qualunque barca; e con ripari provvisori
si potè impedire che l’acqua penetrasse negli ambulacri e nei portici.
Il difensore della seconda opinione fu l’avv. Fea [827], il quale asserì
ostinatamente che l’arena del Colosseo non fu giammai sostrutta, e
che le sostruzioni che noi vediamo son opera dei bassi tempi, e
precisamente dell’epoca dei Frangipani. Il Fea procurò provare il suo
asserto coi seguenti argomenti:
1º Il podio, ammessa l’arena sostrutta, sarebbe stato alto appena
dieci piedi. Malgrado dunque le rotule, i denti e le reti, la sua altezza
era insufficiente a salvare gl’Imperatori, i Pretori, ecc. dai salti delle
tigri e dalla proboscide degli elefanti.
2º Un’arena sostrutta è affatto inadatta per le naumachie.
3º Finalmente il piano rinvenuto, disse, non può essere il vero e
primitivo livello dell’arena; ma questo devesi ricercare in maggiore
profondità.
Il Masdeu [828] tentò di conciliare le due opposte opinioni: scrisse a
questo scopo 21 lettere, ma ricevè ai suoi scritti un’acre risposta
dall’avvocato Fea [829].
Il Nibby, nelle Aggiunte al Nardini [830], propendè per l’opinione
difesa dal Fea; ma nella sua pregievolissima opera Roma nell’Anno
MDCCCXXXVIII cambiò d’opinione, e scrisse:
«Le testimonianze di Suetonio e di Dione apertamente dichiarano
che nell’Anfiteatro Flavio vi si diedero combattimenti navali sotto Tito
e sotto Domiziano. Stando.... ai fatti riconosciuti, e dando il peso
dovuto all’autorità degli antichi scrittori, parmi doversi stabilire, che
da principio, sotto Tito e Domiziano, quando vi si diedero giuochi
navali, l’arena era di livello più basso e non sostrutta; che Traiano
nel restauro fatto nell’Anfiteatro comprese ancora il lavoro di alzare
l’arena al piano attuale, per mezzo di sostruzioni regolari essendo
crollate pe’ terremoti avvenuti sotto Teodosio II e Valentiniano III nel
quinto secolo, e sotto Teodorico sul principio del sesto furono
risarcite secondo lo stile di quei tempi da Lampadio e da Basilio
prefetti di Roma; così si dà ragione della diversità delle costruzioni,
così pure si comprende HARENAM AMPHITHEATRI . . . . restituit,
e quella della lapide di Basilio: ARENAM ET PODIVM QVAE
ABOMINANDI TERRAEMOTVS RVINA PROSTRAVIT . . . .
RESTITVIT: così chiaramente s’intendono i passi di Petronio,
Erodiano e Calpurnio. Il primo nel Satyric. c. IX dice: non taces
gladiator obscoene quem de RVINA ARENA DIMISIT. Erodiano
raccontando le cacce date da Commodo appunto in quest’Anfiteatro,
così si esprime: λεοντων δε ποτε εξ ὑπογαιων ἑκατον αναρρ’
ιφδεντων, ισαριδμοις ακοντιοις παντας απεκτεινεν: ed una volta
essendo stati lanciati su dai sotterranei cento leoni con altrettanti
strali tutti li uccise: finalmente Calpurnio, ecl. VII, v, 69, esclama:

Ah trepidi quoties nos Descendentis arenae

Vidimus in partes ruptaque voragine terrae
Emersisse feras!

Il Lanciani, come altrove dicemmo, opina che, almeno fino dal

principio del secolo III, l’arena lignea fosse pensile sulle proprie
sostruzioni; ed aggiunge [831] che «Pausania nel cap. 12 delle
ΗΛΙΑΚΩΝ § 4, registra fra le grandi opere di Traiano in Roma, καὶ
Θέατρον μέγα κυκλοτερὲς πανταχόθεν [832], cioè l’Anfiteatro Flavio.
Dalla quale inesatta asserzione del geografo alcuni hanno voluto
trarre indizio di restauri avvenuti sotto l’impero dell’ottimo Principe,
dei quali non si ha altrimenti notizia. Il Nibby R. A. I, 421, suppone
che Traiano abbia costruito gli ipogei dell’arena, ma questa è
supposizione gratuita [833]. Sul piano dell’abaco di un capitello a
foglie d’acqua, caduto dal vertice dell’Anfiteatro in fondo all’arena,
rimangono le casse di nove lettere di metallo, alte m. 0,37 spettanti
ad iscrizioni monumentali:

«Il capitello, prosegue, è dei tempi bassi: e non reca maraviglia il

vederlo scolpito con masso di marmo appartenente a più antico
edifizio, forse all’arcus divi Traiani della region prima, le spoglie del
quale servirono ad abbellire il vicino Arco di Costantino» [834].
Il Canina, finalmente, congettura che la costruzione dei muri degli
ipogei suddetti sia dell’epoca di Severo Alessandro.
Alle varie opinioni già esposte mi sia lecito aggiunger la mia.
La sostruzione dell’arena è talmente necessaria ad un anfiteatro,
che se questo ne fosse privo, perderebbe, quasi direi, la sua
speciale caratteristica. Immaginare infatti un edificio anfiteatrale
senza gl’ipogei dell’arena, sarebbe lo stesso che immaginar un
corpo animato senza gli organi interni. La vita, dirò così,
dell’anfiteatro si svolgeva negl’ipogei, e si manifestava sull’arena; e
non mi sembra plausibile l’opinione o la supposizione che
Vespasiano abbia voluto erigere il suo celeberrimo Anfiteatro senza
l’arena sostrutta. Poteva per avventura mancare nell’Anfiteatro per
eccellenza, costruito in pietra, e, giusta l’idea d’Augusto, media urbe,
ciò che ebbero fino i temporanei che lo precedettero? Petronio,
scrittore dei tempi Neroniani, dice: «non taces gladiator obscoene,
quem de ruina arena dimisit?» e poco dopo: «ergo me non ruina
terra potuit haurire . . . . . . . . aufugi iudicium, arenae imposui» [835].
Io opino adunque che l’arena fosse sostrutta fin dal principio, e che
avesse un livello più basso di quello a cui fu poi elevata.
Sennonchè, a cagione delle naumachie (le quali positivamente si
rappresentarono due volte nel nostro Anfiteatro), l’arena fu da prima
sostrutta stabilmente con muri, oppure con un’armatura lignea da
potersi rimuovere all’occorrenza? La seconda ipotesi è inammissibile
per molte ragioni, che credo qui inutile addurre perchè gli scavi
decisero la questione.
Nei muri degl’ipogei si sono rinvenuti avanzi tuttora al posto di massi
regolari di travertino e tufo, che sono la materia adoperata in
grandissima copia nella costruzione dell’Anfiteatro, e specialmente
nei siti ove richiedevasi maggior solidità. I due portici esterni sono
stati costruiti di pietra tiburtina, ed i muri che nel piano terreno
formano i cunei delle scale e dei passaggi, sono composti
d’intelaiature di massi di travertino, racchiudenti specchi in
parallelopipedi di tufo. Di questo parere fu eziandio Lorenzo Re, il
quale, nelle sua Illustrazione e difesa delle Osservazioni
dell’architetto Pietro Bianchi sull’arena e sul podio dell’Anfiteatro
Flavio, dice: «Fig. 8, 9, 10. Porzioni delle sostruzioni dell’arena in
bellissima costruzione di grandi pietre rettangolari uniforme
perfettamente alla generale costruzione dell’Anfiteatro» [836].
Se le sostruzioni dell’arena avessero potuto o no impedire
l’esecuzione delle naumachie, lo vedremo allorquando si parlerà di
queste.
Gli scavi, oltre all’averci indicato negli avanzi dei muri primitivi
l’originaria sostruzione stabile dell’arena, ci hanno pur anche
manifestato l’antico suo livello.
Il muro di perimetro dell’ipogeo ha in ogni quadrante dell’ovale una
serie di otto grandi nicchie arcuate, a fondo piano, larghe m. 3 e
profonde oltre un metro [837]. Dalla fronte di ciascuno dei trentasei
piloni che sostengono gli archi, sporgono due mensoloni di
travertino, i quali si trovano 3 metri circa sotto il livello attuale
dell’arena: tra una mensola e l’altra, nella fronte del pilone, v’è
un’incavatura verticale, a piè della quale è murato un masso di
travertino, lungo quanto è grosso il pilone; l’incavatura poi sarebbe
atta a ricevere una trave (V. Fig. 9ª).
Dall’imposta degli archi in su, per tutto il giro dell’ovale, vedesi un
taglio praticato nella fronte delle nicchie: taglio, che riduce alla metà
circa la profondità delle vôlte, la sommità delle quali è ripresa (dove
più dove meno, secondo che occorreva) con archi di mattoni. Nel
fondo di ciascuna nicchia, dal piano superiore delle mensole in giù,
v’è un’apertura rettangolare, a guisa di piccola finestra, addossata al
pilone, larga m. 0,70 circa, la quale ha un grosso architrave di pietra
tiburtina.

Fig. 9.ª

Nella parte inferiore delle nicchie si vedono addossate ai piloni per

tutta la loro profondità due piccole spalle, sulle quali son gettate
volticelle a sesto scemo, terminate in fronte da archi. Le vôlte,
l’estradosso delle quali trovasi ora al piano inferiore delle mensole,
otturano, per la metà circa, l’altezza delle aperture ora descritte nel
fondo delle nicchie. La costruzione laterizia dei piloni e del fondo
delle nicchie è dell’epoca di Vespasiano, e quindi contemporanea
all’edificazione del monumento; mentre la costruzione degli archi
scemi, delle piccole spalle e della ripresa delle vôlte è discreta
anch’essa, ma d’epoca posteriore a quella dei Flavî.
Sarei di parere che il taglio nella parte superiore delle nicchie e le
volticelle sceme con le loro spalle riportate, sia un lavoro eseguito
contemporaneamente ai pilastri di opera quadrata di tufo, per
formare dietro di essi un passaggio.
Che le trentadue nicchie appartengano alla primitiva disposizione
della parte infima dell’Anfiteatro, oltre alla costruzione dei muri, ce lo
manifesta quella serie di pilastri che noi vediamo costruiti di massi di
tufo, collegati fra loro con architravi della stessa materia, i quali, a
breve distanza dalle mensole, si ergono fin quasi al piano attuale
dell’arena, disposti con regolarità fra loro, ma con nessuna rispetto
alle mensole stesse ed ai piloni retrostanti; dichiarandoci quei
pilastri, col complesso di tutte le circostanze concomitanti, che essi
furono costruiti posteriormente ai piloni, e che questi e le mensole
avevano a quel tempo perduto il loro scopo.
Io congetturo pertanto che, ai tempi di Vespasiano, sopra i
mensoloni fossero collocate orizzontalmente attorno attorno delle
grosse travi, sulle quali e sui muri di opera quadrata degli ipogei
riposassero altre travi che sostenevano il tavolato dell’arena. Posta
la mia supposizione, detratte dal dislivello che v’è tra il piano delle
mensole e quello dell’arena attuale (che è il medesimo dell’antica
rialzata) le grossezze delle travi e del tavolato, ne segue che il livello
dell’arena primitiva era più basso di quello dell’arena posteriormente
rialzata, di circa due metri, e che l’ipogeo ebbe in origine un’altezza
di circa tre metri e mezzo [838]. E siccome il podio nella sua primitiva
costruzione non fu più basso di quello che ora lo vediamo (poichè i
muri che sostengono la gradinata del podio suddetto e le scale che
conducevano al ripiano dei senatori, sono di assoluta costruzione
Vespasianea); così dovrà concludersi che il ciglio superiore del
parapetto del podio all’epoca dei Flavî distava dal piano dell’arena di
circa sette metri.
Disposte le cose in tal maniera, risulta pure che gli archi impostati su
i piloni rimanevano quasi del tutto fuori del livello dell’arena; ed io
credo che questi, muniti di grate, servissero verosimilmente a doppio
scopo: tanto, cioè, per dar luce all’ipogeo, quanto, e principalmente,
nell’esecuzione delle naumachie come a suo luogo vedremo.
Le incavature poi, che appariscono nella fronte dei piloni fra le
mensole dovettero servire, come giustamente osservò il Gori, a
ricevere le travi che sostenevano la grande rete.
Un rozzo graffito antico (V. Fig. 10ª) rinvenuto negli scavi eseguiti nel
1874 dal Comm. Rosa negl’ipogei dell’arena, ha tutto l’aspetto di una
rappresentazione della fronte primitiva del podio. Così anche parve
al Gori [839], e corrisponde, quasi direi, a capello col risultato dei miei
ragionamenti. È questo un frammento di lastra marmorea su cui si
veggono in graffito, una presso l’altra, cinque arcate di un sesto poco
inferiore al semicircolo, munite d’inferriate; sopra queste vi sono pure
in graffito linee che formano una transenna enorme relativamente
agli archi sottoposti; e sembra che in essa si sia voluto
rappresentare, in modo rozzamente convenzionale, la grande rete
del podio. Al di sotto delle arcate poi rimane la parte superiore di due
figure, le quali ci ricordano probabilmente i bestiarî. La riproduzione
che presento a Fig. 10ª è tratta dall’opera del Gori.
 Fig. 10.ª

Per ciò che riguarda il piano dell’arena, esso fu evidentemente

rialzato. Noi non sapremmo precisare l’epoca; ma possiamo con
ogni certezza affermare che ciò avvenne dopo il regno di Domiziano.
Pausania, nell’elenco delle opere fatte da Traiano, dice: «theatrum
magnum undequaque rotundum», ossia l’Anfiteatro Flavio. Varî
scrittori, basandosi su questo passo, opinarono che l’arena fosse
stata rialzata da quell’Imperatore. Ed invero, la serie di pilastri di
opera quadrata di pietra tufacea, che noi vediamo disposti
regolarmente a brevissima distanza dal primitivo muro di perimetro
dell’ipogeo (la cui costruzione ben s’addice ai tempi Traianei), e la
riflessione che, abbandonata dopo la morte di Domiziano l’idea della
naumachia nell’Anfiteatro, si fosse ben presto pensato a sollevare il
piano dell’arena, troppo profondo, affinchè gli spettatori potessero
godere completamente le rappresentazioni gladiatorie e venatorie,
sembrano favorire l’opinione di quei dotti.
L’espressione di Pausania però è troppo ampia, e fuor di questa,
come osserva il Lanciani, non se ne ha altrimenti notizia. Comunque
sia, dal complesso delle cose a me pare che l’arena prima
dell’incendio avvenuto nel regno di Macrino già fosse rialzata.
Molte parti dei muri dell’ipogeo si vedono risarcite in opera laterizia
di un carattere conveniente agl’inizî del secolo III. Questi restauri
furono fatti probabilmente da Eliogabalo e da Severo Alessandro,
dopo l’incendio. Vi si ravvisano poi evidentemente le riparazioni
eseguite nel secolo V da Teodosio II e Valentiniano III, ed i restauri
fatti da Teodorico sul principio del secolo VI.
L’idea finalmente proposta da alcuni, i quali vorrebbero che anche i
Frangipani abbiano fatto dei lavori nell’ipogeo, non mi pare possa
avere fondamento. All’epoca dei Frangipani l’arena era la piazza del
castello: ora perchè questa piazza fosse ben livellata non occorreva
altro che interrar gl’ipogei!...

Scoperta l’arena, si volle ricercare l’antica cloaca che dall’Anfiteatro

portava le acque al Tevere, passando per la valle del Circo Massimo.
Il lodato Fea [840] oppugnò questo progetto per essere, dice, «in
esecuzione difficilissimo e costosissimo per tanto tratto di strada».
Ideò invece di ripristinare la Mèta Sudante, e rendere con
quell’acqua e relativa costruzione di fontane un vantaggio ai cittadini
di quel rione. La spesa, secondo i calcoli del Fea e del muratore
Lezzani, sarebbero state tenuissime; grande invece l’utilità pubblica.
Nessuno di questi progetti fu messo in esecuzione; anzi nel 1814 il
Governo ordinò di ricoprire gl’ipogei, eccettuandone il passaggio di
Commodo.
Nel 1874, ad istanza del Comm. Rosa, si ripristinarono gli scavi nel
Colosseo [841].
A settentrione, sotto il podio, tornarono in luce i tre ambulacri
circolari, già scoperti dal Valadier; ed il Gori [842] s’affrettò anch’egli a
dare il suo giudizio sull’epoca di quei muri. «Questa costruzione,
dice, che poco si adatta colla regolarità usata nelle fabbriche del
primo impero, dimostra che gli ambulacri vennero edificati dopo il
terremoto del VI secolo (?), in un’epoca cioè in cui erano in
decadenza, per la irruzione dei barbari, tutte le belle arti» (V. Fig. 8ª).
Da quel che sopra si è detto giudicherà il lettore quanto sia giusto il
parere del Gori!...
Alla profondità di circa tre metri apparvero 32 delle 72 mensole di
travertino, sporgenti dai piloni delle nicchie poc’anzi descritte (V. Fig.
9ª).
In questo stesso scavo tornarono in luce i cripto-portici, il pavimento,
le bocchette [843], le scale, ecc., di cui già parlammo nel capit. III,
Parte I, ed i residui seguenti:
1º Varî rocchi marmorei, due dei quali di giallo antico.
2º Fusti di colonne, basi e capitelli.
3º Frammenti d’iscrizione, i quali riporteremo all’App. II di questo
lavoro [844].
4º Lucerne fittili, tra le quali una cristiana. L’Armellini [845] così la
descrive; «Fra la varia suppellettile tornata alla luce degli sterri
dell’arena nell’Anfiteatro Flavio, merita particolar attenzione una
lucernina cristiana adorna di storiche e pregevoli rappresentanze. La
lucerna, di cui io parlo, manca di circa una metà rimanendone
abbastanza conservato il disco sul quale si vedono effigiati i tre
giovani ebrei in atto di negare l’adorazione alla statua aurea di
Nabucco. Il concetto artistico è identico a quello che trovasi ripetuto
frequentemente nei sarcofagi cristiani ed anche in taluna delle pitture
delle romane catacombe. Più raro a trovarsi un tal soggetto è nelle
lucerne cristiane, ed è per questo che propongo all’attenzione dei
dotti cotesto non dispregevole cimelio, il quale può aggiungere alcun
lustro benchè assai tenue alle grandiose memorie cristiane del
Colosseo».
5º Sei basi di statue ed un bassorilievo rappresentante un coniglio
agguantato da una zampa di leone scherzante.
6º Nove teste di statue e sette lastre di marmo [846], le quali ultime
hanno uno speciale interesse per i graffiti che in esse scorgiamo.
Nella prima di queste lastre si vedono a graffito le cinque arcate, le
inferriate e la transenna, ecc., di cui sopra parlammo (V. Fig. 10ª).
Nel secondo graffito vi sono tracciati due gladiatori; l’uno è munito di
scudo quadrilatero, l’altro armato di coltello e rete, ed ambedue sono
galeati. In questa scena è forse rappresentata la lotta fra un Trace
od un Mirmillone con un Reziario, giacchè si scorgono assai
chiaramente il tridente ed il balteus [847]. V’è poi una lepre inseguita
da un cane; e più in basso un toro avente sul dorso una specie di
sella: scena che ci ricorda il sarcofago rinvenuto nel palazzo Fiano,
negli scavi eseguiti nel 1874-75.
In un terzo graffito è delineata la figura di un bestiario, avente nella
mano destra il venabulo e nella sinistra la mappa.
Il quarto graffito [848] rappresenta l’arena divisa in due parti. Nella
prima parte scorgesi un bestiario armato di lancia e lottante con due
orsi. Nella seconda, una fiera che trascina una corda, porta un palo
al petto e s’azzuffa con un’altra belva sciolta; mentre l’arenario,
appoggiando il piede destro sul dorso di una fiera, è per colpire con
la lancia un’altra belva fuggente.
Il quinto graffito, fatto in un masso di cipollino, rappresenta un atleta,
il quale colla destra stringe una palma, simbolo della vittoria [849], e
sul petto gli scende una doppia collana [850], torques gladatoria, da
cui pende un ciondolo [851] simile a quello che vedesi nel cippo di
Batone. Al sommo della pietra è scritto [FELICI] TER. L’atleta è del
tutto nudo, tranne il subligaculum, i calzari, ed alcune fasce alle
ginocchia. La figura fu incisa con grosso chiodo: ricordando il
PINGIT ZOZZO della Domus Gelatiana, direi, col Prof. Correra [852]
che questa figura e le altre sono scariphatae.
Nel sesto marmo v’è disegnata la testa di Diana, adorna di diadema
e con frecce in mano.
I diversi sterri ci restituirono finalmente una pietra, in cui è incisa
«una grossa palma, ed altrove, fra alcune palme, leggonsi dei nomi
di gladiatori od atleti come: HONORVS, QVINTIVS, sormontati dal
busto, e vi si scorge l’avanzo di una cartella ansata con le sigle
che potrebbesi leggere PALMA VICTORI FELICITER; e finalmente il
nome di VINDICOMVS» [853].
«Il Comm. Rosa, onde meglio far vedere le vesti, i calzari, le armi, le
fisonomie dei gladiatori, ecc., dipinse a nero l’incavo dei singoli
rilievi» [854].
Più tardi si scavarono le cavee delle fiere, e vennero scoperti gli
ambulacri della parte meridionale degl’ipogei dell’Anfiteatro; e si
misero a nudo le costruzioni laterizie e di tufo, nonchè le mensole di
travertino, simile a quelle del lato opposto. Oltre a ciò si rinvennero
altri capitelli e rocchi di colonne; nello stanzone poi che trovasi a
destra del cripto-portico orientale, e in due ambulacri dell’arena
furono trovate varie tavole di legno, le quali «o sono residui di
macchine o vi furono poste per togliere l’umidità del pavimento» [855].
Nell’ambulacro centrale, finalmente, si rinvennero grosse e lunghe
travi, rafforzate da travicelli messi a traverso, ora del tutto
scomparse.
Nell’Iconografia del suddetto Gori vediamo disegnate alcune
costruzioni che attualmente non esistono. Questa mancanza si deve
al direttore di quegli scavi, il quale «troncò quei muri, credendoli più
recenti; spezzò i massi di tufo che trovò rovesciati al suolo, e li
asportò dall’Anfiteatro» [856].
Essendo Ministro della Pubblica Istruzione il Prof. Guido Baccelli,
s’intrapresero, di concerto coll’amministrazione comunale di Roma,
grandiosi lavori di sterro [857], onde la parte esterna e più conservata
dell’Anfiteatro Flavio possa essere ammirata in tutta la grandezza
delle sue proporzioni e nella magnificenza della sua architettura.
Gli scavi s’incominciarono sulla piazza che guarda la via di S.
Giovanni in Laterano, e precisamente dal punto corrispondente
all’estremità dell’asse maggiore dell’Anfiteatro; e furono continuati,
per una zona larga circa trenta metri, tutt’attorno al monumento.
Questi lavori diedero risultati di non lieve importanza; giacchè
tornarono in luce cinque degli antichi cippi terminali, dei quali già
parlammo nella PARTE I, cap. III; il lastricato di pietra tiburtina, che
girava intorno all’Anfiteatro e che costituiva una zona annessa al
lastricato stesso; nonchè il primitivo pavimento stradale, formato di
poligoni di lava basaltina.
«A Nord dello stesso Anfiteatro, sul declivio dell’Oppio, avvenne poi
un’altra importante scoperta. Alla distanza di m. 18 dal Colosseo e
allo stesso livello di questo, tornò in luce la strada che dalle Carine
dirigevasi al Celio, seguendo il corso della moderna via Labicana. A
Nord della strada rimane una serie di pilastri, costruiti in buon
laterizio, le cui basi poggiano sopra un grande masso rettangolare di
travertino. Sono decorati da mezze colonne, parimenti costruite con
cortina laterizia; ed in origine erano collegati da arcuazioni delle cui
imposte restano tuttora alcuni avanzi. Cotesto porticato, la cui
costruzione presenta i caratteri propri delle fabbriche della seconda
metà del primo secolo, trovasi sopra una linea parallela all’asse
maggiore dell’Anfiteatro, ed il suo punto medio corrisponde (quasi)
all’ingresso dall’estremità settentrionale dell’asse minore» [858].
Dopo gli scavi testè descritti, nessuna importante esplorazione, che
mi sappia, è stata intrapresa nel Colosseo.
 PARTE IV.
CONTROVERSIE SULL’ANFITEATRO FLAVIO.

CAPITOLO PRIMO.
Quest. 1.a — Nella dedicazione dell’Anfiteatro Flavio, ove si
celebrarono le naumachie?

Prima di rispondere a questo quesito e di presentare al lettore le

varie opinioni su questa scabrosa questione, mi sia lecito premettere
che ai tempi di Domiziano, fratello e successore di Tito, l’Anfiteatro
Flavio fu positivamente inondato, vi si fecero giuochi nell’acqua, e vi
si diedero indiscutibilmente battaglie navali. Gli epigrammi XXIV,
XXV, XXVI e XXVIII del libro Spectaculorum di Marziale, e le parole
di Suetonio [859] non ammettono obiezioni di sorta [860]. Ciò
premesso, diciamo:
Nelle solenni feste augurali date da Tito in occasione della
dedicazione della venerabile mole dei Flavî, l’arena anfiteatrale fu
inondata, e vi si eseguirono naumachie. Il fatto lo deduco dalla
narrazione di Dione [861] il quale scrisse: «E dedicando il teatro
venatorio ed il bagno che porta il suo nome, diè (Tito) molti spettacoli
e straordinarî. E molti gladiatori pugnarono a duello, molti in truppa
in battaglie terrestri e navali: conciossiachè avendo fatto riempire
all’improvviso quello stesso teatro di acqua, v’introdusse cavalli e
tori, ed altri animali mansueti ammaestrati a fare entro l’acqua tutto
ciò che erano assuefatti a fare sulla terra e v’introdusse sopra
barche anche uomini, e questi ivi combatterono divisi in Corintî e
Corciresi» [862].
La testimonianza di Dione trova un’eco nell’epigramma XXVIII di
Marziale [863]. Qui il poeta cesareo esalta enfaticamente l’Anfiteatro-
naumachia dei Flavî, dicendoci che in questa Mole si fecero tali
giuochi in acqua che nè nella naumachia d’Augusto nè nel Fucino nè
negli stagni neroniani si sarebbero potuti eseguire. Oltre alla corsa di
carri e alle battaglie navali, egli novera il manovrar dei quadrupedi
entro l’acqua, ed aggiunge che le dee marine Teti e Galatea avean
veduto fra le onde della Flavia naumachia, bestie a loro ignote:

. . . . vidit in undis
Et Thetis ignotas et Galatea feras;

le quali altre non furono che «i cavalli e tori ed altri animali mansueti,
ammaestrati a fare entro l’acqua tutto ciò che erano assuefatti a fare
sulla terra», come appunto ci dice Dione.
Sebbene i citati autori siano sufficientemente chiari nei loro scritti,
nondimeno alcuni, ad es., il Marangoni ed il Gori, basandosi sul
silenzio di Suetonio relativamente ai giuochi navali dati da Tito
nell’Anfiteatro in occasione delle feste inaugurali di quel monumento,
han dubitato dell’asserzione di Dione. Il primo [864] sostiene che la
battaglia navale rappresentata in Roma nella dedicazione del
Colosseo ebbe luogo unicamente nella vecchia naumachia; che
l’inondamento dell’Anfiteatro ed i giuochi, ivi dati nell’acqua e narrati
da Dione, furono eseguiti in altro tempo; e termina (vedremo con
quanta poca saggezza) rinnegando l’autorità del greco storico. Nè è
facile comprendere come egli (il Marangoni) abbia potuto riferire
l’ibidem di Suetonio [865] all’Anfiteatro, quando lo stesso Dione ci
attesta che, per dar nella vecchia naumachia ludi gladiatorî e cacce,
una parte del lago [866] fu coperta con tavolato e circoscritta da
steccati di legno.
Il Gori [867] s’oppone parimenti al passo di Dione, ed asserisce che
Tito non fè eseguire i giuochi navali nell’Anfiteatro, sibbene e
solamente nella vecchia naumachia. Impressionatosi egli della
piccolezza dell’arena inondata; pensando non esser possibile che in
essa vi si potesse rappresentare il famoso combattimento navale
descritto da Tucidide, il quale ebbe luogo nel golfo di Ambracia tra le
flotte dei Corintî e dei Corciresi; e credendo che nel nostro Anfiteatro
vi si fosse dovuta non imitare ma rappresentare assolutamente al
vero la summenzionata battaglia, viene a questa conclusione: «È
dunque assai più probabile il racconto di Suetonio: che, cioè, Tito
facesse eseguire tutti i combattimenti navali nella vecchia
naumachia alimentata dall’acqua alsitina nella valle di S. Cosimato in
Trastevere».
Il dubbio mosso dai citati scrittori non mi pare fondato;
primieramente, perchè il loro argomento è negativo, e quindi non ha
valore; secondariamente poi, perchè nel passo di Suetonio
quell’aggettivo applicato a munus in grado superlativo —
largissimumque — ha tale estensione da poter abbracciare i ludi
gladiatorî, navali e molto più. Che poi Tito abbia data in quella
solennità una battaglia navale nel Nemus Caesarum, ossia nella
vecchia naumachia, non esclude che quel Cesare l’abbia pur data
nell’Anfiteatro: anzi da quell’et (etiam) navale praelium in veteri
naumachia potremmo forse dedurre che la mente di Suetonio sia
stata appunto quella di volerci indicare che, oltre alla battaglia navale
eseguitasi nella vecchia naumachia, ne fosse stata data un’altra
nell’Anfiteatro Flavio, benchè in proporzioni tanto piccole da lasciarla
sottintesa. Ed invero: le lotte gladiatorie e le cacce di belve, date
nella suddetta naumachia di Augusto, adattate all’uopo in quella
circostanza, escludono forse il munus apparatissimum (almeno
gladiatorio e venatorio), che, per testimonianza dello stesso
Suetonio, si diè nell’Anfiteatro?
Il parere del Nibby [868] conferma la mia opinione. Ecco quanto egli
scrive a questo riguardo: «Dione serve di chiosa e dilucidamento a
Suetonio, e fa conoscere che questo scrittore non tenendo conto del
combattimento navale dato nell’Anfiteatro alluse a quello dato nel
Nemus Caesarum colla frase in veteri naumachia, giacchè ivi come
notossi fu la naumachia scavata primieramente da Augusto......
Quanto poi al combattimento navale dell’Anfiteatro fu una vera
parodia di quella de’ Corintii e Corciresi, descritta da Tucidide» [869].
In conclusione: l’esplicita testimonianza di Dione, l’allusione di
Marziale [870] e lo stesso silenzio di Suetonio, il quale con ogni
verisimiglianza può contenere un velato accenno, ci costringono a
ritenere che nelle feste d’inaugurazione date da Tito, l’Anfiteatro
Flavio fu inondato e vi si celebrarono naumachie.
Che nella naumachia di Augusto si eseguissero in quella stessa
circostanza battaglie navali, non v’ha dubbio. Gli storici antichi ce
l’attestano concordemente. Nella dedicazione dell’Anfiteatro,
dunque, si celebrarono giuochi in acqua tanto nella vecchia
naumachia quanto nell’Anfiteatro; anzi quelli celebrati in quest’ultimo
superarono, se non nella grandiosità nella singolarità, quelli eseguiti
nella naumachia di Augusto; tanto che Marziale potè esclamare
dell’Anfiteatro Flavio: «hanc unam norint saecula Naumachiam».
Sennonchè, se è vera la narrazione di Dione e quanto si deduce da
Marziale, l’Anfiteatro dovette fin dall’origine essere stato costruito in
modo da potervi dare all’occorrenza giuochi in acqua!....
Interroghiamo il monumento, e la sua risposta o smentirà Dione o lo
sosterrà.
Abbiam veduto nella Parte III, cap. V, come l’arena dell’Anfiteatro
Flavio fu stabilmente sostrutta fin da principio, e che il suo livello, in
origine più basso, fu poscia [871] sollevato. Abbiam veduto che il
tavolato dell’arena primitiva con la sua armatura in legname
poggiava sulle mensole di travertino che sporgono dai piloni, dei
quali è fornito il muro di perimetro dell’ipogeo, rimanendo perciò il
suo piano ad un livello più basso di circa due metri da quello
dell’arena rialzata; e deducemmo, per legittima conseguenza, che
dalla soglia delle due porte [872] vi dovette essere un piano inclinato
per discendere nell’arena.
Abbiam veduto che gli archi [873] impostati su quei piloni rimanevano
fuori del piano dell’arena poco meno della lunghezza del raggio.
Osservammo che nella parete di fondo di ciascuna di quelle nicchie,
dal piano superiore delle mensole in giù, v’era un’apertura
rettangolare a guisa di piccola finestra. Riscontrammo che le
volticelle a sesto ribassato, le quali tagliano a metà le nicchie, furono
costruite posteriormente, e che, in origine, eran queste vuote dal
piano dell’ipogeo alla loro cima (V. Fig. 9ª).
Nello studio del sotterraneo dell’arena osservammo uno speco (V.
Fig. 11ª) [874], il quale è situato sotto il pavimento del cripto-portico
(Tav. V, lett. K), e si eleva al di sopra del piano dell’ipogeo; si vide
che il sistema di cloache per lo smaltimento delle acque e delle
immondezze si trova sotto il piano dello stesso ipogeo; e che tutte
quelle cloache vanno a far capo ad una di maggiori dimensioni, la
quale gira attorno all’Anfiteatro [875]. Da questa cloaca dovette
certamente partire un braccio che andava a scaricare le acque nel
grandioso collettore emulo della cloaca Massima, il quale corre a piè
del Palatino, lungo la via che dall’Arco di Costantino conduce a S.
Gregorio [876].
La semplice esposizione della struttura della parte infima
dell’Anfiteatro mi sembra renda più che manifesto il pensiero di
Vespasiano: d’aver voluto, cioè, costruire la sua mole in modo che si
potesse a piacimento inondare. Lo speco anzidetto, come lo
persuade la sua orientazione e la sua elevazione rispetto al piano
degl’ipogei, fu con tutta probabilità destinato ad introdurre in questi
un grosso volume d’acqua, a tale scopo derivando dal castello di
divisione, situato sulla piazza della Navicella (per intero od in parte),
la quantità della Claudia condotta dal ramo celimontano, il cui speco
è largo m. 0,716, alto m. 1,633 fino all’imposta della volticella, che ha
m. 0,445 di freccia [877].
 Fig. 11.ª

Sul sito preciso di questo castello non può cader dubbio, avendolo il
Cassio individuato matematicamente con due coordinate — 90 passi
dal portone di S. Stefano Rotondo, e 30 dall’arco di Dolabella. —
Questo dotto scrittore ragiona diffusamente del castello suddetto
nella sua opera Corso delle acque antiche [878]. Ecco le parole con
cui intitola il capitolo: «Degli archi, sui quali condusse Nerone la
Claudia sul Celio diramandone un rivo allo stagno dell’aurea sua
casa. Questi non furono opra di Claudio. Delli bassi; si mostra il
Castello non osservato da moderni antiquari». Di questo lungo
capitolo recherò in NOTA i tratti che più c’interessano [879].
Se il Cassio avesse potuto vedere quello che fortunatamente abbiam
veduto noi, lo sbocco, cioè, di quel sotterraneo condotto all’estremità
dell’asse maggiore dell’Anfiteatro dalla parte del Laterano, ad un
livello superiore al piano dell’ipogeo dell’arena; si sarebbe
risparmiato l’improbo lavoro della ricerca di pozzi e conserve
nell’altipiano artificiale dell’orto dei religiosi del convento de’ Ss.
Giovanni e Paolo, per l’inondazione dell’Anfiteatro Flavio; ed
avrebbe senza dubbio ritenuto con noi che Vespasiano, il quale
risarcì appunto il condotto della Claudia, si servì dello speco
neroniano, che prima conduceva quell’acqua allo stagno, per
l’inondazione della sua magnifica mole.
Il Lanciani [880] giustamente nega che questo speco fosse (come si
credè quando apparve negli scavi del 1874) l’emissario dei
sotterranei dell’arena; ed io convengo pienamente con lui, ed
ammetto che le acque vi dovettero correre «dal Celio verso il bacino
del Colosseo». Convengo eziandio col ch. archeologo che quello
speco abbia servito per uso dello stagno neroniano; ma credo in pari
tempo che servisse ancora alla condotta delle acque per
l’inondazione dell’Anfiteatro; imperocchè nell’edificazione della Mole
Vespasianea lo speco non venne distrutto: ciò che si sarebbe fatto,
se più non serviva, a fine di evitare il considerevole ed incomodo
dislivello tra il piano del criptoportico e quello delle due lunghe
stanze adiacenti e del rimanente degli ipogei.
Quel che più poi mi conferma in questa opinione, si è l’orientamento
simmetrico di questo speco rispetto all’Anfiteatro; la qual cosa ci
costringe a ritenere o che Vespasiano orientasse l’Anfiteatro
relativamente allo speco, o che, con un nuovo braccio, torcesse
l’antico andamento di questo per farlo riuscire come ora lo vediamo,
vale a dire all’estremità orientale dell’asse maggiore; restando
sempre comprovato da quel fatto che Vespasiano si servì dell’antico
speco per l’inondazione dell’Anfiteatro. Anzi sarei di parere che
appunto lo speco che conduceva la Claudia allo stagno di Nerone,
dove si designò d’erigere l’immensa mole, sia stato ii movente nella
mente di Vespasiano di un teatro-naumachia.
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