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The document provides an overview of embedded systems, detailing their components, design levels, and specific concepts such as Register Transfer Level (RTL) and Hardware Description Languages (HDL). It also compares VHDL and Verilog, explains Configurable Logic Blocks in FPGAs, and discusses VHDL syntax and identifiers. Additionally, it includes practical exercises related to VHDL design and error identification in code.

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3 views

sheet1_ele 413_solution

The document provides an overview of embedded systems, detailing their components, design levels, and specific concepts such as Register Transfer Level (RTL) and Hardware Description Languages (HDL). It also compares VHDL and Verilog, explains Configurable Logic Blocks in FPGAs, and discusses VHDL syntax and identifiers. Additionally, it includes practical exercises related to VHDL design and error identification in code.

Uploaded by

eslambasyouni00
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Canadian International College

Faculty of Engineering ELE 413 Embedded Systems


Electronics & Communication Fall 2022/2023
Department.

Sheet1

1. What is an embedded system?


An electronic embedded system is a system that contains a combination of hardware and
software.

Hardware includes the processing unit (microcontroller or microprocessor), inputs, and


outputs.

The software which is loaded onto a microcontroller is a set of instructions that govern
how the system runs.

An embedded system is designed for a specific function or function of a self-contained


system or part of a larger subset of systems.
2. What are the levels of design description?

3. What is Register Transfer Level (RTL)?


In digital circuit design, register-transfer level (RTL) is a design abstraction which
models a synchronous digital circuit in terms of the flow of digital signals (data) between
hardware registers, and the logical operations performed on those signals.
A synchronous circuit consists of two kinds of elements:
Registers (Sequential logic) : synchronize the circuit's operation to the edges of the clock
signal, and are the only elements in the circuit that have memory properties.
Combinational logic: performs all the logical functions in the circuit and it typically
consists of logic gates.
4. What is CAD?
CAD learns how to design the hardware circuits in a professional way using VHDL
language.
5. What is HDL?
HDL (High Definition Language): is a language used to describe the hardware to a
computer and used to make :
1) Verification: to be sure the hardware work correctly.
2) Implementation: generate file after verification to be implemented on FPGA.
6. What is the difference between VHDL and Verilog ?

7. What is the difference between ASIC and FPGA?


8. What are the Configurable Logic Blocks (CLB) in FPGA?
Configurable Logic Blocks contain a number of slices according to their version.
Each slice contains a Lookup table (LUT), Shift registers, register, multiplexer, and
RAM.
Combinatorial Logic is stored in SRAM Look-Up Tables (LUTs) in a CLB.
9. VHDL divides the description of a module into an Entity and an Architecture section.
i. What is the purpose of each of these two sections?
The Entity section specifies the name of the entity as well as the names and types of its
input and output ports.
The Architecture section specifies the name of this architecture for a specific entity and
then contains either a structural or behavioral description of the entity.
Essentially, the Entity section specifies the interface to the entity and the Architecture
section specifies the functionality or composition of the entity.
ii. Would it ever make sense to have multiple alternative Architecture sections for a
single Entity section? Explain.
Yes. A behavioral description might specify the functionality of the entity for simulation
purposes, whereas a structural description might specify the composition of the entity in
terms of lower-level components for documentation purposes. Or alternative behavioral
descriptions might be written to explore tradeoffs between functionality and chip area.
10. What is a STD_LOGIC type?
VHDL uses the STD_LOGIC type to model represent logic values. It includes not only
values of 0 and 1, but also Z, U, X, –, L, W, and H which are needed for some designs.

11. Are statements in VHDL concurrent (like in AHDL) or sequential (like in C or Java)?
Explain.
VHDL statements are generally concurrent, with the exception of statements inside a
process, which are executed sequentially
12.
i. Which of the following are legal VHDL identifiers? 123A, A_123, _A123,
A123_, c1__c2, and, and1

123A illegal, starts with a number


A_123 legal
_A123 illegal, not allowed to place an underscore
as a first or last character
A123_ illegal, not allowed to place an underscore
as a first or last character
c1__c2 illegal, underscores side by side are not
allowed
and illegal, starts with reserved keyword
and1

ii. Which of the following identifiers are equivalent? aBC, ABC, Abc, abc
Basic VHDL identifiers are not case sensitive, i.e. upper- and lower-case letters are
considered identical, hence all given identifiers are equivalent

13. A full adder has the following truth table for its sum (S) and carry (Co) outputs in terms
of its inputs A, B and carry in (Ci).
Derive expressions for S and Co using only AND and OR operators. Hence write a VHDL
description of a full adder as a netlist of AND and OR gates and inverters.
14. Write a VHDL description of the following combinational circuit using concurrent
statements. Each gate has a 5-ns delay, excluding the inverter, which has a 2-ns delay.

15. Write a VHDL design entity that takes a five-bit input, input, and outputs a five-bit value
that is equal to the input with its bits reversed. For example, input 01100, gives output
00110 and input 11110 gives output 01111. You must implement your design entity
using a single concurrent assignment statement. You will need to use the concatenation
operator.
16. The following model code was produced to represent a 2-input NAND gate. It contains
several code errors. What are they?

i. nand gate is an illegal identifier, should be written as nand_gate


ii. Character ; after b in port statement should be a colon :
iii. Character missing after in BIT should be a semi-colon ;
iv. Character ; after c in port statement should be a colon :
v. entity not properly terminated should have end nand_gate;
vi. illegal identifier nand gate repeated in architecture statement
vii. Operator <= illegal after first else.
viii. Must end signal assignment activity statement with an else i.e., in this case, else ‘1’
ix. Activity statement must end with ; (before the end statement).
17. Write a VHDL description of a 3 → 8 decoder.

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