dlcaas2
dlcaas2
Name:Devika
Rollno:23691A2831
CstA
Detailed Explanation:
1. Purpose:
2. Characteristics:
3. Working Principle:
Hit: If the CPU finds the required data in the cache, it’s called a “cache
hit,” and data is fetched quickly.
Miss: If the required data isn’t in the cache, it’s called a “cache miss,” and
the CPU fetches it from the main memory, which is slower.
L2 Cache (Level 2): Larger than L1, slightly slower, located between L1
and CPU cores.
L3 Cache (Level 3): Shared among multiple cores, larger but slower than
L1 and L2.
5. Replacement Policies:
Random Replacement
3. List and briefly describe the different addressing modes used in the
x86 architecture?
1. Immediate Addressing
2. Register Addressing
The operand is in a register.
3. Direct Addressing
Example: MOV AX, [1234h] (Move the value at memory address 1234h to
AX).
4. Indirect Addressing
Example: MOV AX, [BX] (Move the value at the address stored in BX to
AX).
5. Indexed Addressing
Example: MOV AX, [BX + SI] (Move the value from the memory location
determined by BX + SI to AX).
6. Base-Indexed Addressing
7. Relative Addressing
8. Segment-Based Addressing
Uses segment registers (CS, DS, ES, SS) to specify a segment and offset.
Example: MOV AX, DS:[BX] (Move the value in the memory segment
pointed by DS and offset in BX to AX).