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Semiconductor Memories
IEEE PRESS
445 Hoes Lane, P. O. Box 1331
Piscataway, NJ 08855-1331

IEEE PRESS Editorial Board

John B. Anderson, Editor in Chief

P. M. Anderson R. Herrick R. S. Muller

M. Eden G. F. Hoffnagle W. D. Reeve
1\1. E. El-Hawary R. F. Hoyt E. Sanchez-Sinencio
S. Furui S. Kartalopoulos 0.1. Wells
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Dudley R. Kay, Director of Book Publishing
John Griffin, Senior Editor
Lisa Dayne, Assistant Editor
Linda Matarazzo, Editorial Assistant

Orlando Velez, Production Editor

IEEE Solid-StateCircuits Council, Sponsor

SSc-c Liaison to IEEE Press

Stu Tewksbury
West Virginia University

Technical Reviewers
Shri Agarwal
Jet Propulsion Laboratories

David Hoff
Cypress Semiconductor

Jim Kinnison
Johns Hopkins University

Rob Penchuk
Analog Devices
Semiconductor Memories
Technology, Testing,
and Reliability

Ashok K. Sharma

IEEE Solid-State Circuits Council, Sponsor

+IEEE
The Institute of Electrical and Electronics Engineers, Inc., New York

ffiWILEY-
~INTERSCIENCE
A JOHNWILEY & SONS, INC.,PUBLICATION
© 1997 THE INSTITUTEOF ELECTRICAL AND ELECTRONICS
ENGINEERS, INC. 3 Park Avenue, 17th Floor, New York, NY 10016-5997

Published by John Wiley & Sons, Inc., Hoboken, New Jersey.

No part of this publication may be reproduced, stored in a retrieval system, or

transmitted in any form or by any means, electronic, mechanical,
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10 9 8 7 6 5 4

Library of Congress Cataloging-in-Publication Data

Sharma, Ashok K.
Semiconductor memories: technology, testing, and reliability /
Ashok K. Sharma.
p. ern.
Includes index.
ISBN 0-7803-1000-4
1. Semiconductor storage devices. I. Title
TK7895.M4S491996
621.39'732-dc20 96-6824
CIP
Contents

Preface xi

Chapter 1 Introduction 1

Chapter 2 Random Access Memory Technologies 10

2.1 Introduction......................................... 10
2.2 Static Random Access Memories (SRAMs) 12
2.2.1 SRAM (NMOS and CMOS) Cell Structures . . . . . . . . . . . . . . .. 12
2.2.2 MOS SRAM Architectures 14
2.2.3 MOS SRAM Cell and Peripheral Circuit Operation 15
2.2.4 Bipolar SRAM Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . .. 17
2.2.4.1 Direct-CoupledTransistorlogic (DCTl) Technology................ 18
2.2.4.2 Emitter-CoupledLogic (Eel) Technology...... 19
2.2.4.3 SiCMOS Technology................................................................ 20
2.2.5 Silicon-on-Insulator (SOl) Technology 24
2.2.6 Advanced SRAM Architectures and Technologies . . . . . . . . . .. 28
2.2.6.1 1-4 Mb SRAM Designs 28
2.2.6.2 16-64 Mb SRAM Development... 32
2.2.6.3 Gallium Arsenide (GaAs) SRAMs 34
2.2.7 Application-Specific SRAMs 35
2.2.7.1 Serially Accessed Memory (Une Buffers) 35
2.2.7.2 Dual-Port RAMs 36
2.2.7.3 Nonvolatile SRAMs 38
2.2.7.4 Content-AddressableMemories (CAMs) 38
2.3 Dynamic Random Access Memories (DRAMs) 40
2.3.1 DRAM Technology Development 40
2.3.2 CMOS DRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.3.2.1 1 Mb DRAM (Example) 47
2.3.3 DRAM Cell Theory and Advanced Cell Structures . . . . . . . . . .. 50
2.3.3.1 Trench Capacitor Cells 52
2.3.3.2 Stacked Capacitor Cells (STC) 55
2.3.4 BiCMOS DRAMs 58
2.3.5 Soft-Error Failures in DRAMs . . . . . . . . . . . . . . . . . . . . . . . . . .. 60
2.3.6 Advanced DRAM Designs and Architectures . . . . . . . . . . . . . .. 62

v
vi Contents

2.3.6.1 A 16 Mb DRAM (Example) 63

2.3.6.2 ULSI DRAM Developments........ 64
2.3.7 Application-Specific DRAMs 69
2.3.7.1 Pseudostatic DRAMs (PSRAMs) 69
2.3.7.2 Silicon File 69
2.3.7.3 Video DRAMs (VRAMs) 70
2.3.7.4 High-Speed DRAMs 71
2.3.7.5 Application-Specific RAM Glossary and Summary
of Important Characteristics..................................................... 75

Chapter 3 Nonvolatile Memories 81

3.1 Introduction 81
3.2 Masked Read-Only Memories (ROMs) 83
3.2.1 Technology Development and Cell Programming 83
3.2.2 ROM Cell Structures 85
3.2.3 High-Density (Multimegabit) ROMs 87
3.3 Programmable Read-Only Memories (PROMs) 87
3.3.1 Bipolar PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 87
3.3.2 CMOS PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 91
3.4 Erasable (UV)-Programmable Read-Only Memories (EPROMs) 93
3.4.1 Floating-Gate EPROM Cell 93
3.4.2 EPROM Technology Developments .. . . . . . . . . . . . . . . . . . . .. 96
3.4.2.1 1 Mb EPROM (Example) 97
3.4.3 Advanced EPROM Architectures . . . . . . . . . . . . . . . . . . . . . . . . 98
3.4.4 One-Time Programmable (OTP) EPROMs 103
3.5 Electrically Erasable PROMs (EEPROMs) 104
3.5.1 EEPROM Technologies 105
3.5.1.1 Metal-Nitride-Oxide Silicon (MNOS) Memories.................... 105
3.5.1.2 Silicon-oxide Nitride-Qxide Semiconductor (SONOS)
Memories 109
3.5.1.3 Floating-GateTunnelingOxide (FLOTOX) Technology.... 110
3.5.1.4 Textured-Polysilicon Technology............................................. 115
3.5.2 EEPROM Architectures 116
3.5.3 Nonvolatile SRAM (or Shadow RAM) 120
3.6 Flash Memories (EPROMs or EEPROMs) 122
3.6.1 Flash Memory Cells and Technology Developments 123
3.6.2 Advanced Flash Memory Architectures . . . . . . . .. 128

Chapter 4 Memory Fault Modeling and Testing 140

4.1 Introduction........................................ 140
4.2 RAM Fault Modeling 142
4.2.1 Stuck-At Fault Model 142
4.2.2 Bridging Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 145
4.2.3 Coupling Faults 147
4.2.4 Pattern-Sensitive Faults , 151
4.2.5 Miscellaneous Faults 155
4.2.6 GaAs SRAM Fault Modeling and Testing . . . . . . . . . . . . . . . .. 155
4.2.7 Embedded DRAM Fault Modeling and Testing . . . . . . . . . . . .. 156
4.3 RAM Electrical Testing 158
4.3.1 DC and AC Parametric Testing . . . . . . . . . . . . . . . . . . . . . . . .. 158
4.3.2 Functional Testing and some Commonly Used Algorithms ... 158
4.3.3 Functional Test Pattern Selection . . . . . . . . . . . . . . . . . . . . . .. 174
4.4 RAM Pseudorandom Testing . . . . . . . . . . . . . . . . . . . . . . . . . .. 176
Contents vii

4.5 Megabit DRAM Testing 178

4.6 Nonvolatile Memory Modeling and Testing 180
4.6.1 DC Electrical Measurements 181
4.6.2 AC (Dynamic) and Functional Measurements 182
4.6.2.1 256K UVEPROM 182
4.6.2.2 64K EEPROM 183
4.7 IDDQ Fault Modeling and Testing 185
4.8 Application Specific Memory Testing. . . . . . . . . . . . . . . . . . . .. 189
4.8.1 General Testing Requirements . . . . . . . . . . . . . . . . . . . . . . . .. 189
4.8.2 Double-Buffered Memory (DBM) Testing 191

Chapter 5 Memory Design for Testability and FaultTolerance 195

5.1 General Design for Testability Techniques 195
5.1.1 Ad Hoc Design Techniques 196
5.1.1.1 Logic Partitioning.................................................................... 196
5.1.1.2 Input/Output Test Points 196
5.1.2 Structured Design Techniques . . .. 197
5.1.2.1 Level-Sensitive Scan Design 197
5.1.2.2 Scan Path............................................................................... 199
5.1.2.3 Scan/Set Logic....................................................................... 199
5.1.2.4 Random Access Scan............... 200
5.1.2.5 Boundary Scan Testing........................................................... 202
5.2 RAM Built-In Self-Test (BIST) 203
5.2.1 BIST Using Algorithmic Test Sequence 205
5.2.2 BIST Using 13N March Algorithm 207
5.2.3 BIST for Pattern-Sensitive Faults . . . . . . . . . . . . . . . . . . . . . .. 209
5.2.4 BIST Using Built-In Logic Block Observation (BILBO) 210
5.3 Embedded Memory DFT and 81ST Techniques 211
5.4 Advanced BIST and Built-In Self-Repair Architectures 216
5.4.1 Multibit and Line Mode Tests 216
5.4.2 Column Address-Maskable Parallel Test (CMT) Architecture .. 219
5.4.3 BIST Scheme Using Microprogram ROM 220
5.4.4 BIST and Built-In Self-Repair (BISR) Techniques 222
5.5 OFT and BIST for ROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
5.6 Memory Error-Detection and Correction Techniques 230
5.7 Memory Fault-Tolerance Designs . . . . . . . . . . . . . . . . . . . . . .. 241

Chapter 6 Semiconductor Memory Reliability 249

6.1 General Reliability Issues " 249
6.1.1 Semiconductor Bulk Failures 252
6.1.2 Dielectric-Related Failures . . . . . . . . . . . . . . . . . . . . . . . . . . .. 252
6.1.3 Semiconductor-Dielectric Interface Failures 253
6.1.4 Conductor and Metallization Failures . . . . . . . . . . . . . . . . . . . . 255
6.1.5 Metallization Corrosion-Related Failures . . . . . . . . . . . . . . . . . 256
6.1.6 Assembly- and Packaging-Related Failures 257
6.2 RAM Failure Modes and Mechanisms 258
6.2.1 RAM Gate Oxide Reliability 258
6.2.2 RAM Hot-Carrier Degradation 260
6.2.3 DRAM Capacitor Reliability 262
6.2.3.1 Trench Capacitors.................................................................. 262
6.2.3.2 Stacked Capacitors 264
6.2.4 DRAM Soft-Error Failures 264
viii Contents

6.2.5 DRAM Data-Retention Properties 267

6.3 Nonvolatile Memory Reliability 268
6.3.1 Programmable Read-Only Memory (PROM) Fusible Links . .. 268
6.3.2 EPROM Data Retention and Charge Loss . . . . . . . . . . . . . . .. 270
6.3.3 Electrically Erasable Programmable
Read-Only Memories (EEPROMs) 275
6.3.4 Flash Memories 280
6.3.5 Ferroelectric Memories 283
6.4 Reliability Modeling and Failure Rate Prediction . . . . . . . . . . .. 287
6.4.1 Reliability Definitions and Statistical Distributions 287
6.4.1.1 Binomial Distribution 289
6.4.1.2 Poisson Distribution 289
6.4.1.3 Normal (or Gaussian) Distribution 289
6.4.1.4 Exponential Distribution 291
6.4.1.5 Gamma Distribution 291
6.4.1.6 Weibull Distribution 291
6.4.1.7 Lognormal Distribution........................................................... 292
6.4.2 Reliability Modeling and Failure Rate Prediction 292
6.5 Design for Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 296
6.6 Reliability Test Structures 300
6.7 Reliability Screening and Qualification 304
6.7.1 Reliability Testing 304
6.7.2 Screening, Qualification, and Quality Conformance Inspections
(OCI) 310

Chapter 7 Semiconductor Memory Radiation Effects . . . . . . . . . . . .. 320

7.1 Introduction 320
7.2 Radiation Effects 322
7.2.1 Space Radiation Environments 322
7.2.2 Total Dose Effects 325
7.2.3 Single-Event Phenomenon (SEP) 330
7.2.3.1 DRAM and SRAM Upsets 333
7.2.3.2 SEU Modeling and Error Rate Prediction 335
7.2.3.3 SEP In-Orbit Flight Data 337
7.2.4 Nonvolatile Memory Radiation Characteristics 344
7.3 Radiation-Hardening Techniques 347
7.3.1 Radiation-Hardening Process Issues 347
7.3.1.1 Substrate Effects 347
7.3.1.2 Gate Oxide (Dielectric) Effects 347
7.3.1.3 Gate Electrode Effects 348
7.3.1.4 Postgate-Electrode Deposition Processing... 349
7.3.1.5 Field Oxide Hardening 349
7.3.1.6 Bulk CMOS Latchup Considerations 350
7.3.1.7 CMOS SOSISOI Processes 351
7.3.1.8 Bipolar Process Radiation Characteristics............................. 352
7.3.2 Radiation-Hardening Design Issues 352
7.3.2.1 Total Dose Radiation Hardness...... 353
7.3.2.2 Single-Event Upset (SEU) Hardening 358
7.3.3 Radiation-Hardened Memory Characteristics (Example) 363
7.4 Radiation Hardness Assurance and Testing 367
7.4.1 Radiation Hardness Assurance 367
7.4.2 Radiation Testing 369
7.4.2.1 Total DoseTesting 370
7.4.2.2 Single-EventPhenomenon (SEP)Testing 372
Contents ix

7.4.2.3 Dose Rate TransientEffects 376

7.4.2.4 Neutron.lrradiation 377
7.4.3 Radiation Dosimetry 377
7.4.4 Wafer Level Radiation Testing and Test Structures 378
7.4.4.1 Wafer Level RadiationTesting 378
7.4.4.2 Radiation Test Structures.............................. 379

Chapter 8 Advanced Memory Technologies . . . . . . . . . . . . . . . . . . . .. 387

8.1 Introduction 387
8.2 Ferroelectric Random Access Memories (FRAMs) 389
8.2.1 Basic Theory 389
8.2.2 FRAM Cell and Memory Operation 390
8.2.3 FRAM Technology Developments 393
8.2.4 FRAM Reliability Issues " 393
8.2.5 FRAM Radiation Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 395
8.2.6 FRAMs Versus EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
8.3 Gallium Arsenide (GaAs) FRAMs . . . . . . . . . . . . . . . . . . . . . .. 397
8.4 Analog Memories 398
8.5 Magnetoresistive Random Access Memories (MRAMs) 401
8.6 Experimental Memory Devices . . . . . . . . . . . . . . . . . . . . . . . . . 407
8.6.1 Quantum-Mechanical Switch Memories 407
8.6.2 A GaAs n-p-n-p Thyristor/JFET Memory Cell. . . . . . . . . . . . .. 408
8.6.3 Single-Electron Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
8.6.4 Neuron-MOS Multiple-Valued (MV) Memory Technology ..... 409

Chapter 9 High-Density Memory Packaging Technologies . . . . . . . .. 412

9.1 Introduction........................................ 412
9.2 Memory Hybrids and MCMs (2-D) 417
9.2.1 Memory Modules (Commercial) 417
9.2.2 Memory MCMs (Honeywell ASCM) 421
9.2.3 VLSI Chip-an-Silicon (VCOS) Technology 421
9.3 Memory Stacks and MCMs (3-D) 424
9.3.1 3-D Memory Stacks (Irvine Sensors Corporation) 427
9.3.1.1 4 Mb SRAM Short Stack" (Example) 429
9.3.2 3-D Memory Cube Technology (Thomson CSF) 430
9.3.3 3-D Memory MCMs (GE-HOIITI) 431
9.3.3.1 3-D HOI Solid-State Recorder (Example) 432
9.3.4 3-D Memory Stacks (n CHIPS) 432
9.4 Memory MCM Testing and Reliability Issues 435
9.4.1 VCOS OFT Methodology and Screening Flow (Example) 437
9.5 Memory Cards 440
9.5.1 CMO SRAM Card (Example) 442
9.5.2 Flash Memory Cards 442
9.6 High-Density Memory Packaging Future Directions . . . . . . . . . 446

Index 451
Preface

Semiconductor memories are usually consid- in multimegabit DRAMs have resulted in a

ered to be the most vital microelectronics greater demand for application-specific products
component of the digital level designs for main- such as the pseudostatic DRAM (PSRAM),
frame computers and PCs, telecommunications, video DRAM (VDRAM), and high speed
automotive and consumer electronics, and com- DRAM (HSDRAM), e.g., synchronous, cached,
mercial and military avionics systems. Semi- and Rambus (configurations using innovative ar-
conductor memory devices are characterized as chitectures). Each of these specialty memory de-
volatile random access memories (RAMs), or vices has its associated testing and reliability
nonvolatile memory devices. RAMS can either issues that have to be taken into consideration
be static mode (SRAMs) where the logic infor- for board and system level designs.
mation is stored by setting up the logic state of a Nonvolatile memories such as read-only
bistable flip-flop, or through the charging of a memories (ROMs), programmable read-only
capacitor as in dynamic random access memo- memories (PROMs), and erasable and program-
ries (DRAMs). The nonvolatile memory data mable read-only memories (EPROMs) in both
storage mode may be permanent or reprogram- ultraviolet erasable (UVPROM) and electrically
mable, depending upon the fabrication technol- erasable (EEPROM) versions have also made
ogy used. significant improvements in both density and
In the last decade or so, semiconductor performance. Flash memories are being fabri-
memories have advanced both in density and cated in 8 and 16 Mb density devices for use in
performance because of phenomenal develop- high-density nonvolatile storage applications
ments in submicron technologies. DRAMs are such as memory modules and memory cards.
considered key technology drivers and predic- The continuously evolving complexity of
tors of semiconductor manufacturing process memory devices makes memory fault modeling,
scaling and performance trends. According to test algorithms, design for testability (DFT),
the Semiconductor Industries Association's re- built-in self-test (BIST), and fault tolerance
cent technology road map, the DRAMs are ex- areas of signific.ant concern. The general relia-
pected to increase in density from 64 Mb in 1995 bility issues pertaining to semiconductor de-
to 64 Gb in 2010. The growing demands for PCs vices in bipolar and MOS technologies are
and workstations using high-performancemicro- applicable to memories also. In addition, there
processors are the key targets of DRAM design- are some special RAM failure modes and mech-
ers and manufacturers. The technical advances anisms, nonvolatile memory reliability issues,

xi
xii Preface

and reliability modeling and failure prediction following: Introduction; Random Access Mem-
techniques that are reviewed in this book. ory technology, both SRAMs, DRAMs, and their
Radiation effects on semiconductor mem- application-specific architectures; Nonvolatile
ories is an area of growing concern. In general, Memories such as ROMs, PROMs, UVPROMs,
the space radiation environment poses a certain EEPROMs, and flash memories; Memory Fault
radiation risk to electronic components on earth Modeling and Testing; Memory Design for
orbiting satellites and planetary mission space- Testability and Fault Tolerance; Semiconductor
crafts, and the cumulative effect of damage from Memory Reliability; Semiconductor Memory
charged particles such as electrons and protons Radiation Effects; Advanced Memory Tech-
on semiconductor memories can be significant. nologies; and High-Density Memory Packaging
The memory scaling for higher densities has Technologies.
made them more susceptible to logic upsets and This book should be of interest and be
failures. This book provides a detailed coverage useful to a broad spectrum of people in the
of those radiation effects, including single-event semiconductor manufacturing and electronics
phenomenon (SEP) modeling and error rate pre- industries, including engineers, system level de-
diction, process and circuit design radiation signers, and managers in the computer, telecom-
hardening techniques, radiation testing proce- munications, automotive, commercial satellite,
dures, and radiation test structures. and military avionics areas. It can be used both
Several advanced memory technologies as an introductory treatise as well as an ad-
that are in the development stages are reviewed, vanced reference book.
such as ferroelectric random access memories I am thankful to all of the technical review-
(FRAMs), GaAs FRAMs, analog memories, ers who diligently reviewed the manuscript and
magnetoresistive random access memories provided valuable comments and suggestions
(MRAMs), and quantum-mechanical switch that I tried to incorporate into the final version. I
memories. Another area of current interest cov- would like to thank several people at Goddard
ered in the book is the section on high-density Space Flight Center, especially George Kramer,
memory packaging technologies, which in- Ann Garrison, Ronald Chinnapongse, David
cludes memory hybrids and multichip module Cleveland, Wentworth Denoon, and Charles
(MCM) technologies, memory stacks and 3-D Vanek. Special thanks and acknowledgments are
MCMs, memory MCM testing and reliability is- also due to various semiconductor memory man-
sues, and memory cards. In high-density mem- ufacturers and suppliers for providing product in-
ory development, the future direction is to formation specification sheets and permission to
produce mass memory configurations of very reprint their material. And the author and IEEE
high bit densities ranging from tens of Press acknowledge the efforts of Rochit Raj-
megabytes to several hundred gigabytes. suman as a technical reviewer and consultant.
There are very few books on the market Finally, the acknowledgments would be
that deal exclusively with semiconductor mem- incomplete without thanks to Dudley R. Kay,
ories, and the information available in them is Director of Book Publishing, John Griffin, and
fragmented-some of it is outdated. This book Orlando Velez, along with the other staff mem-
is an attempt to provide a comprehensive and in- bers at IEEE Press, including the Editorial
tegrated coverage in three key areas of semicon- Board for their invaluable support.
ductor memories: technology, testing and Ashok K. Sharma
reliability. It includes detailed chapters on the Silver Spring, Maryland
Semiconductor Memories
 1
Introduction

Semiconductor memories are usually consid- consumer electronics industries. A combination

ered to be the most vital microelectronic com- of single-chip volatile as well as nonvolatile
ponent of digital logic system design, such as memory storage modes is also available in de-
computers and microprocessor-based applica- vices such as nonvolatile SRAM (nvRAM) for
tions ranging from satellites to consumer elec- use in systems that require fast, reprogrammable
tronics. Therefore, advances in the fabrication nonvolatile memory. In addition, dozens of spe-
of semiconductor memories including process cial memory architectures have evolved which
enhancements and technology developments contain some additional logic circuitry to opti-
through the scaling for higher densities and mize their performance for application-specific
faster speeds help establish performance stan- tasks.
dards for other digital logic families. Semicon- This book on semiconductor memories
ductor memory devices are characterized as covers random access memory technologies
volatile random access memories (RArv1s)~ or (SRAMs and DRAMs) and their application-
nonvolatile memory devices. In RAMs, the specific architectures; nonvolatile memory tech-
logic information is stored either by setting up nologies such as read-only memories (ROMs),
the logic state of a bistable flip-flop such as in a programmable read-only memories (PROMs),
static random access memory (SRAM), or and erasable and programmable read-only
through the charging of a capacitor as in a dy- memories (EPROrvls) in both ultraviolet eras-
namic random access memory (DRAM). In ei- able (UVPROM) and electrically erasable
ther case, the data are stored and can be read out (EEPROM) versions; memory fault modeling
as long as the power is applied, and are lost and testing; memory design for testability and
when the power is turned off; hence, they are fault tolerance; semiconductor memory reliabil-
called volatile memories, ity; semiconductor memory radiation effects;
Nonvolatile memories are capable of stor- advanced memory technologies; and high-
ing the data, even with the power turned off. The density memory packaging technologies.
nonvolatile memory data storage mode may be Chapter 2 on "Random Access Memory
permanent or reprogrammable, depending upon Technologies," reviews the static and dynamic
the fabrication technology used. Nonvolatile RAM technologies as well as their application-
memories are used for program and microcode specific architectures. In the last two decades of
storage in a wide variety of applications in the semiconductor memory growth, the DRAMs
computer, avionics, telecommunications, and have been the largest volume volatile memory

1
2 Chap. 1 • Introduction

produced for use as main computer memories periodically refreshed in order to prevent it from
because of their high density and low cost per leaking away. A significant improvement in
bit advantage. SRAM densities have generally DRAM evolution has been the switch from
lagged a generation behind the DRAMs, i.e., the three-transistor (3-T) designs to one-transistor
SRAMs have about one-fourth the capacity of (1-T) cell design that has enabled production of
DRAMs, and therefore tend to cost about four 4 and 16 Mb density chips that use advanced,
times per bit as the DRAMs. However, the 3-D trench capacitor and stacked capacitor cell
SRAMs offer low-power consumption and structures. DRAMs of 64 Mb density have been
high-performance features which make them sampled, and prototypes for 256 Mb are in de-
practical alternatives to the DRAMs. Nowa- velopment. The DRAMs are susceptible to soft
days, a vast majority of SRAMs are being fabri- errors (or cell logic upset) occurring from alpha
cated in the NMOS and CMOS technologies, particles produced by trace radioactive packag-
and a combination of two technologies (also re- ing material. In NMOS/CMOS DRAM designs,
ferred to as the mixed-MOS) for commodity various techniques are used to reduce their sus-
SRAMs. ceptibility to the soft-error phenomenon. The
Bipolar memories using emitter-coupled BiCMOS DRAMs have certain advantages over
logic (ECL) provide very fast access times, but the pure CMOS designs, particularly in access
consume two-three times more power than time. The technical advances in multimegabit
MOS RAMs. Therefore, in high-density and DRAMs have resulted in greater demand for
high-speed applications, various combinations application-specific products such as the pseu-
of bipolar and MOS technologies are being dostatic DRAM (PSRAM) which uses dynamic
used. In addition to the MaS and bipolar mem- storage cells but contains all refresh logic on-
ories referred to as the "bulk silicon" tech- chip that enables it to function similarly to a
nologies, silicon-on-insulator (SOl) isolation SRAM. Video DRAMs (VDRAMs) have been
technology such as silicon-on-sapphire (SOS) produced for use as the multiport graphic
SRAMs have been developed for improved ra- buffers. A high-speed DRAM (HSDRAM) has
diation hardness. The SRAM density and per- been developed with random access time ap-
formance are usually enhanced by scaling down proaching that of SRAMs while retaining the
the device geometries. Advanced SRAM de- density advantage of 1-T DRAM design. Some
signs and architectures for 4 and 16 Mb density other examples of high-speed DRAM innova-
chips with submicron feature sizes (e.g., 0.2-0.6 tive architectures are synchronous, cached, and
urn) are reviewed. Application-specific mem- Rambus" DRAMs.
ory designs include first-in first-out (FIFO), Chapter 3 reviews various nonvolatile
which is an example of shift register memory ar- memory (NVM) technologies. A category of
chitecture through which the data are trans- NVM is read-only memories (ROMs) in which
ferred in and out serially. The dual-port RAMs the data are written permanentlyduring manufac-
allow two independent devices to have simulta- turing, or the user-programmable PROMs in
neous read and write access to the same mem- which the data can be written only once. The
ory. Special nonvolatile, byte-wide RAM PROMs are available in both bipolar and CMOS
configurations require not only very low oper- technologies. In 1970, a floating polysilicon-
ating power, but have battery back-up data- gate-based erasable programmable read-only
retention capabilities. The content-addressable memory was developed in which hot electrons
memories (CAMs) are designed and used both are injected into the floating gate and removed ei-
as the embedded modules on larger VLSI chips ther by ultraviolet internal photoemission or
and as stand-alone memory for specific system Fowler-Nordheim tunneling. The EPROMs (also
applications. known as UVEPROMs) are erased by removing
The DRAMs store binary data in cells on them from the target system and exposing them
capacitors in the form of charge which has to be to ultraviolet light. Since an EPROM consists of
Chap. I • Introduction 3

single-transistorcells, they can be made in den- the floating-gate EEPROM cells. The improve-
sities comparable to the DRAMs. Floating-gate ments in flash EEPROM cell structures have re-
avalanche-injection MOS transistors (FAMOS) sulted in the fabrication of 8 and 16 Mb density
theory and charge-transfer mechanisms are dis- devices for use in high-density nonvolatile stor-
cussed. Several technology advances in cell age applications such as memory modules and
structures, scaling, and process enhancements memory cards.
have made possible the fabrication of 4-16 Mb Chapter 4 on "Memory Fault Modeling
density EPROMs. A cost-effective alternative and Testing," reviews memory failure modes
has been the one-time programmable (OTP) and mechanisms, fault modeling, and electrical
EPROM introducedby the manufacturers for the testing. The memory device failures are usually
high-volumeapplications ROM market. represented by a bathtub curve and are typically
An alternative to EPROM(or UVEPROM) grouped into three categories, depending upon
has been the development of electrically erasable the product's operating life cycle stage where the
PROMs (EEPROMs) which offer in-circuit pro- failures occur. Memory fault models have been
gramming flexibility. The several variations of developed for the stuck-at faults (SAFs), transi-
this technology include metal-nitride-oxide- tion faults (TFs), address faults (AFs), bridging
semiconductor (MNOS), silicon-oxide-nitride- faults (BFs), coupling faults (CFs), pattern-
oxide-semiconductor (SONDS), floating-gate sensitive faults (PSFs), and the dynamic (or
tunneling oxide (FLOTOX), and textured poly- delay) faults. A most commonly used model is
silicon. Since the FLOTOX is the most com- the single-stuck-at fault (SSF) which is also re-
monly used EEPROM technology, the Fowler- ferred to as the classical or standard fault model.
Nordheim tunneling theory for a FLOTOX tran- However, the major shortcoming of the stuck-at
sistor operation is reviewed. The conventional, fault model is that the simulation using this
full functional EEPROMs have several advan- model is no longer an accurate quality indicator
tages, including the byte-erase, byte-program, for the ICs like memory chips. A large percent-
and random access read capabilities. The conven- age of physical faults occurring in the ICs can be
tional EEPROMs used NOR-gate cells, but the considered as the bridging faults (BFs) consist-
modified versions include the NAND-structured ing of shorts between two or more cells or lines.
cells that have been used to build 5 V-only Another important category of faults that can
4 Mb EEPROMs. An interesting NVM architec- cause the semiconductor RAM cell to function
ture is the nonvolatile SRAM, a combination of erroneously is the coupling or PSFs. March tests
EEPROM and SRAM in which each SRAM cell in various forms have been found to be quite ef-
has a corresponding "shadow" EEPROM cell. fective for detecting the SAFs, TFs, and CFs.
The EPROMs, including UVEPROMs and Many algorithms have been proposed for the
EEPROMs, are inherently radiation-susceptible. neighborhood pattern-sensitive faults (NPSFs)
The SONOS technology EEPROMs have been based on an assumption that the memory array's
developed for military and space applications physicaland logical neighborhoods are identical.
that require radiation-hardened devices. Flash This may not be a valid assumption in state-of-
memories based on EPROM or EEPROM tech- the-art memory chips which are being designed
nologies are devices for which the contents of all with the spare rows and columns to increase
memoryarray cells can be erased simultaneously yield and memory array reconfiguration, if
through the use of an electrical erase signal. The needed. The embedded RAMs which are being
flash memories, because of their bulk erase used frequently are somewhat harder to test be-
characteristics, are unlike the floating-gate cause of their limited observability and control-
EEPROMs whichhave select transistors incorpo- lability. A defect-oriented (inductive fault)
rated in each cell to allow for the individual byte analysis has been shown to be quite useful in
erasure. Therefore, the flash memories can be finding various defect mechanisms for a given
made roughly two or three times smaller than layout and technology.
4 Chap. 1 • Introduction

In general, the memory electrical testing general guidelines for a logic design based on
consists of the de and ac parametric tests and practical experience are called the ad hoc design
functional tests. For RAMs, various functional techniques such as logic partitioning, and addi-
test algorithms have been developed for which tion of some I/O test points for the embedded
the test time is a function of the number of RAMs to increase controllability and observ-
memory bits (n) and range in complexity from ability. Structured design techniques are based
O(n) to 0(n 2) . The selection of a particular set of upon a concept of providing uniform design for
test patterns for a given RAM is influenced by the latches to enhance logic controllability, and
the type of failure modes to be detected, mem- commonly used methodologies include the
ory bit density which influences the test time, level-sensitive scan design (LSSD), scan path,
and the memory ATE availability. These are the scan/set logic, random access scan, and the
deterministic techniques which require well- boundary scan testing (BST). The RAM BIST
defined algorithms and memory test input pat- techniques can be classified into two categories
terns with corresponding measurements of as the "on-line BIST" and "off-line BIST." The
expected outputs. An alternate test approach BIST is usually performed by applying certain
often used for the memories is random (or test patterns, measuring the output response
pseudorandom) testing which consists of apply- using linear feedback shift registers (LFSRs),
ing a string of random patterns simultaneously and compressing it. The various methodologies
to a device under test and to a reference mem- for the BIST include exhaustive testing, pseudo-
ory, and comparing the outputs. Advanced random testing, and the pseudoexhaustive test-
megabit memory architectures are being de- ing. For the RAMs, two BIST approaches have
signed with special features to reduce test time been proposed that utilize either the random
by the use of the multibit test (MBT), line mode logic or a microcoded ROM. The major advan-
test (LMT), and built-in self-test (BIST). The tages associated with a microcoded ROM over
functional models for nonvolatile memories are the use of random logic are a shorter design
basically derived from the RAM chip functional cycle, the ability to implement alternative test
model, and major failure modes in the EPROMs algorithms with minimal changes, and ease in
such as the SAFs, AFs, and BFs can be detected testability of the microcode. The RAM BIST
through functional test algorithms. Recent stud- implementation strategies include the use of the
ies have shown that monitoring of the elevated algorithmic test sequence (ATS), the 13N March
quiescent supply currents (IDDQ) appears to be algorithm with a data-retention test, a fault-
a good technique for detecting the bridging fail- syndrome-based strategy for detecting the PSFs,
ures. The IDDQ fault models are being devel- and the built-in logic block observation
oped with a goal to achieve 100% physical (BILBO) technique. For the embedded memo-
defect coverage. Application-specific memories ries, various DFf and BIST techniques have
such as the FIFOs, video RAMs, synchronous been developed such as the scan-path-based
static and dynamic RAMs, and double-buffered flag-scan register (FLSR) and the random-
memories (DBMs) have complex timing re- pattern-based circular self-test path (CSTP).
quirements and multiple setup modes which re- Advanced BIST architectures have been
quire a suitable mix of sophisticated test implemented to allow parallel testing with on-
hardware, the DFf and BIST approach. chip test circuits that utilize multibit test (MBT)
Chapter 5 reviews the memory design for and line mode test (LMT). An example is the
testability (DFT) techniques, RAM and ROM column address-maskable parallel test (CMT)
BIST architectures, memory error-detection and architecture which is suitable for the ultrahigh-
correction (EDAC) techniques, and the memory density DRAMs. The current generation mega-
fault-tolerance designs. In general, the memory bit memory chips include spare rows and
testability is a function of variables such as cir- columns (redundancies) in the memory array to
cuit complexity and design methodology. The compensate for the faulty cells. In addition, to
Chap. 1 • Introduction 5

improve the memory chip yield, techniques perform satisfactorily for a given time at a de-
such as the built-in self-diagnosis (BISD) and sired confidence level under specified operating
built-in self-repair (BISR) have been investi- and environmental conditions. The memory de-
gated. BIST schemes for ROMs have been de- vice failures are a function of the circuit design
veloped that are based on exhaustive testing and techniques, materials, and processes used in
test response compaction. The conventional ex- fabrication, beginning from the wafer level
haustive test schemes for the ROMs ·use com- probing to assembly, packaging, and testing.
paction techniques which are parity-based, The general reliability issues pertaining to semi-
count-based, or polynomial-division-based (sig- conductor devices in bipolar and MOS tech-
nature analysis). nologies are applicable to the memories also,
The err-ors in semiconductor memories such as the dielectric-related failures from
can be broadly categorized into hard failures gate-oxide breakdown, time-dependent dielec-
caused by permanent physical damage to the de- tric breakdown (TDDB), and ESD failures; the
vices, and soft errors caused by alpha particles dielectric-interface failures such as those caused
or the ionizing dose radiation environments. by ionic contamination and hot carrier effects:
The most commonly used error-correcting the conductor and metallization failures, e.g.,
codes (ECC) which are used to correct hard electromigration and corrosion effects; the as-
and soft errors are the single-error-correction sembly and packaging-related failures. How-
and double-error-detection (SEC-DED) codes, ever, there are special reliability issues and
also referred to as the Hamming codes. How- failure modes which are of special concern for
ever, these codes are inadequate for correcting the RAMs. These issues include gate oxide reli-
double-bitlword-line soft errors. Advanced 16 ability defects, hot-carrier degradation, the
Mb DRAM chips have been developed that use DRAM capacitor charge-storage and data-reten-
redundant word and bit lines in conjunction tion properties, and DRAM soft-error failures.
with the ECC to produce an optimized fault tol- The memory gate dielectric integrity and relia-
erance effect. In a new self-checking RAM ar- bility are affected by all processes involved in
chitecture, on-line testing is performed during the gate oxide growth.
normal operations without destroying the stored The high-density DRAMs use 3-D storage
data. A fault tolerance synergism for memory cell structures such as trench capacitors, stacked
chips can be obtained by a combined use of re- capacitor cells (STCs), and buried storage elec-
dundancy and ECC. A RAM fault tolerance ap- trodes (BSEs). The reliability of these cell struc-
proach with dynamic redundancy can use either tures depends upon the quality and growth of
the standby reconfiguration method, or memory silicon dioxide, thin oxide/nitride (ON), and
reconfiguration by the graceful degradation oxide/nitride/oxide (DNa) composite films.
scheme. To recover from soft errors (transient The reduced MaS transistor geometries from
effects), memory scrubbing techniques are often scaling of the memory devices has made them
used which are based upon the probabilistic or more susceptible to hot carrier degradation ef-
deterministic models. These techniques can be fects. In DRAMs, the alpha-particle-induced
used to calculate the reliability rate R(t) and soft-error rate (SER) can be improved by using
MTTF of the memory systems. special design techniques. Nonvolatile memo-
Chapter 6 reviews general reliability is- ries, just like volatile memories, are also suscep-
sues for semiconductor devices such as the tible to some specific failure mechanisms. For
memories, RAM failure modes and mecha- PROMs with fusible links, the physical integrity
nisms, nonvolatile memories reliability, reliabil- and reliability of fusible links are a major con-
ity modeling and failure rate prediction, design cern. In floating-gate technologies such as
for reliability, and reliability test structures. The EPROMs and EEPROMs, data retention charac-
reliability of a semiconductor device such as a teristics and the number of write/erase cycles
memory is the possibility that the device will without degradation (endurance) are the most
6 Chap. 1 • Introduction

critical reliability concerns. The ferroelectric issues, radiation testing, radiation dosimetry,
memory reliability concerns include the aging wafer level radiation testing, and test structures.
effects of temperature, electric field, and the The space radiation environment poses a certain
number of polarization reversal cycles on ferro- radiation risk to all electronic components on
electric films used (e.g., PZT). earth orbiting satellites and the planetary mis-
Reliability failure modeling is a key to the sion spacecrafts. Although the natural space en-
failure rate predictions, and there are many sta- vironment does not contain the high dose rate
tistical distributions such as the Poisson, Normal pulse characteristics of a weapon environment
(or Gaussian), Exponential, Weibull, and Log- (often referred to as the "gamma dot"), the cu-
normal that are used to model various reliability mulative effect of ionization damage from
parameters. There are several reliability predic- charged particles such as electrons and protons
tion procedures for predicting electronic compo- on semiconductor memories can be significant.
nent reliability such as MIL-HDBK-217 and In general, the bipolar technology memories
Bellcore Handbook. However, the failure rate (e.g., RAMs, PROMs) are more tolerant to total
calculation results for semiconductor memories dose radiation effects than the nonhardened,
may vary widely from one model to another. De- bulk MOS memories. For the MOS devices, the
sign for reliability (DFR), which includes failure ionization traps positive charge in the gate oxide
mechanisms modeling and simulation, is an im- called the oxide traps, and produces interface
portant concept that should be integrated with states at the Si-Si0 2 interface. The magnitude
the overall routine process of design for perfor- of these changes depends upon a number of fac-
mance. The method of accelerated stress aging tors such as total radiation dose and its energy;
for semiconductor devices such as memories is dose rate; applied bias and temperature during
commonly used to ensure long-term reliability. irradiation; and postirradiation annealing condi-
For nonvolatile memories, endurance modeling tions. Ionization radiation damage causes
is necessary in the DFR methodology. An ap- changes in the memory circuit parameters such
proach commonly employed by the memory as standby power supply currents, I/O voltage
manufacturers in conjunction with the end-of- threshold levels and leakage currents, critical
line product testing has been the use of reliability path delays, and timing specification degrada-
test structures and process (or yield) monitors in- tions.
corporated at the wafer level in kerf test sites and The single-event phenomenon (SEP) in
"drop-in" test sites on the chip. The purpose of the memories is caused by high-energy particles
reliability testing is to quantify the expected fail- such as those present in the cosmic rays passing
ure rate of a device at various points in its life through the device to cause single-event upsets
cycle. The memory failure modes which can be (SEUs) or soft errors, and single-event latchup
accelerated by a combined elevated temperature (SEL) which may result in hard errors. The im-
and high-voltage stress are the threshold voltage pact of SEU on the memories, because of their
shifts, TDDB leading to oxide shorts, and data- shrinking dimensions and increasing densities,
retention degradation for the nonvolatile memo- has become a significant reliability concern.
ries. MIL-STD-883, Method 5004 Screening The number of SEUs experienced by a mem-
Procedure (or equivalent) are commonly used by ory device in a given radiation environment
the memory manufacturers to detect and elimi- depends primarily on its threshold for upsets,
nate the infant mortality failures. MIL-STD-883, usually expressed by its critical charge Qc or
Method 5005 Qualification and QCI Procedures the critical LET and the total device volume
(or equivalent) are used for high-reliability mili- sensitive to ionic interaction, i.e., creation of
tary and space environments. electron-hole (e-h) pairs. The Qc is primarily
Chapter 7, entitled "Semiconductor Mem- correlated to circuit design characteristics. Criti-
ory Radiation Effects," reviews the radiation- cal LET for a memory is found experimentally
hardeningtechniques,radiation-hardening design by bombarding the device with various ion
Chap. 1 • Introduction 7

species (e.g., in a cyclotron). For the memory defines the test apparatus, procedures, and other
devices flown in space, radiation tolerance is as- requirements for effects from the Co-60 gamma
sessed with respect to the projected total dose ray source. Radiation testing requires calibra-
accumulated, which is the sum of absorbed dose tion of the radiation source and proper dosime-
contributions from all ionizing particles, and is try. Sometimes, radiation test structures are used
calculated (in the form of dose-depth curves) by at the wafer (or chip level) as process monitors
sophisticated environmental modeling based for radiation hardness assurance.
upon the orbital parameters, mission duration, Chapter 8 reviews several advanced mem-
and thickness of spacecraft shielding. It is im- ory technologies such as the ferroelectric ran-
portant to verify ground test results obtained by dom access memories (FRAMs), GaAs FRAMs,
observation of actual device behavior in orbit. analog memories, magnetoresistive random
Several in-orbit satellite experiments have been access memories (MRAMs), and quantum-
designed to study the effect of the radiation par- mechanical switch memories. In the last few
ticle environment on semiconductor devices years, an area of interest in advanced non-
such as memories. volatile memories has been the development of
The nonvolatile MOS memories are also thin-film ferroelectric (FE) technology that uses
subject to radiation degradation effects. The ra- magnetic polarization (or hysteresis) properties
diation hardness of memories is influenced by a to build the FRAMs. The high-dielectric-
number of factors, both process- and design-re- constant materials such as lead zirconate titan-
lated. The process-related factors which affect ate (PZT) thin film can be used as a capacitive,
radiation response are the substrate effects, gate nonvolatile storage element similar to trench ca-
oxidation and gate electrode effects, post- pacitors in the DRAMs. This FE film technol-
polysilicon processing, and field oxide harden- ogy can be easily integrated with standard
ing. The CMOS SOIlSOS technologies which semiconductor processing techniques to fabri-
utilize insulator isolation as opposed to the junc- cate the FRAMs which offer considerable size
tion isolation for bulk technologies offer a sub- and density advantage. A FRAM uses one tran-
stantial advantage in the latchup, transient sistor and one capacitor cell. Although the
upset, and SED characteristics. The memory cir- FRAMs have demonstrated very high write en-
cuits can be designed for total dose radiation durance cycle times, the FE capacitors depolar-
hardness by using optimized processes (e.g., ize over time from read/write cycling. Therefore,
hardened gate oxides and field oxides) and good thermal stability, fatigue from polarization rever-
design practices. The bulk CMOS memories sal cycling, and aging of the FRAMs are key re-
have been hardened to SEU by using an appro- liability concerns. In general, the FE capacitors
priate combination of processes (e.g., thin gate and memories made from thin-film PZT have
oxides, twin-tub process with thin epitaxial lay- shown high-radiation-tolerance characteristics
ers) and design techniques such as utilizing suitable for space and military applications. The
polysilicon decoupling resistors in the cross- FE element processing has also been combined
coupling segment of each cell. with GaAs technology to produce ferroelectric
Radiation sensitivity of unhardened mem- nonvolatile (or FERRAMs) prototypes of 2KJ4K
ory devices can vary from lot to lot, and for bit density levels.
space applications, radiation testing is required The memory storage volatile (or non-
to characterize the lot radiation tolerance. The volatile) usually refers to the storage of digital
ground-based radiation testing is based upon a bits of information ("O"s and "T's), However,
simulation of space environment by using radia- recently, analog nonvolatile data storage has
tion sources such as the Cobalt-60, X-ray tubes, also been investigated using the EEPROMs and
particle accelerators, etc. For example, total FRAMs in applications such as audio recording
dose radiation testing on the memories is per- of speech and analog synaptic weight storage
formed per MIL-STD-883, Method 1019, which for neural networks. This nonvolatile analog
8 Chap. I • Introduction

storage is accomplished by using the EEPROMs reliability military and space applications, her-
which are inherently analog memories on a cell- metically sealed ceramic packages are usually
by-cell basis because each floating gate can preferred. For high-density memory layouts on
store a variable voltage. The sensed value of a the PC boards, various types of packaging con-
cell's conductivity corresponds to the value of figurations are used to reduce the board level
the analog level stored. This technology has memory package "footprint." However, increas-
been used in audio applications such as single- ing requirements for denser memories have led
chip voice messaging systems. Another technol- to further compaction of packaging technolo-
ogy development for nonvolatile storage is the gies through the conventional hybrid manufac-
magnetoresistive memory (MRAM) which uses turing techniques and MCMs. For the assembly
a magnetic thin-film sandwich configured in of MCMs, various interconnection technologies
two-dimensional arrays. These MRAMs are have been developed such as the wire bonding,
based upon the principle that a material's mag- tape automated bonding (TAB), flip-chip bond-
netoresistance will change due to the presence ing, and high-density interconnect (HDI).
of a magnetic field. The magnetoresistive tech- A commonly used multichip module con-
nology has characteristics such as a nondestruc- figuration for the DRAMs is the single-in-line
tive readout (NDRO), very high radiation memory module (SIMM). Several variations on
tolerance, higher write/erase endurance com- 3-D MCM technology have evolved for the
pared to the FRAMs, and virtually unlimited memories, with a goal of improving storage den-
power-off storage capability. Another variation sities while lowering the cost per bit. The density
on this technology is the design and conceptual of chip packaging expressed as the "silicon effi-
development of micromagnet-Hall effect ran- ciency" is determined by the ratio of silicon die
dom access memory (MHRAM) where infor- area to the printed circuit board (or substrate)
mation is stored in small magnetic elements. area. An example is the memory MCMs fabri-
The latest research in advanced memory tech- cated by Honeywell, Inc. for the Advanced
nologies and designs includes the solid-state de- Spacebome Computer Module (ASCM) in the
vices that use quantum-mechanical effects such following two technologies: MCM-D using thin-
as resonant-tunneling diodes (RTDs) and reso- film multilayer copper/polyimide interconnects
nant-tunneling hot-electron transistors (RHETs) on an alumina ceramic substrate mounted in a
for possible development of gigabit memory perimeter-leaded cofired ceramic flatpack, and
densities. These devices are based upon the neg- MCM-C which used a multilayer cofired alu-
ative resistance (or negative differential conduc- mina package. In the chip-on-board (COB)
tance) property which causes a decrease in packaging, the bare memory chip (or die) is di-
current for an increase in voltage. This effect rectly attached to a substrate, or even PC board
has been used in the development of a SRAM (such as FR4 glass epoxy). IBM (now LORAL
cell that uses two RTDs and one ordinary tunnel Federal Systems) has developed VLSI chip-on-
diode (TO) for the complete cell. silicon (VCaS) MCMs which combine HDI
Chapter 9, "High-Density Memory Pack- technology with a flip-chip, C4 (controlled-
aging Technologies," reviews commonly used collapse chip connect) attach process.
memory packages, memory hybrids and 2-D An extension of 2-D planar technology
multichip modules (MCMs), memory stacks has been the 3-D concept in which the memory
and 3-D MCMs, memory MCM testing and reli- chips are mounted vertically prior to the attach-
ability issues, memory cards, and high-density ment of a suitable interconnect. The" 3-D ap-
memory packaging future directions. The most proach can provide higher packaging densities
common high-volume usage semiconductor because of reduction in the substrate size, mod-
RAMs and nonvolatile memories use "through- ule weight, and volume; lower line capacitance
the-hole" (or insertion mount) and the surface and drive requirements; and reduced signal
mount technology (SMT) packages. For high- propagation delay times. Four generic types of
Chap. 1 • Introduction 9

3-D packaging technologies are currently being techniques such as the boundary scan and level-
used by several manufacturers: layered die, die sensitive scan design (LSSD) are often used in
stacked on edge, die stacked in layers, and verti- conjunction with the design for the reliability ap-
cally stacked modules. An example is Texas In- proach. Another application for high-density
struments (TI) 3-D HOI MCM packaging memory bare chip assembly has been the devel-
technology that has been used for the develop- opment of memory cards that are lightweight
ment of a solid-state recorder (SSR) for DARPA plastic and metal cards containing the memory
with initial storage capacity of 1.3 Gb expand- chips and associated circuitry. They offer signifi-
able to 10.4 Gb. cant advantages in size, weight, speed, and power
However, MCM defects and failures can consumption. These cards integrate multiple
occur due to the materials, including the sub- volatile/nonvolatile memory technologies, and
strate, dice, chip interconnections, and manu- are intended to serve as alternatives for tradi-
facturing process variations; lack of proper tional hard disks and floppy drives in notebook
statistical process control (SPC) during fabrica- computers and mobile communication equip-
tion and assembly; inadequate screening and ment.
qualification procedures; and a lack of proper de- In high-density memory development, the
sign for testability (OFT) techniques.Availability future direction is to produce mass memory
of "known-good-die" (KGD) and "known-good- configurations of very high bit densities ranging
substrate" (KGS) are important prerequisites for from tens of megabytes to several hundred giga-
high-yield MCMs and minimizing the need for bytes by integrating 3-D technology into the
expensive module rework/repair. The MCM DFf MCMs.
 2
Random Access
Memory Technologies

2.1 INTRODUCTION Early static RAMs were developed in three sep-

arate technologies: bipolar, NMOS, and CMOS.
Semiconductor memory devices are generally By the middle of the 1980s, the vast majority of
categorized as volatile or nonvolatile random SRAMs were made in CMOS technology.
access memories (RAMs). In RAMs, the infor- SRAMs are currently available in many vari-
mation is stored either by setting the state of a eties, ranging from the conventional MOS
bistable flip-flop circuit or through the charging (NMOS or CMOS) to high-speed bipolar and
of a capacitor. In either of these methods, the in- GaAs SRAM designs. Full bipolar SRAMs, al-
formation stored is destroyed if the power is in- though less than 1% of the total SRAM market,
terrupted. Such memories are therefore referred are still available in lower densities for very
to as volatile memories. If the data are stored high-speed applications. The lower end com-
(i.e., written into the memory) by setting the modity SRAMs are represented by the "mixed-
state of a flip-flop, they will be retained as long MOS" technology which is a combination of
as the power is applied and no other write sig- CMOS and NMOS for high-density applica-
nals are received. The RAMs fabricated with tions, and by the full CMOS technology for a
such cells are known as static RAMs, or combination of high-density and low-power
SRAMs. When a capacitor is used to store data requirements. High-speed and high-density
in a semiconductor RAM, the charge needs to SRAMs are fabricated in both CMOS and
be periodically refreshed to prevent it from mixed-Mfrfi technologies, as well as combina-
being drained through the leakage currents. tions of bipolars and CMOS, called BiCMOS.
Hence, the volatile memories based on this ca- SRAM speed has been usually enhanced
pacitor-based storage mechanism are known as by scaling of the MOS process since shorter
the dynamic RAMs, or DRAMs. gate channel length, L( eft) translates quite lin-
SRAM densities have generally lagged early into faster access time. Figure 2-1(a)
behind those for the DRAMs (1:4), mainly be- shows the plot of SRAM wafer average access
cause of the greater number of transistors in a time versus L( eff). This scaling of the process
static RAM cell. For example, a 256 kb SRAM from first -generation to second-generation
has about the same number of transistors as a 1 SRAMs has resulted in support of higher den-
Mb DRAM. However, static RAMs are being sity products, as shown in the L(eft) versus den-
widely used in systems today because of their sity logarithmic plot of Figure 2-1 (b). Section
low-power dissipation and fast data access time. 2.2 of this chapter discusses in detail various

10
 ....
Sec. 2.1 • Introduction 11

en 20 - - - - - - - - - - . - - - - - - - . , . - - - ,
.~,~..
Low-power dissipation and faster access times
£
w have been obtained, even with an increase in
•
~
~ 18 .....
'
chip size for every successive generation of
(f)
DRAMs, as shown in Figure 2-2 [2]. The

. ..•........
(f)
w
U
o DRAM memory array and peripheral circuitry
« 16 ,...
w
such as decoders, selectors, sense amplifiers, and

........ .
(!)
«a:: output drivers are fabricated using combinations
w 14.- of n-channel and p-channel MOS transistors. As
>
«
"

a: a result, 1 Mb DRAMs have reached maturity in

w 12
u, _ ___'_ ___'___ ___"__ _.....o--_----' production, and nowadays, 4 and 16 Mb
«
'---_~

~ 0.4 0.5 0.6 0.7 0.8 0.9 1.0 DRAMs are being offered by several manufac-
L(eff) (microns) turers. While the density of DRAMs has been
(a) approximately quadrupling every three years,
neither their access time nor cycle time has im-
3.0 proved as rapidly. To increase the DRAM
2.5 throughput, special techniques such as page
2.0
en mode, static column mode, or nibble mode have
c
1.5 •
0 FIRST been developed. The faster DRAMs are fabri-
U 1.2 • GENERATION
cated with speciallyoptimized processes and in-
I 1.0
e- 0.8 novative circuit design techniques. In some new
•
Q)
SECOND
::r 0.6 GENERATION DRAMsbeing offered with wide on-chip buses,
C)
0-J 0.5 1024-4096 memory locations can be accessed
0.4
in parallel, e.g., cache DRAMs, enhanced
0,3 DRAMs, synchronous DRAMs, and Rambus
0.2 L-...--...J~____'_---"_---""_ ___"_ --' DRAMs. Section 2.3 of this chapter discusses
4K 16K 64K 256K 1M 4M 16M 64M the DRAM technology development; CMOS
LOG DENSITY
DRAMs; DRAM cell theory and advanced cell
(b)
structures; BiCMOS DRAMs; soft-errorfailures
Figure 2-1. (a) SRAM wafer average access time
versus L(eff).(b) L(eff) versus SRAM
density logarithmic plot. (From [I], 500
with permissionof IEEE.) ACCESS: NOMINAL CONDITION
POWER : Vee + 10%, 25C
230ns CYCLE
§'
S
100 1000 a:
SRAM (NMOS and CMOS) cell structures; c:::;-
w
;:
MOS SRAM architectures, cell, and peripheral E 50
.s 500 0
0-
POWER
circuits operation; bipolar SRAM (EeL and w en
N
en .s
BiCMOS) technologies; silicon-on-insulator w
0- :E
(SOl) technologies; advanced SRAM architec- I i=
U 10 100
tures and technologies; and some application-
(f)
en
w
specific SRAMs. 5 ACCESS TIME 50 U
U
In the last decade of semiconductor mem- «
ories growth, dynamic random access memories
(DRAMs) have been produced in the largest 4K 16K 64K256K1M 4M 16M64M256M1G
quantities because of their high density and low MEMORYCAPACITY (bit)
cost per bit advantage. Maincomputermemories Figure 2-2. Trends in standard DRAM develop-
are mostlyimplemented using the DRAMs, even ment. (From [2], with permission of
though they lag behind the SRAMs in speed. IEEE.)
12 Chap. 2 • Random Access Memory Technologies

in DRAMs; advanced DRAM designs and archi- and two depletion mode pull-up transistors.
tectures; and a few application-specific DRAMs. A significant improvement in cost and power
dissipation was achieved by substituting ion-
implanted polysilicon load resistors for the two
2.2 STATIC RANDOM ACCESS
pull-up transistors. These were called R-Ioad
MEMORIES (SRAMs)
NMOS, and a successor to these is called the
"mixed-MOS" or "resistor-load CMOS." These
SRAM is classifiedas a volatilememorybecause
SRAMs consisted of an NMOS transistor ma-
it depends upon the application of continuous
trix with high ohmic resistor loads and CMOS
power to maintain the stored data. If the power is
peripheral circuits which allowed the benefit of
interrupted, the memory contents are destroyed
lower standby power consumption while retain-
unless a back-up battery storage system is main-
ing the smaller chip area of NMOS SRAMs.
tained. SRAM output widthrangesfrom 1 to 32 b
The transition from the R-Ioad NMOS to the R-
wide. Standard inputs and outputs include inter-
load CMOS SRAMs occurred at the 4 kb den-
facing with CMOS, TfL, and ECL circuits.
sity level. At the same time, the concept of
Power supply range includes standard 5 V and
power-down mode controlled by the chip enable
new 3.3 V standard for battery-powered applica-
pin (eE) also appeared. In this low-voltage
tions. A SRAM is a matrix of static, volatile
standby mode, the standby current for the
memorycells, and addressdecodingfunctions in-
mixed-MOS parts is typically in the microamp
tegrated on-chip to allow access to each cell for
(J..LA) range, and for the full CMOS, in the
read/write functions. The semiconductor memory
nanoamp (nA) range. This low-power dissipa-
cells use active element feedback in the form of
tion in the standby mode opened the potential
cross-coupled inverters to store a bit of informa-
for high-density battery back-up applications.
tion as a logic "one" or a "zero" state.The active
The mixed-MOS and the full NMOS de-
elements in a memorycell need a constant source
signs have higher standby currents than the
of de (or static) power to remain latched in the
CMOS SRAMs. However, the mixed-MOS
desired state. The memory cells are arranged in
technique provides better scaling advantages
parallel so that all the data can be receiv~d or .re-
and relatively lower power dissipation. The
trieved simultaneously. An address multiplexing
early CMOS RAMs with metal gate technology
scheme is used to reduce the numberof input and
were mostly used in the aerospace and other
output pins. As SRAMs have evolved, they have
high-reliability applications for their wider
undergone a dramatic increase in their density.
noise margins, wider supply voltage tolerance,
Most of this has been due to the scaling down to
higher operating temperature range, and lower
smaller geometries. For example, the 4 kb MOS
power consumption. MOS SRAMs be.c~me
SRAM used 5 J.Lm minimum feature size, while
more popular with the development of silicon
the 16 kb, 64 kb, 256 kb, and 1 Mb SRAMs were
gate technology in which the two levels of i.nter-
built with 3.0, 2.0, 1.2, and 0.8 IJ.m feature size,
connections through polysilicon and aluminum
respectively. Now,the 4 and 16Mb SRAMs have
allowed reduction in cell area, enabling the fab-
been developed with 0.6-0.4 IJ.m process tech-
rication of larger and denser memory arrays. In
nology. Also, scaling of the feature size reduces
the mid-1980s, a vast majority of all SRAMs
the chip area, allowing higher density SRAMs to
were being made in several variations, such as
be made more cost effectively.
the CMOS or mixed-MOS formation in n-well,
p-well, or the twin-tub technologies.
2.2.1 SRAM (NMOS and CMOS)
Figure 2-3 shows an MOS SRAM cell
Cell Structures
with load devices which may either be the en-
The basic SRAM cell made up of cross- hancement or depletion mode transistors as in
coupled inverters has several variations. The an NMOS cell, PMOS transistors in a CMOS
early NMOS static RAM cells consisted of six- cell, or load resistors in a mixed-MOS or an R-
transistor designs with four enhancement mode load cell. The access and storage transistors are
Sec. 2.2 • Static Random Access Memories (SRAMs) 13

through the cell, except during switching, The

depletion load and resistive load have a low
level of current flowing through them, and
hence the standby power dissipation is always
higher than that of the CMOS cell.
Figure 2-4(a) shows the basic CMOS
SRAM cell consisting of two transistors and two
load elements in a cross-coupled inverterconfig-
uration,with two select transistors added to make
up a six-transistor cell. Figure 2-4(b) shows
the use of polysilicon load resistors instead of
PMOStransistors in the CMOS cell, which allows
Figure 2-3. A general schematic of a SRAM mem- up to a 300/0 reduction in the cell size in double-
ory cell. polysilicon technology, using buried contacts.
There can be several application-specific
variations in the basic SRAM cell. Figure
enhancement mode NMOS.The purpose of load 2-4(c) shows an eight-transistor, double-ended,
devices (L) is to offset the charge leakage at the dual-port static cell. This is useful in cache ar-
drains of the storage and select transistors. chitectures, particularly as an embedded mem-
When the load transistor is PMOS, the resulting ory in a microprocessor chip. This chip can be
CMOS cell has essentially no current flow simultaneously accessed through both of the

(a) (b)

BIT

(c)
MATCH

(d)

Figure 2-4. Various configurations of CMOS SRAM cells. (a) Six-transistor full
CMOS. (b) Four transistors with R-load NMOS. (c) Dual-portwith
double-ended access. (d) Content-addressable memory(CAM).
14 Chap. 2 • Random Access Memory Technologies

ports. Figure 2-4( d) shows a nine-transistor and interface circuitry to external signals. The
content-addressable memory (CAM) cell. This memory array nominally uses a square or a rec-
is used in applications where knowledge of the tangular organization to minimize the overall
contents of the cell, as well as location of the chip area and for ease in implementation. The
cell, are required. rationale for the square design can be seen by
considering a memory device that contains 16K
I-bit storage cells. A memory array with 16K lo-
2.2.2 MOS SRAM Architectures
cations requires 14 address lines to allow selec-
Figure 2-5 shows (a) a typical SRAM basic tion of each bit (2 14 = 16,384). If the array were
organization schematic, and (b) the storage cell organized as a single row of 16 Kb, a 14-to-16K
array details. Each memory cell shares electrical line decoder would be required to allow individ-
connections with all the other cells in its row and ual selection of the bits. However, if the mem-
column. The horizontal lines connected to all the ory is organized as a 128-row X 128-column
cells in a row are called the "word lines," and the square, one 7-to-128 line decoder to select a row
vertical lines along which the data flow in and and another 7-to-128 line decoder to select a
out of the cells are called the "bit lines." Each column are required. Each of these decoders can
cell can be uniquely addressed, as required, be placed on the sides of the square array. This
through the selection of an appropriate word and 128-row X 128-column matrix contains 16,384
a bit line. Some memories are designed so that a cross-points which allow access to all individual
group of four or eight cells can be addressed; the memory bits. Thus, the square memory array or-
data bus for such memories is called nibble or ganization results in significantly less area for
one byte wide, respectively. the entire chip. However, the 16K memory may
In a RAM, the matrix of parallel memory also be organized as a 64-row X 256-column (or
cells is encircled by the address decoding logic 256 X 64) array.

! l
Vee GND
2 N Rows
Row
Address
1
1
2
2 One Cell
Row
Decoder
Memory Array
2 N Rows
2 M Columns

Column
Decoder

Column
Address

(a)

Figure 2-5. (a) A typical SRAM basic organization schematic.

Sec. 2.2 • Static Random Access Memories (SRAMs) 15

SelO ,. ~ ,

Data 0 Data 0 Data m Datam

(b)

Figure 2-5 (cont.), (b) The storage cell array details.

Most RAMs operate such that the row ad- propagation delay from the time when the ad-
dress enables all cells along the selected row. dress is presented at the memory chip until the
The contents of these cells become available data are available at the memory output. The
along the column lines. The column address is cycle time is the minimum time that must be al-
used to select the particular column containing lowed after the initiation of the read operation
the desired data bit which is read by the sense (or a write operation in a RAM) before another
amplifier and routed to the data-output pin of read operation can be initiated.
the memory chip. When a RAM is organized to
access n bits simultaneously, the data from n
2.2.3 MOS SRAM Cell and Peripheral
columns are selected and gated to n data-output
Circuit Operation
pins simultaneously. Additional circuitry, in-
cluding sense amplifiers, control logic, and tri- A basic six-transistor CMOS SRAM cell
state input/output buffers, are normally placed and its layout are shown in Figure 2-6. The bit
along the sides of a cell array. information is stored in the form of voltage lev-
The two important time-dependent perfor- els in the cross-coupled inverters. This circuit
mance parameters of a memory are the "read- has two stable states, designated as "1" and "0."
access time" and the "cycle time." The first If, in the logic state" 1," the point Cs is high and
timing parameter (access time) represents the point C6 is low, then T} is off and Tz is on; also,
16 Chap. 2 • Random Access Memory Technologies

C, AS

Cs
--+--4-----------+-----+-w
TS~""""""+_--t~..,......
B WI
..........~--+-I~~

(a) (b)

Figure 2-6. Six-transistor CMOS SRAM cell. (a) Schematic diagram. (b) Layout. (From Bastiaens and Gubbels
[3], 1988, with permission of Philips Electronics, Eindhoven, The Netherlands.)

T3 is on and T4 is off. The logic HO" state would lower than B. This differential signal is detected
be the opposite, with point Cs low and ('6 high. by a differential amplifier connected to the bit
During the read/write operations, the row ad- and bit lines, amplified, and fed to the output
dress of the desired cell is routed to the row ad- buffer. The process for reading a "0" stored in
dress decoder which translates it and makes the the cell is opposite, so that the current flows
correct word line of the addressed row high. through Ts and T} to ground, and the bit line B
This makes transistors Ts and T6 in all cells of has a lower potential than B. The READ opera-
the row switch Han." The column address de- tion is nondestructive, and after reading, the
coder translates the column address, and makes logic state of the cell remains unchanged.
connection to the bit line B and the inverse bit For a WRITE operation into the cell, data
line B of all cells in the column addressed. are placed on the bit line and data are placed on
A READ operation is performed by start- the bit line. Then the word line is activated. This
ing with both the bit and bit lines high and se- forces the cell into the state represented by the
lecting the desired word line. At this time, data bit lines, so that the new data are stored in the
in the cell will pull one of the bit lines low. The cross-coupled inverters. In Figure 2-6, if the in-
differential signal is detected on the bit and bit formation is to be written into a cell, then B be-
lines, amplified, and read out through the output comes high and B becomes low for the logic
buffer. In reference to Figure 2-6, reading from state" I." For the logic state "0," B becomes low
the cell would occur if Band B of the appropri- and Ii high. The word line is then raised, causing
ate bit lines are high. If the cell is in state HI," the cell to flip into the configuration of the de-
then T) is off and T2 is on. When the word line sired state.
of the addressed column becomes high, a CUf- SRAM memory cell array's periphery con-
rent starts to flow from B through T6 and T 2 to tains the circuitry for address decoding and the
ground. As a result, the level of 1J becomes READIWRITE sense operations. Typical write
Sec. 2.2 • Static Random Access Memories (SRAMs) 17

circuitry consists of inverters on the input RAMs are considered clocked or not
buffers and a pass transistor with a write control clocked, based on the external circuitry. Asyn-
input signal to the bit and bit lines. Read cir- chronous (nonclocked) SRAMs do not require
cuitry generally involves the use of single- external clocks, and therefore have a very sim-
ended differential sense amplifiers to read the pIe system interface, although they have some
low-level signals from the cells. The data path is internal timing delays. Synchronous (clocked)
an important consideration with the SRAMs, SRAMs do require system clocks, but they are
since the power delay product is largely deter- faster since all the inputs are clocked into the
mined by the load impedance along the data memory on the edge of the system clock.
path. The read data path circuitry can be static or
dynamic. SRAMs have been designed which
2.2.4 Bipolar SRAM Technologies
turn on or turn off the various sections of data
path as needed to reduce the operating power of The earliest semiconductor memories
the device. The internal signals in an outwardly were built in bipolar technology. Nowadays,
"static" RAM are often generated by a tech- bipolar memories arc primarily used in high-
nique called "Address Transition Detection" speed applications. Bipolar RAMs are often
(ATD) in which the transition of an address line "word-oriented" and require two-step decoding.
is detected to generate the various clock signals. For example, in a I-kb X I-b memory orga-
The input circuitry for SRAMs consists of the nized as a 32-row X 32-colull1n array, the row
address decoders, word line drivers, and de- decoder selects one of the 32 rows, and all of the
coder controls. Figure 2-7 shows the various 32 b (the "word") are read out and placed in a
SRAM circuit elements. register. A second 5 b code is used to access the

:~~fD CLOCK----al

WORD
WORD
LINE

A2 ~ to-----WORD BUFFER

(a)

BIT BIT

BIT-(
DATA IN

DATA

(c) (d)

Figure 2-7. VariousSRAM circuit elements. (a) Static row decoder. (b) Dynamic row decoder. (c) Simple write
circuitry. (d) Inverter amplifier. (e) Differential sense amplifier. (From [4}. with permission of
Wiley, New York.)
18 Chap. 2 • Random Access Memory Technologies

register and select the desired bit. Similarly, sistors, two resistors, and a power source. In this
the data are stored by writing an entire word configuration, one of the transistors is always
simultaneously. The broad category of bipolar conducting, holding the other transistor OFF.
memories include the SRAMs fabricated in When an external voltage forces the OFF tran-
direct-coupled transistor logic (DCTL), emitter- sistor into conduction, the initially ON transistor
coupled logic (ECL), and mixed BiCMOS tech- turns off and remains in this condition until an-
nologies. other external voltage resets it. Since only one
of the cross-coupled transistors conducts at any
2.2.4.1 Direct-Coupled Transistor Logic given time, the circuit has only two stable states
(DCTL) Technology. The architectures for which can be latched to store information in the
bipolar SRAMs are basically similar to those of form of logic 1s and Os. The cell state is stable
MOS SRAMs. Historically, transistor-transistor until forced to change by an applied voltage.
logic (TTL) has been the most commonly used The circuit in Figure 2-8 is an expanded
bipolar technology. A simple bipolar DCTL version of the DCTL memory cell [5], [37]. In
RAM memory cell consists of two bipolar tran- this figure, the data lines are connected to Q1

3.5V

2.5 V _R_t-- ---t..-- ---+_ _

~
0.4 V

Write 1 Read 1 Write 0 Read 0

2.5
R

C
1.5 V

\ 2.5V
C 1.5V~
/ \. ./
I
Figure 2-8. Direct-coupled memory cell (DCTL) with Schottky diodes. (From D. A. Hodges and H. Jackson
[37], with permission of McGraw-Hill Inc., New York.)
Sec. 2.2 • Static Random Access Memories (SRAMs) 19

and Q2 through the Schottky diodes D 1 and D2. "1," the row is pulled low, and current flows
To explain the operationof this cell, assume that through C through D2, R4 , and Q2 to R. The re-
a stored 1 corresponds to the state with Q2 on. sulting drop in voltage on C indicates the pres-
The row selection requires that the row voltage ence of a stored "1."
should be pulled low. To write a "1," the voltage
on line C is raised, forward-biasing diode D r: 2.2.4.2 Emmiter-Coupled Logic (ECL)
This forces sufficientcurrent through R1 so that Technology. Another popular bipolar technol-
the voltage at node 1 increases to tum on Q2' ogy is the emitter-coupled logic (EeL). The
The current gain of Q1 is sufficiently high, and EeL memories provide very small access times
it remains in saturation so that most of the volt- with typical propagation delays of less than 1 ns
age drop appears across R3. When Q2 turns on, and clock rates approaching 1 GHz. This high
its collector voltage drops rapidly, turning off performance is achieved by preventing the
Q I' The currents in R I and R2 are always much cross-coupled transistors from entering into the
smaller than the current used for writing, so that saturation region. Figure 2-9 shows an EeL
the voltage drops across R3 and R4 are much memorycell [37]. In this configuration, the data
smaller than Vbe(on)' In the standby condition, lines are connected to the emitters of the two
D 1 and D2 are reverse-biased. To read a stored transistors. Although both transistors have two

..5::::
1.3V
_R.....~------ .......-

~ _R_-+- ~.--_---__+_--
O.3V

1.5V

Write 1 Read 1 Write 0 Read 0

'---------------
x.;---.II
C 1.5 V \ -----"~
o
C 1.5V

Figure 2-9. Emitter-coupled logic (EeL) memory cell. (From D. A. Hodges and H. Jackson [37], with permis-
sion of McGraw-Hili Inc., New York.)
20 Chap. 2 • RandomAccess MemoryTechnologies

emitters each, this cell is not a TTL circuit be- technology was the high packaging density
cause they operate in their normal mode (as op- since the cells were quite compact, in contrast to
posed to the inverted) modes. The operation of the conventional bipolar memory cells using re-
the cell is based on using the multiple-emitter sistors for the load impedance of the flip-flop
transistors as the current switches. The voltage transistors. However, I2L technology for memo-
levels are selected such that these transistors ries failed to be commercially successful be-
never conduct simultaneously. The read and cause of the process- and structure-related
write operation is controlled by switching the dependencies of its speed-power performance
current in the conducting transistor from the characteristics. The BiCMOS technology was
row line to the appropriate data line. preferred for high-speed and high-performance
The basic operation of an ECL cell is ex- applications.
plained with Figure 2-9. Assume that a logic '~I"
is stored with Q} on. The row selection requires 2.2.4.3 BiCMOS Technology. In high-
that both Rand R* go to the positive levels as density and high-speed applications, vario:... ~
shown. To write a "I," the column line C must combinations of bipolar and MOS technologies
be held low, which forward-biases the emitter of have been investigated.The BiCMOS process is
Q l' regardless of the previous state of the cell. more complex because of the additional steps
As a result, the collector-emitter voltage of QI required. Bipolar ECL input and output buffers
drops quickly, removing the base drive from Q2' have been used with the CMOS memories, both
When the row voltage returns to the standby to interface to a bipolar circuit as well as to in-
levels, Q I remains "on," with its base current crease the performance. The CMOS memory
coming from R2. Cell current flows through Q) cells have lower power consumption, better sta-
and returns to ground through the line R. The bility, and a smaller area compared to an equiv-
emitters connected to C and Care reverse- alent bipolar cell. Therefore, the BiCMOS
biased in the standby condition. To read a stored designs offer optimization of these parameters,
"1," the cell is selected in the same way as for since the various circuit elements are selectively
writing. The emitters connected to R become chosen to maximize the performance [6]. For
reverse-biased, and the current flowing in Q1 example, since the bipolar n-p-n output transis-
transfers to the emitter connected to C. The tors provide large output drive, BiCMOS gates
resulting rise in voltage on C indicates the pres- are effective with high capacitive nodes, such as
ence of a stored "I." The writing and reading those in the decoders, word line drivers, and
operation for a "0" are complementary to those output buffers. The control logic with small fan-
described for a "1." out can still use CMOS gates. The sense ampli-
A major drawback in the ECL technology fiers which require high gain and high input
is that a very low value of resistors is required, sensitivity for fast sensing of small differential
which results in a constant current in the storage bit line swings are built in bipolar logic. Figure
cell. This constant current drain causes rela- 2-10 shows the BiCMOS circuit elements with a
tively higher power dissipation compared to the typical mix of various technologies [7]. There
TfL or MOS memories. can be some variations on this technology mix,
Another bipolar logic developed in the depending upon the manufacturer's process.
1970s was the integrated injection logic (I2L). In a typical double-polysilicon technology
This evolved from the bipolar memory cell de- CMOS SRAM process, the first poly level
sign in which the old direct-coupled transistor forms the MOS transistor gate; the second poly
logic (DCTL) was shrunk to the single comple- level forms highly resistive load resistors in the
mentary transistor equivalent. In memory cells, four-transistor CMOS memory cell, and makes
lateral p-n-p transistors were used as the current contact to the silicon substrate. Since a poly-to-
source and multicollector n-p-n transistors as substrate contact already exists in such a
the inverters. The major attractive feature of this process, a bipolar transistor with a polysilicon
Sec. 2.2 • Static Random Access Memories (SRAMs) 21

..
GI
Memory Cell
Poly 1
s
;:
~Mern !l ry-C9tr~
-
..
~ array=_=_~
-- =-- =- = = : .::: .:.
GI
;:
::l
lD
'5
1-.-Y:ckco(h!r~ ~l 0-
'5
o
D Bipolar IY-pre-decoder I Bipo lar Transistor
Poly 2

I V-input butler I
D BiCMOS
DeMOS

Figure 2-10. BiCMOS circuit elements.

emitter can be produced with minimum com- (a)

plexity. The emitter is created by a dopant diffu-
sion from a doped poly into the silicon substrate
where an implanted base is present. Figure 2-
II (a) shows the schematic cross-section of a
double-polysilicon SRAM with second poly as
a bipolar emitter [81 .
A high-performance CMOS process can
be obtained from a core CMOS process by the
addition of a few steps such as: (I) use of a
(b)
buried layer and an epitaxial layer, (2) a base re-
gion for bipolar transistors usually by ion im-
Figure 2-11. Schematic cross-sections. (a) A dou-
plantation, and (3) an additional collector region
ble-polysilicon SRAM with second
(collector sink or collector plug) to reduce col- poly as bipolar emitter. (b)Typical
lector resistance. Typically. the added steps may process enhancements for creating
increase process complexity by 10-20%. Figure BiCMOS [8).
2-11 (b) shows the typical enhancements to a
core double-polysilicon process for creating
high-performance BiCMOS memories. lows more cells per bit-line pair without signifi-
The higher density commodity SRAMs cantly increasing the delay.
tend to exhibit a balance of speed and power A 4 Mb BiCMOS SRAM was developed
characteristics. The various density levels of by Fujitsu in 1991. It uses a wired-OR data bus
very high-speed CMOS and BiCMOS SRAMs in the sense circuit, a column redundant circuit,
are specifically designed to optimize per- and a 16 b parallel test circuit [91 . Figure 2-
formance, often at the expense of chip area 12(a) shows a block diagram of this SRAM. It
and power consumption. The new generation has a typical address access time of 7 ns, a write
BiCMOS includes many improvements. such as pulse width of 4 ns, and active current consump-
the use of fast data bus in the sense circuit: paral- tion of about 120 mA for a 4M X l-b configura-
lel test circuits using the ECL sense amplifiers; tion. A symmetrical chip layout divides the bit
optimized division of memory matrix to reduce lines, word lines. and decoder lines to reduce
parasitic capacitance on the signal lines (bit. the ground noise from high-speed operation.
word, and decoder); and column redundant cir- The memory matrix is divided into four planes,
cuits suitable for divided word line architectures. each consisting of 16 blocks. The column re-
The use of low-resistance metal interconnects al- dundant circuit is shown in Figure 2- l2(b). The
22 Chap. 2 • Random Access Memory Technologies

CSW& PSA CSW&PSA

ColumnDecoder ColumnDecoder
-- -Data BaSS Pa~s- -
CSW& PSA CSW& PSA

(a)

PLANE-SEL.
Y-ADD. 3 ~-+---------+----+-f---.J-+"""
Y-ADD. 2 --.-+----------+--t-+-+-~_+_ -
Y-ADD. 1 '-4-+-1...--------+-+-+-+--+-~H_+_+.....
X-ADD. 1 "+-i~I-------__+--+-+-........-+-~t_+__+_+-

2nd Poly 1st AI 1st Poly 3rd Poly

Normal Columns Redundant Columns

(b) (c)

Figure 2-12. Fujitsu 4 Mb SRAM. (a) Block diagram. (b) Column redundant circuit. (c) Cross-section. (From
[9], with permissionof IEEE.)

redundancy is provided by two rows and eight SRAM, only four redundant column arrays are
columns, which provide more flexibility than placed in the 1 Mb plane to form a redundant
the conventional architecture. The column ar- section, and they are used for any column array
rays are distributed throughout each block and in the plane. The process technology is 0.6 um
can replace cells within the block. In this 4 Mb triple-polysilicon and double-metal BiCMOS.
Sec. 2.2 • Static Random Access Memories (SRAMs) 23

The first polysilicon layer forms the gate elec- that performsthe following three functions: cre-
trodes of the MOS transistors, and the second ating self-aligned contact landing pads in the
layer forms the emitter electrodes of the bipolar SRAM bit cell, forming an emitter of the bipolar
transistors. For memory cells, the VEE lines are n-p-n transistor, and providing a global inter-
formed with the second polysilicon layer, and connect. The third polysilicon layer forms the
the 50 GO loads are formed with the third poly- teraohm resistor load for the bit cell. This
silicon layer. The minimum gate lengths are 0.6 process provides a peak cutoff frequency (fr) of
and 0.8 J.1m for the NMOS and PMOS transis- 14 GHz with a collector-emitter breakdown
tors, respectively. The thickness of the gate voltage (BV CEO) of 6.5 V, and ECL minimum
oxide is 15 nm. Figure 2-12(c) shows the cross- gate delays of IOS·ps at a gate current of 3S0
section of this BiCMOS device. f.1A/J.1m 2 have been achieved.
A 0.5 urn BiCMOS technology has been The mainframe computers and supercom-
developed for fast 4 Mb SRAMs in which bipo- puters require high-speed ECL 110 SRAMs,
lar transistors are added to an existing 0.5 urn whereas the high-performance workstations
CMOS process [10]. This process requires the usually requireTTL 110 SRAMs operating with
growth of a thin epitaxial layer, as well as the microprocessors at low supply voltages. In
addition of three masking steps as follows: self- order to meet both of these requirements, an ap-
aligned buried layer, deep collector, and active proach has been developed that uses the metal
base. The original CMOS process featured self- mask operation technique to fabricate a 4 Mb
aligned twin-well formation, framed mask poly- BiCMOS SRAM that can have either a 6 ns ac-
buffered LOCOS (FMPBL) isolation, a 150 A cess time at 750 mW and 50 MHz, or an 8 ns
thick gate oxide, surface-channel NMOS and access time at 230 mWand 50 MHz using an
buried-channel PMOS transistors, disposable ECL lOOK or 3.3 V TTL interface, respectively
polysilicon spacer module, three levels of poly- [11]. A 3.3 V supply voltage is desirable for
silicon, and two layers of metallization. Figure MOSFETs with a 0.55 urn gate length to ensure
2-13 shows the schematic cross-section of this higher reliability. For an ECL lOOK interface,
technology [10]. Three levels of polysilicon are EeL I/O buffers are supplied at -4.5 V VEE'
used in this process. The first layer is the gate while the 4 Mb SRAM core circuit is suppliedat
electrode for the CMOS transistors. The second -3.3 V VEE" which is generated by an internal
layer is the tungsten-polycide/polysilicon stack voltage converter. The 4 Mb SRAM core con-
sists of BiCMOS address decoders, MOS mem-
ory cells, and bipolar sense amplifiers.
In order to achieve high-speedaddress ac-
cess times, a combinationof the following tech-
nologies were used:

• A Bi-NMOS converter that directly con-

verts the ECL level to a CMOS level
• A high-speed Bi-NMOS circuit with
low-threshold-voltage NMOSFETs
• A design methodology for optimizing
P + BURIEDLAYER
N.... BURIEDLAYER
both the number of decoder gate stages
N-WELL and the size of gate transistors
< 100> P·SUBSTRATE
NMOS PMOS NPN
• High-speed bipolar sensing circuits for
3.3 V supply voltage.
Figure 2-13. Schematic cross-section of the 0.5 urn
BiCMOS technology. (From [10], with This process was used to fabricate a 4 Mb
permission of IEEE.) SRAM in 0.55 J-Lm BiCMOS technology with
24 Chap. 2 • Random Access Memory Technologies

quadruple-level polysilicon, double-level metal, 2.2.5 Silicon-an-Insulator

p-substrate, and triple-well. The first-level (SOl) Technology
polysilicon layer was used for the MOSFET
gate electrodes, the second poly for VEE' (- 3.3 The MaS and bipolar technologies dis-
V), the third poly for high resistive loads in cussed so far are referred to as the bulk silicon
memory cells, and the fourth level poly for technologies. Traditionally, dielectrically iso-
bipolar emitter electrodes. In memory cell ar- lated (01) processing has been used to reduce
rays, double-level metal layers were used for the charge generation in the substrate and to ob-
bit lines (first level) and word lines (second tain radiation hardness for military and space
level). The memory cell size is 5.8 X 3.2 f..Lm 2 applications. This fabrication technique is par-
and consists of two high resistive loads and ticularly suited to bipolar devices which need a
four NMOSFETs. thick active layer. Since the 1960s, a significant
An experimental 16 Mb BiCMOS SRAM amount of work has been done using sapphire
has been developed in 0.4 J.Lm process to achieve for both substrate and insulator; this technology
220 MHz fully random read-write operations was called silicon-an-sapphire (SOS), and is a
[ Ill]. The memory circuit design techniques restricted version of the sal technology. The
include the following: (1) zigzag double word enhanced device performance (increase in
line, (2) centralized bit-line load layout, and speed) of sal device structures results from the
(3) phase-locked loop (PLL) with a multistage- reduced parasitic substrate capacitance, while
tapped (MST) voltage-controlled oscillator the improved radiation hardness results from the
(VCO). This VCO consists of a voltage-current absence of charge generation in the silicon sub-
converter and a nine-stage current-limited strate.
CMOS inverter ring oscillator. The internal In sal technology, small islands of silicon
SRAM timing pulses are generated from the out- are formed on an insulator film. Using SOl fab-
put signals at each stage and are proportional to rication processes coupled with lateral isolation
the clock cycle. Since all the timing margins can techniques, completely latchup free circuits
be expanded by making the clock cycle time can be fabricated because there are no parasitic
longer, this technique allows more flexibility for p-n-p-n paths. Also, the SOl films can be made
high-frequency timing designs. The PLL is used extremely thin, resulting in fully depleted
as an internal clock generator to achieve a clock MOSFETs which have been shown to operate at
frequency above 200 MHz. very high speeds (2 GHz) [12]. Thin-film
In this 16 Mb BiCMOS memory design, SOl/CMOS devices and circuits have reduced
the internal SRAM macro is made fully static short channel effects, reduced hot electron gen-
(asynchronous) by using the bipolar sensing cir- eration, and sharper subthreshold slopes [13].
cuits which operate at high speed with only However, because of relatively low wafer yield
small bit-line voltage swing and do not require problems, the major market for SOl chips is in
clocked equalization that is used in the CMOS military and aerospace applications. The real
sensing operations. It uses the wave pipeline impact of SOl technology on the commercial
technique, which implies that at a certain time market is expected to occur in the manufactur-
period, two signals (waves) exist simultane- ing of submicron devices (0.25 urn) since, at
ously on the data path. The bit-line delay is min- that point, the production costs for bulk/epi
imized by optimizing the location of bit-line wafers will be greater or equivalent to the sal
load (BL load) PMOSFETs. To reduce the time wafers.
for write to the same as that for the read opera- Some of the important sal technologies
tion, postwrite equalizer (PW Eq) PMOSFETs used to produce the starting material include:
are distributed to three positions on a bit-line separation by implanted oxygen (SIMOX), zone
pair. A write cycle time of 4.5 ns is achieved melt recrystallization (ZMR), full isolation by
using this layout. porous oxidized silicon (FIPOS), epitaxial
Sec. 2.2 • Static Random Access Memories (SRAMs) 25

lateral overgrowth (ELO), wafer bonding and delays (or higher operating speeds) per stage for
etchback (a modified DI process), and silicon- the sal devices relative to bulk CMOS [16].
on-sapphire (SOS) process. SOl 64 kb SRAM fully functional proto-
SIMOX is the most commonly used tech- types have been demonstrated by some compa-
nique, and requires a high dose of oxygen (0-) nies. The sal SRAMs with 256 kb and higher
ions, which provides the minimum concentra- densities are under development. SIMOX is
tion necessary to form a continuous layer of attractive for military and space electronic
Si0 2. The energy of the implant must be high systems requiring high-speed, low-power,
enough so that the peak of the implant is suffi- radiation-hardeneddevices that can operate reli-
ciently deep within the silicon (0.3-0.5 urn). ably over a wide temperature range. It is a good
The wafer is normally heated to about 400°C candidate for power IC and telecommunications
during the implantation process to ensure that applications which must integrate low-voltage
the surface maintains its crystallinity during the control circuits with the high-voltage devices
high implantation dose. A postimplant anneal is [14]. This technology is well suited for integrat-
performed in neutral ambient (N 2) or He for a ing the bipolar and CMOS devices on the same
sufficient time (3-5 h) at a high temperature chip. The use of wafers on which no epitaxial
(IIOO-1175°C) to form a buried layer of Si02. layer is deposited following oxygen implanta-
This anneal step also allows excess oxygen to tion and annealing (referred to as thin-film
out-diffuse, thereby increasing the dielectric SIMOX) has also been studied. Thin-film
strength of the buried-oxide layer. After the an- SIMOX processing is simpler than a bulk
nealing step, the crystalline silicon surface layer process because there is no need to form doped
is typically only 100-300 nm thick [14]. There- wells, and shallow junctions are automatically
fore, an additional layer of epitaxial silicon is formed when the doping impurity reaches the
deposited so that single-crystal regions (0.5 J.1m underlying buried oxide. However, the SIMOX
or greater) are available for fabrication. process does have a number of disadvantages,
A simplified cross-section of a thin-film including the following:
SOl CMOS inverter is shown in Figure 2-14(a)
[15]. A comparison was made betweenthe device • The process requires the availability of
and the circuit performance of 0.5 J.1m CMOS on special oxygen implanters.
an ultra-thin sal ring oscillatorwith 0.4 urn bulk • The thickness of the buried oxide layer
CMOS devices. Figure 2-14(b) shows smaller is limited to about 0.5 urn, whereas for

. .

en
sQ)
150
C>
co
en
~ 100
>-
co
0

0
•••
Q)
a o 0
50 o 0 c 0
0 0
Silicon Substrate
2 3 4 5 6 7
Power Supply Voltage (V) (0 Sal, • bulk).

(a) (b)

Figure 2-14. (a) Cross-section of a thin-film SOl CMOS inverter [15]. (b) Delay for bulk CMOS and SIMOX
fora ring oscillator [16]. (From [15] and [161, with permission of IEEE.)
26 Chap. 2 • Random Access Memory Technologies

some high-voltage applications, a radiation effects and circuit-hardening tech-

greater thickness may be required. niques are discussed in more detail in Chapter 7.
• The SOl surface silicon film and the de- The early CMOS/SOS logic devices such
posited epitaxial layer may contain as the gates, flip-flops, buffers, and small coun-
some residual damage from the implant ters were fabricated with an aluminum-gate
process. The implantation parameters process on n-type silicon islands, where the
and annealing schedules must also be NMOS and PMOS transistors were formed and
appropriately chosen to provide opti- interconnected. The gate alignedover the channel
mum IC performance because the mi- after formation of the channel region overlapped
crostructure of the surface silicon film is both the source and drain regions to assure a total
very sensitive to the oxygen dose and channel coverage. However, this overlap created
the postoxygen-implant annealing tem- gate-to-source and gate-to-drain capacitance,
perature. which increased the switching delays. This AI-
gate process was subsequently replaced by the
Due to the floating substrate, SOl MOS- silicon-gate technology, which offered improved
FETs show a dip in their I-V characteristics, performance, In the silicon-gate process, the
generally known as "kink effect." However, in channel oxide and the polysilicon gate structure
the SOl RAMs, this kink effect has been elimi- are defined prior to the source and drain. The
nated by electrically shorting the source and polysilicon gate then serves as a mask to define
substrate. In the zone-melting recrystallization both the source and the drain; thus, the gate is
(ZMR) process, which is currently in evolution, perfectly aligned with no overlap in this "self-
the basic steps consist of oxidation and poly-Si aligned silicon-gate" technique. In the following
deposition, followed by a zone-melting tech- steps, an oxide is deposited (or grown) over the
nique to recrystallize the polysilicon. The melt- gate, contact windows are defined in the oxide,
ing of the polysilicon layer can be accomplished and aluminum metallization is applied for the in-
by lasers, electron beams, arc lamps, or strip terconnections. Figure 2-15 shows the various
heaters. The ZMR fabrication equipment is rela- processing steps for RCA (now Harris Corpora-
tively inexpensive compared to that for the tion) CMOS/SOStechnology [17].
SIMOX process. The ZMR defect densities are In summary, the key features of a
being improved through seeding, the use of en- SIMOX-based process are the extended temper-
capsulation layers, and other process-enhance- ature range compared to bulk silicon, lower par-
ment techniques [13]. asitic capacitance from reduced junction areas,
The silicon-on-sapphire (SOS) technol- and dielectric isolation which provides latchup
ogy has been extensively used for military and immunity. SIMOX is the most commonly used
space applications. In SOS, the active device is - SOl technique suitable for VLSI fabrication, al-
built upon a silicon island on a sapphire sub- though it requires expensive ion implanters and
strate. Thus, all n-channel transistors are com- long implant times. Thomson-CSF Semicon-
pletely isolated from the p-channel transistors ductors uses an SOI-HD process with side and
by the sapphire substrate. There are no parasitic bottom oxides which provide total isolation of
transistors to latch up in the SOS, and the capac- the device. Figure 2-16 shows the cross-section
itance associated with the reverse-biased sub- of this thin CMOS SOI-HD structure which
strate junctions is eliminated. This gives the uses a special gate oxide process to achieve high
SOS process an important advantage over the resistance against various types of radiation, in-
bulk CMOS in terms of switching speed [17]. cluding the neutrons and heavy ions [112]. This
The sapphire substrate provides inherent radia- technology, available in two versions as 1.2 J.1m
tion hardness against the alpha-particle-induced (HS013-HD) and 0.8 J.1m (HSOI4-HD) design
soft errors; ionizing total-dose, transient, and rules with two and three metal levels, is used in
neutron radiation; and cosmic ray upsets. These fabricating 16,64, and 256K SRAMs.
Sec. 2.2 • Static Random Access Memories (SRAMs) 27

\ I \ PHOSPHORUS (n')
EPI EPI
SAPPHIRE
+ + + t + + + + + + , +
• ISLANDDEFINITION
(a)
PHOTORESIST
• PHOSPHORUS (n') ION IMPLANT
(f)
++ +

• BORONIMPLANT
(b) • CONTACT I
(g)
CHANNEL OXIDE

_.-...---
POC1 3 DIFFUSION
POLY

• CHANNELOXIDE -BPSG
• POLYSILICON DEPOSITION - OPEN CONTACT ON PSG
• POCI3 DIFFUSION • REFLOW
(c) (h)
PSG AI

f?4
POLY Si0 2

II ~GATE ~
}
• POLYSILICON GATE DEFINITION
• OXIDEGROWTH - ALUMINUM DEPOSITION
(d) (i)
BORON (p~) KEY:
PHOTORESIST
t t t t t t t t t t t.t
~

Ii P: i
~ 200AAI 1:·:;:··3 OXIDE(Si0 2 ) _ BPSG

OAI

• BORON (p") ION IMPLANT

(e)

Figure 2-15. Typical RCA CMOS/SOS processing steps. (From RCA Databook [17], with permission of Harris
Corporation.)

As bulk CMOS technology advances to- latchup elimination. The SOl MOSFETs can be
ward sub-O.25 IJ-m channel length, the SOl tech- made fully depleted, allowing only unidirec-
nologies appear promising because of their tional current flow in the circuit. This virtually
reduced parasitic capacitance, lower threshold eliminates the kink effect normally associated
voltage and body-charging effects. In general, with the SOS/SOI MOSFETs because of the
substantial advantages are being projected for floating substrate. The hot electron effect which
the SOl memory technology, especially in the causes threshold instabilities in the MaS de-
military and space environment, because of a vices through charge injection in the gate oxide
substantial reduction in the soft-error rate and is also reduced in the fully depleted SOl.
28 Chap . 2 • Random Access Memory Technologies

Passivation

Interlayer dielectric 2

-i- " "

Poly 51 gate

p substrate . .-

Figure 2-16. Thomson-CSF Semiconductors CMOS SOI-HD

process cross-section [112).

A new low-power and high-stability SOl low fan-in, low fan-out. However, it has been
SRAM technology has been developed by using difficult to design RAM blocks for these high-
laser recrystallization techniques in which self- speed CMOS circuits. A technique has been de-
aligned. p-channel SOl MOSFETs for load de- veloped for a high-speed CMOS RAM structure
vices in memory cells are stacked over bottom based on a six-transistor (6-T) static memory
n-channel bulk MOSFETs for both driver and cell, which is capable of several hundred million
transfer gates in a 3-D configuration [18J. For accesses per second [113]. This technique uti-
process simplicity, no specific planarization lizes the following key design approaches:
process is utilized for an intermediate insulating
layer between the top SOl and bottom bulk • A proper pipelining of the address de-
MOSFETs. This technique increases the on/off coder with an option to include pre-
ratio of SOl MOSFETs by a factor of 104, and charged logic in the latches.
reduces the source-drain leakage current by a • Integration of a high-performance sense
factor of 10-100 compared with that for polysil- amplifier in the clocking scheme that in-
icon thin-film transistors (TFTs) fabricated by cludes two types of latches--one that
using low-temperature regrowth of amorphous generates new output during a clock low
silicon . A test 256 kb SRAM was fabricated (p-Iatches), and the second type, during
using this process with only memory cell re- a clock high (n-Iatches).
gions in a stacked 3-D structure and peripheral
circuits in conventional CMOS technology. The This new RAM technique was demon-
total number of process steps is roughly the strated in the design of a 32-word X 64-b (2048
same as that for polysilicon TFT load SRAMs. b), three-ported (two read and one write) regis-
The process steps can be reduced to 83% of ter file running at 420 MHz, using a standard 1.0
those for the TFT load SRAMs if both the pe- J.Lm process.
ripheral circuit and memory cells are made with
p-channel SOl and n-channel bulk MOSFETs.
2.2.6 Advanced SHAM Architectures
In recent years, several circuits with oper-
and Technologies
ating frequencies above 400 MHz have been
designed in the industry standard CMOS 2.2.6.1 1-4 Mb SRAM Designs. SRAM
processes. Typically, these designs are highly speed has usually been enhanced by scaling
pipelined, i.e., they use a clocking strategy with down the device geometries. The shorter gate
a single clock net. Also, these designs use care- channel length, L(eff) translates quite linearly
ful device sizing and their logical blocks have into faster access times. The scaling of the
Sec. 2.2 • Static Random Access Memories (SRAMs) 29

process also results in higher density memories. been primarily responsible for the density and
Since 50-60% area of a SRAM is the memory performance improvements [I].
array, the problem of reducing the chip size di- The polysilicon load resistors have been
rectly relates to reducing the cell area. Figure 2- commonly used up to I Mb SRAM designs;
17(a) shows the cell size as a function of SRAM however, their use at 4 Mb and higher densities
density [4]. Figure 2-l7(b) shows the evolution to achieve both low power and high speed be-
of MOS SRAMs: the shrinking line widths and comes quite challenging. The requirement for a
a variety of process enhancements which have small chip size demands a very small memory
cell, which can only be obtained by the scaled
1000 , . . . - - - - - - - - - - - - - - - - , polyresistor cell. The standby current require-
ment sets a minimum value to the load resis-
tance. On the other hand, the resistance must be
small enough to provide sufficient current to the
storage node so that the charge does not leak
100 away. Another factor in the design of an R-Ioad
N cell is that the power supply of the memory
E
~ array in the 0.5-0.6 J,Lm technologies has to be
Q)
N
0(i) less than 5 V, even though the external chip sup-
Q) ply voltage is maintained at 5 V.
U
10 Several companies continued to optimize
the R-Ioad cell at the 4 Mb SRAM density level,
whereas the others looked for an alternative cell
which would reduce the drawbacks of the R-
load cell but retain its small size. An alternative
approach in the 4 Mb generation was the de-
velopment of a six-transistor cell with four
64K 256K 1M 4M 16M 64M 256M NMOS transistors in the silicon substrate and
Density the two PMOS load transistors formed in the
(a) thin-film polysilicon layers above the cell, in the
same manner as the resistor loads were stacked
in the R-load cell. A I Mb SRAM with stacked
45
transistors-in-poly cell in 0.8 J.1m technology
~ 35
<'0
FIRST
GENERATION
was developed by NEe in 1988 [19]. This
~ 25 • • SRAM employed the p-channel polysilicon re-
o
(/)

~
20
SECOND
• • • sistors as cell load devices with offset gate-drain
U 15 GENERATION • o
structure in the second-level poly with the gate
U
~
(!)
12
10 CMOS 0
o
below it in the first-level poly. It was stacked on
9 8 ~~~~~~ ~~~~~~SMET AL ~~~y~~~~~~NNT;
0
the n-channel driver transistors. This verticalcell
NMOS LOCAL AMPS SELF·ALlGNED CNTS
BLOCK ARCHT. INTERCON. ADVANCES BIOMOS
offered the size benefit of the R-Ioad resistor cell
~I. ·1-
_
5'----~-..I..--..L.-.._~_....I..__-L-
-, __L._....J and the noise margin of the six-transistor cell.
4K 16K 64K 256K 1M 4M 16M 64M
LOG DENSITY
Subsequently, various process enhancements
were made by many companies to reduce the cell
(b)
size and the standby current.
Figure 2-17. (a) SRAM cell size plotted against In 4 Mb and higher density SRAMs with
density [4] (source: various ISSC Pro- increasing cell density and reduced supply
ceedings, 1976-1990). (b) Evolution voltage to eliminate hot carrier degradation, it
of MOS SRAM technology. (From [I], becomes difficult to maintain low standby cur-
with permission of IEEE.) rent without degrading the noise immunity. A
30 Chap . 2 • Random Access Memory Technologies

stacked-CMOS SRAM cell with polysilicon layer is used for the gates of the access and dri-
thin-film transistor (TFf) load has been devel- ver NMOS transistors and for the Vss line, the
oped that leads not only to an increase of the second polysilicon layer for the gate of the TFf
cell static noise margin (SNM), but also to re- load, and the third polysilicon layer for the ac-
duction of the cell area [20]. In this cell config- tive layer of the TFf load and the Vee line. Fig-
uration, the off-current and on-current of the ure 2-18 shows the stacked-CMOS SRAM cell
TFf load are the important parameters to (a) schematic cross-section, (b) circuit diagram,
reduce standby current and increase noise im- and (c) layout [20].
munity, respectively. In this approach, an im- Hitachi has developed a 4 Mb CMOS
provement of the electrical characteristics of SRAM in 0.5 J.Lm process, four-level poly, two-
the TFf load has been achieved by using a spe- level metal, with a polysilicon PMOS load
cial solid phase growth (SPG) technique. The memory cell with an area of 17 J.Lm 2 [21]. This
fabrication of this cell is based on three-level had a standbycurrent of 0.2 J.LA at a supply volt-
polysilicon technology: the first polysilicon age of 3 V and address access time of 23 ns. The

-===.. .- ._--_._.__
' pO P-Well I
-r-t

_ _ _ _ _ _ _.._ N-Sub .
II
Unit Cell Length

Wd
(a)

BL Bi:
[::j [::j

01

Vee

BIT BIT

(b) (e)

Figure 2-18. A stacked -CMOS SRAM cell. (a) Schematic cross-

section. (b) Circuit diagram. (c) Layout. (From [20].
with permission of IEEE .)
Sec. 2.2 • Static Random Access Memories (SRAMs) 31

memory cell has excellent soft-error immunity ture drastically reduced the word-decoder area,
and low-voltage operating capability. Fast sense achieving a small chip area of 122 mrrr'.
amplifier circuits were used to reduce the access In 1990, Mitsubishi introduced a 4 Mb
time. A noise immune data-latch circuit was CMOS SRAM fabricated with 0.6 urn process
used to get a low active current of 5 rnA at an technology which utilized quadruple-polysili-
operating cycle of 1 us. A quadruple-array con (including polycide), double-metal, twin-
word-decoder architecture was employed in well CMOS technology [22]. Figure 2-19(a)
which the word decoders for four memory sub- shows a memory cell cross-section, as well as
arrays are laid out in one region. This architec- the process and device parameters. The memory

Processand DeviceParameters

TECHNOLOGY O.6JlmCMOS
N-SUB, TWIN-WELL
QUADRUPLE POLY-Si
DOUBLE METAL
DESIGN RULE O.6Jlm (minimum)
TRANSISTOR L = O.6J.1m (NMOS)
o.sum (PMOS)
Tox = 15nm
MEMORY CELL HIGHRESISTIVE LOAD
pwell R = 10TO

(a)

Z-ADDRESS I
•
BUFFER

PREDECOD~R l BLOCKSELECTOR
FIll IINF= (,An .

-- (lATE
onl lJMIJ JI-I-(

SENSE AMPLIFIER & WRITEDRIVER

CS,WE 1/0 x1/x4 V-ADDRESS

BUFFER BUFFER CONTROLLER BUFFER
&
t

(b)

Figure 2-19. A 4 Mb CMOS SRAM. (a) Memory cell cross-section, process and deviceparameters. (b) Block
diagram. (From [22], with permission of IEEE.)
32 Chap. 2 • Random Access Memory Technologies

cell size is 3.5 X 5.3 J.Lm 2• The first polysilicon 20(a) shows a memory cell layout, conventional
(polycide) is used for the gate electrode of the versus split word-line cell. Figure 2-20(b) shows
transistors. The second polysilicon layer, which a block diagram of the 16 Mb CMOS SRAM.
is used to form a "contact pad," is electrically NEC has developed a 3.3 V, 16 Mb
isolated from the first polycide and laid over it; CMOS SRAM with an access time of 12 ns and
this results in cell size compaction. The second typical standby current of 0.8 IJ.A by using a 0.4
polysilicon and the diffusion area are silicided urn quadruple-polysilicon, double-metal tech-
with a self-alignment technique to reduce the nology with thin-film transistor (TFf) load
sheet resistance. The third polysilicon is used memory cells [24]. The fast access time (12 ns)
for the interconnection and power supply line of was achieved through the various design opti-
the memory cell. The fourth polysilicon forms mization techniques, including:
the high resistive load of 10 TO to achieve a low
standby current. The bit lines are formed by the • An automated transistor size optimiza-
first metal with a barrier metal layer. This tion.
SRAM has a 20 ns access time at a supply volt- • Chip architectural optimization that
age of 3.3 V, achieved by a new word-decoding used center pads to shorten the bit and
scheme and high-speed sense amplifiers. It also data-bus delays. Also, the rotated mem-
has a fast address mode which is suitable for ory cell architecture halves the length of
cache memory applications. Figure 2-19(b) the global word lines. A hierarchical
shows a block diagram of the SRAM. data read-bus structure with a buffer be-
2.2.6.2 16-64 Mb SRAM Development. tween the subglobal and global read
For 16 Mb and higher density SRAMs, improve- buses helps reduce the data bus delays
ments in the MOSFET characteristics alone can- by 33%. To further reduce the read bus
not provide the high performance necessary for transmission delay, presetting the bus
advanced processing requirements. As the cell lines to the midlevel called read-bus mid-
size is reduced through scaling, it becomes more level preset scheme (RBMIPS) is used.
difficult to maintain stable operation at a low • This SRAM has three test modes: redun-
supply voltage of 3 V. Therefore, it is necessary dancy row test mode, redundancy column
to incorporate improved process and circuit tech- test mode, and 16 b parallel test mode.
niques and optimization of the chip architecture.
Currently, the 16 Mb SRAM is in development A single-bit-line cross-point cell activation
stages. In the ISSC Conferences during the last (SCPA) architecture has been developed by Mit-
few years, several advanced 16 Mb CMOS subishi to reduce the size of 16 Mb and higher
SRAM designs and architectural developments density SRAMs [25]. The supply voltage of this
have been presented. experimental device is 3 V. The column current
In 1992, Fujitsu presented development which constitutes a major portion of active cur-
plans on a 16 Mb CMOS SRAM, organized as rent in the SRAMs refers to the current flowing
4M words X 4 b [23]. Low power dissipation and from the bit line to the storage node of the mem-
access time of 15 ns are obtained by a reduced ory cell through the access transistor when the ac-
voltage amplitude data bus connected to a latched cess transistor is in the on-state. The conventional
cascaded sense amplifier and a current sense am- divided word-line (OWL) structure to reduce the
plifier. Double-gate pMOS thin-film-transistor column current requires a large number of block
(TFf) load-cell technology reduces the standby divisions, proportional to the memory density in
current. A "split word-line" memory cell layout 16 Mb SRAM chips, whereas the SCPA architec-
pattern, quintuple polysilicon layers, double ture realizes a smaller column current with a 10%
metal layers, and a 0.4 IJ.m photolithography re- smaller memory core versus the DWL structure.
sult in a 2.1 X 4.15 IJ.m 2 memory cell. This The experimental device with 2.2 X 3.9 IJ.m 2 cell
SRAM has a 16 b parallel test mode. Figure 2- was fabricated using a five-layer polysilicon, sin-
Sec. 2.2 • Static Random Access Memories (SRAMs) 33

(a) Conventional cell (b) Split word-line cell

D Active area • 1st polysilicon

(a)

_ I I I/O buffer CS buffer}l-{ Y addressJ

IX address ~ I CSA 1...--
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+
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~
Pre decoder Pre decoder Pre decoder Pre decoder
~ ~
; DLS LSA, WA ~ DLS, LSA, WA DLS, LSA, WA H' DLS, LSA, WA'-
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Upper 8

l~~ ~ g, ~ ~~.
!
data bus
g>1 \€
~ i~' /g. ~·I··· ~ J go •••••••••••. ~

~:.; 0,
Column decoder
~
Column decoder
(X) r 1Column decoder r ~
Column decoder
.~ Lower 8
data bus

~
DLS, LSA. WA ~~ DLS. LSA. WA DLS, LSA, WA ~ .. DLS. LSA. WA j

~ D .... ~ ~... ~~ " ~" ~~ " "" F-

~
; _ ····· ···..·..·..····•··..··..···..··..············..··1··..· .;
h
IX address r
I
eSA
IIObutter H r1 X addressl

(b)

Figure 2-20. A 16 Mb CMOS SRAM Fujitsu. (a) Memory cell layout. (b) Block diagram. (From [23], with per-
mission of IEEE.)

gle-aluminum, 0.4 J.Lm CMOS wafer process the SCPA architecture which has a dif-
technology. These are some of the major features ferent memory cell configuration.
of the SCPA architecture:
A 9 ns 16 Mb CMOS SRAM has been de-
• A new PMOS precharging boost circuit veloped by Sony Corporation using a 0.35 J.Lm
which is used to boost the word line and process with quadruple-polysilicon and double-
activated only during the write cycle. aluminum technology [26].This design utilizes a
• A modified data-sensing scheme utiliz- current-mode, fully nonequalized data path by
ing a dummy cell since the conventional using a stabilized feedback current sense ampli-
differential amplifier cannot be used in fier (SFCA)that provides a small input resistance
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 CHAPTER I
I was, am now, and shall have no end. I exercise dominion over
all creatures and over the affairs of all who are under the protection
of my image. I am ever present to help all who trust in me and call
upon me in time of need. There is no place in the universe that
knows not my presence. I participate in all the affairs which those
who are without call evil because their nature is not such as they
approve. Every age has its own manager, who directs affairs
according to my decrees. This office is changeable from generation
to generation, that the ruler of this world and his chiefs may
discharge the duties of their respective offices every one in his own
turn. I allow everyone to follow the dictates of his own nature, but
he that opposes me will regret it sorely. No god has a right to
interfere in my affairs, and I have made it an imperative rule that
everyone shall refrain from worshiping all gods. All the books of
those who are without are altered by them; and they have declined
from them, although they were written by the prophets and the
apostles. That there are interpolations is seen in the fact that each
sect endeavors to prove that the others are wrong and to destroy
their books. To me truth and falsehood are known. When temptation
comes, I give my covenant to him that trusts in me. Moreover, I give
counsel to the skilled directors, for I have appointed them for
periods that are known to me. I remember necessary affairs and
execute them in due time. I teach and guide those who follow my
instruction. If anyone obey me and conform to my commandments,
he shall have joy, delight, and goodness.
 CHAPTER II
I requite the descendants of Adam, and reward them with various
rewards that I alone know. Moreover, power and dominion over all
that is on earth, both that which is above and that which is beneath,
are in my hand. I do not allow friendly association with other people,
nor do I deprive them that are my own and that obey me of
anything that is good for them. I place my affairs in the hands of
those whom I have tried and who are in accord with my desires. I
appear in divers manners to those who are faithful and under my
command. I give and take away; I enrich and impoverish; I cause
both happiness and misery. I do all this in keeping with the
characteristics of each epoch. And none has a right to interfere with
my management of affairs. Those who oppose me I afflict with
disease; but my own shall not die like the sons of Adam that are
without. None shall live in this world longer than the time set by me;
and if I so desire, I send a person a second or a third time into this
world or into some other by the transmigration of souls.
 CHAPTER III
I lead to the straight path without a revealed book; I direct aright
my beloved and my chosen ones by unseen means. All my teachings
are easily applicable to all times and all conditions. I punish in
another world all who do contrary to my will. Now the sons of Adam
do not know the state of things that is to come. For this reason they
fall into many errors. The beasts of the earth, the birds of heaven,
and the fish of the sea are all under the control of my hands. All
treasures and hidden things are known to me; and as I desire, I take
them from one and bestow them upon another. I reveal my wonders
to those who seek them, and in due time my miracles to those who
receive them from me. But those who are without are my
adversaries, hence they oppose me. Nor do they know that such a
course is against their own interests, for might, wealth, and riches
are in my hand, and I bestow them upon every worthy descendant
of Adam. Thus the government of the worlds, the transition of
generations, and the changes of their directors are determined by
me from the beginning.
 CHAPTER IV
I will not give my rights to other gods. I have allowed the creation
of four substances, four times, and four corners; because they are
necessary things for creatures. The books of Jews, Christians, and
Moslems, as of those who are without, accept in a sense, i. e., so far
as they agree with, and conform to, my statutes. Whatsoever is
contrary to these they have altered; do not accept it. Three things
are against me, and I hate three things. But those who keep my
secrets shall receive the fulfilment of my promises. Those who suffer
for my sake I will surely reward in one of the worlds. It is my desire
that all my followers shall unite in a bond of unity, lest those who are
without prevail against them. Now, then, all ye who have followed
my commandments and my teachings, reject all the teachings and
sayings of such as are without. I have not taught these teachings,
nor do they proceed from me. Do not mention my name nor my
attributes, lest ye regret it; for ye do not know what those who are
without may do.
 CHAPTER V
O ye that have believed in me, honor my symbol and my image,
for they remind you of me. Observe my laws and statutes. Obey my
servants and listen to whatever they may dictate to you of the
hidden things. Receive that that is dictated, and do not carry it
before those who are without, Jews, Christians, Moslems, and
others; for they know not the nature of my teaching. Do not give
them your books, lest they alter them without your knowledge.
Learn by heart the greater part of them, lest they be altered.
Thus endeth the book of Al-Jilwah, which is followed by the book
of Maṣḥaf Reš, i. e., the Black Book.

Mashaf Reš (The Black Book)

In the beginning God created the White Pearl out of his most
precious essence. He also created a bird named Angar. He placed
the White Pearl on the back of the bird, and dwelt on it for forty
thousand years. On the first day, Sunday, God created Melek Anzazîl,
and he is Ṭâ´ûs-Melek, the chief of all. On Monday he created Melek
Dardâel, and he is Šeiḫ Ḥasan. Tuesday he created Melek Israfel,
and he is Šeiḫ Šams (ad-Dîn). Wednesday he created Melek Miḫâel,
and he is Šeiḫ Abû Bakr. Thursday he created Melek Azrâel, and he
is Sajad-ad-Dîn. Friday he created Melek Šemnâel, and he is Naṣir-
ad-Dîn. Saturday he created Melek Nurâel, and he is Yadin (Faḫr-ad-
Dîn). And he made Melek Ṭâ´ûs ruler over all.38
After this God made the form of the seven heavens, the earth, the
sun, and the moon. But Faḫr-ad-Dîn created man and the animals,
and birds and beasts. He put them all in pockets of cloth, and came
out of the Pearl accompanied by the Angels. Then he shouted at the
Pearl with a loud voice. Thereupon the White Pearl broke up into
four pieces, and from its midst came out the water which became an
ocean. The world was round, and was not divided. Then he created
Gabriel and the image of the bird. He sent Gabriel to set the four
corners. He also made a vessel and descended in it for thirty
thousand years. After this he came and dwelt in Mount Lališ. Then
he cried out at the world, and the sea became solidified and the land
appeared, but it began to shake. At this time he commanded Gabriel
to bring two pieces of the White Pearl; one he placed beneath the
earth, the other stayed at the gate of heaven. He then placed in
them the sun and the moon; and from the scattered pieces of the
White Pearl he created the stars which he hung in heaven as
ornaments. He also created fruit-bearing trees and plants and
mountains for ornaments to the earth. He created the throne over
the carpet.39 Then the Great God said: “O Angels, I will create Adam
and Eve; and from the essence of Adam shall proceed Šehar bn Jebr,
and of him a separate community shall appear upon the earth, that
of Azazîl, i. e., that of Melek Ṭâ´ûs, which is the sect of the Yezidis.
Then he sent Šeiḫ ‘Adî bn Musâfir from the land of Syria, and he
came (and dwelt in Mount) Lališ. Then the Lord came down to the
Black Mountain. Shouting, he created thirty thousand Meleks, and
divided them into three divisions. They worshiped him for forty
thousand years, when he delivered them to Melek Ṭâ´ûs who went
up with them to heaven. At this time the Lord came down to the
Holy Land (al-ḳuds), and commanded Gabriel to bring earth from the
four corners of the world, earth, air, fire, and water. He created it
and put in it the spirit of his own power, and called it Adam.
Then he commanded Gabriel to escort Adam into Paradise, and to
tell him that he could eat from all the trees but not of wheat.40 Here
Adam remained for a hundred years. Thereupon, Melek Ṭâ´ûs asked
God how Adam could multiply and have descendants if he were
forbidden to eat of the grain. God answered, “I have put the whole
matter into thy hands.” Thereupon Melek Ṭâ´ûs visited Adam and
said “Have you eaten of the grain?” He answered, “No, God forbade
me.” Melek Ṭâ´ûs replied and said, “Eat of the grain and all shall go
better with thee.” Then Adam ate of the grain and immediately his
belly was inflated. But Melek Ṭâ´ûs drove him out of the garden,
and leaving him, ascended into heaven. Now Adam was troubled
because his belly was inflated, for he had no outlet. God therefore
sent a bird to him which pecked at his anus and made an outlet, and
Adam was relieved.
Now Gabriel was away from Adam for a hundred years. And Adam
was sad and weeping. Then God commanded Gabriel to create Eve
from under the left shoulder of Adam. Now it came to pass, after the
creation of Eve and of all the animals, that Adam and Eve quarreled
over the question whether the human race should be descended
from him or her, for each wished to be the sole begetter of the race.
This quarrel originated in their observation of the fact that among
animals both the male and the female were factors in the production
of their respective species. After a long discussion Adam and Eve
agreed on this: each should cast his seed into a jar, close it, and seal
it with his own seal, and wait for nine months. When they opened
the jars at the completion of this period, they found in Adam’s jar
two children, male and female. Now from these two our sect, the
Yezidis, are descended. In Eve’s jar they found naught but rotten
worms emitting a foul odor. And God caused nipples to grow for
Adam that he might suckle the children that proceeded from his jar.
This is the reason why man has nipples.
After this Adam knew Eve, and she bore two children, male and
female; and from these the Jews, the Christians, the Moslems, and
other nations and sects are descended. But our first fathers are
Šeth, Noah, and Enosh, the righteous ones, who were descended
from Adam only.
It came to pass that trouble arose between a man and his wife,
resulting from the denial on the part of the woman that the man was
her husband. The man persisted in his claim that she was his wife.
The trouble between the two was settled, however, through one of
the righteous men of our sect, who decreed that at every wedding a
drum and a pipe should be played as a testimony to the fact that
such a man and such a woman were married legally.
 Then Melek Ṭâ´ûs came down to earth for our sect (i. e., the
Yezidis), the created ones, and appointed kings for us, besides the
kings of ancient Assyria, Nisroch, who is Našir-ad-Dîn; Kamush, who
is Melek Faḫr-ad-Dîn, and Artâmîs, who is Melek Šams-(ad-)Dîn.
After this we had two kings, Šabur (Sapor) First (224-272 a. d.) and
Second (309-379), who reigned one hundred and fifty years; and
our amirs down to the present day have been descended from their
seed. But we hated four kings.
Before Christ came into this world our religion was paganism. King
Ahab was from among us. And the god of Ahab was called
Beelzebub. Nowadays we call him Pir Bub. We had a king in Babylon,
whose name was Baḫtnaṣar; another in Persia, whose name was
Aḥšuraš; and still another in Constantinople, whose name was
Agriḳâlus. The Jews, the Christians, the Moslems, and even the
Persians, fought us; but they failed to subdue us, for in the strength
of the Lord we prevailed against them. He teaches us the first and
last science. And one of his teachings is:
Before heaven and earth existed, God was on the sea, as we
formerly wrote you. He made himself a vessel and traveled in it in
kunsiniyat41 of the seas, thus enjoying himself in himself. He then
created the White Pearl and ruled over it for forty years. Afterward,
growing angry at the Pearl, he kicked it; and it was a great surprise
to see the mountains formed out of its cry; the hills out of its
wonders; the heavens out of its smoke. Then God ascended to
heaven, solidified it, established it without pillars. He then spat upon
the ground, and taking a pen in hand, began to write a narrative of
all the creation.
In the beginning he created six gods from himself and from his
light, and their creation was as one lights a light from another light.
And God said, “Now I have created the heavens; let some one of
you go up and create something therein.” Thereupon the second god
ascended and created the sun; the third, the moon; the fourth, the
vault of heaven; the fifth, the farḡ (i. e., the morning star); the sixth,
paradise; the seventh, hell. We have already told you that after this
they created Adam and Eve.
And know that besides the flood of Noah, there was another flood
in this world. Now our sect, the Yezidis, are descended from Na‘umi,
an honored person, king of peace. We call him Melek Miran. The
other sects are descended from Ham, who despised his father. The
ship rested at a village called ‘Ain Sifni,42 distant from Mosul about
five parasangs. The cause of the first flood was the mockery of
those who were without, Jews, Christians, Moslems, and others
descended from Adam and Eve. We, on the other hand, are
descended from Adam only, as already indicated. This second flood
came upon our sect, the Yezidis. As the water rose and the ship
floated, it came above Mount Sinjar,43 where it ran aground and was
pierced by a rock. The serpent twisted itself like a cake and stopped
the hole. Then the ship moved on and rested on Mount Judie.
Now the species of the serpent increased, and began to bite man
and animal. It was finally caught and burned, and from its ashes
fleas were created. From the time of the flood until now are seven
thousand years. In every thousand years one of the seven gods
descends to establish rules, statutes, and laws, after which he
returns to his abode. While below, he sojourns with us, for we have
every kind of holy places. This last time the god dwelt among us
longer than any of the other gods who came before him. He
confirmed the saints. He spoke in the Kurdish language. He also
illuminated Mohammed, the prophet of the Ishmaelites, who had a
servant named Mu‘âwiya. When God saw that Mohammed was not
upright before him, he afflicted him with a headache. The prophet
then asked his servant to shave his head, for Mu‘âwiya knew how to
shave. He shaved his master in haste, and with some difficulty. As a
result, he cut his head and made it bleed. Fearing that the blood
might drop to the ground, Mu‘âwiya licked it with his tongue.
Whereupon Mohammed asked, “What are you doing, Mu‘âwiya?” He
replied, “I licked thy blood with my tongue, for I feared that it might
drop to the ground.” Then Mohammed said to him, “You have
sinned, O Mu‘âwiya, you shall draw a nation after you. You shall
oppose my sect.” Mu‘âwiya answered and said, “Then I will not enter
the world; I will not marry.”
It came to pass that after some time God sent scorpions upon
Mu‘âwiya, which bit him, causing his face to break out with poison.
Physicians urged him to marry lest he die. Hearing this, he
consented. They brought him an old woman, eighty years of age, in
order that no child might be born. Mu‘âwiya knew his wife, and in
the morning she appeared a woman of twenty-five, by the power of
the great God. And she conceived and bore our god Yezid. But the
foreign sects, ignorant of this fact, say that our god came from
heaven, dispised and driven out by the great God. For this reason
they blaspheme him. In this they have erred. But we, the Yezidi sect,
believe this not, for we know that he is one of the above-mentioned
seven gods. We know the form of his person and his image. It is the
form of a cock which we possess. None of us is allowed to utter his
name, nor anything that resembles it, such as šeitân (Satan), ḳaitân
(cord), šar (evil), šat (river), and the like. Nor do we pronounce
mal‘ûn (accursed), or la‘anat (curse), or na‘al44 (horseshoe), or any
word that has a similar sound. All these are forbidden us out of
respect for him. So ḫass (lettuce) is debarred. We do not eat it, for it
sounds like the name of our prophetess Ḫassiah. Fish is prohibited,
in honor of Jonah the prophet. Likewise deer, for deer are the sheep
of one of our prophets. The peacock is forbidden to our Šeiḫ and his
disciples, for the sake of our Ṭâ´ûs. Squash also is debarred. It is
forbidden to pass water while standing, or to dress up while sitting
down, or to go to the toilet room, or to take a bath according to the
custom of the people.45 Whosoever does contrary to this is an
infidel. Now the other sects, Jews, Christians, Moslems, and others,
know not these things, because they dislike Melek Ṭâ´ûs. He,
therefore, does not teach them, nor does he visit them. But he dwelt
among us; he delivered to us the doctrines, the rules, and the
traditions, all of which have become an inheritance, handed down
from father to son. After this, Melek Ṭâ´ûs returned to heaven.
 One of the seven gods made the sanjaḳs46 (standards) and gave
them to Solomon the wise. After his death our kings received them.
And when our god, the barbarian Yezîd, was born, he received these
sanjaḳs with great reverence, and bestowed them upon our sect.
Moreover, he composed two songs in the Kurdish language to be
sung before the sanjaḳas in this language, which is the most ancient
and acceptable one. The meaning of the song is this:
Hallelujah to the jealous God.
As they sing it, they march before the sanjaḳs with timbrels and
pipes. These sanjaḳs remain with our emir, who sits on the throne of
Yezîd. When these are sent away, the ḳawwâls assemble with the
emir, and the great general, the šeiḫ, who is the representative of
Šeiḫ Nasir-ad-Dîn, i. e., Nisroch, god of the ancient Assyrians.47 They
visit the sanjaḳs. Then they send each sanjaḳ in care of a ḳawwâl to
its own place; one to Ḫalataneye, one to Aleppo, one to Russia, and
one to Sinjar. These sanjaḳs are given to four ḳawwâls by contract.
Before they are sent, they are brought to Šeiḫ ‘Adî’s tomb, where
they are baptized amid great singing and dancing. After this each of
the contractors takes a load of dust from Šeiḫ ‘Adî’s tomb. He
fashions it into small balls, each about the size of a gall nut, and
carries them along with the sanjaḳs to give them away as blessings.
When he approaches a town, he sends a crier before him to prepare
the people to accept the ḳawwâl and his sanjaḳ with respect and
honor. All turn out in fine clothes, carrying incense. The women
shout, and all together sing joyful songs. The ḳawwâl is entertained
by the people with whom he stops. The rest give him silver presents,
everyone according to his means.
Besides these four sanjaḳs, there are three others, seven in all.
These three are kept in a sacred place for purposes of healing. Two
of them, however, remain with Šeiḫ ‘Adî, and the third remains in the
village of Baḥazanie, which is distant from Mosul about four hours.
Every four months these ḳawwâls travel about. One of them must
travel in the province of the emir. They travel in a fixed order,
differing each year. Every time he goes out, the traveler must
cleanse himself with water made sour with summaḳ (sumac) and
anoint himself with an oil. He must also light a lamp at each idol that
has a chamber. This is the law that pertains to the sanjaḳs.
The first day of our new year is called the Serṣâlie, i. e., the
beginning of a year. It falls on the Wednesday of the first week in
April.48 On that day there must be meat in every family. The wealthy
must slaughter a lamb or an ox; the poor must kill a chicken or
something else. These should be cooked on the night, the morning
of which is Wednesday, New Year’s day. With the break of day the
food should be blessed. On the first day of the year alms should be
given at tombs where the souls of the dead lie.
Now the girls, large and small, are to gather from the fields
flowers of every kind that have a reddish color. They are to make
them into bundles, and, after keeping them three days, they are to
hang them on the doors49 as a sign of the baptism of the people
living in the houses. In the morning all doors will be seen well
decorated with red lilies. But women are to feed the poor and needy
who pass by and have no food; this is to be done at the graves. But
as to the ḳawwâls, they are to go around the tombs with timbrels,
singing in the Kurdish language. For so doing they are entitled to
money. On the above-mentioned day of Serṣâlie no instruments of
joy are to be played, because God is sitting on the throne (arranging
decrees for the year),50 and commanding all the wise and the
neighbors to come to him. And when he tells them that he will come
down to earth with song and praise, all arise and rejoice before him
and throw upon each the squash of the feast. Then God seals them
with his own seal. And the great God gives a sealed decision to the
god who is to come down. He, moreover, grants him power to do all
things according to his own will. God prefers doing good and charity
to fasting and praying. The worship of any idol, such as Seyed-ad-
Dîn or Šeiḫ Šams is better than fasting. Some layman is to give a
banquet to a kôchak after the fasting of the latter forty days,
whether it be in summer or in winter. If he (the kôchak) says this
entertainment is an alms given to the sanjaḳ, then he is not released
from his fasting. When it comes to pass that the yearly tithe-
gatherer finds that the people have not fully paid their tithes, he
whips them till they become sick, and some even die. The people
are to give the kôchaks money to fight the Roman army, and thus
save the sect (Yezidis) from the wrath of the man of the year.
Every Friday a load of gifts is to be brought as an offering to an
idol. At that time, a servant is to call the people aloud from the roof
of a kôchak’s house, saying, it is the call of the prophet to a feast. All
are to listen reverently and respectfully; and, on hearing it, every
one is to kiss the ground and the stone on which he happens to
lean.
It is our law that no ḳawwâl shall pass a razor over his face. Our
law regarding marriage is that at the time of the wedding a loaf of
bread shall be taken from the house of a kôchak and be divided
between the bride and the bridegroom, each to eat one-half. They
may, however, eat some dust from Šeiḫ ‘Adî’s tomb instead of the
bread for a blessing. Marriage in the month of April is forbidden, for
it is the first month of the year. This rule, however, does not apply to
ḳawwâls; they may marry during this month. No layman is allowed
to marry a kôchak’s daughter. Everyone is to take a wife from his
own class. But our emir may have for a wife any one whom he
pleases to love. A layman may marry between the ages of ten and
eighty; he may take for a wife one woman after another for a period
of one year. On her way to the house of the bridegroom, a bride
must visit the shrine of every idol she may happen to pass; even if
she pass a Christian church, she must do the same. On her arrival at
the bridegroom’s house, he must hit her with a small stone in token
of the fact that she must be under his authority. Moreover, a loaf of
bread must be broken over her head as a sign to her that she must
love the poor and needy. No Yezidi may sleep with his wife on the
night the morning of which is Wednesday, and the night the morning
of which is Friday. Whosoever does contrary to this commandment is
an infidel. If a man steal the wife of his neighbor, or his own former
wife, or her sister or mother, he is not obliged to give her dowry, for
she is the booty of his hand. Daughters may not inherit their father’s
wealth. A young lady may be sold as an acre of land is sold. If she
refuses to be married, then she must redeem herself by paying her
father a sum of money earned by her service and the labor of her
hand.
Here ends Kitâb Reš, which is followed by several stories, some of
which are told secretly, some openly.
APPENDIX TO PART I
 APPENDIX TO PART I
They say our hearts are our books, and our šeiḫs tell us
everything from the second Adam until now and the future. When
they notice the sun rise, they kiss the place where the rays first fall;
they do the same at sunset, where its rays last fall. Likewise they
kiss the spot where the moon first casts its rays and where it last
casts them. They think, moreover, that by the multiplication of
presents to šeiḫs and idols they keep troubles and afflictions away.
There is a great difference among the ḳôchaks, they contradict
one another. Some say, “Melek Ṭâ´ûs appears to me and reveals to
me many revelations.” Others say, “We appear to people in many
different ways.” Some believe that Christ is Šeiḫ Šams himself. They
say that they have had prophets in all times; the ḳôchaks are the
prophets. One of the ḳôchaks says in one of his prophecies: “I was
in Jonah’s ship, where a lot was cast in my presence. It fell on
Jonah; and he was thrown into the sea, where he remained forty
days and nights.” Another said: “I was sitting with the great God,
who said, ‘I hope the time will come when I shall send Christ to the
world.’ I said to him, ‘Yes.’ Then he sent him. After making a sign in
the sun, Christ came down to the earth.” He appeared to our sect
only, and made for us seven circles, which are at Šeiḫ ‘Adî. Now he
appeared to us because we observe the necessary order, which the
other sects do not observe. Their origin and race are unknown; ours
are known. We are emirs and sons of emirs; we are šeiḫs and sons
of šeiḫs; we are ḳôchaks and sons of ḳôchaks, etc. But Christians
and Moslems make priests and mullas for themselves out of those
who had none of their kindred in those offices before, and never will
have afterward. We are better than they. We are allowed to drink
wine; our young men also may desire it when they, in company with
women, engage in religious dancing and playing. Some of the
ḳôchaks and šeiḫs, however, are not allowed to drink it. When one is
about to die, he is visited by a ḳôchak, who places a bit of Šeiḫ ‘Adî’s
dust in his mouth. Before he is buried his face is anointed with it.
Moreover, the dung of sheep is placed on his tomb. Finally, food is
offered on behalf of the dead. The ḳôchaks pray for the dead at the
graves, for which service they are paid. They tell the relatives of the
dead what they see in dreams and visions, and the condition of their
dead, whether they have been translated to the human or to the
animal race. Some people hide silver or gold coins that they plan to
take out in case they are born the second time in this world. Some
believe that the spirits of many righteous persons travel in the air.
Those spirits make revelations to the ḳôchaks, who are acquainted
with the world of mysteries and secrets. Life and death are in their
hands. Hence the fate of the people depends on the gratitude and
honor which they show the ḳôchaks. According to Yezidis, hell has
no existence. It was created in the time of the first Adam, they say,
when our father, Ibrîḳ al-Aṣfar, was born.51 By reason of his
generosity and noble deeds, Ibrîḳ had many friends. Now, when he
viewed hell he became very sad. He had a small baḳbûḳ aṣfar,52 into
which, as he kept weeping his tears fell. In seven years it was filled.
He then cast it into hell, and all its fires were put out that mankind
might not be tortured. This incident relates to one of the noble
deeds of our first father, Ibrîḳ al-Aṣfar. They have many more such
upright men of noble deeds. Such an one is Mohammed Rašân,
whose resting place is behind the mount of Šeiḫ Mattie.53 He
(Rašân) is exceedingly strong, so that the most sacred oaths are
sworn by him. If any one becomes sick, he takes refuge in making
vows to ḫasin, i. e., pillars of idols. Now there is a place of religious
pilgrimage which is called Sitt Nafîsah. This place is a mulberry tree
in the village of Ba‘ašîḳa. Another such place is called ‘Abdi Rašân,
and is in the village of ḳarabek. A third place of pilgrimage is in the
village Baḥzanie, which is called Šeiḫ Bakû. Nearby is a spring, and
beside this is a mulberry tree. Whoever is afflicted with fever, goes
to that tree, hangs on its branches a piece of cloth from his clothes,
and casts bread in the spring for the fish. All this he does that he
may be cured. They entertain the belief that whoever unties or
shakes off one of the shreds of cloth will catch the disease with
which the man was afflicted when he hung it up. There are many
such trees in the village of Ba‘ašîḳa, and in some other places. There
is also a spring of water, called in the common language ‘Ain aṣ-
Ṣafra (Yellow Spring). The Yezidis call it Kanî-Zarr.54 In this swim
those who are afflicted with the disease of abû-ṣafar (jaundice). But
those who are troubled with dropsy go for cure to the house of the
Pir that lives in the village of Man Reš.
When they assemble at Šeiḫ ‘Adî’s, no one is allowed to cook
anything. Everyone is to eat from Šeiḫ ‘Adî’s table. As to the
ḳôchaks, every one of them sits on a stone, as one sits in prayer. To
them the laity go, seeking succor. They give them money while
making their petition, and vow to the stone on which the ḳôchak
sits, sheep and oxen, everyone according to his means. Now, at the
New Year the places are given in contract. When they assemble at
the New Year, they dance and play with instruments of joy. Before
eating the kabdûš, i. e., the vowed ox, they swim in the water of
Zamzam, a spring coming from beneath the temple of Šeiḫ ‘Adî.
Then they eat in haste, snatching meat from the pot like fanatics, so
that their hands are frequently burned. This practice is in accordance
with their rules. After eating, they go up the mountain, shooting with
their guns, and then return to Šeiḫ ‘Adî. Everyone of them takes a
little dust and preserves it for the times of wedding and death. They
wear entwined girdles which they call the ties of the back (belt).
They baptize these and the sanjaḳs with the water of Zamzam. He
who is called Jawiš55 wears a stole which is woven from the hair of a
goat. It is nine spans in length and around it are sansûls (tinsels).
When the gathering comes to an end, they collect the money from
the ḳôchaks and the contractors, and bring it to the emir. After
everyone has taken according to his rank, the remainder goes to the
emir.
They have another gathering which takes place at the feast of Al-
Hijâjj. At this pilgrimage they go up to the mountain which is called
Jabal al-‘Arafât.56 After remaining there an hour, they hasten toward
Š
Šeiḫ ‘Adî. He who arrives there before his companions is praised
much. Hence everyone tries to excel. The one who succeeds
receives abundant blessings.
They still have another assembly. This is called “the road of the
ḳôchaks,” when each, putting a rope around his neck, goes up the
mountain. After collecting wood they bring it to Šeiḫ ‘Adî, carrying it
on their backs. The wood is used for heating purposes and for the
emir’s cooking.
During these assemblies the sanjaḳs are passed around. In the
first place they are washed with water made sour with sumac in
order to be cleansed from their rust. The water is given away in
drinks for purposes of blessing. In return money is taken. In the
second place, the ḳôchaks go around with the sanjaḳs to collect
money.
In their preaching, the šeiḫs tell the people that all kings have
come from their descent, such as Nisroch,57 who is Nasr-ad-Dîn, and
Kamuš who is Faḫr-ad-Dîn, and Artâmîs, who is Šams-ad-Dîn, and
many others, as Shabur and Yoram; and many royal names of the
ancient kings, together with their own (Yezidi) kings, are from their
seed. The sign of the Yezidi is that he wears a shirt with a round
bosom. It differs from that of the other people, the bosom of whose
shirts are open all the way down.
There is one occasion when no Yezidi will swear falsely, viz., when
one draws a circle on the ground, and tells him that this circle
belongs to Ṭâ´ûs-Melek, Šeiḫ ‘Adî, and Yezîd, and baryshabaḳei. He
places him in the middle of the circle, and then tells him that Melek
Ṭâ´ûs and all those who were mentioned above will not intercede
for him after his death, and that the shirt of the Jewish Nasim58 be
on his neck, and that the hand of Nasim be on his neck and eye, and
that Nasim be his brother for the next world, and let him be to him
for a šeiḫ and a pir if he does not tell the truth. Then if he swears to
tell the truth, he cannot conceal anything. For an oath made under
such conditions is considered greater than that made in the name of
God, and even than that made in the name of one of their prophets.
They fast three days in a year from morning till evening. The fast
falls in December, according to the oriental calendar. They have no
prayer59 except what is mentioned above, such as that referring to
the sun and the moon, and asking help from šeiḫs and holy places
when they say, “O Šeiḫ ‘Adî, O Šeiḫ Sams,” and the like. They are all
forbidden to teach their children anything, with the exception of two
stanzas which they teach their children out of necessity and because
it is traditional.
A story is told about them by reliable people. Once when Šeiḫ
Naṣir was preaching in a village at Mount Sinjar, there was a
Christian mason in the audience who, seeing the house filled with
people, thought they were going to pray. He then pretended to take
a nap, that he might amuse himself with what he should hear. He
knew the Kurdish language. When the Christian seemed to be
asleep, but was really awake and listening, Šeiḫ Naṣir began to
preach saying: “Once the great God appeared to me in vision. He
was angry at Jesus because of a dispute with him. He therefore
caught him and imprisoned him in a den which had no water. Before
the mouth of the den he placed a great stone. Jesus remained in the
den a long time, calling upon the prophets and the saints for help
and asking their aid. Every one whose succor Jesus asked went to
beg the great God to release him. But God did not grant their
requests. Jesus therefore remained in a sorrowful state, knowing not
what to do.” After this the preacher remained silent for a quarter of
an hour, and thus a great silence prevailed in the house. Then he
went on to say: “O poor Jesus, why are you so forgotten, so
neglected? Do you not know that all the prophets and all the saints
have no favor with the great God unto Melek Ṭâ´ûs? Why have you
forgotten him and have not called upon him?” Saying this, the
preacher again remained silent as before. Afterward he again
continued: “Jesus remained in the den till one day when he
happened to remember Melek Ṭâ´ûs. He then sought his aid,
praying, ‘O Melek Ṭâ´ûs, I have been in this den for some time. I am
imprisoned; I have sought the help of all the saints, and none of
them could deliver me. Now, save me from this den.’ When Melek Ṭâ
´ûs heard this, he descended from heaven to earth quicker than the
twinkling of an eye, removed the stone from the top of the den, and
said to Jesus, ‘Come up, behold I have brought thee out.’ Then both
went up to heaven. When the great God saw Jesus, he said to him,
‘O Jesus, who brought thee out of the den? Who brought thee here
without my permission?’ Jesus answered and said, ‘Melek Ṭâ´ûs
brought me out of the den and up here.’ Then God said, ‘Had it been
another, I would have punished him, but Melek Ṭâ´ûs is much
beloved by me; remain here for the sake of my honor.’ So Jesus
remained in heaven.” The preacher added, “Notice that those who
are without do not like Melek Ṭâ´ûs. Know ye that in the
resurrection he will not like them either, and he will not intercede for
them. But, as for us, he will put us all in a tray, carry us upon his
head, and take us into heaven, while we are in the tray on his head.”
When the congregation heard this, they rose up, kissed his clothes
and feet, and received his blessing.
Now the views of the Yezidis regarding the birth of Christ and the
explanation of the name of the Apostle Peter, are found in one of
their stories, which runs thus: “Verily Mary the Virgin mother of
Jesus, begat Jesus in a manner unlike the rest of women. She begat
him from her right side,60 between her clothes and her body. At that
time the Jews had a custom that, if a woman gave birth, all her
relatives and neighbors would bring her presents. The women would
call, carrying in their right hand a plate of fruits which were to be
found in that season, and in the left hand they would carry a stone.
This custom was a very ancient one. Therefore when Mary the Virgin
gave birth to Jesus, the wife of Jonah, who is the mother of Peter,
came to her; and, according to the custom, carried a plate of fruit in
her right hand and a stone in her left. As she entered and gave Mary
the plate, behold, the stone which was in her left hand begat a
male. She called his name Simon Cifa, that is, son of the stone.
Christians do not know these things as we do.”
 They have a story explaining the word heretic. It is this: When the
great God created the heavens, he put all the keys of the treasuries
and the mansions there in the hands of Melek Ṭâ´ûs, and
commanded him not to open a certain mansion. But he, without the
knowledge of God, opened the house and found a piece of paper on
which was written, “Thou shalt worship thy God alone, and him
alone shalt thou serve.” He kept the paper with him and allowed no
one else to know about it. Then God created an iron ring and hung it
in the air between the heaven and the earth. Afterward he created
Adam the first. Melek Ṭâ´ûs refused to worship Adam when God
commanded him to do so. He showed the written paper which he
took from the mansion and said, “See what is written here.” Then
the great God said, “It may be that you have opened the mansion
which I forbade you to open.” He answered, “Yes.” Then God said to
him, “You are a heretic, because you have disobeyed me and
transgressed my commandment.”
From this we know that God speaks in the Kurdish language, that
is from the meaning of this saying, “Go into the iron ring which I, thy
God, have made for whosoever does contrary to my commandment
and disobeys me.”
When one criticizes such a story as this by saying that God drove
Melek Ṭâ´ûs from heaven and sent him to hell because of his pride
before God the most high, they do not admit that such is the case.
They answer: “Is it possible that one of us in his anger should drive
out his child from his house and let him wait until the next day
before bringing him back? Of course not. Similar is the relation of
the great God to Melek Ṭâ´ûs. Verily he loves him exceedingly. You
do not understand the books which you read. The Gospel says, ‘No
one ascended up to heaven but he who came down from heaven.’
No one came down from heaven but Melek Ṭâ´ûs and Christ. From
this we know that the great God has been reconciled to Melek Ṭâ
´ûs, who went up to heaven, just as God came down from heaven
and went up again.”
 The following is a story told of a kôchak: It is related that at one
time there was no rain in the village of Ba‘ašîḳa. In this village there
was a Yezidi whose name was Kôchak Berû. There were also some
saints and men of vision dwelling there. They (people) gathered to
ask Berû to see about the rain. He told them, “Wait till tomorrow
that I may see about it.” They came to him on the next day and
said, “What have you done concerning the question of rain? We are
exceedingly alarmed by reason of its being withheld.” He answered:
“I went up to heaven last night and entered into the divan where the
great God, Šeiḫ ‘Adî, and some other šeiḫs and righteous men were
sitting. The priest Isaac was sitting beside God. The great God said
to me, ‘What do you want, O Kôchak Berû; why have you come
here?’ I said to him, ‘My lord, this year the rain has been withheld
from us till now, and all thy servants are poor and needy. We
beseech thee to send us rain as thy wont.’ He remained silent and
answered me not. I repeated the speech twice and thrice,
beseeching him. Then I turned to the šeiḫs who sat there, asking
their help and intercession. The great God answered me, ‘Go away
until we think it over.’ I came down and do not know what took place
after I descended from heaven. You may go to the priest Isaac and
ask him what was said after I came down.” They went to the priest
and told him the story, and asked him what was said after Kôchak
Berû came down. This priest Isaac was a great joker. He answered
them, “After the kôchak came down, I begged God for rain on your
behalf. It was agreed that after six or seven days he would send it.”
They waited accordingly, and by a strange coincidence, at the end of
the period it rained like a flood for some time. Seeing this, the
people believed in what they were told, and honored the priest
Isaac, looking upon him as one of the saints, and thinking that he
must have Yezidi blood in him. For more than twenty years this story
has been told as one of the tales of their saints.
Once Šeiḫ ‘Adî bn Musâfir and his murids were entertained by God
in heaven. When they arrived, they did not find straw for their
animals. Therefore Šeiḫ ‘Adî ordered his murids to carry straw from
his threshing floor on the earth. As it was being transported, some
fell on the way, and has remained as a sign in heaven unto our day.
It is known as the road of the straw man.
They think that prayer is in the heart; therefore they do not teach
their children about it. And in their book neither is there any rule
regarding prayer, nor is prayer considered a religious obligation.
Some assert that at one time Šeiḫ ‘Adî, in company with Šeiḫ ‘Abd-
al-ḳâdir, made a pilgrimage to Mecca, where he remained four years.
After his absence Melek Ṭâ´ûs appeared to them (the two šeiḫs) in
his symbol. He dictated some rules to them and taught them many
things. Then he was hidden from them. Four years later Šeiḫ ‘Adî
returned from Mecca; but they refused him and would not accept
him. They asserted that he had died or ascended to heaven. He
remained with them, but was without his former respect. When the
time of his death came, Melek Ṭâ´ûs appeared to them and
declared, “This is Šeiḫ ‘Adî himself, honor him.” Then they honored
him and buried him with due veneration, and made his tomb a place
of pilgrimage. In their estimation it is a more excellent spot than
Mecca. Everyone is under obligation to visit it once a year at least;
and, in addition to this, they give a sum of money through the šeiḫs
to obtain satisfaction (that Šeiḫ ‘Adî may be pleased with them).
Whoever does this not is disobedient.
Moreover, it is said that the reason why the pilgrimage to his tomb
is regarded as excellent by us and by God is that in the resurrection
Šeiḫ ‘Adî will carry in a tray all the Yezidis upon his head and take
them into paradise, without requiring them to give account or
answer. Therefore they regard the pilgrimage to his tomb as a
religious duty greater than the pilgrimage to Mecca.
There are some domes, huts, around the tomb of Šeiḫ ‘Adî. They
are there for the purpose of receiving blessings from the tomb. And
they are all attributed to the great Šeiḫs, as the hut of ‘Abd-al-ḳâdir-
al-Jîlânî;61 the hut of Šeiḫ ḳadîb-al-Bân; the hut of Šeiḫ Šams-ad-
Dîn; the hut of Šeiḫ Manṣûr-al-Ḥallâj, and the hut of Šeiḫ Ḫasan-al-
Baṣrî. There are also some other huts. Each hut has a banner made
of calico. It is a sign of conquest and victory.
Eating of deer’s meat is forbidden them, they say, because the
deer’s eyes resemble the eyes of Šeiḫ ‘Adî. Verily his virtues are well-
known and his praiseworthy qualities are traditions handed down
from generation to generation. He was the first to accept the Yezidi
religion. He gave them the rules of the religious sect and founded
the office of the ṣeiḫ. In addition to this, he was renowned for his
devotion and religious exercise. From Mount Lališ, he used to hear
the preaching of ‘Abd-al-ḳâdir-al-Jîlâni in Bagdad. He used to draw a
circle on the ground and say to the religious ones, “Whosoever
wants to hear the preaching of Al-Jîlânî, let him enter within this
circle.” The following custom, which we have, began with him: If we
wish to swear to anyone, a ṣeiḫ draws a circle, and he who is to take
an oath, enters into it.
At one time, passing by a garden, Šeiḫ ‘Adî asked about lettuce;
and, as no one answered, he said, “Huss” (hush). For this reason
lettuce is forbidden and not eaten.
As regards fasting, they say about the month of Ramaḍân that it
was dumb and deaf. Therefore, when God commanded the Moslems
to fast, he likewise commanded the Yezidis, saying to them in the
Kurdish language, “sese,” meaning “three.” The Mohammedans did
not understand it; they took it for “se,” “thirty.” For this reason, they
(Yezidis) fast three days. Moreover, they believe there are eating,
drinking, and other earthly pleasures in the next world.62 Some hold
that the rule of heaven is in God’s hands, but the rule of the earth is
in Šeiḫ ‘Adî’s hands. Being exceedingly beloved by God, he bestowed
upon him according to ‘Adî’s desire.
They believe in the transmigration of souls. This is evinced by the
fact that when the soul of Manṣûr-al-Ḥallâj parted from his body
when the Caliph of Bagdad killed him and cast his head into the
water, his soul floated on the water. By a wonderful chance and a
strange happening, the sister of the said Manṣûr went to fill her jar.
The soul of her brother entered it. Without knowing what had
happened, she came with it to the house. Being tired, she felt thirsty
and drank from the jar. At that moment the soul of her brother
entered her, but she did not perceive it until she became pregnant.
She gave birth to a son who resembled Šeiḫ Manṣûr himself. He
became her brother according to birth and her son according to
imputation. The reason why they do not use drinking-vessels which
have narrow mouths, or a net-like cover, is that when one drinks
water from them they make a sound. When the head of Šeiḫ Manṣûr
was thrown into the water it gurgled. In his honor they do not use
the small jars with narrow necks.
They assert that they expect a prophet who will come from Persia
to annul the law of Mohammed and abrogate Islam. They believe
that there are seven gods, and that each god administers the
universe for ten thousand years; and that one of these gods is
Lasiferos, the chief of the fallen angels, who bears also the name
Melek Ṭâ´ûs. They make him a graven image after the form of a
cock63 and worship it. They play the tambourine and dance before it
to make it rejoice with them. They (ḳawwâls) travel within the
Yezidis’ villages to collect money, at which time they take it into the
houses that it may bless and honor them. Some say that Šeiḫ ‘Adî is
a deity; others that he is like a Vizier to God. To him all things are
referred. This is Melek Ṭâ´ûs age. The ruling and administrative
power is in his hands until the thousandth year. When the time
comes to an end he will deliver the power to the next god to rule
and administer until another thousand years shall be ended, and so
on until the seventh god. And yet there is accord and love among
these gods, and none is jealous of the one who may rule and
administer the world for a period of ten thousand years. They have a
book named Al Jilwah that they ascribe to Šeiḫ ‘Adî, and they suffer
no one who is not one of them to read it.
Mention is made in some of their books that the First Cause is the
Supreme God, who before he created this world, was enjoying
himself over the seas;64 and in his hand was a great White Pearl,
with which he was playing. Then he resolved to cast it into the sea,
and when he did so this world came into being.
Moreover, they think themselves not to be of the same seed from
which the rest of mankind sprung, but that they are begotten of the
son of Adam, who was born to Adam of his spittle. For this reason
they imagine themselves nobler and more pleasing to the gods than
others.
They say they have taken fasting and sacrifice from Islam;
baptism from Christians; prohibition of foods from the Jews; their
way of worship from the idolaters; dissimulation of doctrine from the
Rafiḍis (Shi‘ites); human sacrifice and transmigration from the pre-
Islamic paganism of the Arabs and from the Sabians. They say that
when the spirit of man goes forth from his body, it enters into
another man if it be just; but if unjust, into an animal.
THE POEM IN PRAISE OF ŠEIḪ ‘ADÎ
Peace Be unto Him
My understanding surrounds the truth of things,
And my truth is mixed up in me,
And the truth of my descent is set forth by itself,
And when it was known it was altogether in me.
And all that are in the universe are under me,
And all the habitable parts and deserts,
And everything created is under me,
And I am the ruling power preceding all that exists.
And I am he that spoke a true saying,
And I am the just judge and the ruler of the earth.
And I am he that men worship in my glory,
Coming to me and kissing my feet.
And I am he that spread over the heavens their height.
And I am he that cried in the beginning.
And I am he that of myself revealeth all things,
And I am he to whom came the book of good tidings
From my Lord, who burneth the mountains.
And I am he to whom all created men come
In obedience to kiss my feet.
I bring forth fruit from the first juice of early youth
By my presence, and turn toward me my disciples.
And before this light the darkness of the morning cleared away.
I guide him that asketh for guidance.
I am he that caused Adam to dwell in Paradise
And Nimrod to inhabit a hot burning fire.
And I am he that guided Aḥmed the Just,
And let him into my path and way.
And I am he unto whom all creatures
Come for my good purposes and gifts.
And I am he that visited all the heights,
And goodness and charity proceed from my mercy.
And I am he that made all hearts to fear
My purpose, and they magnify the majesty and power of my
awfulness.
And I am he to whom the destroying lion came
Raging, and I shouted against him and he became stone.
And I am he to whom the serpent came,
And by my will I made him dust.
And I am he that struck the rock and made it tremble,
And made to burst from its sides the sweetest of waters.[65]
And I am he that sent down the certain truth;
For me is the book that comforteth the oppressed.
And I am he that judged justly,
And when I judged it was my right
And I am he that made the springs65 to give water,
Sweeter and pleasanter than all waters.
And I am he that caused it to appear in my mercy,
And by my power I called it the pure.
And I am he to whom the Lord of heaven hath said,
Thou art the just Judge and Ruler of the earth.
And I am he that disclosed some of my wonders,
And some of my virtues are manifested in that which exists.
And I am he that caused the mountains to bow,
To move under me and at my will.66
And I am he before whose majesty the wild beasts cried;
They turned to me worshiping, and kissed my feet.
And I am ‘Adî aš-Šâmî, the son of Musâfir.
Verily the All-Merciful has assigned unto me names,
The heavenly throne, and the seat, and the (seven) heavens, and
the earth.
In the secret of my knowledge there is no God but me.
These things are subservient to my power.
O mine enemies, why do you deny me?
O men, deny me not, but submit.
In the day of judgment you will be happy in meeting me.
Who dies in my love, I will cast him
In the midst of Paradise, by my will and pleasure;
But he that dies unmindful of me
Will be thrown into torture in misery and affliction.
I say I am the only one and the exalted;
I create and make rich those whom I will.
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