Analog and Digital VLSI design

Lecture2: Fabrication process

BITS Pilani Dr. Samatha Benedict
Pilani Campus
 Fabrication
How are chips made?

Transfer the layout design onto silicon wafer using fabrication

processes

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CMOS process
Diffusion/Ion implantation

Chemical Vapour deposition (CVD)

Lithography

Diffusion/Ion implantation

Deposition (Sputtering, Evaporation

Electrochemical deposition

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How to get the Silicon wafer

 Seed rod is rotated

and pulled up.
 Orientation of seed
and ingot are
matched

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 Different fabrication processes

Diffusion/Ion implantation : Process for introduction of dopants

The area to be doped is exposed to the required dopant while the rest of the wafer is coated with an
impenetrable material such as SiO2

Diffusion: Dopants are introduced as gas at high Ion implantation: Dopants are introduced as ions using a
temperature (~1000C) in a furnace Dopants diffuse directed beam
vertical and lateral The acceleration determines the vertical penetration

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Deposition : Different materials can be deposited using the chemical (CVD) or physical route (PVD). The area to be
deposited is exposed

CVD: Vapours are introduced as gas at high PVD: material is obtained by bombardment from a
temperature (~650C) which then react and deposit on substrate using ions, the bombarded material deposits
the surface on surface

SiO2, polysilicon etc are deposited using CVD

Metals are deposited using PVD

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Lithography : process of creating opening on a wafer using a predetermined design
The design (layout) is printed on a quartz wafer. The areas to be exposed are transparent while the rest is opaque.

Photoresist is a light sensitive

material which undergoes reaction
after exposure to light.
2 types: Positive photoresist which
softens after exposure and this can
be removed. Negative which
hardens after exposure

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Epitaxy is the process of the controlled growth of a crystalline doped layer of silicon on a single crystal substrate

Orientation is determined by the underlying crystal.

Why is it needed?
2 Types of Epitaxy
1.Better material - grow higher purity silicon by
epitaxy than the silicon in the substrate.
2.Different material - Epitaxy allows for the growth of
material different from the substrate such as SiGe. This
is how heterojunction bipolar transistors (HBT) and
modern MOSFETs are made.
3.Doping reversal - Using implantation or diffusion
restricts the layer design of transistors. Without epitaxy,
the heaviest doping must be on the top in the
(shallowest) layer. Epitaxy allows a lower doped layer
to be grown on a higher doped layer.

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nMOS fabrication process

1. Pure Si single crystal

2. P-type impurity is lightly doped

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3. SiO2 Deposited over si surface

4. Photoresist is deposited over SiO2 layer

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5. Photoresist layer is exposed to UV Light through a mask

6. Developer removes unpolymerised

photoresist. It will cause no effect on Si
surface
7a. Etching [HF acid is used] will remove SiO2 layer
which is in direct contact with etching solution

7b. Unpolymerised photoresist is also etched away

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8. A thin layer of SiO2 grown over the entire
chip surface

9. A thin layer of polysilicon is grown

over the entire chip surface to form
GATE

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10. A layer of photoresist is coated over polysilicon layer

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11. Photoresist is exposed to UV Light

12. Etching will remove that portion of Thin

SiO2 which is not exposed to UV light
13. Polymerised photoresist is also stripped
away

14. n+ Doping to form SOURCE and DRAIN

15. A thick layer of SiO2 (1 μm) is again grown

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 16. Photoresist is grown over thick SiO2.
Selected areas of the poly GATE and
SOURCE and DRAIN are exposed where
contact cuts are to be made

17. The region of photoresist which is

not exposed by UV light will become
soft. This unpolymerised photoresist
and SiO2 below it are etched away.
18. The contact cuts are formed for S,
D and G (hardened photoresist is
stripped away).

19. Metal (aluminium) is deposited over

the surface of whole chip (1 μm
thickness)
20. Photoresist is deposited over the metal.

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 21. UV Light is passed through Mask-4
(with a aim of removing all metal other
than metal in contact-cuts)

22. Photoresist and metal which is not

exposed to UV light are etched away
23. Final n-MOS Transistor

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Layout: Done by mask layout
designer

Silicon wafer: processed by the

process engineer

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Layout design rules

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 Stick diagram

Displays the edges and nodes of the circuit which aids further layout design

Technology decides the minimum size requirements and spacing

between layers

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CMOS Inverter Layout

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 Design Rules

Minimum Width The widths (and lengths) of the geometries defined

on a mask must exceed a minimum value imposed by both
lithography and the processing capabilities of the technology

Minimum Spacing The geometries built on the same mask or, in some
cases, different masks must be separated by a minimum spacing.

Minimum Enclosure the n-well and the p+ implant must surround the
transistor with sufficient margin to guarantee that the device is
contained by these geometries despite tolerances

Minimum Extension Some geometries must extend beyond the edge of

others by a minimum value.
The gate polysilicon must have a minimum extension beyond the active area
to ensure proper transistor action at the edge.

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 If we can minimize the number of diffusion-area breaks both for nMOS and for pMOS
transistors, the separation between the polysilicon gate columns can be made smaller, which will
reduce the overall horizontal dimension and, hence, the circuit layout area.

 The number of diffusion breaks can be minimized by changing the ordering of the
polysilicon columns.
 Euler’s Graph
 A simple method for finding the optimum gate ordering is the Euler-path approach: find a Euler path in the pull-down
graph and a Euler path in the pull-up graph with identical ordering of input labels, i.e., find a common Euler path for
both graphs.

 The Euler path is defined as an uninterrupted path that traverses each edge (branch) of the graph exactly once

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 Analog layout techniques

 Wide transistors are usually “folded” so as to reduce both the S/D

junction area and the gate resistance.
 A simple folded structure may prove inadequate for very wide
devices, necessitating the use of multiple “fingers”
 As a rule of thumb, the width of each finger is chosen such that the
resistance of the finger is less than the inverse transconductance
associated with the finger.
 In low-noise applications, the gate resistance must be one-fifth to
one-tenth of 1/gm.

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 While the gate resistance can be reduced by decomposing the
 For a layout with three fingers, the total
transistor into more parallel fingers, the capacitance
perimeter of the source or the drain is equal
associated with the perimeter of the source/drain areas
to 2(2E +2W/3) = 4E +4W/3, whereas with
increases
five fingers, it is equal to 3(2E +2W/5) = 6E
 In general, for an odd number of fingers N, the S/D perimeter +6W/5.
capacitance is given by

 For minimum S/D capacitance, no of fingers multiplied

by E must be less than W

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Symmetry: asymmetries in fully differential circuits
introduce input-referred offsets, thus limiting the minimum
signal level that can be detected.

While some mismatch is inevitable, inadequate attention

to symmetry in the layout may result in large offsets

The two transistors are laid out with different

orientations, the matching suffers greatly because
many steps in lithography and wafer processing
behave differently along different axes.

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 Gate shadowing effect

The choice between the layout is determined by a subtle effect called “gate shadowing.”

 Gate shadowing is caused by the gate polysilicon during the source/drain implantation because the implant
is tilted by about 7o to avoid channeling
 As a result, a narrow strip in the source or drain region receives less implantation, creating a small
asymmetry between the source and drain side diffusions after the implanted areas are annealed.

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 In Fig. (a), if the shadowed terminal is distinguished as the drain
(or the source), then the two devices sustain no asymmetry
resulting from shadowing.
 In Fig.(b), on the other hand, the transistors are not identical
even if the shadowed terminals are distinguished because the
source region of M1 “sees” M2 to its right, whereas the source
region of M2 sees only the field oxide.
 Similarly, the drains of M1 and M2 see different structures to
their left. In other words, the surrounding environment of M1 is
not identical to that of M2.
 For this reason, the topology of Fig. (a) is preferable.

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 The asymmetry inherent in the structures of Fig. 19.15(b) can be ameliorated by adding “dummy” transistors to
the two sides so that M1 and M2 see approximately the same environment.
 However, in more complex circuits, such measures cannot be easily applied.

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 An unrelated metal line passing over only one transistor indeed degrades the symmetry, increasing the mismatch
between M1 and M2.
 In such cases, a replica must be produced on the other side

 Symmetry becomes more difficult to establish for large

transistors. In the differential pair of the two transistors
have a large width so as to achieve a small input offset
voltage, but gradients along the x axis give rise to
appreciable mismatches.
 To reduce the error, a “common-centroid” configuration
may be used such that the effect of first-order gradients
along both axes is canceled
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 Common Centroid layout

 The idea is to decompose each transistor into two halves

that are placed diagonally opposite each other and
connected in parallel.
 However, the routing of interconnects in this layout is
quite difficult, often leading to systematic asymmetries or
in the capacitances from the wires to ground and
between the wires.

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  We have 2 components A and B. A and B can be anything resistor, capacitor,
transistor.
 We split A and B into 4 smaller components A1to A4 and B1 to B4

 Common centroid technique: Place A and B such that they have the same centroid

A1B1B2A2
B3A3A4B4

A1B1A2B2
B3A3B4A4
 Interdigitated technique: Place A and B in alternating fashion

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(W/L)3 = (W/L)4

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(W/L)1 = 2(W/L)2

Can also use M1 M1 M2 M2 M1 M1

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Example of common centroid matching

 M1 and M2 must match

 M3 and M4 must match, M6 must be wider by 4xM3
 M7 must be 2x M5
Device capacitances

W/L = 40; hence since L = 2λ ; W = 80 λ

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 Reduce parasitic capacitance
Achieved through junction sharing

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 Interconnect Parasitic

Analyse the interconnect in terms of:

 Resistance
 Capacitance
 Parallel plate
 Sidewall/Fringe
 Coupling
 Elmore model: calculate delay due to
parasitics

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 Interconnect Parasitic

Delay estimation considers 3 main contributors to the output load:

(i) internal parasitic capacitances of the transistors
(ii) interconnect (line) capacitances
(iii) input capacitances of the fan-out gates.

The load conditions imposed by the interconnection lines present serious problems, especially in submicron
circuits.

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Why parasitics are important

 The line is a three-dimensional structure in metal and/or

polysilicon, usually has a non-negligible resistance in
addition to its capacitance.
 The (length/width) ratio of the wire usually dictates that
the parameters are distributed, making the interconnect a
true transmission line.

 Interconnection line is in very close proximity to a number

of other lines, either on the same level or on different
levels.
 The capacitive/inductive coupling and the signal
interference between neighboring lines should also be
taken into consideration for an accurate estimation of
delay.

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 Governing principle to model

 If the time of flight across the interconnection line is much shorter than the signal rise/fall times, then the wire
can be modeled as a capacitive load, or as a lumped or distributed RC network.

 If the interconnection lines are sufficiently long and the rise times of the signal waveforms are comparable to
the time of flight across the line, then the inductance also becomes important, and the interconnection lines
must be modeled as transmission lines

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 But as the fabrication technologies move to finer
submicron technology, the intrinsic gate delays tend to
decrease significantly.
 The overall chip size and the worst-case line length on
a chip tend to increase mainly due to increasing chip
complexity, hence interconnect delay is important
submicron technologies.
 The widths of metal lines shrink, the transmission line
effects and signal coupling between neighboring lines
also become important
Interconnect capacitance estimation

 Each interconnection line (wire) is a three-dimensional

structure in metal and/or polysilicon, with significant
variations of shape, thickness, and vertical distance from the
ground plane (substrate).

 Interconnect line is typically surrounded by a number of

other lines, either on the same level or on different levels.

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Interconnect segment runs parallel to the chip surface and is
separated from the ground plane by a dielectric (oxide) layer of
height (h)

2 components: parallel plate capacitance and side wall

capacitance

In interconnect lines where the wire thickness (t) is comparable

in magnitude to the ground-plane distance (h),fringing electric
fields significantly increase the total parasitic capacitance

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 Total parasitic capacitance of the line is not only
increased by the fringing-field effects, but also by
the capacitive coupling between the lines.

 This coupling between the interconnect lines is

mainly responsible for signal crosstalk, where
transitions in one line can cause noise in the other
lines

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 Variation of the fringing-field factor FF = Ctotal/Cpp, as
a function of (t/h), (w/h) and (w/l)

 The influence of fringing fields increases with the

decreasing (w/h) ratio, and that the fringing-field
capacitance can be as much as 10-20 times larger than
the parallel-plate capacitance.

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Different capacitances and effect of scaling

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Yuan and Trick capacitance estimation

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Interconnect resistance estimation

The resistance of a line depends on the type of material used, the

dimensions of the line and the number and locations of the contacts on
that line

 As a first-order approximation the total lumped resistance may be

assumed to be connected in series with the total lumped
capacitance of the wire.

 The effects of the parasitic resistance must be taken into account

for longer wire segments.

 Important in case of polysilicon interconnects

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 Calculation of interconnect delay
RC delay model
Parasitics of the interconnect line consists of one lumped
resistance and one lumped capacitance

Output voltage waveform of this simple RC circuit is found as

Simple lumped RC network model provides a
very rough approximation of the actual transient
behavior of the interconnect line.
The rising output voltage reaches the 50%-point at t = τPLH

The propagation delay for the simple lumped RC network

Lumped RC model can be significantly improved
by dividing the total line resistance into two equal
parts (the T-model)
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 The transient behavior of an interconnect line can be more accurately represented using the RC ladder network.
 Each RC-segment consists of a series resistance (R/N), and a capacitance (C/N) connected between the node and the
ground.
 It can be expected that the accuracy of this model increases with increasing N, where the transient behavior
approaches that of a distributed RC line for very large values of N.

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 Elmore delay

Conditions to be met to use Elmore delay (i) there are no resistor loops in this circuit, (ii) all of the capacitors in
an RC tree are connected between a node and the ground, and (iii) there is one input node in the circuit

 Let Pi denote the unique path from the input node to node i, i = 1, 2, 3, ..., N.

 Let Pij = Pi Pj denote the portion of the path between the input and the node i, which is
U
common to the path between the input and node j.

Elmore delay at node i of this RC tree is given by the following expression.

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 Elmore delay at node 7 is

Elmore delay at node 5 is

τD5

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 For a uniform RC ladder network, consisting of identical elements (R/N) and (C/N)

For very large N (distributed RC line behavior), this delay expression reduces to

If the length of the interconnection line is sufficiently large and the rise/fall times of the signal waveforms
are comparable to the time of flight across the line, then the interconnect line must be modeled as a
transmission line,

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 Process Issues

Shallow Trench Isolation Issues

 Modern MOS devices are surrounded by a shallow
“trench” so as to avoid the formation of a channel
between adjacent transistors called “shallow trench
isolation”.
 This structure is filled with oxide and exhibits a different
thermal expansion coefficient from that of silicon.
 As a result, during fabrication steps, the STI and the
enclosed silicon area expand and contract differently.
 This STI-induced “stress” alters the electrical properties
of the MOS transistor, introducing substantial error in its
I/V characteristics.

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Well Proximity Effects
 n-well is formed by an N-type implant onto the exposed
areas of silicon.
 The unexposed areas are covered by a thick layer consisting
of oxide and photoresist
 The implant does not occur at a 90◦ angle with respect to the
wafer, thus reflecting from the walls formed by oxide and
photoresist and creating nonuniform doping in the n-well.
 The border areas of the n-well receive a different doping
density from those in the middle of the n-well.
 Consequently, the PMOS devices located near the edges of
the n-well have different I/V characteristics compared to
those in the middle.
 We call this effect the “well proximity” error.
 The current mirror arrangement exhibits mismatches
between M1 and M2 or M3 because M1 is more heavily
influenced by the implant reflections.

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Latchup
 It is phenomenon that occurs when parasitic bipolar
transistors formed by the substrate, well and diffusion turn
on
 A path for current between Vdd and ground formed by the
presence of cross coupled npn and pnp transistors.
 During power up if a substantial current flows Vsub
increases turning on npn, this in turn causes a drop in Vwell
turning on pnp. Once pnp is turned on Vsub increases
causing a positive feedback with large current flow
 Solutions:
 1. Minimize Rsub and Rwell through epitaxial heavily doped
silicon
 2. Place substrate and well taps close and use well taps for
every 5 to 10 transistors and connect to appropriate supply
 3. Use of guard rings: Substrate or well taps tied to propoer
supply that completely surround the transistor of concern
 Photolithography
Microchemicals Silicon wafer production
https://www.youtube.com/watch?v=IF2pDoPBv10
https://www.youtube.com/watch?v=2qLI-NYdLy8

https://www.youtube.com/watch?v=D1ALNg3z2gk

https://www.youtube.com/watch?v=c9arR8T0Qts

Infineon Chip manufacturing: From sand to silicon

https://www.youtube.com/watch?v=bor0qLifjz4

TSMC Automated fabrication

https://www.youtube.com/watch?v=4Q_n4vdyZzc

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