Latches and Flip Flops

Basic Stable Memory Element

Bistable Multivibrators
Latch
• Bistable multivibrator

• State change triggers

• Level triggered
• Clock edge triggered (Flip Flops)
Memory Elements and Their Excitation Functions

To generate the Y’s: memory devices must be supplied with appropriate input values
• Excitation functions: switching functions that describe the impact of xi’s and yj’s on the
memory-element input
• Excitation table: its entries are the values of the memory-element inputs

Most widely used memory elements: flip-flops, which are made of latches
• Latch: remains in one state indefinitely until an input signals directs it to do otherwise

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Set-Reset (SR) Latch (NOR Gate)
Working
Set-Reset (SR) Latch (NAND Gate)
Chatterless Switch
Clocked/Gated SR Latch
 Timing the SR latch
x1 z1
Tperiod
xl Combinational zm
logic

y1 Y1
ton

y2 Y2 R
S y y
C Clock
y
yk Yk R y
S
(a) Block diagram. (b) Logic diagram.
``Memory’’ devices

• A clock is a periodic signal that is used to keep time in

sequential circuits.
• Duty Cycle is the ration of ton/Tperiod
• We want to keep ton small so that in the same clock
pulse only a single computation is performed.
• We want to keep Tperiod sufficient so that there is
enough time for the next input to be computed.
11
Trigger or T Latch
Value 1 applied to its input triggers the latch to change state

S 1 y
1 y T
T Clock
0 y
0 y
R

(a) Block diagram. (b) Deriving the T latch from the

clocked SR latch.
Excitations requirements:

y(t+1) = Ty’(t) + T’y(t)

= T + y(t)
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The JK Latch
Unlike the SR latch, J = K = 1 is permitted: when it occurs, the latch acts
like a trigger and switches to the complement state

J S 1 y
J 1 y
Clock C
K 0 y
K 0 y
R

(a) Block diagram. (b) Constructing the JK latch from the

Excitation requirements: clocked SR latch.

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The D Latch
The next state of the D latch is equal to its present excitation:
y(t+1) = D(t)

D J 1 y
D 1 y
Clock C
Clock 0 y
K 0 y

(a) Block diagram. (b) Transforming the JK latch to

the D latch.

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Clock Timing
Clocked latch: changes state only in synchronization with the clock pulse
and no more than once during each occurrence of the clock pulse
Duration of clock pulse: determined by circuit delays and signal
propagation time through the latches
• Must be long enough to allow latch to change state, and
• Short enough so that the latch will not change state twice due to the same
excitation
Excitation of a JK latch within a sequential circuit:
• Length of the clock pulse must allow the latch to generate the y’s
• But should not be present when the values of the y’s have propagated
through the combinational circuit

Combinational
logic

y J
1

y
0 K Clock

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JK Flip Flop
Master Slave JK Flip Flop
D Flip Flop with Asynchronous Preset Clear
D Flip Flop with Synchronous Preset Clear
Residual problem with above DFF
• Let the gate delay be Δ
• Let D=0, Clk=1
• Let D=1 and just before Δ time, Clk=0
• Master latch has the invalid input combination of 00
• Before valid inputs could appear at the steering gates of the master latch, Clk=0
• Now, invalid input combination of 11 is presented to the slave steering gates,
with Clock'=1
• Slave latch has the invalid input combination of 00
• Output of DFF is indeterminate

• Problem may be avoided if D remains steady when Clk=1, allowed to change only
when Clk=0
Setup and hold times
• Setup time: It is defined as the minimum amount of time before the active clock edge by which
the data must be stable for it to be latched correctly; any violation in this required time causes
incorrect data to be captured and is known as a setup violation

Time available for data at D2 to reach D1 after active clock edge

Tclk + Tskew - Tsetup
Time needed for date to reach D1 from D2 after active clock edge
Tc2q + Tcomb
Resulting constraint
Tc2q + Tcomb ≤ Tclk + Tskew - Tsetup
Tc2q + Tcomb + Tsetup ≤ Tclk + Tskew
 Hold time
It is defined as the minimum amount of time after the active clock edge by which the data
must be stable for it to be latched correctly; any violation in this required time causes incorrect data
to be captured and is known as a hold violation

Minimum time for data at D2 to reach D1 after active clock edge

Tc2q + Tcomb
Time for data to remain steady at D1 after active clock edge
Tskeq + Thold
Resulting constraint
Tc2q + Tcomb ≥ Tskeq + Thold
Edge-triggered Flip-flop
Positive (negative) edge-triggered D flip-flip: stores the value at the D input
when the clock makes a 0 -> 1 (1 -> 0) transition
• Any change at the D input after the clock has made a transition does not
have any effect on the value stored in the flip-flop

A negative edge-triggered D flip-flop:

• When the clock is high, the output of the bottommost (topmost) NOR gate
is at D’ (D), whereas the S-R inputs of the output latch are at 0, causing it
to hold previous value
• When the clock goes low, the value from the
bottommost (topmost) NOR gate gets transferred
as D (D’) to the S (R) input of the output latch
– Thus, output latch stores the value of D
• If there is a change in the value of the D R y
input after the clock has made its transition, Clock
the bottommost NOR gate attains value 0 S y
– However, this cannot change the SR
inputs of the output latch

D
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Positive Edge Triggered DFF
Counters
Binary Ripple Counter (Asynchronous)
Up/Down Binary Ripple Counter
Decade Counter
Combination of Counters
Counter Applications
Glitch (Temporary Undesired States)
Synchronous Counters
Synchronous Counter using JK Flip Flop
Synchronous Counter
Synchronous Counter
Up/Down Counter
UP Counting
Down Counting
Shift Registers

Serial In Parallel Out

Used in Computer Memory as Bit Arrays

Converts Serial Input to Parallel Output
Parallel In Serial Out
Bidirectional Shift Register with Parallel IO
Barrel Shift/Rotate