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The document outlines interregister transfers and instruction design within a machine architecture context, detailing various operations involving registers such as ACC, A, S, and L. It explains the instruction cycle, which includes the fetch and decode stages, and provides specific instruction designs for operations like DUP and NEG. The document includes a series of steps and cycles required for executing these instructions, emphasizing the sequential processing of commands by the CPU.

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The document outlines interregister transfers and instruction design within a machine architecture context, detailing various operations involving registers such as ACC, A, S, and L. It explains the instruction cycle, which includes the fetch and decode stages, and provides specific instruction designs for operations like DUP and NEG. The document includes a series of steps and cycles required for executing these instructions, emphasizing the sequential processing of commands by the CPU.

Uploaded by

2523793320wzy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Interregister transfers and

instruction design
Blackboard exercise notes
W machine architecture
address bus

wel wyl wea

L il A

weak ACC czyt


Memory
dod ALU
wyad
ode (Arithmetic pisz

Code Address
I przep Logic Unit) S

wei weja wyak wes wys

data bus

2
Interregister transfers
• (L) → A • ((A)) → S
• (S) → I • ((A)) → ACC
• (ACC) → S • -((A)) → ACC
• (AD) → A • -(ACC) → ACC
• (AD) → L • (ACC)+(S) → ACC
• (S) → ACC • (ACC)+((A)) → S
• 0 → ACC • ((L)) → I
• -(S) → ACC • ((AD)) → ACC

3
Interregister transfers
• (ACC)+((AD)) → ACC • (0)+(1) → ACC
• ((L))+((L)+1) → ACC • 2*(0)+(1) → 2
• (S) → (A) • -(ACC) → 1
• (ACC) → (L) • (1)-(0) → 2
• 0 → (AD)+1 • (0)+((1)) → (2)
• 0→1
• (ACC) → (AD)
• (ACC) → ((AD))

4
Instruction cycle
• The instruction cycle (also known as the fetch-execute cycle) is
the cycle that the central processing unit (CPU) follows in order to
process instructions
• It is composed of two main stages: the fetch and decode stage,
and the execute stage
• The instructions that make up the program are executed
sequentially (each instruction is being processed before the next
one is started)
• The program counter (L register) is a special register that holds the
memory address of the next instruction to be executed
5
Fetch and decode stage
• 2 cycles required:
• First phase – sending the wyl
address of the next instruction:
wyl, wea wea
• Second phase – reading and
il
decoding the current
instruction: czyt, wys, wei czyt
and calculating the address of
the next instruction: il wys

wei

6
Fetch and decode stage
• 2 cycles required:
• First phase – sending the wyl
address of the next instruction:
wyl, wea (done at the end of the wea
previous instruction)
il
• Second phase – reading and
decoding the current czyt
instruction: czyt, wys, wei
and calculating the address of wys
the next instruction: il
(first phase of the current wei
instruction: czyt wys wei il)

7
DUP instruction design
• 2∙(ACC) → ACC

8
DUP instruction design
• 2∙(ACC) → ACC
• First phase: czyt wys wei il
• Muliplying by 2: (ACC) + (ACC) → (ACC) wyak weja dod weak
• Next instruction address to A: (L) → A wyl wea

9
DUP instruction design
2∙(ACC) → ACC
1. czyt wys wei il
2. wyak weja dod weak wyl wea

10
NEG instruction design
• -((AD)) → ACC

11
NEG instruction design
• -((AD)) → ACC
• First phase: czyt wys wei il
• address transferring: (AD) → A wyad wea
• Read data from memory: ((A)) → S czyt
• Calculate zero in accumulator: (ACC)-(ACC) → ACC
wyak weja ode weak
• Subtract: (ACC) – (S) → S
wys weja ode weak
• Next instruction address to A: wyl wea
12
NEG instruction design
• -((AD)) → ACC
• czyt wys wei il ;
• wyad wea;
• Read data from memory: (3) ((A)) → S czyt
• Calculate zero in accumulator: (2) (ACC)-(ACC) → ACC
wyak weja ode weak
• Subtract: (3) (ACC) – (S) → S
wys weja ode weak
• Next instruction address to A: (3) wyl wea
13
NEG instruction design
-((AD)) → ACC
1. First phase: czyt wys wei il
2. wyad wea wyak weja ode weak
3. czyt wys weja ode weak wyl wea

14

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