Arduino UNO Pin Description

EEARH (EEPROM Address Register High Byte) - - - - - - EEAR 9 EEAR 8

EEARL (EEPROM Address Register Low Byte) EEAR 7 EEAR 6 EEAR 5 EEAR 4 EEAR 3 EEAR 2 EEAR 1 EEAR 0
EEDR (EEPROM Data Register) D7 D6 D5 D4 D3 D2 D1 D0

EECR (EEPROM Control Register) - - EEPM1 EEPM0 EERIE EEMPE EEPE EERE
EERE (EEPROM Read Enable): 1 = Read from EEPROM EERIE (EEPROM Ready Interrupt Enable)
EEPE (EEPROM Program Enable): 1 = Write to EEPROM, SET EEMPE bit first EEMPM1:0 (EEPROM Programming Mode Bits): 0 0 = Erase and Write
EEMPE (EEPROM Master Program Enable): 1 = Master Write to EEPROM, 0 1 = Erase Only 1 0 = Write Only 1 1 = (Reserved)

TCNT0 (timer/Counter register) D7 D6 D5 D4 D3 D2 D1 D0

TCCR0A (Timer/Counter Control Register A) COM0A1 COM0A0 COM0B1 COM0B0 - - WGM01 WGM00
TCCR0B (Timer/Counter Control Register B) FOC0A FOC0B - - WGM02 CS02 CS01 CS00
WGM02 WGM01 WGM00 CS02 CS01 CS00 CS02 CS01 CS00
0 0 0 Normal Mode 0 0 0 No Clock Source 1 0 0 CLK / 256
0 1 0 CTC Mode 0 0 1 CLK (No Prescalling) 1 0 1 CLK / 1024
0 1 0 CLK / 8 1 1 0 External CLK on T0 on (CLK on Falling Edge.)
0 1 1 CLK / 64 1 1 1 External CLK on T0 on (CLK on Rising Edge)
TIFR0 (Timer/Counter Interrupt Flag Register 0) - - - - - OCF0B OCF0A TOV0
TOV0 : Timer 0 overflow flag bit 0 = Timer 0 did not overflow, 1 = Timer 0 has overflowed (going from 0xFF to 0x00)
OCF0A : Timer 0 output compare flag A bit 0 = Compare match did not occur. 1 = compare match occurred

TCNT2 (timer/Counter register) D7 D6 D5 D4 D3 D2 D1 D0

TCCR2A (Timer/Counter Control Register A) COM2A1 COM2A0 COM2B1 COM2B0 - - WGM21 WGM20
TCCR2B (Timer/Counter Control Register B) FOC2A FOC2B - - WGM22 CS22 CS21 CS20
WGM22 WGM21 WGM20 CS22 CS21 CS20 CS22 CS21 CS20
0 0 0 Normal Mode 0 0 0 No Clock Source 1 0 0 CLK / 64
0 1 0 CTC Mode 0 0 1 CLK (No Prescalling) 1 0 1 CLK / 128
0 1 0 CLK / 8 1 1 0 CLK / 256
0 1 1 CLK / 32 1 1 1 CLK / 1024
TIFR2 (Timer/Counter Interrupt Flag Register 2) - - - - - OCF2B OCF2A TOV2
TOV2 : Timer 2 overflow flag bit 0 = Timer 2 did not overflow, 1 = Timer 2 has overflowed (going from 0xFF to 0x00)
OCF2A : Timer 2 output compare flag A bit 0 = Compare match did not occur. 1 = compare match occurred

TCNT1H (timer/Counter register High Byte) D7 D6 D5 D4 D3 D2 D1 D0

TCNT1L (timer/Counter register Low Byte ) D7 D6 D5 D4 D3 D2 D1 D0
TCCR1A (Timer/Counter Control Register A) COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10
TCCR1B (Timer/Counter Control Register B) ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10
WGM12 WGM11 WGM10 CS12 CS11 CS10 CS12 CS11 CS10
0 0 0 Normal Mode 0 0 0 No Clock Source 1 0 0 CLK / 256
1 0 0 CTC Mode 0 0 1 CLK (No Prescalling) 1 0 1 CLK / 1024
0 1 0 CLK / 8 1 1 0 External CLK on T1 on (CLK on Falling Edge.)
0 1 1 CLK / 64 1 1 1 External CLK on T1 on (CLK on Rising Edge)
TIFR1 (Timer/Counter Interrupt Flag Register 1) - - ICF1 - - OCF1B OCF1A TOV1
TOV1 : Timer 2 overflow flag bit 0 = Timer 2 did not overflow, 1 = Timer 2 has overflowed (going from 0xFFFF to 0x0000)
OCF1A : Timer 2 output compare flag A bit 0 = Compare match did not occur. 1 = compare match occurred

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SREG (Status Register) I T H S V N Z C
Global Interrupt Bit Copy Overflow Negative
Description Half Carry Sign Flag Zero Flag Carry Flag
Enable Storage Flag Flag

TIMSK0 ( Timer Interrupt Mask Register 0) - - - - - OCIE0B OCIE0A TOI0E

(D0) TOI0E Timer0 Overflow Interrupt Enable 0 = Disable Timer0 Overflow Interrupt 1 = Enable Timer0 Overflow Interrupt
(D1) OCIE0A Timer0 Output Compare Match Interrupt Enable A 0 = Disable Compare Match A Interrupt 1 = Enable Interrupt
(D2) OCIE0B Timer0 Output Compare Match Interrupt Enable B 0 = Disable Compare Match B Interrupt 1 = Enable Interrupt

TIMSK2 ( Timer Interrupt Mask Register 2) - - - - - OCIE2B OCIE2A TOI2E

(D0) TOI2E Timer2 Overflow Interrupt Enable 0 = Disable Timer2 Overflow Interrupt 1 = Enable Timer2 Overflow Interrupt
(D1) OCIE2A Timer2 Output Compare Match Interrupt Enable A 0 = Disable Compare Match A Interrupt 1 = Enable Interrupt
(D2) OCIE2B Timer2 Output Compare Match Interrupt Enable B 0 = Disable Compare Match B Interrupt 1 = Enable Interrupt

TIMSK1 ( Timer Interrupt Mask Register 1) - - ICIE - - OCIE1B OCIE1A TOI1E

(D0) TOI1E Timer1 Overflow Interrupt Enable 0 = Disable Timer1 Overflow Interrupt 1 = Enable Timer1 Overflow Interrupt
(D1) OCIE1A Timer1 Output Compare Match Interrupt Enable A 0 = Disable Compare Match A Interrupt 1 = Enable Interrupt
(D2) OCIE1B Timer1 Output Compare Match Interrupt Enable A 0 = Disable Compare Match B Interrupt 1 = Enable Interrupt

EIMSK (External Interrupt Mask Register) - - - - - - INT1 INT0

(D0) INT1 External Interrupt Request 1 0 = Disable Interrupt 1 = Enable External Interrupt at T0 Pin.
(D1) INT0 External Interrupt Request 0 Enable 0 = Disable Interrupt 1 = Enable External Interrupt at T1 Pin.

EICRA (External Interrupt Control Register) A - - - - ISC11 ISC10 ISC01 ISC00

ISC11 ISC10 Description ISC01 ISC00 Description
0 0 A low level of INT0 generates an interrupt request 0 0 A low level of INT1 generates an interrupt request
0 1 Any logical change on INT0 generates an Interrupt request 0 1 Any logical change on INT1 generates an Interrupt req.
1 0 The falling edge of INT0 generates an interrupt 1 0 The falling edge of INT1 generates an interrupt
1 1 The rising edge of INT0 generates an interrupt 1 1 The rising edge of INT1 generates an interrupt

PCICR (Pin Change Interrupt Control Register) - - - - - PCIE2 PCIE1 PCIE0

(D0) PCIE0 1 = Any change on any enabled PCINT23..16 pin (Port D) (Arduino Pins 0 to 7) will cause an interrupt. 0 = interrupt is disabled
(D1) PCIE1 1 = Any change on any enabled PCINT14..8 pin (Port C) (Arduino Pins A0 to A5) will cause an interrupt 0 = interrupt is disabled
(D2) PCIE2 1 = Any change on any enabled PCINT7..0 pin (Port B) (Arduino Pins 8 to 13) will cause an interrupt. 0 = interrupt is disabled

PCMSK2 (Pin Change Mask Register 2) PCINT 23 PCINT 22 PCINT 21 PCINT 20 PCINT 19 PCINT 18 PCINT 17 PCINT 16
Port D PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Arduino Pins 7 6 5 4 3 2 1 0

PCMSK1 (Pin Change Mask Register 1) - PCINT 14 PCINT 13 PCINT 12 PCINT 11 PCINT 10 PCINT 9 PCINT 8
Port C - PC6 PC5 PC4 PC3 PC2 PC1 PC0
Arduino Pins - - A5 A4 A3 A2 A1 A0

PCMSK0 (Pin Change Mask Register 0) PCINT 7 PCINT 6 PCINT 5 PCINT 4 PCINT 3 PCINT 2 PCINT 1 PCINT 8
Port B PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Arduino Pins - - 13 12 11 10 9 8

Interrupt Vector Name in Arduino Interrupt Vector Name in Arduino

External Interrupt request 0 INT0_vect Time/Counter0 Compare Match A TIMER0_COMPA_vect
External Interrupt request 1 INT1_vect Time/Counter0 Overflow TIMER0_OVF_vect
External Interrupt request 2 INT2_vect SPI Serial Transfer Complete SPI_STC_vect
Pin Change Interrupt Request 0 PCINT0_vect USART Rx Complete USART_RX_vect
Pin Change Interrupt Request 1 PCINT1_vect USART Data Register Empty USART_UDRE_vect
Pin Change Interrupt Request 2 PCINT2_vect USART Tx Complete USART_TX_vect
Time/Counter2 Compare Match A TIMER2_COMPA_vect ADC Conversion Complete ADC_vect
Time/Counter2 Overflow TIMER2_OVF_vect EEPROM ready EE_READY_vect
Time/Counter1 Compare Match A TIMER1_COMPA_vect Analog Comparator ANALOG_COMP_vect
Time/Counter1 Overflow TIMER1_OVF_vect Two-wire Serial Interface TWI_vect

UCSR0A(USART Control and Status Register A) RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0
RXC0 (USART Receive Complete): 1 = There is new data in receive buffer DOR0 (Data Over Run): 1 = Data Over Run condition is detected
TXC0 (USART Receive Complete): 1 = data has been transmitted. UPE0 (USART Parity Error): 1 = Received byte had a Parity Error.
UDRE0 (USART Data Register Empty): 1 = transmit buffer is empty. U2X0(Double the USART Transmission Speed): 1 = double baud rate
0 = transmit buffer contains data to be transmitted. MPCM0 (Multi-processor Communication Mode): 1= Enable Multi-processor
FE0 (Frame Error): 1 = There is frame Error Communication.
UCSR0B (USART Control and Status Register B) RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80
RXCIE0 (RX Complete Interrupt Enable): TXEN0 (Transmitter Enable): 1 = Enables the USART Transmitter
1 = enables interrupt on the RXC0 Flag. UCSZ02 (Character Size): UCSZ02 bit combined with the UCSZ01:0 bits in UCSR0C sets the
TXCIE (TX Complete Interrupt Enable): number of data bits (Character Size) in a frame the Receiver and Transmitter.
1 = enables interrupt on the TXC0 Flag. RXB80 (Receive Data Bit 8): RXB80 is the ninth data bit of the received character when
UDRIE0 (USART Data Register Empty Interrupt Enable): operating with serial frames with nine data bits
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1 = enables interrupt on the UDRE0 Flag TXB80 (Transmit Data Bit 8): TXB80 is the ninth data bit in the character to be transmitted
RXE0 (Receiver Enable): 1 = Enables the USART Receiver when operating with serial frames with nine data bits.

UMSEL0
UMSEL01 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0
UCSR0C (USART Control and Status Register C) 0
UMSEL0[1:0] Mode UPM0[1:0] Parity Mode USBS0 (Stop Bit Select): 0 = 1 Stop Bit, 1 = 2 Stop Bits
00 Asynchronous USART 00 Disabled UCSZ0 [1:0] (Character Size): For UCSZ02=1 in UCSR0A
01 Synchronous USART 01 Reserved 0 0 = 5 bit Character Size 0 1 = 6 bit Character Size
10 (Reserved) 10 Enabled, Even Parity 1 0 = 7 bit Character Size 1 1 = 8 bit Character Size
11 Master SPI (MSPIM) 11 Enabled, Odd Parity UCPOL0 (Clock Polarity): This bit is used for synchronous mode only.

UDR0 (USART Data Register) D7 D6 D5 D4 D3 D2 D1 D0

UBRR0H (USART Baud Rate Register High Byte) - - - - UBRR0[11:8]

UBRR0L (USART Baud Rate Register Low Byte) UBRR0[7:0]

ADMUX ( ADC Multiplexer Register ) REFS1 REFS0 ADLAR - MUX3 MUX2 MUX1 MUX0
REFS1 REFS0 Reference Voltage Selection Bits MUX3…0 Pin Select MUX3…0 Pin Select MUX3…0 Pin Select
0 0 VREF = A REF Pin Set externally 0000 ADC0 0101 ADC5 1010 (Reserved)
0 1 VREF = AVCC Pin Same as VCC 0001 ADC1 0110 ADC6 1100 (Reserved)
1 0 Reserved 0010 ADC2 0111 ADC7 1101 (Reserved)
1 1 V REF = Internal 1.1v 0011 ADC3 1000 ADC8 Temp. 1110 1.1 V (VBG)
ADLAR 0 = Right Adjust ADC value, 1 = Left Adjust 0100 ADC4 1001 (Reserved) 1111 0V (GND)

ADCSRA ( ADC Control and Status Register A ) ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0
ADEN 1 = Enable the ADC, 0 = Disable ADC. ADPS2…0 CLK Division ADPS2…0 CLK Division
ADSC 1 = start conversion process. 000 2 100 16
ADATE 1 = Auto triggering of the ADC is enabled 001 2 101 32
ADIF 1 = ADC has completed its conversion, 0 = busy in conversion 010 4 110 64
ADIE 1 = Enables the ADC conversion complete interrupt. 011 8 111 128

LM35 Temperature Sensor Series Selection Guide LM34 Temperature Sensor Series Selection Guide
Part Temp. Range Accuracy Output Scale Part Temp. Range Accuracy Output Scale
LM35A -55 C to+150 C +1.0 C 10 mV/C LM34A -50 F to +300 F +2.0 F 10 mV/F
LM35 -55 C to +150 C +1.5 C 10 mV/C LM34 -50 F to +300 F +3.0 F 10 mV/F
LM35CA -40 C to +110 C +1.0 C 10 mV/C LM34CA -40 F to +230 F +2.0 F 10 mV/F
LM35C -40 C to +110 C +1.5 C 10 mV/C LM34C -40 F to +230 F +3.0 F 10 mV/F
LM35D 0 C to +100C +2.0 C 10 mV/C LM34D -32 F to +212 F +4.0 F 10 mV/F

SPSR ( SPI Status Register ) SPIF - - - - - - SPI2X

(Bit 7) SPIF : SPI Interrupt Flag : In master mode, this bit is set in two situations: when a serial transfer is completed, or when SS pin is an input and is driven
low by an external device. Setting the SPIF flag to one will cause an interrupt if SPIE in SPCR is set and global interrupts are enabled.
(Bit 6) WCOL : Write Collision Flag : The WCOL bit is set if you write on SPDR during a data transfer.
(Bit 0) SPI2X : Double SPI Speed : When the SPI is in master mode, setting this bit to one doubles the SPI speed.
Notice that both the WCOL bit and the SPIF bit are cleared when you read the SPI Status Register and then access the SPI Data Register. Alternatively, the
SPIF bit is cleared by hardware when executing the corresponding interrupt handler.

SPCR ( SPI Control Register ) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPRO
(Bit 7) SPIE : SPI Interrupt Enable : 1 = enable the SPI interrupt. (Bit 3) CPOL: Clock Polarity : This bit set the base value of clock when it is
(Bit 6) SPE: SPI Enable : 1 = enable the SPI. 0 = disable the SPI. idle. At CPOL = 0 the base value of the clock is zero while at CPOL = 1 the
(Bit 5) DORD : Data Order : 1 = The LSB is transmitted first base value of the clock is one.
0 = The MSB is transmitted first. (Bit 2) CPHA : Clock Phase : CPHA = 0 means sample on the leading (first)
(Bit 4) MSTR : Master/Slave Select : 1 = work in master mode clock edge, while CPHA = 1 means sample on the trailing (second) clock.
0 = work in slave mode. Notice that if the SS pin is configured as an input and (Bit 1) SPR1 : SPI Clock Rate Select 1 (Bit 0) SPRO: SPI Clock Rate Select 0
is driven low while MSTR is 1, MSTR will be cleared, and SPIF will become set. (Bit 1,2) control the SCK rate of the device in master mode. See Table below
SPI2X SPR1 SPRO SCK Frequency SPI2X SPR1 SPRO SCK Frequency
0 0 0 Fosc/4 1 0 0 Fosc/2 (Not recommended)
0 0 1 Fosc/16 1 0 1 Fosc/8
0 1 0 Fosc/64 1 1 0 Fosc/32
0 1 1 Fosc/128 1 1 1 Fosc/64

SPDR ( The SPI Data Register ) D7 D6 D5 D4 D3 D2 D1 D0

List of Commands in MAX7221

Command D15… D11 D10 D9 D8 Hex Code
D12
No operation X 0 0 0 0 Xo
Set value of digit 0 X 0 0 0 1 XI
Set value of digit 1 X 0 0 1 0 X2
Set value of digit 2 X 0 0 1 1 X3
Set value of digit 3 X 0 1 0 0 X4
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Set value of digit 4 X 0 1 0 1 X5
Set value of digit 5 X 0 1 1 0 X6
Set value of digit 6 X 0 1 1 1 X7
Set value of digit 7 X 1 0 0 0 X8
Set decoding mode X 1 0 0 1 X9
Set intensity of light X 1 0 1 0 XA
Set scan limit X 1 0 1 1 XB
Turn on/ off X 1 1 0 0 XC
Display test X 1 1 1 1 XF
Notes: 1) X means do not care.
2) Digits are designated as 0-7 to drive total of eight 7-segment LEDs.

TWBR ( TWI Bit Rate Register ) TBR7 TBR6 TBR5 TBR4 TBR3 TBR2 TBR1 TBR0

TWSR ( TWI Status Register ) TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPS0
(Bit 7… 3) TWS7…3 : TWI Status : These Five Bits show the status of the TWI
control and Bus XTAL
(Bit 1… 0) TWPS1…0 : TWI Prescaler Bits : These bits control the bit rate
frequency=
prescaler
16+ 2×TWBR×4 TWPS

TWCR ( TWI Control Register ) TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE
(Bit 7) TWINT: TWI Interrupt : This bit is set by hardware when the TWI (Bit 4) TWSTO: TWI STOP condition bit : In master mode, making this
module has finished its current job. If the TWI and general interrupt are bit HIGH causes the TWI to generate a STOP condition. This bit is cleared
enabled, changing TWINT to one will cause the MCU to jump to the TWI by hardware when the STOP condition is transmitted.
interrupt vector. Clearing this flag starts the operation of the TWI. TWINT (Bit 3) TWWC: TWI Write Collision Flag : This bit is set HIGH when we
must be cleared by software. attempt to access the TWI Data Register when TWINT is low. This flag is
(Bit 6) TWEA: TWI Enable Acknowledge : Making this bit HIGH will enable cleared by writing to the TWDR register when TWINT is high.
the generation of ACK when needed in slave or receiver mode. (Bit 2) TWEN: TWI Enable : Making this bit HIGH enables the TWI
(Bit 5) TWSTA: TWI START condition Bit : Making this bit HIGH will module.
generate a START condition if the bus is free; otherwise, the TWI module (Bit 0) TWIE: TWI Interrupt Enable : Making this bit HIGH enables the
waits for the bus to become free and then generates a START condition TWI interrupt if the general interrupt is enabled.

Simplified Block Diagram of DS1307 (Maxim / Dallas Semiconductor)

ADDRESS Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Function Range
00H CH 10 Seconds Seconds Seconds 00 – 59
01H 0 10 Minutes Minutes Minutes 00 – 59
1 = 12 hr 0=AM 1=PM 10 Hour Hours Hours 01 – 12
02H 0
0 = 24 hr 10 Hour Hours Hours 00 – 23
03H 0 0 Day Day 01 – 07
04H 0 Date Date 01 – 31
05H 0 Month Month 00 – 99
06H 10 Year Year Year 00 – 59
07H OUT 0 0 SQWE 0 0 RS1 RS0 Control –
08H-3FH RAM 56 x 8 00H – FFH

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