8 7 6 5 4 3 2 1

CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

J40I MLB 9 0001102890 ENGINEERING RELEASED 2011-04-07

D Thu Apr 7 18:48:24 2011 D

PDF CSA CONTENTS SYNC MASTER DATE PDF CSA CONTENTS SYNC MASTER DATE PDF CSA CONTENTS SYNC MASTER DATE
TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

1 1 Table of Contents J40I 11/23/2010 41 43 FIREWIRE CONNECTOR REFERENCE_MLB 11/23/2010 81 100 CPU Constraints REFERENCE_MLB 11/23/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

2 2 System Block Diagram REFERENCE_MLB 11/23/2010 42 44 HDD SATA CONNECTORS REFERENCE_MLB 11/23/2010 82 101 Memory Constraints REFERENCE_MLB 11/23/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

3 3 Power Block Diagram REFERENCE_MLB 11/23/2010 43 46 USB EXTERNAL CONNECTORS REFERENCE_MLB 11/30/2010 83 102 PCH Constraints 1 REFERENCE_MLB 11/23/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

4 4 COMMON PARTS TABLE REFERENCE_MLB 11/23/2010 44 47 IR CONTROLLER REFERENCE_MLB 11/23/2010 84 103 PCH Constraints 2 REFERENCE_MLB 11/23/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

5 5 Revision History REFERENCE_MLB 11/23/2010 45 48 IR/LED, PWR BTTN REFERENCE_MLB 11/23/2010 85 104 Ethernet/FW Constraints REFERENCE_MLB 11/23/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

6 6 POWER CONN / FLOW REFERENCE_MLB 11/23/2010 46 49 SMC REFERENCE_MLB 11/23/2010 86 105 T29 Constraints REFERENCE_MLB 11/23/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

7 7 POWER FLOW CONT. REFERENCE_MLB 11/23/2010 47 50 SMC Support REFERENCE_MLB 11/23/2010 87 106 SMC Constraints REFERENCE_MLB 11/23/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

8 8 SPECIFIC ALIASES, TABLES J40S 12/30/2010 48 51 LPC+ Debug Connector REFERENCE_MLB 11/23/2010 88 107 GPU (Whistler) CONSTRAINTS REFERENCE_MLB 11/23/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

9 9 MECHANICAL, GROUND VIAS REFERENCE_MLB 11/23/2010 49 52 SMBus Connections J40S 11/23/2010 89 108 Project Specific Constraints REFERENCE_MLB 11/23/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

10 10 CPU DMI/PEG/FDI/RSVD J40I 11/23/2010 50 53 Voltage & Load Side Current Sensing REFERENCE_MLB 11/23/2010 90 109 PCB Rule Definitions REFERENCE_MLB 11/23/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

11 11 CPU CLOCK/MISC/JTAG J40I 11/23/2010 51 54 High Side Current Sensing REFERENCE_MLB 11/23/2010 91 120 FUNCTIONAL / ICT TEST PROPERTIES REFERENCE_MLB 11/23/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

12 12 CPU DDR3 INTERFACES J40I 11/23/2010 52 55 THERMAL SENSORS J40S 11/23/2010 92 500 LAST SCHEMATIC PAGE
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

13 13 CPU POWER J40I 11/23/2010 53 56 AUDIO:CODEC REFERENCE_MLB 11/23/2010 93 501 Cross Reference Page
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

14 14 CPU GROUNDS J40I 11/23/2010 54 57 AUDIO:LINE-IN REFERENCE_MLB 11/23/2010 94 502 Cross Reference Page
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

15 16 CPU DECOUPLING-I J40I 11/23/2010 55 58 AUDIO:HEADPHONE AMP REFERENCE_MLB 11/23/2010 95 503 Cross Reference Page
C TABLE_TABLEOFCONTENTS_ITEM

16 17 CPU DECOUPLING-II J40I 11/23/2010

TABLE_TABLEOFCONTENTS_ITEM

56 59 AUDIO:SPEAKER AMP REFERENCE_MLB 11/23/2010

TABLE_TABLEOFCONTENTS_ITEM

96 504 Cross Reference Page C

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

17 18 PCH SATA/PCIE/CLK/LPC/SPI REFERENCE_MLB 11/23/2010 57 60 AUDIO:JACKS REFERENCE_MLB 11/23/2010 97 505 Cross Reference Page
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

18 19 PCH DMI/FDI/GRAPHICS REFERENCE_MLB 11/23/2010 58 61 AUDIO:JACK TRANSLATORS REFERENCE_MLB 11/23/2010 98 506 Cross Reference Page
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

19 20 PCH PCI/FLASHCACHE/USB REFERENCE_MLB 11/23/2010 59 64 SPI BOOT ROM REFERENCE_MLB 11/23/2010 99 507 Cross Reference Page
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

20 21 PCH MISC REFERENCE_MLB 12/07/2010 60 65 Fan Control Circuit REFERENCE_MLB 11/23/2010 100 508 Cross Reference Page
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

21 22 PCH POWER REFERENCE_MLB 11/23/2010 61 67 Power FETs REFERENCE_MLB 12/13/2010 101 509 Cross Reference Page
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

22 23 PCH GROUNDS REFERENCE_MLB 11/23/2010 62 68 Power Control 1/ENABLE REFERENCE_MLB 11/23/2010 102 510 Cross Reference Page
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

23 24 PCH DECOUPLING REFERENCE_MLB 11/23/2010 63 69 POWER CONTROL CONT. REFERENCE_MLB 11/23/2010 103 511 Cross Reference Page
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

24 25 CPU & PCH XDP REFERENCE_MLB 11/30/2010 64 71 VR - SYSTEM AGENT SUPPLY REFERENCE_MLB 11/23/2010 104 512 Cross Reference Page
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

25 26 USB HUBS REFERENCE_MLB 11/23/2010 65 72 VR - 3.3V S5 AND 5V S4 REFERENCE_MLB 11/23/2010

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

26 27 CLOCKS, CRYSTALS J40S 11/23/2010 66 73 DDR 1.5V VR REFERENCE_MLB 11/23/2010

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

27 28 RTC SUPPORT, RESETS REFERENCE_MLB 11/30/2010 67 74 VR - CPU VCORE & GPU CONTROLLER J40I 11/23/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

28 29 CPU Memory S3 Support REFERENCE_MLB 11/23/2010 68 75 VR - CPU VCORE OUTPUT PHASES J40I 11/23/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

29 30 SO-DIMM Pinswaps REFERENCE_MLB 11/23/2010 69 76 VR - GPU J40S 12/15/2010

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

30 31 DDR3 SO-DIMM Connector A-1 REFERENCE_MLB 11/23/2010 70 77 VR - 1.05V S0 J40I 12/02/2010

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

31 32 DDR3 SO-DIMM Connector A-2 REFERENCE_MLB 12/01/2010 71 78 VR - MISC REFERENCE_MLB 11/23/2010

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

32 33 DDR3 Support REFERENCE_MLB 11/23/2010 72 79 PSU CONNECTOR, MISC CAPS REFERENCE_MLB 11/23/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

B 33
TABLE_TABLEOFCONTENTS_ITEM
34 FSB/DDR3/FRAMEBUF Vref Margining REFERENCE_MLB 11/23/2010 73
TABLE_TABLEOFCONTENTS_ITEM
80 NO GPU GLUE REFERENCE_MLB 11/23/2010
B
34 35 SD CARD READER REFERENCE_MLB 12/03/2010 74 90 T29 Host (1 of 2) J40S 12/01/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

35 36 WIRELESS,BT CONNECTOR REFERENCE_MLB 11/23/2010 75 91 T29 Host (2 of 2) J40S 11/23/2010

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

36 38 ETHERNET CONNECTOR REFERENCE_MLB 11/23/2010 76 92 T29 Power Support J40S 11/23/2010

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

37 39 ETHERNET PHY (CAESAR IV) REFERENCE_MLB 11/23/2010 77 93 DisplayPort/T29 A MUXing J40S 11/23/2010
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

38 40 ETHERNET SUPPORT REFERENCE_MLB 11/30/2010 78 94 DisplayPort/T29 A Connector J40S 12/01/2010

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

39 41 FW LLC/PHY (XIO2211B) REFERENCE_MLB 11/23/2010 79 97 HDMI SHIFTER REFERENCE_MLB 11/23/2010

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

40 42 FW: 1394B MISC REFERENCE_MLB 11/23/2010 80 98 HDMI CONNECTOR REFERENCE_MLB 11/23/2010

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

DOCUMENTS / BOARDS / ASSEMBLIES

A PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION A
DRAWING TITLE
051-8768 1 SCHEM,MLBI,J40I SCH
SCH,MLB,J40
820-2993 1 PCBF,MLBI,J40I MLB DRAWING NUMBER SIZE

639-1558 PCBA,MLBI,J40I Apple Inc. 051-8768 D

REVISION
R
085-2372 1 DEV LIST,MLBI,J40I DEV1 DEVELOPMENT_LIST 9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 512
DRAWING SHEET
TITLE=SHORTSTACK III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
ABBREV=DRAWING IV ALL RIGHTS RESERVED 1 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

U1000
U8000
J2500
GDDR XDP CONN
INTEL CPU
J3100
WHISTLER GPU SANDYBRIDGE 2C+2 / 4C+2
PCIE X8 J2900
2 DIMMs
PCIE X4 DDR3-1067/1333MHZ
GDDR DIMM
D D
HDMI DP
POWER SUPPLY

GPIO FDI DMI RTC

TEMP SENSORS

GREEN CLOCK
MISC
CLK
OR BUFFER U6400 POWER SENSE
25MHZ
CRYSTAL SPI
Boot ROM
SPI
FAN CONN AND CONTROL
SATA
CONN
HDD1 3GHZ
INTEL U4900
SATA BSB B,0 SMS ADC Fan Ser
Prt J5100
COUGAR POINT-MPCH LPC+SPI Conn
SMC Port80,serial
SATA LPC
C T29
CONN 3GHZ C
HDD2
U1800
LIGHT RIDGE
J3401 J4600
eDP OUT X28/X16 EXTERNAL A
PWR Bluetooth
USB HDMI OUT PG 16-21 USB
J9400 CTRL
DP RGB OUT
M-DP OR DP DP OUT
HSIO J4610 J4501

0 1 2 3 4 5 6 7 8 9 10111213
DVI OUT
CONN OR EXTERNAL D
HDMI TMDS OUT EXTERNAL B EXTERNAL C IR
USB USB USB

(UP TO 14 DEVICES)
P1 P3 P2
U4550
USB
LVDS OUT
HUB-2 U4800

USB
IR
Controller
USE HUBS BECAUSE OF PCH BUG.
P3 P1 P2
J9700 U4500
USB
HDMI HUB-1
OR
B CONN
B
JTAG SMBUS
J2550

PCH XDP PCI-E HDA DIMM’s

(UP TO 8 LINES)
CONN

U6201
AUDIO
Codec
LINEIN
HPOUT CLKSDALINEOUT
EXT SPDIFOUT
MIC

LINE INPUT HP/LO

U4100 U3900 J3500 FILTER AMP
A XIO2211 E-NET SD Card SPEAKER
AMPs
SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
BCM57765 CONN PAGE TITLE

AUDIO IO SWITCH System Block Diagram

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

J3401 J4310 J4000 REVISION
R

X28/X16 FW
9.0.0
E-NET NOTICE OF PROPRIETARY PROPERTY: BRANCH
AirPort CONN CONN AUDIO THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
CONNs THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
2 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 2 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

C C

B B

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

Power Block Diagram

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
3 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 3 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

Alternate Parts
TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER
TABLE_ALT_ITEM

128S0286 128S0248 ? ? 39UF CAP FROM SANYO AND CHEMI-CON

TABLE_ALT_ITEM

132S0099 132S0203 ? ? 0.1UF CAP,X7R

PLATFORM CONTROL HUB (PCH) TABLE_ALT_ITEM

D PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION

138S0676 138S0691 ? 22UF CAP FROM MURATA
TABLE_ALT_ITEM
D
138S0681 138S0638 ? 10UF CAP FROM TAIYO YUDEN
337S3980 1 IC,PCH,COUGAR_POINT,QMZQ,SUPER SKU,BGA,ES1/B0 U1800 CRITICAL COUGAR_POINT:B0

337S4022 1 IC,PCH,COUGAR_POINT,QXXX,SUPER SKU,BGA,QS/B1 U1800 CRITICAL COUGAR_POINT:B1 TABLE_ALT_ITEM

152S0138 152S0694 ? ? INDUCTOR FROM VISHAY

337S4025 1 IC,PCH,COUGAR_POINT,QNJH,SUPER SKU,BGA,QS/B2 U1800 CRITICAL COUGAR_POINT:B2

337S4029 1 IC,PCH,COUGAR_POINT,SLH9D,BD82HM65,BGA,PRQ/B2 U1800 CRITICAL COUGAR_POINT:B2_PRQ_OLD TABLE_ALT_ITEM

152S1447 152S1269 ? ? INDUCTOR FROM CYNTEC

337S4087 1 IC,PCH,COUGAR_POINT,SLJ4P,BD82HM65,BGA,PRQ/B3 U1800 CRITICAL COUGAR_POINT:B3_PRQ TABLE_ALT_ITEM

152S1282 152S1155 ? ? INDUCTOR FROM CYNTEC

TABLE_ALT_ITEM

152S1366 152S1289 ? ? INDUCTOR FROM TOKO

TABLE_ALT_ITEM

155S0641 155S0397 ? ? FERRITE FROM LAIRD

TABLE_ALT_ITEM

155S0457 155S0329 ALL MAG LAYERS ALT TO MURATA

TABLE_ALT_ITEM

157S0058 157S0055 ALL DELTA ALT TO TDK MAGNETICS

PROGRAMMED PARTS TABLE_ALT_ITEM

PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 353S3196 353S3326 ? ? DIFFERENT TEMP RATING

341T0338 1 IC,EFI BOOTROM,J40 U6400 CRITICAL BASE: 335S0770,335S0769 TABLE_ALT_ITEM

371S0679 371S0652 ? ? PIN DIODE FROM NXP

341T0335 1 IC,SMC,J40G U4900 CRITICAL SMC:J40G BASE: 338S0895
TABLE_ALT_ITEM

341T0336 1 IC,SMC,J40I U4900 CRITICAL SMC:J40I BASE: 338S0895 376S0914 376S0881 ? SI7121DN AS ALTERNATE

341T0337 1 IC,SMC,J40S U4900 CRITICAL SMC:J40S BASE: 338S0895 TABLE_ALT_ITEM

376S0957 376S0999 ? DUAL FET FROM FAIRCHILD

341T0340 1 IC,IR CONTROLLER,J40 U4700 CRITICAL BASE: 338S0375 TABLE_ALT_ITEM

376S0958 376S0953
C 341T0341 1 IC,ENET ROM J40 U3990 CRITICAL BASE: 335S0539, 335S0663, OR 335S0800
376S1000 376S0960
?

?
DUAL FET FROM FAIRCHILD

DUAL FET FROM FAIRCHILD

TABLE_ALT_ITEM
C
TABLE_ALT_ITEM

376S0972 376S0612 ? FET FROM ROHM

TABLE_ALT_ITEM

376S0613 376S0859 ? OLDER DUAL FET FROM TOSHIBA

TABLE_ALT_ITEM

376S0855 376S0859 ? DUAL FET FROM DDS

TABLE_ALT_ITEM

376S0977 376S0859 ? DUAL FET FROM DDS

TABLE_ALT_ITEM

138S0703 138S0648 ? CAP FROM MURATA

TABLE_ALT_ITEM

197S0339 197S0179 ? OSC. FROM SITIME

TABLE_ALT_ITEM

376S0926 376S0610 ? DUAL FET FROM FAIRCHILD

TABLE_ALT_ITEM

376S0572 376S0659 ? FET FROM ALPHA OMEGA

TABLE_ALT_ITEM

377S0124 377S0057 ? VARISTOR FROM AMOTECH

NON-SCHEMATIC PARTS

PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION

B 825-6838 1 LBL,SERIAL NUMBER LBL B

www.teknisi-indonesia.com

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

COMMON PARTS TABLE

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
4 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 4 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

C C

B B

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

Revision History
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
5 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 5 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
BATTERY "G3" RAILS
3.3V ON WHEN UNIT HAS BATTERY POWER
G3
PPVBATT_G3_RTC OUT 27
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

DIODES
3.3V FET
D G3 3.3V D
PP3V3_G3_RTC OUT 17 18 21 27 91
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
ENET
PP3V3_ENET OUT 26 37 38 62 91
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6 MM
"G3H" RAILS MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
ON WHEN UNIT HAS AC POWER
VR 47 38 35 34 33 28 25 20 19 6 PP3V3_S4
1.2V 91 65 61 48 47 46 45 43 27 6 PP3V3_G3H
91 78 77 61 50 49

91 65 61 48 47 46 45 43 27 6 PP3V3_G3H
PSU ENET DEVELOPMENT
1
R0600
DEVELOPMENT
1
R0602
DEVELOPMENT
1
R0603
PP1V2_ENET
12V MAKE_BASE=TRUE
VOLTAGE=1.2V
OUT 37 38 91
200
1%
200
1% 1%
200
G3H MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.2MM
1/16W
MF-LF
2 402
1/16W
MF-LF
2 402
1/16W
MF-LF
2 402
PP12V_G3H_PSU OUT 51 72 91 MAX_NECK_LENGTH=3 MM
MAKE_BASE=TRUE ITS_PLUGGED_IN ITS_ALIVE ITS_BREATHING
VOLTAGE=12V NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE
MIN_LINE_WIDTH=0.6 mm A A A
MIN_NECK_WIDTH=0.2 mm
MAX_NECK_LENGTH=3 MM LED0600 LED0602 LED0603
GREEN-3.6MCD GREEN-3.6MCD GREEN-3.6MCD
K 2.0X1.25MM-SM K 2.0X1.25MM-SM K 2.0X1.25MM-SM
DEVELOPMENT DEVELOPMENT DEVELOPMENT
DEVELOPMENT ITS_BREATHING_Q
NO_TEST=TRUE
Q0603
SSM3K15FV D 3
"S4" RAILS SOD-VESM-HF

PP12V_G3H
C MAKE_BASE=TRUE
VOLTAGE=12.8V
MIN_LINE_WIDTH=0.6 mm
OUT 41 51 60 65 72 78 ON IN RUN AND SLEEP
1 G
C
SMC_SYS_LED S 2
MIN_NECK_WIDTH=0.25 mm 46 45 IN
MAX_NECK_LENGTH=3 MM
PP12V_G3H_CPUDDR
MAKE_BASE=TRUE
VOLTAGE=12.8V
OUT 51 64 66 68 69 70
VR
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm 5V
MAX_NECK_LENGTH=3 MM
S4
PP5V_S4 OUT 28 43 44 45 61 65 66 78 91
EG BOARDS ONLY. MAKE_BASE=TRUE 67 62 61 60 58 57 53 52 51 50
PP3V3_S0
LDO PP12V_G3H_GPU
MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
27 24 23 21 20 19 18 17 13 7
49 47 41 40 39 38 37 34 31 30
91 89 79 77 76 74 73 72 71 DEVELOPMENT
1
5V VOLTAGE=12.8V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
MAX_NECK_LENGTH=3 MM
R0605
200
G3H MAX_NECK_LENGTH=3 MM
1%
1/16W
MF-LF
PP5V_G3H
MAKE_BASE=TRUE
VOLTAGE=5V
OUT 45 47 61 65 91
FET 2 402
CATERR_LED_R
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM 3.3V DEVELOPMENT
MAX_NECK_LENGTH=3 MM
S4 1
R0615 A DEVELOPMENT
LED0605
PP3V3_S4 OUT 6 19 20 25 28 33 34 35 38 47 49 100K RED
VR MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.50MM
50 61 77 78 91 5%
1/16W
MF-LF K
2X125-SM

3.3V MIN_NECK_WIDTH=0.20MM
MAX_NECK_LENGTH=3 MM
2 402
CATERR_LED
G3H 6
PP3V3_G3H OUT 6 27 43 45 46 47 48 61 65 91
DEVELOPMENT
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 MM
D Q0605
MIN_NECK_WIDTH=0.2 MM DMB53D0UV
MAX_NECK_LENGTH=3 MM
SOT-563
B DEVELOPMENT
CATERR_R 2 G
B
R0616 3 DEVELOPMENT
81 11 CPU_CATERR_L 1
20K 2 CPU_CATERR_RL 5 Q0605 S
IN DMB53D0UV
VR 5%
1/16W
MF-LF 4
SOT-563 1

1.5V 402

"S5" RAILS S3
PP1V5_S3 OUT 28 30 31 32 61 66 72 91
MAKE_BASE=TRUE
STANDARD STANDBY STATE. VOLTAGE=1.5V
MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM
FET
5V
S5
PP5V_S5 OUT 23 61
MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.1 MM
MAX_NECK_LENGTH=3 MM

FET
3.3V VR
S5 0.75V
PP3V3_S5
MAKE_BASE=TRUE
OUT 17 18 19 20 21 23 24 25 27 28
59 61 62 78 89 91
S3
PPDDRVREF_S3
A VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
OUT 33 66 91

SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
MAX_NECK_LENGTH=3 MM MAKE_BASE=TRUE PAGE TITLE

POWER CONN / FLOW

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 6 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
1.05V Rails

PP1V05_S0_VCCIO
VR MAKE_BASE=TRUE
VOLTAGE=1.05V
OUT 10 11 13 15 67 91

1.05V MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM PP1V05_S0 OUT 24 46 50 62 70 76

S0 MAX_NECK_LENGTH=3 MM

FET
5V
D S0 D
PP5V_S0 OUT 23 24 41 42 48 61 62 64 67 68 PP1V05_S0_PCH OUT 17 18 21 23 50
MAKE_BASE=TRUE 69 70 71 80 91 MAKE_BASE=TRUE
VOLTAGE=5V VOLTAGE=1.05V
MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM

XW0700
SM
1 2 PP5V_S0_AUDIO PP1V8_S0
MAKE_BASE=TRUE
VOLTAGE=5V
OUT 53
VR MAKE_BASE=TRUE
VOLTAGE=1.8V
OUT 15 18 21 23 26 71

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM 1.8V MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

XW0701
SM
MAX_NECK_LENGTH=3 MM
S0 MAX_NECK_LENGTH=3 MM

1 2 PP5V_S0_AUDIO_AMP OUT 56
MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM

FET PP1V8_S0_CPU_VCCPLL_R OUT 13 15

3.3V MAKE_BASE=TRUE
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5 MM
S0 MIN_NECK_WIDTH=0.2 MM
PP3V3_S0 OUT
51 52 53 57 58 60 61 62 67 71
6 13 17 18 19 20 21 23 24 27 30

C MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
31 34 37 38 39 40 41 47 49 50
72 73 74 76 77 79 89 91
C
MAX_NECK_LENGTH=3 MM

VR
LDO 0.75V PP0V75_S0_DDRVTT OUT 28 30 31 66 91

1.5V S0 MAKE_BASE=TRUE
VOLTAGE=0.75V
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
S0 MAX_NECK_LENGTH=3 MM
PP1V5_S0 OUT 17 21 23 39 53 71 72 91
MAKE_BASE=TRUE
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
MAX_NECK_LENGTH=3 MM

PPVCCSA_S0_CPU
VR MAKE_BASE=TRUE
VOLTAGE=1.0V
OUT 13 16 50 64

MIN_LINE_WIDTH=0.5 MM
CPU-SA MIN_NECK_WIDTH=0.2 MM

S0 MAX_NECK_LENGTH=3 MM

B B

PPVCORE_S0_CPU
VR MAKE_BASE=TRUE
VOLTAGE=1.25V
OUT 10 13 15 50 67 68 91

MIN_LINE_WIDTH=0.6 MM
CPU-CORE MIN_NECK_WIDTH=0.25 MM

S0 MAX_NECK_LENGTH=3 MM
FET
1.5V
SW
69
PPVAXG_S0_CPU PP1V5_VDDQ_CPU_R
VR 16 13
67 50 MAKE_BASE=TRUE
VOLTAGE=1.25V VOLTAGE=1.5V
OUT 50 61

MIN_LINE_WIDTH=0.6 MM MIN_LINE_WIDTH=0.5 MM
CPU-AXG MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 mm

S0 MAX_NECK_LENGTH=3 MM

(IG BOARDS ONLY.)

PP1V5_VDDQ_CPU OUT 11 13 16 28 31 32 50 62

VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5 MM
A MIN_NECK_WIDTH=0.2 mm
SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

POWER FLOW CONT.

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
7 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 7 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

INTEL INTEGRATED GRAPHICS

FDI BUS.
10 IN =FDI_DATA_P<7..0> MAKE_BASE=TRUE FDI_DATA_P<7..0> OUT 18 81

10 IN =FDI_DATA_N<7..0> MAKE_BASE=TRUE FDI_DATA_N<7..0> OUT 18 81

10 OUT =FDI_INT MAKE_BASE=TRUE FDI_INT IN 18 81

10 OUT =FDI_FSYNC<1..0> MAKE_BASE=TRUE FDI_FSYNC<1..0> IN 18 81

10 =FDI_LSYNC<1..0> MAKE_BASE=TRUE FDI_LSYNC<1..0> 18 81

D
OUT
NO PCIE TO EXTERNAL GRAPHICS
IN
D
10 OUT =PEG_D2R_N<7..0> MAKE_BASE=TRUE NC_PEG_D2RN<7..0> 91

10 OUT =PEG_D2R_P<7..0> MAKE_BASE=TRUE NC_PEG_D2RP<7..0> 91

10 IN =PEG_R2D_C_N<7..0> MAKE_BASE=TRUE NC_PEG_R2D_CN<7..0> 91

10 IN =PEG_R2D_C_P<7..0> MAKE_BASE=TRUE NC_PEG_R2D_CP<7..0> 91

84 17 IN PEG_CLK100M_N MAKE_BASE=TRUE NC_PEG_CLK100MN 91

84 17 IN PEG_CLK100M_P MAKE_BASE=TRUE NC_PEG_CLK100MP 91

EXTERNAL DISPLAY PORT

18 BI =IG_DP_EXTA_DDC_CLK MAKE_BASE=TRUE DP_EXTA_DDC_CLK BI 77 83

18 BI =IG_DP_EXTA_DDC_DATA MAKE_BASE=TRUE DP_EXTA_DDC_DATA BI 77 83

18 BI =IG_DP_EXTA_AUXCH_C_N MAKE_BASE=TRUE DP_EXTA_AUXCH_C_N BI 77 83

18 BI =IG_DP_EXTA_AUXCH_C_P MAKE_BASE=TRUE DP_EXTA_AUXCH_C_P BI 77 83

18 OUT =IG_DP_EXTA_HPD MAKE_BASE=TRUE DP_EXTA_HPD IN 77 83

18 IN =IG_DP_EXTA_ML_C_N<3..0> MAKE_BASE=TRUE DP_EXTA_ML_C_N<3..0> OUT 77 83

18 IN =IG_DP_EXTA_ML_C_P<3..0> MAKE_BASE=TRUE DP_EXTA_ML_C_P<3..0> OUT 77 83

HDMI
18 BI =IG_HDMI_LS_SCL MAKE_BASE=TRUE HDMI_LS_SCL BI 79 83

18 BI =IG_HDMI_LS_SDA MAKE_BASE=TRUE HDMI_LS_SDA BI 79 83

18 OUT =IG_HDMI_LS_HPD MAKE_BASE=TRUE HDMI_LS_HPD IN 79 83

18 IN =IG_HDMI_DATA_C_N<2..0> MAKE_BASE=TRUE HDMI_DATA_C_N<2..0> OUT 79 83

=IG_HDMI_DATA_C_P<2..0> HDMI_DATA_C_P<2..0>
C 18

18
IN
IN =IG_HDMI_CLK_C_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE HDMI_CLK_C_N
OUT
OUT
79 83

79 83
C
18 IN =IG_HDMI_CLK_C_P MAKE_BASE=TRUE HDMI_CLK_C_P OUT 79 83 USED FOR T29 IC
ZT0840
T29 STDOFF-4.0OD1.85H-SM
1

teknisi-indonesia
PCIE
ZT0841
10 OUT =PCIE_T29_D2R_N<3..0> MAKE_BASE=TRUE PCIE_T29_D2R_N<3..0> IN 74 84
STDOFF-4.0OD1.85H-SM
10 OUT =PCIE_T29_D2R_P<3..0> MAKE_BASE=TRUE PCIE_T29_D2R_P<3..0> IN 74 84 1
10 IN =PCIE_T29_R2D_C_N<3..0> MAKE_BASE=TRUE PCIE_T29_R2D_C_N<3..0> OUT 74 84

10 IN =PCIE_T29_R2D_C_P<3..0> MAKE_BASE=TRUE PCIE_T29_R2D_C_P<3..0> OUT 74 84

T29 DISPLAY PORT INPUT

18 BI =IG_DP_T29SNK0_CTRL_CLK MAKE_BASE=TRUE DP_T29SNK0_CTRL_CLK BI 74

18 BI =IG_DP_T29SNK0_CTRL_DATA MAKE_BASE=TRUE DP_T29SNK0_CTRL_DATA BI 74

18 BI =IG_DP_T29SNK0_AUXCH_C_N MAKE_BASE=TRUE DP_T29SNK0_AUXCH_C_N BI 74 83

18 BI =IG_DP_T29SNK0_AUXCH_C_P MAKE_BASE=TRUE DP_T29SNK0_AUXCH_C_P BI 74 83

18 OUT =IG_DP_T29SNK0_HPD MAKE_BASE=TRUE DP_T29SNK0_HPD IN 74 83

18 IN =IG_DP_T29SNK0_ML_C_N<3..0> MAKE_BASE=TRUE DP_T29SNK0_ML_C_N<3..0> OUT 74 83

18 IN =IG_DP_T29SNK0_ML_C_P<3..0> MAKE_BASE=TRUE DP_T29SNK0_ML_C_P<3..0> OUT 74 83

B PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION B

338S0945 1 IC,T29,SLHAJ,FCBGA,15X15MM U9000 CRITICAL
335S0550 1 IC,EEPROM,SERIAL,SPI,4KX8,1.8V,MLP8,LF U9090 CRITICAL T29ROM:BLANK
341T0342 1 IC,CONF ROM,T29,J40I,S U9090 CRITICAL T29ROM:PROG_IS
341T0380 1 IC,CONF ROM,T29,J40G U9090 CRITICAL T29ROM:PROG_G
337S3997 1 IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25 U9330 CRITICAL T29MCU:BLANK
341T0339 1 IC,PROGRMD,T29 PORT MCU,HVQFN25 U9330 CRITICAL T29MCU:PROG

PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION

353S3312 1 IC,CBTL04DP081A,2:1 DP MUX,QFN U9390 CRITICAL T29DPMUX:NXP
353S3312 1 IC,CBTL04DP081A,2:1 DP MUX,QFN U9390 CRITICAL T29DPMUX:BOTH
353S3055 1 IC,PI3VEDP212,2:1 DP MUX,QFN U9390 CRITICAL T29DPMUX:PERICOM

TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER
TABLE_ALT_ITEM

353S3055 353S3312 T29DPMUX:BOTH ? DP MUX FROM PERICOM

A SYNC_MASTER=J40S SYNC_DATE=12/30/2010 A
PAGE TITLE

SPECIFIC ALIASES, TABLES

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
8 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 8 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
CPU / NB HEATSINK MOUNTING HOLES / NUTS POGO PINS FOR GROUNDING HEATPIPE ASSEMBLY.
ZT0960 ZT0961
STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH
1 1 ZP0900 ZP0902
POGO-2.0OD-3.6H-K86-K87 POGO-2.0OD-3.6H-K86-K87
SM SM
1 1

D ZT0962
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0966
STDOFF-4.5OD.98H-1.1-3.48-TH
D
ZP0901 ZP0903 ZP0907
1 1 POGO-2.0OD-3.6H-K86-K87 POGO-2.0OD-3.6H-K86-K87 POGO-2.0OD-3.6H-K86-K87
SM SM SM
1 1 1

ENCLOSURE MOUNTING POSTS

ZT0940 ZT0941 ZP0920 ZP0921 ZP0922
STDOFF-4.5OD10.75H-1.1-3.48-TH STDOFF-4.5OD10.75H-1.1-3.48-TH 1.4DIA-SHORT-EMI-MLB-M97-M98 1.4DIA-SHORT-EMI-MLB-M97-M98 1.4DIA-SHORT-EMI-MLB-M97-M98
SM SM SM
1 1
1 1 1

C C

REAR I/O FENCE MOUNTING BOSS

BLOWER SUPPORT POST.
ZT0910 ZT0912
4.0OD1.55H-M1.6X0.35-ST 4.0OD1.55H-M1.6X0.35-ST ZT0970
1 1 STDOFF-3.04OD6.1H-1.3-1.9-TH1
1

ZT0911 ZT0913
4.0OD1.55H-M1.6X0.35-ST
4.0OD1.55H-M1.6X0.35-ST
1
1

ZT0914 SPEAKER BOSS

4.0OD1.55H-M1.6X0.35-ST
1
ZT0915
4.0OD1.55H-M1.6X0.35-ST
B 1
B
DEVELOPMENT
J0900
1
To be distributed after simulation A
SM-TP3P4X1P8-TOP

DEVELOPMENT
ZH0930 ZH0935 ZH0940 ZH0945 ZH0950 ZH0955 J0901
HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA HOLE-VIA 1
1 1 1 1 1 1 A
SM-TP3P4X1P8-TOP

ZH0931 ZH0941 ZH0951 ZH0956

ZH0936 ZH0946 HOLE-VIA PLACE ONE ON EACH SIDE OF BOARD
HOLE-VIA HOLE-VIA 1 HOLE-VIA
1 HOLE-VIA 1 HOLE-VIA 1 IN EASILY ACCESSIBLE LOCATION.
1 1
LABEL "GND".

ZH0932 ZH0942 ZH0952 ZH0957

ZH0937 HOLE-VIA
HOLE-VIA HOLE-VIA ZH0947 1 HOLE-VIA
1 HOLE-VIA 1 1
1 HOLE-VIA
1

ZH0933 ZH0943 ZH0953 ZH0958

ZH0938 HOLE-VIA HOLE-VIA
HOLE-VIA HOLE-VIA ZH0948 1 1
1 HOLE-VIA 1
1 HOLE-VIA
1

ZH0944 ZH0954
ZH0934 HOLE-VIA
HOLE-VIA 1
A HOLE-VIA
1
1 ZH0949
HOLE-VIA SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
1 PAGE TITLE

MECHANICAL, GROUND VIAS

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
Digital Ground R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
GND 57 56 GND_AUDIO_SPKRAMP THE INFORMATION CONTAINED HEREIN IS THE
MIN_LINE_WIDTH=0.2MM PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
MIN_NECK_WIDTH=0.15MM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MAX_NECK_LENGTH=3 MM
VOLTAGE=0V
MAKE_BASE=TRUE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
9 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 9 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

OMIT_TABLE NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.
CRITICAL R1010 OMIT_TABLE
24.9 2 PP1V05_S0_VCCIO CRITICAL
81 CPU_PEG_COMP 1 7 10 11 13 15 67 91

81 18 IN DMI_S2N_N<0> M2 DMI_RX_0* U1000 PEG_ICOMPI G3

PLACE_NEAR=U1000.G3:12.7MM
1%
1/16W
81 24 10 IN CPU_CFG<0> B50 CFG_0 U1000 RSVD_28 BE7 CPU_MEM_VREFDQ_A 10
81 18 DMI_S2N_N<1> P6 DMI_RX_1* SANDY-BRIDGE PEG_ICOMPO G1 MF-LF 81 10 CPU_CFG<1> C51 CFG_1 BGA RSVD_29 BG7 CPU_MEM_VREFDQ_B 10
IN 402 IN (5 OF 9)
81 18 DMI_S2N_N<2> P1 DMI_RX_2* MOBILE-2C-35W PEG_RCOMPO G4 81 10 CPU_CFG<2> B54 CFG_2
IN IN RESERVED N42
BGA D53 RSVD_30 NC
81 18 DMI_S2N_N<3> P10 DMI_RX_3* 81 10 CPU_CFG<3> CFG_3

SANDY-BRIDGE
MOBILE-2C-35W
IN (1 OF 9) H22 =PEG_D2R_N<0> IN L42
PEG_RX_0* 8 RSVD_31 NC
D 81 18 IN DMI_S2N_P<0> N3 DMI_RX_0 PEG_RX_1* J21 =PEG_D2R_N<1>
IN
IN 8
81 10

81 10
IN
IN
CPU_CFG<4>
CPU_CFG<5>
A51
C53
CFG_4
CFG_5
RSVD_32 L45
L47
NC D
81 18 IN DMI_S2N_P<1> P7 DMI_RX_1 PEG_RX_2* B22 =PEG_D2R_N<2> IN 8
C55 RSVD_33 NC
81 10 IN CPU_CFG<6> CFG_6
81 18 IN DMI_S2N_P<2> P3 DMI_RX_2 PEG_RX_3* D21 =PEG_D2R_N<3> IN 8
H49 M13
81 10 IN CPU_CFG<7> CFG_7 RSVD_34 NC
81 18 IN DMI_S2N_P<3> P11 DMI_RX_3 PEG_RX_4* A19 =PEG_D2R_N<4> IN 8
A55 M14
TP_CPU_CFG<8> CFG_8 RSVD_35 NC
PEG_RX_5* D17 =PEG_D2R_N<5> IN 8 PLACE_NEAR=U1000.H43:50.8MM
H51 U14
81 18 OUT DMI_N2S_N<0> K1 DMI_TX_0* TP_CPU_CFG<9> CFG_9 RSVD_36 NC
PEG_RX_6* B14 =PEG_D2R_N<6> IN 8
PLACE_SIDE=BOTTOM
K49 W14
81 18 OUT DMI_N2S_N<1> M8 DMI_TX_1* TP_CPU_CFG<10> CFG_10 RSVD_37 NC
PEG_RX_7* D13 =PEG_D2R_N<7> IN 8 PPVCORE_S0_CPU 7 10 13 15 50 67 68 91
K53 P13
81 18 OUT DMI_N2S_N<2> N4 DMI_TX_2* TP_CPU_CFG<11> CFG_11 RSVD_38 NC
A11 =PCIE_T29_D2R_N<0>

DMI
DMI_N2S_N<3> R2 PEG_RX_8* IN 8 PPVCORE_S0_CPU 7 10 13 15 50 67 68 91
TP_CPU_CFG<12> F53
81 18 OUT DMI_TX_3* CFG_12
PEG_RX_9* B10 =PCIE_T29_D2R_N<1> IN 8 NOSTUFF G53 RSVD_39 AT49NC
1 1
TP_CPU_CFG<13> CFG_13
81 18 OUT DMI_N2S_P<0> K3 DMI_TX_0 PEG_RX_10* G8 =PCIE_T29_D2R_N<2> IN 8 R1064 R1070 L51 RSVD_40 K24 NC
TP_CPU_CFG<14> CFG_14
81 18 OUT DMI_N2S_P<1> M7 DMI_TX_1 PEG_RX_11* A8 =PCIE_T29_D2R_N<3> IN 8 49.9 49.9 F51 AH2
1% 1% TP_CPU_CFG<15> CFG_15 RSVD_41 NC
81 18 OUT DMI_N2S_P<2> P4 DMI_TX_2 PEG_RX_12* B6 NC_PEG_D2RN<12> 91 1/16W 1/16W D52 AG13
MF-LF MF-LF 81 10 IN CPU_CFG<16> CFG_16 RSVD_42 NC
81 18 OUT DMI_N2S_P<3> T3 DMI_TX_3 PEG_RX_13* H8 NC_PEG_D2RN<13> 91 402 2 2 402 L53 AM14
TP_CPU_CFG<17> CFG_17 RSVD_43 NC
PEG_RX_14* E5 NC_PEG_D2RN<14> 91 PLACE_NEAR=U1000.H45:50.8MM
AM15
RSVD_44 NC
8 OUT =FDI_DATA_N<0> U7 FDI0_TX_0* PEG_RX_15* K7 NC_PEG_D2RN<15> 91
PLACE_SIDE=BOTTOM
H43 VCC_VAL_SENSE
CPU_VCC_VALSENSE_P
8 OUT =FDI_DATA_N<1> W11 FDI0_TX_1* VOLTAGE=1.25V K43 VSS_VAL_SENSE RSVD_45 N50 NC
PEG_RX_0 K22 =PEG_D2R_P<0> IN 8 CPU_VCC_VALSENSE_N
=FDI_DATA_N<2> W1

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

8 OUT FDI0_TX_2* VOLTAGE=0V
PEG_RX_1 K19 =PEG_D2R_P<1> IN 8
H45 VAXG_VAL_SENSE
8 OUT =FDI_DATA_N<3> AA6 FDI0_TX_3* CPU_AXG_VALSENSE_P
PEG_RX_2 C21 =PEG_D2R_P<2> IN 8 VOLTAGE=1.05V K45 VSSAXG_VAL_SENSE
=FDI_DATA_N<4> W6 D19 =PEG_D2R_P<3> CPU_AXG_VALSENSE_N
8 OUT FDI1_TX_0* PEG_RX_3 IN 8 VOLTAGE=0V
8 =FDI_DATA_N<5> V4 FDI1_TX_1* PEG_RX_4 C19 =PEG_D2R_P<4> 8 TP_CPU_VCC_DIE_SENSE F48 VCC_DIE_SENSE
OUT IN
=FDI_DATA_N<6> Y2 D16 =PEG_D2R_P<5> NOSTUFF
8 OUT FDI1_TX_2* PEG_RX_5 IN 8

8 OUT =FDI_DATA_N<7> AC9 FDI1_TX_3* PEG_RX_6 C13 =PEG_D2R_P<6> IN 8

R10651 1
R1071 89 52 OUT CPU_THERMD_P H48 RSVD_6 DC_TEST_A4 A4
C4
TP_CPU_DC_TEST_A4
49.9 49.9 K48 RSVD_7 DC_TEST_C4 CPU_DC_TEST_C4_D3
PEG_RX_7 D12 =PEG_D2R_P<7> IN 8 1% 1% 89 52 OUT CPU_THERMD_N D3
8 OUT =FDI_DATA_P<0> U6 FDI0_TX_0 1/16W 1/16W DC_TEST_D3
PEG_RX_8 C11 =PCIE_T29_D2R_P<0> IN 8 MF-LF MF-LF BA19 RSVD_8 D1
8 OUT =FDI_DATA_P<1> W10 FDI0_TX_1 402 2 2 402 NC DC_TEST_D1 TP_CPU_DC_TEST_D1
=PCIE_T29_D2R_P<1>

PCI EXPRESS BASED INTERFACE SIGNALS

PEG_RX_9 C9 IN 8
=FDI_DATA_P<2> W3 FDI0_TX_2 PLACE_NEAR=U1000.K45:50.8MM
AV19 RSVD_9 DC_TEST_A58 A58 TP_CPU_DC_TEST_A58
8 OUT
PEG_RX_10 F8 =PCIE_T29_D2R_P<2> IN 8 PLACE_SIDE=BOTTOM NC
=FDI_DATA_P<3> AA7 AT21 A59 CPU_DC_TEST_C59_A59
C 8

8
OUT

=FDI_DATA_P<4> W7
FDI0_TX_3

FDI1_TX_0
PEG_RX_11
PEG_RX_12
C8
C5
=PCIE_T29_D2R_P<3>
NC_PEG_D2RP<12> 91
IN 8
NC
BB21
NC
RSVD_10
RSVD_11
DC_TEST_A59
DC_TEST_C59 C59 C
OUT BB19 A61 CPU_DC_TEST_C61_A61
PLACE_NEAR=U1000.K43:50.8MM
NC RSVD_12 DC_TEST_A61
8 OUT =FDI_DATA_P<5> T4 FDI1_TX_1 PEG_RX_13 H6 NC_PEG_D2RP<13> 91 PLACE_SIDE=BOTTOM
AY21 C61
NC RSVD_13 DC_TEST_C61
8 OUT =FDI_DATA_P<6> AA3 FDI1_TX_2 PEG_RX_14 F6 NC_PEG_D2RP<14> 91
BA22 D61 TP_CPU_DC_TEST_D61
NC RSVD_14 DC_TEST_D61
8 OUT =FDI_DATA_P<7> AC8 FDI1_TX_3 PEG_RX_15 K6 NC_PEG_D2RP<15> 91
AY22 BD61 TP_CPU_DC_TEST_BD61
NC RSVD_15 DC_TEST_BD61
=FDI_FSYNC<0> AA11 FDI0_FSYNC PEG_TX_0* G22 =PEG_R2D_C_N<0> AU19 RSVD_16 DC_TEST_BE61 BE61 CPU_DC_TEST_BE59_BE61
8 IN OUT 8
NC
=FDI_FSYNC<1> AC12 FDI1_FSYNC PEG_TX_1* C23 =PEG_R2D_C_N<1> AU21 RSVD_17 DC_TEST_BE59 BE59
8 IN OUT 8
NC
PEG_TX_2* D23 =PEG_R2D_C_N<2> BD21 RSVD_18 DC_TEST_BG61 BG61 CPU_DC_TEST_BG59_BG61
8 =FDI_INT U11 FDI_INT
OUT 8
NC
IN F21 =PEG_R2D_C_N<3> BD22 BG59
PEG_TX_3* OUT 8
NC RSVD_19 DC_TEST_BG59
91
11 10 7 PP1V05_S0_VCCIO BD25 BG58 TP_CPU_DC_TEST_BG58
67 15 13 8 IN =FDI_LSYNC<0> AA10 FDI0_LSYNC PEG_TX_4* H19 =PEG_R2D_C_N<4> OUT 8
NC RSVD_20 DC_TEST_BG58
R1030 8 IN =FDI_LSYNC<1> AG8 FDI1_LSYNC PEG_TX_5* C17 =PEG_R2D_C_N<5> OUT 8
BD26
NC RSVD_21 DC_TEST_BG4 BG4 TP_CPU_DC_TEST_BG4
24.9 2 BG22 BG3
1 EDP_COMP PEG_TX_6* K15 =PEG_R2D_C_N<6> OUT 8
NC RSVD_22 DC_TEST_BG3 CPU_DC_TEST_C4_BE3_BG3
1% AD2 EDP_ICOMPO PEG_TX_7* F17 =PEG_R2D_C_N<7> 8
BE22 RSVD_23 DC_TEST_BE3 BE3
1/16W
PLACE_NEAR=U1000.AF3:12.7MM
OUT NC
MF-LF AF3 EDP_COMPIO PEG_TX_8* F14 =PCIE_T29_R2D_C_N<0> BG26 RSVD_24 DC_TEST_BG1 BG1 CPU_DC_TEST_C4_BE1_BG1
402 OUT 8
NC
PEG_TX_9* A15 =PCIE_T29_R2D_C_N<1> BE26 RSVD_25 DC_TEST_BE1 BE1
OUT 8
NC
EMBEDDED DISPLAY PORT

91 NC_EDP_HPD AG11 EDP_HPD BF23 BD1

PEG_TX_10* J14 =PCIE_T29_R2D_C_N<2> OUT 8
NC RSVD_26 DC_TEST_BD1 TP_CPU_DC_TEST_BD1
NC_EDP_AUXN AG4 EDP_AUX* PEG_TX_11* H13 =PCIE_T29_R2D_C_N<3> BE24 RSVD_27
91 OUT 8
NC
91 NC_EDP_AUXP AF4 EDP_AUX PEG_TX_12* M10 NC_PEG_R2D_CN<12> 91

PEG_TX_13* F10 NC_PEG_R2D_CN<13> 91

91 NC_EDP_TXN<0> AC3 EDP_TX_0*
PEG_TX_14* D9 NC_PEG_R2D_CN<14> 91 NOTE: Intel is investigating future processor VREF_DQ generation to replace M1 and M2.
91 NC_EDP_TXN<1> AC4 EDP_TX_1*
PEG_TX_15* J4 NC_PEG_R2D_CN<15> 91 This would require routing processor signal balls BE7 and BG7 for Sandy Bridge 2-core
91 NC_EDP_TXN<2> AE11 EDP_TX_2*
to SO-DIMM connectors directly. FETs are needed in order to avoid potential leakage while system is in S3 state.
91 NC_EDP_TXN<3> AE7 EDP_TX_3* PEG_TX_0 F22 =PEG_R2D_C_P<0> OUT 8
A23 =PEG_R2D_C_P<1> NOSTUFF
PEG_TX_1 OUT 8
91 NC_EDP_TXP<0> AC1 EDP_TX_0 R1021
PEG_TX_2 D24 =PEG_R2D_C_P<2> OUT 8
91 NC_EDP_TXP<1> AA4 EDP_TX_1 0
PEG_TX_3 E21 =PEG_R2D_C_P<3> OUT 8 33 30 PP0V75_S3_MEM_VREFDQ_A 1 2 CPU_MEM_VREFDQ_A 10
91 NC_EDP_TXP<2> AE10 EDP_TX_2
B 91 NC_EDP_TXP<3> AE6 EDP_TX_3
PEG_TX_4
PEG_TX_5
G19
B18
=PEG_R2D_C_P<4>
=PEG_R2D_C_P<5>
OUT
OUT
8

8
5%
1/16W
MF-LF
1 NOSTUFF
R1020 B
K17 =PEG_R2D_C_P<6>
402 1K
Intel Doc 438297 Huron River SFF DG rev1.0 section 2.2.1 recommendation. PEG_TX_6 OUT 8 1%
1/16W
PEG_TX_7 G17 =PEG_R2D_C_P<7> OUT 8 MF-LF
NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating
even if internal Graphics is disabled since they are PEG_TX_8 E14 =PCIE_T29_R2D_C_P<0> 8
2 402
OUT
shared with other interfaces.
PEG_TX_9 C15 =PCIE_T29_R2D_C_P<1> OUT 8 NOSTUFF
PEG_TX_10 K13 =PCIE_T29_R2D_C_P<2> OUT 8
R1023
0
NOTE: The EDP_HPD processor input is a low voltage active low signal. PEG_TX_11 G13 =PCIE_T29_R2D_C_P<3> OUT 8 33 31 PP0V75_S3_MEM_VREFDQ_B 1 2 CPU_MEM_VREFDQ_B 10
Therefore, an inverting level shifter is required on the motherboard
to convert the active high signal from Embedded DisplayPort sink device PEG_TX_12 K10 NC_PEG_R2D_CP<12> 91 5% 1 NOSTUFF
to low voltage signals for the processor
(refer to latest Processor EDS for DC specifications). PEG_TX_13 G10 NC_PEG_R2D_CP<13> 91
1/16W
MF-LF R1022
402 1K
If HPD is disabled while eDP interface is still enabled, PEG_TX_14 D8 NC_PEG_R2D_CP<14> 91 1%
connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard. 1/16W
This signal can be left as no-connect if entire eDP interface is disabled. PEG_TX_15 K4 NC_PEG_R2D_CP<15> 91 MF-LF
2 402

81 10 CPU_CFG<16>
81 10 CPU_CFG<7>
81 10 CPU_CFG<6> 81 10 CPU_CFG<3>
81 10 CPU_CFG<5> 81 10 CPU_CFG<1>
81 10 CPU_CFG<4> 81 24 10 CPU_CFG<0>

81 10 CPU_CFG<2>
NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
R10421 R10441 R10451 R10461 R10471 R10401 R10411 R10431 R10491
1K 1K 1K 1K 1K 1K 1K 1K 1K
5% 5% 5% 5% 5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
A MF-LF
402 2
MF-LF
402 2
MF-LF
402 2
MF-LF
402 2
MF-LF
402 2
MF-LF
402 2
MF-LF
402 2
MF-LF
402 2
MF-LF
402 2 A
PAGE TITLE

CPU DMI/PEG/FDI/RSVD
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION DRAWING NUMBER SIZE
These can be Placed close to J2500 and Only for debug access

337S4034 1 SNB,SR071,PRQ,J1,2.3,35W,2+2,1.30,3M,BGA U1000 CRITICAL CPU:PRQ_2G3DC Apple Inc. 051-8768 D

REVISION
FOR SANDYBRIDGE PROCESSOR R
337S4035 1 SNB,SR04A,PRQ,J1,2.5,35W,2+2,1.30,3M,BGA U1000 CRITICAL CPU:PRQ_2G5DC 9.0.0
CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS NOTICE OF PROPRIETARY PROPERTY: BRANCH
337S4036 1 SNB,SR041,PRQ,J1,2.7,35W,2+2,1.30,4M,BGA U1000 CRITICAL CPU:PRQ_2G7DC
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED THE POSESSOR AGREES TO THE FOLLOWING: PAGE
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
10 OF 512
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 10 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

15 13 PP1V05_S0_VCCQ

91 67 15 13 11 10 7 PP1V05_S0_VCCIO OMIT_TABLE
CRITICAL
1
R1140
NOSTUFF NOSTUFF NOSTUFF
U1000 1K
5%
1 1 1 SANDY-BRIDGE 1/16W
R1100 R1104 R1102 MOBILE-2C-35W
MF-LF
2 402
1K 51 1K
R11011 5%
1/16W
5%
1/16W
5%
1/16W
BGA
(2 OF 9)
BCLK J3 DMI_CLK100M_CPU_P IN 17 81

60.4 MF-LF MF-LF MF-LF BCLK* H2 DMI_CLK100M_CPU_N IN 17 81

1% 402 2 2 402 2 402
1/16W
MF-LF C57 PROC_DETECT* DPLL_REF_CLK AG3 DPLL_REF_CLKP
402 2 NC Unused eDP CLK
DPLL_REF_CLK* AG1 DPLL_REF_CLKN

CLOCKS
81 18 OUT CPU_PROC_SEL_L F49 PROC_SELECT*
BCLK_ITP N59 ITPCPU_CLK100M_P IN 17 81
1
C 81 6 CPU_CATERR_L C49 CATERR*
BCLK_ITP* N58 ITPCPU_CLK100M_N IN 17 81
R1141
1K
5%
C
OUT
1/16W
(IPU) PRDY* N53 XDP_CPU_PRDY_L OUT 24 81 MF-LF
81 46 20 CPU_PECI A48 PECI (IPU) PREQ* N55 XDP_CPU_PREQ_L 24 81
2 402
BI IN
R1103

THERMAL
56.2 1
81 67 47 BI CPU_PROCHOT_L 2 CPU_PROCHOT_R_L C45 PROCHOT* (IPU) TCK L56 XDP_CPU_TCK IN 24 81

1% (IPU) TMS L55 XDP_CPU_TMS IN 24 81

PP1V5_VDDQ_CPU 1/16W
62 50 32 31 28 16 13 7 MF-LF 81 20 OUT PM_THRMTRIP_L D45 THERMTRIP* (IPU) TRST* J58 XDP_CPU_TRST_L IN 24 81
402
1
R1120 (IPU) TDI M60 XDP_CPU_TDI
200 81 18 PM_SYNC C48 PM_SYNC IN 24 81
1% IN XDP_CPU_TDO
1/16W TDO L59 OUT 24 81
MF-LF CPU_PWRGD B46 UNCOREPWRGOOD
R1121 81 24 20 IN

PWR MGMT
402 2

JTAG & BPM

130 DBR* K58 XDP_DBRESET_L OUT 24 27 81
81 28 18 IN PM_MEM_PWRGD 2 1 PM_MEM_PWRGD_R BE45 SM_DRAMPWROK
1%
1/16W PLT_RESET_LS1V1_L D44 RESET* (IPU) BPM_0* G58 XDP_BPM_L<0> BI 24 81
MF-LF
402 (IPU) BPM_1* E55 XDP_BPM_L<1> BI 24 81

28 OUT CPU_MEM_RESET_L AT30 SM_DRAMRST* (IPU) BPM_2* E59 XDP_BPM_L<2> BI 24 81

DDR3 MISC
(IPU) BPM_3* G55 XDP_BPM_L<3> BI 24 81
81 CPU_SM_RCOMP<0> BF44 SM_RCOMP_0
(IPU) BPM_4* G59 XDP_BPM_L<4> BI 24 81
81 CPU_SM_RCOMP<1> BE43 SM_RCOMP_1
(IPU) BPM_5* H60 XDP_BPM_L<5> BI 24 81
81 CPU_SM_RCOMP<2> BG43 SM_RCOMP_2
(IPU) BPM_6* J59 XDP_BPM_L<6> BI 24 81

(IPU) BPM_7* J61 XDP_BPM_L<7> BI 24 81

91 67 15 13 11 10 7
PP1V05_S0_VCCIO

R11121 1
R1113 1
R1114 1
R1111
B R11261
75
140
1%
1/16W
25.5
1%
1/16W
1%
200
1/16W
10K
5%
1/16W
B
1% MF-LF MF-LF MF-LF MF-LF
1/16W 402 2 2 402 2 402 2 402
MF-LF
402 2 R1125
43.2 1
27 24 IN CPU_RESET_L 2
1%
1/16W
MF-LF
402

www.teknisi-indonesia.com

A A
PAGE TITLE

CPU CLOCK/MISC/JTAG
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
11 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 11 OF 104

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

OMIT_TABLE OMIT_TABLE
CRITICAL CRITICAL
82 29 BI MEM_A_DQ<0> AG6 SA_DQ_0 U1000 SA_CK_0 AU36 MEM_A_CLK_P<0> OUT 30 82 82 29 BI MEM_B_DQ<0> AL4 SB_DQ_0 U1000 SB_CK_0 BA34 MEM_B_CLK_P<0> OUT 31 82

82 29 MEM_A_DQ<1> AJ6 SA_DQ_1 BGA SA_CK_0* AV36 MEM_A_CLK_N<0> 30 82 82 29 MEM_B_DQ<1> AL1 SB_DQ_1 BGA SB_CK_0* AY34 MEM_B_CLK_N<0> 31 82
BI OUT BI OUT
(3 OF 9) (4 OF 9)
82 29 BI MEM_A_DQ<2> AP11 SA_DQ_2 82 29 BI MEM_B_DQ<2> AN3 SB_DQ_2
SA_CKE_0 AY26 MEM_A_CKE<0> 30 82 SB_CKE_0 AR22 MEM_B_CKE<0> 31 82

MOBILE-2C-35W

SANDY-BRIDGE
MOBILE-2C-35W
MEM_A_DQ<3> AL6 OUT MEM_B_DQ<3> AR4 OUT

SANDY-BRIDGE
82 29 BI SA_DQ_3 82 29 BI SB_DQ_3

D 82 29

82 29
BI
BI
MEM_A_DQ<4>
MEM_A_DQ<5>
AJ10
AJ8
SA_DQ_4
SA_DQ_5
SA_CK_1 AT40 MEM_A_CLK_P<1> OUT 30 82
82 29

82 29
BI
BI
MEM_B_DQ<4>
MEM_B_DQ<5>
AK4
AK3
SB_DQ_4
SB_DQ_5
SB_CK_1 BA36 MEM_B_CLK_P<1> OUT 31 82 D
SA_CK_1* AU40 MEM_A_CLK_N<1> OUT 30 82 SB_CK_1* BB36 MEM_B_CLK_N<1> OUT 31 82
82 29 BI MEM_A_DQ<6> AL8 SA_DQ_6 82 29 BI MEM_B_DQ<6> AN4 SB_DQ_6
82 29 BI MEM_A_DQ<7> AL7 SA_DQ_7 SA_CKE_1 BB26 MEM_A_CKE<1> OUT 30 82 82 29 BI MEM_B_DQ<7> AR1 SB_DQ_7 SB_CKE_1 BF27 MEM_B_CKE<1> OUT 31 82

82 29 BI MEM_A_DQ<8> AR11 SA_DQ_8 82 29 BI MEM_B_DQ<8> AU4 SB_DQ_8

82 29 BI MEM_A_DQ<9> AP6 SA_DQ_9 SA_CS_0* BB40 MEM_A_CS_L<0> OUT 30 82 82 29 BI MEM_B_DQ<9> AT2 SB_DQ_9 SB_CS_0* BE41 MEM_B_CS_L<0> OUT 31 82

82 29 BI MEM_A_DQ<10> AU6 SA_DQ_10 SA_CS_1* BC41 MEM_A_CS_L<1> OUT 30 82 82 29 BI MEM_B_DQ<10> AV4 SB_DQ_10 SB_CS_1* BE47 MEM_B_CS_L<1> OUT 31 82

82 29 BI MEM_A_DQ<11> AV9 SA_DQ_11 82 29 BI MEM_B_DQ<11> BA4 SB_DQ_11

82 29 BI MEM_A_DQ<12> AR6 SA_DQ_12 SA_ODT_0 AY40 MEM_A_ODT<0> OUT 30 82 82 29 BI MEM_B_DQ<12> AU3 SB_DQ_12 SB_ODT_0 AT43 MEM_B_ODT<0> OUT 31 82

82 29 BI MEM_A_DQ<13> AP8 SA_DQ_13 SA_ODT_1 BA41 MEM_A_ODT<1> OUT 30 82 82 29 BI MEM_B_DQ<13> AR3 SB_DQ_13 SB_ODT_1 BG47 MEM_B_ODT<1> OUT 31 82

MEMORY CHANNEL B
82 29 BI MEM_A_DQ<14> AT13 SA_DQ_14 82 29 BI MEM_B_DQ<14> AY2 SB_DQ_14
82 29 BI MEM_A_DQ<15> AU13 SA_DQ_15 SA_DQS_0* AL11 MEM_A_DQS_N<0> BI 29 82 82 29 BI MEM_B_DQ<15> BA3 SB_DQ_15 SB_DQS_0* AL3 MEM_B_DQS_N<0> BI 29 82

82 29 BI MEM_A_DQ<16> BC7 SA_DQ_16 SA_DQS_1* AR8 MEM_A_DQS_N<1> BI 29 82 82 29 BI MEM_B_DQ<16> BE9 SB_DQ_16 SB_DQS_1* AV3 MEM_B_DQS_N<1> BI 29 82

82 29 BI MEM_A_DQ<17> BB7 SA_DQ_17 SA_DQS_2* AV11 MEM_A_DQS_N<2> BI 29 82 82 29 BI MEM_B_DQ<17> BD9 SB_DQ_17 SB_DQS_2* BG11 MEM_B_DQS_N<2> BI 29 82

82 29 BI MEM_A_DQ<18> BA13 SA_DQ_18 SA_DQS_3* AT17 MEM_A_DQS_N<3> BI 29 82 82 29 BI MEM_B_DQ<18> BD13 SB_DQ_18 SB_DQS_3* BD17 MEM_B_DQS_N<3> BI 29 82

82 29 BI MEM_A_DQ<19> BB11 SA_DQ_19 SA_DQS_4* AV45 MEM_A_DQS_N<4> BI 29 82 82 29 BI MEM_B_DQ<19> BF12 SB_DQ_19 SB_DQS_4* BG51 MEM_B_DQS_N<4> BI 29 82

82 29 BI MEM_A_DQ<20> BA7 SA_DQ_20 SA_DQS_5* AY51 MEM_A_DQS_N<5> BI 29 82 82 29 BI MEM_B_DQ<20> BF8 SB_DQ_20 SB_DQS_5* BA59 MEM_B_DQS_N<5> BI 29 82

82 29 BI MEM_A_DQ<21> BA9 SA_DQ_21 SA_DQS_6* AT55 MEM_A_DQS_N<6> BI 29 82 82 29 BI MEM_B_DQ<21> BD10 SB_DQ_21 SB_DQS_6* AT60 MEM_B_DQS_N<6> BI 29 82

MEMORY CHANNEL A
82 29 BI MEM_A_DQ<22> BB9 SA_DQ_22 SA_DQS_7* AK55 MEM_A_DQS_N<7> BI 29 82 82 29 BI MEM_B_DQ<22> BD14 SB_DQ_22 SB_DQS_7* AK59 MEM_B_DQS_N<7> BI 29 82

82 29 BI MEM_A_DQ<23> AY13 SA_DQ_23 82 29 BI MEM_B_DQ<23> BE13 SB_DQ_23

82 29 BI MEM_A_DQ<24> AV14 SA_DQ_24 SA_DQS_0 AJ11 MEM_A_DQS_P<0> BI 29 82 82 29 BI MEM_B_DQ<24> BF16 SB_DQ_24 SB_DQS_0 AM2 MEM_B_DQS_P<0> BI 29 82

82 29 BI MEM_A_DQ<25> AR14 SA_DQ_25 SA_DQS_1 AR10 MEM_A_DQS_P<1> BI 29 82 82 29 BI MEM_B_DQ<25> BE17 SB_DQ_25 SB_DQS_1 AV1 MEM_B_DQS_P<1> BI 29 82

82 29 BI MEM_A_DQ<26> AY17 SA_DQ_26 SA_DQS_2 AY11 MEM_A_DQS_P<2> BI 29 82 82 29 BI MEM_B_DQ<26> BE18 SB_DQ_26 SB_DQS_2 BE11 MEM_B_DQS_P<2> BI 29 82

82 29 BI MEM_A_DQ<27> AR19 SA_DQ_27 SA_DQS_3 AU17 MEM_A_DQS_P<3> BI 29 82 82 29 BI MEM_B_DQ<27> BE21 SB_DQ_27 SB_DQS_3 BD18 MEM_B_DQS_P<3> BI 29 82

82 29 BI MEM_A_DQ<28> BA14 SA_DQ_28 SA_DQS_4 AW45 MEM_A_DQS_P<4> BI 29 82 82 29 BI MEM_B_DQ<28> BE14 SB_DQ_28 SB_DQS_4 BE51 MEM_B_DQS_P<4> BI 29 82

82 29 BI MEM_A_DQ<29> AU14 SA_DQ_29 SA_DQS_5 AV51 MEM_A_DQS_P<5> BI 29 82 82 29 BI MEM_B_DQ<29> BG14 SB_DQ_29 SB_DQS_5 BA61 MEM_B_DQS_P<5> BI 29 82

82 29 BI MEM_A_DQ<30> BB14 SA_DQ_30 SA_DQS_6 AT56 MEM_A_DQS_P<6> BI 29 82 82 29 BI MEM_B_DQ<30> BG18 SB_DQ_30 SB_DQS_6 AR59 MEM_B_DQS_P<6> BI 29 82

C 82 29

82 29
BI MEM_A_DQ<31>
MEM_A_DQ<32>
BB17
BA45
SA_DQ_31
SA_DQ_32
SA_DQS_7 AK54 MEM_A_DQS_P<7> BI 29 82 82 29

82 29
BI MEM_B_DQ<31>
MEM_B_DQ<32>
BF19
BD50
SB_DQ_31
SB_DQ_32
SB_DQS_7 AK61 MEM_B_DQS_P<7> BI 29 82 C
BI BI
82 29 BI MEM_A_DQ<33> AR43 SA_DQ_33 SA_MA_0 BG35 MEM_A_A<0> OUT 30 82 82 29 BI MEM_B_DQ<33> BF48 SB_DQ_33 SB_MA_0 BF32 MEM_B_A<0> OUT 31 82

82 29 BI MEM_A_DQ<34> AW48 SA_DQ_34 SA_MA_1 BB34 MEM_A_A<1> OUT 30 82 82 29 BI MEM_B_DQ<34> BD53 SB_DQ_34 SB_MA_1 BE33 MEM_B_A<1> OUT 31 82

82 29 BI MEM_A_DQ<35> BC48 SA_DQ_35 SA_MA_2 BE35 MEM_A_A<2> OUT 30 82 82 29 BI MEM_B_DQ<35> BF52 SB_DQ_35 SB_MA_2 BD33 MEM_B_A<2> OUT 31 82

82 29 BI MEM_A_DQ<36> BC45 SA_DQ_36 SA_MA_3 BD35 MEM_A_A<3> OUT 30 82 82 29 BI MEM_B_DQ<36> BD49 SB_DQ_36 SB_MA_3 AU30 MEM_B_A<3> OUT 31 82

82 29 BI MEM_A_DQ<37> AR45 SA_DQ_37 SA_MA_4 AT34 MEM_A_A<4> OUT 30 82 82 29 BI MEM_B_DQ<37> BE49 SB_DQ_37 SB_MA_4 BD30 MEM_B_A<4> OUT 31 82

82 29 BI MEM_A_DQ<38> AT48 SA_DQ_38 SA_MA_5 AU34 MEM_A_A<5> OUT 30 82 82 29 BI MEM_B_DQ<38> BD54 SB_DQ_38 SB_MA_5 AV30 MEM_B_A<5> OUT 31 82

82 29 BI MEM_A_DQ<39> AY48 SA_DQ_39 SA_MA_6 BB32 MEM_A_A<6> OUT 30 82 82 29 BI MEM_B_DQ<39> BE53 SB_DQ_39 SB_MA_6 BG30 MEM_B_A<6> OUT 31 82

82 29 BI MEM_A_DQ<40> BA49 SA_DQ_40 SA_MA_7 AT32 MEM_A_A<7> OUT 30 82 82 29 BI MEM_B_DQ<40> BF56 SB_DQ_40 SB_MA_7 BD29 MEM_B_A<7> OUT 31 82

82 29 BI MEM_A_DQ<41> AV49 SA_DQ_41 SA_MA_8 AY32 MEM_A_A<8> OUT 30 82 82 29 BI MEM_B_DQ<41> BE57 SB_DQ_41 SB_MA_8 BE30 MEM_B_A<8> OUT 31 82

82 29 BI MEM_A_DQ<42> BB51 SA_DQ_42 SA_MA_9 AV32 MEM_A_A<9> OUT 30 82 82 29 BI MEM_B_DQ<42> BC59 SB_DQ_42 SB_MA_9 BE28 MEM_B_A<9> OUT 31 82

82 29 BI MEM_A_DQ<43> AY53 SA_DQ_43 SA_MA_10 BE37 MEM_A_A<10> OUT 30 82 82 29 BI MEM_B_DQ<43> AY60 SB_DQ_43 SB_MA_10 BD43 MEM_B_A<10> OUT 31 82

82 29 BI MEM_A_DQ<44> BB49 SA_DQ_44 SA_MA_11 BA30 MEM_A_A<11> OUT 30 82 82 29 BI MEM_B_DQ<44> BE54 SB_DQ_44 SB_MA_11 AT28 MEM_B_A<11> OUT 31 82

82 29 BI MEM_A_DQ<45> AU49 SA_DQ_45 SA_MA_12 BC30 MEM_A_A<12> OUT 30 82 82 29 BI MEM_B_DQ<45> BG54 SB_DQ_45 SB_MA_12 AV28 MEM_B_A<12> OUT 31 82

82 29 BI MEM_A_DQ<46> BA53 SA_DQ_46 SA_MA_13 AW41 MEM_A_A<13> OUT 30 82 82 29 BI MEM_B_DQ<46> BA58 SB_DQ_46 SB_MA_13 BD46 MEM_B_A<13> OUT 31 82

82 29 BI MEM_A_DQ<47> BB55 SA_DQ_47 SA_MA_14 AY28 MEM_A_A<14> OUT 30 82 82 29 BI MEM_B_DQ<47> AW59 SB_DQ_47 SB_MA_14 AT26 MEM_B_A<14> OUT 31 82

82 29 BI MEM_A_DQ<48> BA55 SA_DQ_48 SA_MA_15 AU26 MEM_A_A<15> OUT 30 82 82 29 BI MEM_B_DQ<48> AW58 SB_DQ_48 SB_MA_15 AU22 MEM_B_A<15> OUT 31 82

82 29 BI MEM_A_DQ<49> AV56 SA_DQ_49 82 29 BI MEM_B_DQ<49> AU58 SB_DQ_49

82 29 BI MEM_A_DQ<50> AP50 SA_DQ_50 82 29 BI MEM_B_DQ<50> AN61 SB_DQ_50
82 29 BI MEM_A_DQ<51> AP53 SA_DQ_51 82 29 BI MEM_B_DQ<51> AN59 SB_DQ_51
82 29 BI MEM_A_DQ<52> AV54 SA_DQ_52 82 29 BI MEM_B_DQ<52> AU59 SB_DQ_52
82 29 BI MEM_A_DQ<53> AT54 SA_DQ_53 82 29 BI MEM_B_DQ<53> AU61 SB_DQ_53
82 29 BI MEM_A_DQ<54> AP56 SA_DQ_54 82 29 BI MEM_B_DQ<54> AN58 SB_DQ_54
82 29 BI MEM_A_DQ<55> AP52 SA_DQ_55 82 29 BI MEM_B_DQ<55> AR58 SB_DQ_55
82 29 BI MEM_A_DQ<56> AN57 SA_DQ_56 82 29 BI MEM_B_DQ<56> AK58 SB_DQ_56

B 82 29

82 29
BI
BI
MEM_A_DQ<57>
MEM_A_DQ<58>
AN53
AG56
SA_DQ_57
SA_DQ_58
82 29

82 29
BI
BI
MEM_B_DQ<57>
MEM_B_DQ<58>
AL58
AG58
SB_DQ_57
SB_DQ_58
B
82 29 BI MEM_A_DQ<59> AG53 SA_DQ_59 82 29 BI MEM_B_DQ<59> AG59 SB_DQ_59
82 29 BI MEM_A_DQ<60> AN55 SA_DQ_60 82 29 BI MEM_B_DQ<60> AM60 SB_DQ_60
82 29 BI MEM_A_DQ<61> AN52 SA_DQ_61 82 29 BI MEM_B_DQ<61> AL59 SB_DQ_61
82 29 BI MEM_A_DQ<62> AG55 SA_DQ_62 82 29 BI MEM_B_DQ<62> AF61 SB_DQ_62
82 29 BI MEM_A_DQ<63> AK56 SA_DQ_63 82 29 BI MEM_B_DQ<63> AH60 SB_DQ_63

82 30 OUT MEM_A_BA<0> BD37 SA_BS_0 82 31 OUT MEM_B_BA<0> BG39 SB_BS_0

82 30 OUT MEM_A_BA<1> BF36 SA_BS_1 82 31 OUT MEM_B_BA<1> BD42 SB_BS_1
82 30 OUT MEM_A_BA<2> BA28 SA_BS_2 82 31 OUT MEM_B_BA<2> AT22 SB_BS_2

82 30 OUT MEM_A_CAS_L BE39 SA_CAS* 82 31 OUT MEM_B_CAS_L AV43 SB_CAS*

82 30 OUT MEM_A_RAS_L BD39 SA_RAS* 82 31 OUT MEM_B_RAS_L BF40 SB_RAS*
82 30 OUT MEM_A_WE_L AT41 SA_WE* 82 31 OUT MEM_B_WE_L BD45 SB_WE*

A SYNC_DATE=11/23/2010 A
PAGE TITLE

CPU DDR3 INTERFACES

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
12 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 12 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

69 67 50 16 7
PPVAXG_S0_CPU OMIT_TABLE
CRITICAL
PPVCORE_S0_CPU OMIT_TABLE PP1V5_VDDQ_CPU
50 15 10 7
91 68 67 CRITICAL PP1V05_S0_VCCIO 7 10 11 13 15 67 91
AA46 VAXG_1 U1000 7 11 13 16 28 31 32 50
62

(NOT controlled by VCCIO_SEL)

AB47 VAXG_2 BGA
A26 VCC_1 U1000 VCCIO_1 AF46 Fixed at 1.05V AB50 VAXG_3 (7 OF 9) VDDQ_1 AJ28
D

SANDY-BRIDGE

MOBILE-2C-35W
D A29
A31
VCC_2
VCC_3 (6 OF 9)
BGA VCCIO_3
VCCIO_4
AG48
AG50
AB51
AB52
VAXG_4
VAXG_5
VDDQ_2
VDDQ_3
AJ33
AJ36
A34 AG51 AB53 AJ40

SANDY-BRIDGE
MOBILE-2C-35W
VCC_4 VCCIO_5 VAXG_6 VDDQ_4
A35 VCC_5 VCCIO_6 AJ17 AB55 VAXG_7 VDDQ_5 AL30
A38 VCC_6 VCCIO_7 AJ21 AB56 VAXG_8 VDDQ_6 AL34
A39 VCC_7 VCCIO_8 AJ25 AB58 VAXG_9 VDDQ_7 AL38
A42 VCC_8 VCCIO_9 AJ43 AB59 VAXG_10 VDDQ_8 AL42
C26 VCC_9 VCCIO_10 AJ47 AC61 VAXG_11 VDDQ_9 AM33
C27 VCC_10 VCCIO_11 AK50 AD47 VAXG_12 VDDQ_10 AM36
C32 VCC_11 VCCIO_12 AK51 AD48 VAXG_13 VDDQ_11 AM40
C34 AL14 AD50 AN30

DDR3-1.5V RAILS
VCC_12 VCCIO_13 VAXG_14 VDDQ_12
C37 VCC_13 VCCIO_14 AL15 AD51 VAXG_15 VDDQ_13 AN34
C39 AL16 AD52 AN38

GRPHICS
VCC_14 VCCIO_15 VAXG_16 VDDQ_14
C42 VCC_15 VCCIO_16 AL20 AD53 VAXG_17 VDDQ_15 AR26
D27 VCC_16 VCCIO_17 AL22 AD55 VAXG_18 VDDQ_16 AR28 PPVCCSA_S0_CPU
64 50 16 13 7
D32 VCC_17 VCCIO_18 AL26 AD56 VAXG_19 VDDQ_17 AR30
D34 VCC_18 VCCIO_19 AL45 AD58 VAXG_20 VDDQ_18 AR32
D37 VCC_19 VCCIO_20 AL48 AD59 VAXG_21 VDDQ_19 AR34
D39 VCC_20 VCCIO_21 AM16 AE46 VAXG_22 VDDQ_20 AR36
D42 VCC_21 VCCIO_22 AM17 N45 VAXG_23 VDDQ_21 AR40 R13821
E26 AM21 P47 AV41 100
VCC_22 VCCIO_23 VAXG_24 (IPU) VDDQ_22 1%
E28 AM43 P48 AW26 1/16W
VCC_23 VCCIO_24 VAXG_25 VDDQ_23 MF-LF
E32 AM47 P50 BA40 402 2
VCC_24 VCCIO_25 VAXG_26 VDDQ_24
E34 VCC_25 VCCIO_26 AN20 P51 VAXG_27 VDDQ_25 BB28
E37 VCC_26 VCCIO_27 AN42 P52 VAXG_28 VDDQ_26 BG33
E38 VCC_27 VCCIO_28 AN45 P53 VAXG_29

QUIET
PEG AND DDR

F25 AN48 P55 AM28

RAIL
PP1V5_S3_CPU_VCCDQ
C F26
VCC_28
VCC_29
VCCIO_29

VCCIO_30 AA14
P56
VAXG_30
VAXG_31
VCCDQ_1
VCCDQ_2 AN26
16
C
F28 VCC_30 P61 VAXG_32
VCCIO_31 AA15
F32 VCC_31 T48 VAXG_33 VDDQ_SENSE BC43 TP_CPU_VDDQ_SENSEP
VCCIO_32 AB17
F34 VCC_32 T58 VAXG_34 VSS_SENSE_VDDQ BA43 TP_CPU_VDDQ_SENSEN
AB20

SENSE
VCCIO_33

LINE
F37 VCC_33 T59 VAXG_35
VCCIO_34 AC13 VCCSA_SENSE U10 CPU_VCCSA_SENSE 64
F38 T61 OUT
VCC_34 AD16 VAXG_36
F42 VCCIO_35 U46
VCC_35 AD18 VAXG_37 D48 CPU_VCCSA_VID<0>
G42 VCCIO_36 V47 VCCSA_VID_0 64
VCC_36 VAXG_38
AD21 D49 CPU_VCCSA_VID<1>
CORE SUPLLY

H25 VCCIO_37 V48 (IPU) VCCSA_VID_1 OUT 64 81

VCC_37 AE14 VAXG_39
H26 VCCIO_38 V50
VCC_38 AE15 VAXG_40 AY43
H28 VCCIO_39 V51 SM_VREF CPU_DDR_VREF
VOLTAGE=0.75V 13
VCC_39 AF16 VAXG_41
H29 VCCIO_40 V52
VCC_40 AF18 VAXG_42
H32 VCCIO_41 V53
VCC_41 AF20 VAXG_43
H34 VCCIO_42 V55
VCC_42 AG15 VAXG_44
H35 VCCIO_43 V56
H37
VCC_43
VCCIO_44 AG16
V58
VAXG_45 R13141 1
R1313
VCC_44 AG17 VAXG_46 10K 10K
H38 VCCIO_45 PP3V3_S0 51 52 53 57 58 60 61 62 67 71 V59 5% 5%
VCC_45 AG20 6 7 17 18 19 20 21 23 24 27 30 VAXG_47 1/16W 1/16W
H40 VCCIO_46 31 34 37 38 39 40 41 47 49 50
72 73 74 76 77 79 89 91 W50 MF-LF MF-LF
VCC_46 AG21 VAXG_48 402 2 2 402
J25 VCCIO_47 1 W51
VCC_47 AJ14 R1320 PP1V05_S0_VCCIO 7 10 11 13 15 67 91 VAXG_49
J26 VCCIO_48 W52
VCC_48 AJ15 10K VAXG_50
J28 VCCIO_49 5% PLACE_NEAR=R1310.2:2.54mm W53
VCC_49 1/16W 1 1 VAXG_51
J29 VCC_50 VCCIO_50 W16 MF-LF
2 402
R1302 R1300 W55 VAXG_52
J32 W17 130PLACE_NEAR=U1000.C44:2.54mm 75 W56
VCC_51 VCCIO_51 1% 1% VAXG_53
J34 1/16W 1/16W W61 PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.
VCC_52 For Future Compatibility MF-LF MF-LF VAXG_54
J35 BC22 2 402
43.2 2 402 Y48
VCC_53 VCCIO_SEL CPU_VCCIO_SEL R1310 VAXG_55
J37 VCC_54 4021/16W 1 2 1%MF-LF CPU_VIDALERT_L 67 81
Y61 VAXG_56
B J38 AM25 PP1V05_S0_VCCQ
IN
B
QUIET

VCC_55 VCCPQE_1 PP1V5_VDDQ_CPU

RAIL

11 15 PLACE_NEAR=U1000.A44:38mm
62 50 32 31 28 16 13 11 7
J40 AN22 F45 VAXG_SENSE

SENSE
VCC_56 VCCPQE_2 R1311 CPU_AXG_SENSE_P

LINE
81 67 OUT Note. VOLTAGE=1.05V
J42 4021/16W 0 1 2 CPU_VIDSCLK G45 VSSAXG_SENSE NOSTUFF 1
VCC_57 5%MF-LF OUT 67 81 81 67 OUT CPU_AXG_SENSE_N
Note. VOLTAGE=0V
R1330
K26 VCC_58 VIDALERT* A44 81 CPU_VIDALERT_L_R 100
SVID

PLACE_NEAR=U1000.BJ44:2.54mm 5%
K27 VCC_59 VIDSCLK B43 81 CPU_VIDSCLK_R R1312 15 7 PP1V8_S0_CPU_VCCPLL_R BB3 VCCPLL_1 1/16W

1.8V
RAIL
MF-LF
K29 VCC_60 VIDSOUT C44 81 CPU_VIDSOUT_R 4021/16W 0 1 2 5%MF-LF CPU_VIDSOUT BI 67 81
BC1 VCCPLL_2 402 2
K32 VCC_61 BC4 VCCPLL_3
K34 F43 CPU_DDR_VREF 13
VCC_62 VCC_SENSE CPU_VCCSENSE_P 64 50 16 13 7 PPVCCSA_S0_CPU
SENSE
LINES

K35 G43 L17 NOSTUFF 1 NOSTUFF

VCC_63 VSS_SENSE CPU_VCCSENSE_N VCCSA_1 R1331
K37 VCC_64
PP1V05_S0_VCCIO 7 10 11 13 15 67 91
L21 VCCSA_2 100
1 C1330
VCCIO_SENSE AN16 CPU_VCCIOSENSE_P
PLACE_NEAR=U1000.BJ44:2.54mm
5% 0.1UF
K39 VCC_66 N16 VCCSA_3 1/16W 10%
AN17 16V
K42 VSS_SENSE_VCCIO CPU_VCCIOSENSE_N NOSTUFF N20 MF-LF 2 X7R-CERM
VCC_67 1 VCCSA_4 402 2 402
L25 VCC_68 R1362 N22 VCCSA_5
L28 100 PLACE_NEAR=U1000.AN16:50.8mm
P17

SA RAIL
VCC_69 1% PLACE_SIDE=BOTTOM VCCSA_6
L33 1/16W P20
VCC_70 MF-LF VCCSA_7 PLACE_NEAR=U1000.BJ44:2.54mm
L36 VCC_71 2 402 R16 VCCSA_8
PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.
L40 VCC_72 R18 VCCSA_9
Note. VOLTAGE=1.25V OUT 67 81
N26 VCC_73 R21 VCCSA_10
OUT 67 81
N30 VCC_74 Note. VOLTAGE=0V
U15 VCCSA_11
N34 VCC_75 Note. VOLTAGE=1.05V 70 81
V16 VCCSA_12
OUT
N38 VCC_76 70 81
V17 VCCSA_13
OUT
Note. VOLTAGE=0V
V18 VCCSA_14
V21 VCCSA_15
W20 VCCSA_16
NOSTUFF
1
R1363
100
A 1%
1/16W
MF-LF
PLACE_NEAR=U1000.AN17:50.8mm
PLACE_SIDE=BOTTOM
SYNC_MASTER=J40I SYNC_DATE=11/23/2010 A
PAGE TITLE
2 402
CPU POWER
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side. REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
13 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 13 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

OMIT_TABLE
OMIT_TABLE CRITICAL
CRITICAL A9 VSS U1000 VSS AM34
A13 VSS BGA VSS AM38
BG13 VSS U1000 VSS M11
A17 VSS (8 OF 9) VSS AM42
BG17 VSS BGA VSS M15
(9 OF 9) A21 VSS VSS VSS AM45
BG21 VSS VSS M58

SANDY-BRIDGE
MOBILE-2C-35W
VSS A25 VSS VSS AM48
BG24 VSS VSS N1

SANDY-BRIDGE
MOBILE-2C-35W
A28 VSS VSS AM58

D
BG28
BG37
VSS
VSS
VSS
VSS
N17
N21
A33
A37
VSS VSS AN1
AN21
D
BG41 N25 VSS VSS
VSS VSS A40 AN25
BG45 N28 VSS VSS
VSS VSS A45 AN28
BG49 N33 VSS VSS
VSS VSS A49 AN33
BG53 N36 VSS VSS
VSS VSS A53 AN36
C29 N40 VSS VSS
VSS VSS AA1 AN40
C35 N43 VSS VSS
VSS VSS AA8 AN43
C40 N47 VSS VSS
VSS VSS AA13 AN47
D4 N48 VSS VSS
VSS VSS AA50 AN50
D6 N51 VSS VSS
VSS VSS AA51 AN54
D10 N52 VSS VSS
VSS VSS AA52 AP7
D14 N56 VSS VSS
VSS VSS AA53 AP10
D18 N61 VSS VSS
VSS VSS AA55 AP51
D22 P9 VSS VSS
VSS VSS AA56 AP55
D26 P14 VSS VSS
VSS VSS AB16 AR7
D29 P16 VSS VSS
VSS VSS AB18 AR13
D35 P18 VSS VSS
VSS VSS AB21 AR17
D40 P21 VSS VSS
VSS VSS AB48 AR21
D43 P58 VSS VSS
VSS VSS AB61 AR41
D46 P59 VSS VSS
VSS VSS AC6 AR48
D50 R4 VSS VSS
VSS VSS AC10 AR61
D54 R17 VSS VSS
VSS VSS AC14 AT4
D58 R20 VSS VSS
VSS VSS AC46 AT14
E3 R46 VSS VSS
VSS VSS AD4 AT19
E25 T1 VSS VSS
VSS VSS AD17 AT36
E29 T47 VSS VSS
VSS VSS AD20 AT45
C E35
E40
VSS
VSS
VSS
VSS
T50
T51
AD61
VSS
VSS
VSS
VSS AT52
www.teknisi-indonesia.com
C
AE8 VSS VSS AT58
F13 VSS VSS T52
AE13 VSS VSS AU1
F15 VSS VSS T53
AF1 VSS VSS AU7
F19 VSS VSS T55
AF17 VSS VSS AU11
F29 VSS VSS T56
AF21 VSS VSS AU28
F35 VSS VSS U8
AF47 VSS VSS AU32
F40 VSS VSS U13
AF48 VSS VSS AU51
F55 VSS VSS V20
AF50 VSS VSS AV17
G6 VSS VSS V61
AF51 VSS VSS AV21
G48 VSS VSS W8
AF52 VSS VSS AV22
G51 VSS VSS W13
AF53 VSS VSS AV34
G61 VSS VSS W15
AF55 VSS VSS AV40
H4 VSS VSS W18
AF56 VSS VSS AV48
H10 VSS VSS W21
AF58 VSS VSS AV55
H14 VSS VSS W46
AF59 VSS VSS AW7
H17 VSS VSS Y4
AG7 VSS VSS AW13
H21 VSS VSS Y47
AG10 VSS VSS AW43
H53 VSS VSS Y58
AG14 VSS VSS AW61
H58 VSS VSS Y59
AG18 VSS VSS AY4
J1 VSS AG47 VSS VSS AY9
J49 VSS AG52 VSS VSS AY14
J55 VSS AG61 VSS VSS AY19
K8 VSS AH4 VSS VSS AY30
K11 VSS AH58 VSS VSS AY36
K21 VSS VSS_NCTF A5
AJ7 VSS VSS AY41
B K51
L16
VSS
VSS
VSS_NCTF
VSS_NCTF
A57
BC61
AJ13
AJ16
VSS VSS AY45
AY49
B
L20 BD3 VSS VSS
VSS VSS_NCTF AJ20 AY55
L22 BD59 VSS VSS
VSS VSS_NCTF AJ22 AY58
L26 BE4 VSS VSS
VSS VSS_NCTF AJ26 BA1
L30 BE58 VSS VSS
VSS VSS_NCTF AJ30 BA11
L34 BG5 VSS VSS
VSS VSS_NCTF AJ34 BA17
L38 BG57 VSS VSS
VSS VSS_NCTF AJ38 BA21
L43 C3 VSS VSS
VSS VSS_NCTF AJ42 BA26
L48 C58 VSS VSS
VSS VSS_NCTF AJ45 BA32
L61 D59 VSS VSS
VSS VSS_NCTF AJ48 BA48
M4 E1 VSS VSS
VSS VSS_NCTF AK1 BA51
M6 E61 VSS VSS
VSS VSS_NCTF AK52 BB53
VSS VSS
AL10 VSS VSS BC5
AL13 VSS VSS BC13
AL17 VSS VSS BC57
AL21 VSS VSS BD8
AL25 VSS VSS BD12
AL28 VSS VSS BD16
AL33 VSS VSS BD19
AL36 VSS VSS BD23
AL40 VSS VSS BD27
AL43 VSS VSS BD32
AL47 VSS VSS BD36
AL61 VSS VSS BD40
AM4 BD44
A AM13
VSS
VSS
VSS
VSS BD48 A
AM20 VSS VSS BD52 PAGE TITLE
AM22 VSS VSS BD56 CPU GROUNDS
AM26 VSS VSS BE5 DRAWING NUMBER SIZE
AM30 VSS VSS BG9
Apple Inc. 051-8768 D
REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
14 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 14 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide

CPU VCORE DECOUPLING

Intel recommendation (Section 6.2): 35x 2.2uF, 25x 22uF, 4x 470uF

91 68 67 50 13 10 7 PPVCORE_S0_CPU
NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
1 C1600 1 C1601 1 C1602 1 C1603 1 C1604 1 C1605 1 C1606 1 C1607 1 C1608 1 C1609 1 C1610 1 C1611 1 C1612 1 C1613 1 C1614 1 C1615 1 C1616 1 C1617 1 C1618 1 C1619 1 C1620 1 C1621 1 C1622 1 C1623 1 C1624
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM

D
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
D
NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
1 C1625 1 C1626 1 C1627 1 C1628 1 C1629 1 C1630 1 C1631 1 C1632 1 C1633 1 C1634 1 C1635 1 C1636 1 C1637 1 C1638 1 C1639 1 C1640 1 C1641 1 C1642 1 C1643 1 C1644 1 C1645 1 C1646 1 C1647 1 C1648 1 C1649
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF

1 C1650 1 C1651 1 C1652 1 C1653 1 C1654

2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF 402-LF 402-LF 402-LF

PLACEMENT_NOTE (C1655-C1666):

Place close to U1000 on top side.

1 C1655 1 C1656 1 C1657 1 C1658 1 C1659 1 C1660 1 C1661 1 C1662 1 C1663 1 C1664 1 C1665 1 C1666
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1 2 6.3V 6.3V
X5R-CERM1 2 X5R-CERM1 2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603

C PLACEMENT_NOTE (C1667-C1679):

Place close to U1000 on bottom side.

C
1 C1667 1 C1668 1 C1669 1 C1670 1 C1671 1 C1672 1 C1673 1 C1674 1 C1675 1 C1676 1 C1677 1 C1678 1 C1679
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1 2 6.3V 6.3V
X5R-CERM1 2 X5R-CERM1 2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603

CPU VCCIO/VCCPQ DECOUPLING

Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF CPU VCCPLL DECOUPLING
PLACEMENT_NOTE (C1684-C167F): Intel recommendation (section 6.4): 2x 1uF, 1x 330uF

PLACEMENT_NOTE (C1646-C1671):
Place on bottom side of U1000
U100.
13 11 10 7
91 67
PP1V05_S0_VCCIO
Place near U1000 on top side
R1600
B 1 C1684
1UF
1 C1685
1UF
1 C1686
1UF
1 C1687
1UF
1 C1688
1UF
1 C1689
1UF
1 C1690
1UF
1 C1691
1UF
1 C1692
1UF
1 C1693
1UF
1 C1694
1UF
1 C1695
1UF
1 C1696
1UF 71 26 23 21 18 7 PP1V8_S0 1
0 2
PP1V8_S0_CPU_VCCPLL_R 7 13
B
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 5% CRITICAL
2 10V 2 10V 2 10V 10V
2 X5R 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 10V
2 X5R 2 10V 2 10V 1/16W
X5R
402-1
X5R
402-1
X5R
402-1 402-1
X5R
402-1
X5R
402-1
X5R
402-1
X5R
402-1
X5R
402-1
X5R
402-1 402-1
X5R
402-1
X5R
402-1 MF-LF
402
1 C160X 1 C160Y 1
C160Z
1UF 1UF 270UF
10% 10% 20%
2 10V
X5R 2 10V
X5R 2V
2 TANT
PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA
402-1 402-1 CASE-B4-SM
PLACE_NEAR=U1000.AK61:5mm
PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA

1 C1697 1 C1698 1 C1699 1 C169A 1 C169B 1 C169C 1 C169D 1 C169E 1 C169F 1 C161A 1 C161B 1 C161C 1 C161D CPU VCCPLL Low pass filter
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R
10V
2 X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R
402-1 402-1 402-1 402-1 402-1 402-1 402-1 402-1 402-1 402-1 402-1 402-1 402-1

PLACEMENT_NOTE (C1672-C1681):

Place near U1000 on bottom side

1 C161E 1 C161F 1 C162A 1 C162B 1 C162C 1 C162D 1 C162E 1 C167A 1 C167B 1 C167C
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V
2 X5R 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R
603 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1

A SYNC_MASTER=J40I SYNC_DATE=11/23/2010 A
PAGE TITLE
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
CRITICAL
CPU DECOUPLING-I
DRAWING NUMBER SIZE
R1601 051-8768 D
0.0102
1 PP1V05_S0_VCCQ 11 13
Apple Inc. REVISION
VOLTAGE=1.05V R
1%
1/4W 1 C167F MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
9.0.0
MF
0603 1UF MAX_NECK_LENGTH=3 MM NOTICE OF PROPRIETARY PROPERTY: BRANCH
10% THE INFORMATION CONTAINED HEREIN IS THE
2 10V
X5R PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
402-1 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
16 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 15 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

VAXG DECOUPLING
Intel recommendation (section 6.3): 21x 1uF, 6x 10uF, 6x 22uF, 2x 470uF

PLACEMENT_NOTE (C1700-C1710):
69 67 50 13 7 PPVAXG_S0_CPU
Place on bottom side of U1000
U100.

1 C1700 1 C1701 1 C1702 1 C1703 1 C1704 1 C1705 1 C1706 1 C1707 1 C1708 1 C1709 1 C1710 1 C1770 1 C1771 1 C1772 1 C1773 1 C1774 1 C1775
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 10PF 10PF 10PF 10PF 10PF 10PF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 5% 5% 5% 5% 5% 5%

D 2 10V
X5R
402-1
2 10V
X5R
402-1
2 10V
X5R
402-1
2 10V
X5R
402-1
2 10V
X5R
402-1
2 10V
X5R
402-1
2 10V
X5R
402-1
2 10V
X5R
402-1
2 10V
X5R
402-1
2 10V
X5R
402-1
10V
2 X5R
402-1
25V
2 NPO
201
25V
2 NPO
201
25V
2 NPO
201
25V
2 NPO
201
25V
2 NPO
201
25V
2 NPO
201 D
PLACEMENT_NOTE (C1711-C1716):

1 C1711 1 C1712 1 C1713 1 C1714 1 C1715 1 C1716 1 C1776 1 C1777 1 C1778 1 C1779 1 C1780 1 C1781
10UF 10UF 10UF 10UF 10UF 10UF 10PF 10PF 10PF 10PF 10PF 10PF
20% 20% 20% 20% 20% 20% 5% 5% 5% 5% 5% 5%
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
25V
2 NPO
25V
2 NPO
25V
2 NPO
25V
2 NPO
25V
2 NPO
25V
2 NPO
0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 201 201 201 201 201 201

PLACEMENT_NOTE (C1717-C1722):

1 C1717 1 C1718 1 C1719 1 C1720 1 C1721 1 C1722 1 C1782 1 C1783 1 C1784 1 C1785 1 C1786 1 C1787
22UF
20%
2 6.3V
X5R-CERM1
22UF
20%
2 6.3V
X5R-CERM1
22UF
20%
2 6.3V
X5R-CERM1
22UF
20%
2 6.3V
X5R-CERM1
20%
22UF
2 6.3V
X5R-CERM1
22UF
20%
2 6.3V
X5R-CERM1
teknisi-indonesia 5%
10PF
25V
2 NPO
5%
10PF
25V
2 NPO
5%
10PF
25V
2 NPO
5%
10PF
25V
2 NPO
5%
10PF
25V
2 NPO
10PF
5%
25V
2 NPO
0603 0603 0603 0603 0603 0603 201 201 201 201 201 201

C C

CPU VDDQ/VCCDQ DECOUPLING

Intel recommendation (Section 6.5): 10x 1uF, 8x 10uF, 1x 330uF

PLACEMENT_NOTE (C1738-C1747):

62 50 32 31 28 13 11 7 PP1V5_VDDQ_CPU
Place on bottom side of U100.
U1000
CPU VCCSA DECOUPLING
1 C1738 1 C1739 1 C1740 1 C1741 1 C1742 1 C1743 1 C1744 1 C1745 1 C1746 1 C1747 Intel recommendation (Section 6.6): 6x 1uf, 5x 10uf, 1x 330uf
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF PLACEMENT_NOTE (C1758-C1762):
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R
402-1 402-1 402-1 402-1 402-1 402-1 402-1 402-1 402-1 402-1 64 50 13 7 PPVCCSA_S0_CPU Place on bottom side of U1000
U100.

Place close to U1000 on bottom side

1 C1748 1 C1749 1 C1750 1 C1751 1 C1752 1 C1753 1 C1754 1 C1755

1 C1758 1 C1759 1 C1760 1 C1761 1 C1762
1UF 1UF 1UF 1UF 1UF
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10% 10% 10% 10% 10%
20% 20% 20% 20% 20% 20% 20% 20% 2 10V 2 10V 2 10V 2 10V 2 10V
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V X5R X5R X5R X5R X5R
B CERM-X5R
0402-1
CERM-X5R
0402-1
X5R
603
CERM-X5R
0402-1
CERM-X5R
0402-1
CERM-X5R
0402-1
X5R
603
CERM-X5R
0402-1
402-1 402-1 402-1 402-1 402-1 B
CRITICAL
1
C1756 1 C1763 1 C1764 1 C1765 1 C1766 1 C1767
270UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20%
2 2V
TANT 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
CASE-B4-SM 0402-1 0402-1 0402-1 0402-1 0402-1

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

CRITICAL
CRITICAL 1
R1702 C1768
270UF
0.0102
1
20%
PP1V5_S3_CPU_VCCDQ 13 2 2V
TANT
1% VOLTAGE=1.5V CASE-B4-SM
1/4W MIN_LINE_WIDTH=0.5 MM
MF
0603
1 C1757 MIN_NECK_WIDTH=0.2 mm
1UF
10%
10V
2 X5R
402-1

A SYNC_MASTER=J40I SYNC_DATE=11/23/2010 A
PAGE TITLE

CPU DECOUPLING-II
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
17 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 16 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
50 23 21 18 17 7 PP1V05_S0_PCH
PLACE_NEAR=U1800.Y47:2.54mm

84 LPC_R_AD<0> R1860 1 2 33 LPC_AD<0> BI 46 48 84 R18901

5%1/20W MF 201 90.9
27 IN PCH_CLK32K_RTCX1 A20 RTCX1 U1800 FWH0/LAD0 C38
84 LPC_R_AD<1> R1861 1 2 33 LPC_AD<1> BI 46 48 84
MF 1%
1/20W
PCH_CLK32K_RTCX2 C20 RTCX2 COUGAR-POINT FWH1/LAD1 A38 5%1/20W MF 201
27 OUT
MOBILE
FWH2/LAD2 B37 84 LPC_R_AD<2> R1862 1 2 33 LPC_AD<2> BI 46 48 84 PCIE_ENET_D2R_N BG34 PERN1 U1800 SMBALERT*/GPIO11 E12 PCH_GPIO11 201 2
FCBGA 5%1/20W MF 201 84 37 IN 17

(1 OF 10) FWH3/LAD3 C37

LPC_R_AD<3> R1863 1 2 33 LPC_AD<3> 84 37 IN PCIE_ENET_D2R_P BJ34 PERP1 COUGAR-POINT
D20 OMIT 84
5%1/20W MF 201 BI 46 48 84
AV32 MOBILE SMBCLK H14 SMBUS_PCH_CLK OUT 49 84
RTC_RESET_L RTCRST* PCIE_ENET_R2D_C_N PETN1
17
FWH4/LFRAME* D36 84 LPC_FRAME_R_L R1864 1 2 33 LPC_FRAME_L OUT 46 48 84
84 37 OUT
PCIE_ENET_R2D_C_P AU32 PETP1
FCBGA SMBDATA C9 SMBUS_PCH_DATA BI 49 84

PCH_SRTCRST_L G22 SRTCRST* 5%

1/20W MF 201 84 37 OUT (2 OF 10)
17
LDRQ0* E36 NC_LPC_DREQ0_L OMIT

RTC
LPC
91

D 17 PCH_INTRUDER_L K22 INTRUDER* LDRQ1*/GPIO23 K36

(IPU)
T29_PWR_EN_PCH OUT 20
PP3V3_S0 50 51 52 53 57 58 60 61 62 67
6 7 13 17 18 19 20 21 23 24 27
91 84 35

91 84 35
IN
IN
PCIE_AP_D2R_N
PCIE_AP_D2R_P
BE34
BF34
PERN2
PERP2
SML0ALERT*/GPIO60 A12 SML_PCH_0_ALERT_L 17
D
C17
30 31 34 37 38 39 40 41 47 49 SML0CLK C8 SML_PCH_0_CLK 49
17 PCH_INTVRMEN_L INTVRMEN SERIRQ V5 LPC_SERIRQ 71 72 73 74 76 77 79 89 91
84 35 PCIE_AP_R2D_C_N BB32 PETN2 OUT
1
OUT
AY32 SML0DATA G12 SML_PCH_0_DATA BI 49
R1820 84 35 OUT PCIE_AP_R2D_C_P PETP2
N34 AM3 10K BG36
84 17 HDA_BIT_CLK_R HDA_BCLK SATA0RXN SATA_HDD1_D2R_N IN 42 83 5% 84 39 IN PCIE_FW_D2R_N PERN3 SML1ALERT*/PCHHOT*/GPIO74 C13 SML_PCH_1_ALERT_L 17
AM1 1/20W BJ36
SATA0RXP SATA_HDD1_D2R_P MF PCIE_FW_D2R_P PERP3

SMBUS
IN 42 83 84 39 IN
L34 AP7 2 201 AV34 SML1CLK/GPIO58 E14 SML_PCH_1_CLK OUT 49 84
84 17 HDA_SYNC_R HDA_SYNC SATA0TXN SATA_HDD1_R2D_C_N 42 83 84 39 PCIE_FW_R2D_C_N PETN3
AP5
OUT
BI 46 48
OUT
AU34 SML1DATA/GPIO75 M16 SML_PCH_1_DATA BI 49 84
SATA0TXP SATA_HDD1_R2D_C_P OUT 42 83 84 39 OUT PCIE_FW_R2D_C_P PETP3
17 PCH_SPKR T10 SPKR
SATA1RXN AM10 SATA_HDD2_D2R_N 42 83 91 NC_PCIE_4_D2RN BF36 PERN4
IN
SATA1RXP AM8 SATA_HDD2_D2R_P NC_PCIE_4_D2RP BE36 PERP4

IHDA
84 17 HDA_RST_R_L K34 HDA_RST*
IN 42 83 91

SATA1TXN AP11 SATA_HDD2_R2D_C_N 42 83 91 NC_PCIE_4_R2D_CN AY34 PETN4

OUT
SATA1TXP AP10 SATA_HDD2_R2D_C_P 42 83 91 NC_PCIE_4_R2D_CP BB34 PETP4
HDA_SDIN0 E34 OUT
84 53 IN HDA_SDIN0
91 NC_HDA_SDIN1 G34 HDA_SDIN1 SATA2RXN AD7 NC_SATA_C_D2RN 91 91 NC_PCIE_5_D2RN BG37 PERN5
NC_HDA_SDIN2 C34 HDA_SDIN2 SATA2RXP AD5 NC_SATA_C_D2RP NC_PCIE_5_D2RP BH37 PERP5

PEG
91 91 91
A34 AH5 AY36 CLKOUT_PEG_A_N AB37 PEG_CLK100M_N OUT 8 84
91 NC_HDA_SDIN3 HDA_SDIN3 SATA2TXN NC_SATA_C_R2D_CN 91 91 NC_PCIE_5_R2D_CN PETN5
AH4 BB36 CLKOUT_PEG_A_P AB38 PEG_CLK100M_P OUT 8 84
SATA2TXP NC_SATA_C_R2D_CP 91 91 NC_PCIE_5_R2D_CP PETP5
84 17 HDA_SDOUT_R A36 HDA_SDO
SATA3RXN AB8 NC_SATA_D_D2RN 91 91 NC_PCIE_6_D2RN BJ38 PERN6
AB10 BG38 CLKOUT_DMI_N AV22 DMI_CLK100M_CPU_N OUT 11 81
C36 SATA3RXP NC_SATA_D_D2RP 91 91 NC_PCIE_6_D2RP PERP6
74 17 OUT JTAG_T29_TMS HDA_DOCK_EN*/GPIO33 AF3 AU36 CLKOUT_DMI_P AU22 DMI_CLK100M_CPU_P OUT 11 81
N32 SATA3TXN NC_SATA_D_R2D_CN 91 91 NC_PCIE_6_R2D_CN PETN6

SATA
38 IN ENET_MEDIA_SENSE_RDIV HDA_DOCK_RST*/GPIO13 AF1 AV36
SATA3TXP NC_SATA_D_R2D_CP 91 91 NC_PCIE_6_R2D_CP PETP6
Y7 PP1V05_S0_PCH 7 17 18 21 23 50
BG40 CLKOUT_DP_N AM12 NC_PCH_CLKOUT_DPN 91
J3 SATA4RXN NC_SATA_E_D2RN 91 91 NC_PCIE_7_D2RN PERN7
81 24 IN XDP_PCH_TCK JTAG_TCK Y5 1 BJ40 CLKOUT_DP_P AM13 NC_PCH_CLKOUT_DPP 91
NC_SATA_E_D2RP R1830 NC_PCIE_7_D2RP

PCI-E*
SATA4RXP 91 91 PERP7
81 24 XDP_PCH_TMS H7 JTAG_TMS JTAG SATA4TXN AD3 NC_SATA_E_R2D_CN 91 37.4 91 NC_PCIE_7_R2D_CN AY40 PETN7
IN
1%

FROM CLK BUFFER

SATA4TXP AD1 NC_SATA_E_R2D_CP 1/20W NC_PCIE_7_R2D_CP BB40 PETP7 CLKIN_DMI_N BF18 PCIE_CLK100M_PCH_N
81 24 XDP_PCH_TDI K5 JTAG_TDI
91
MF
91 IN 17 84
IN
CLKIN_DMI_P BE18 PCIE_CLK100M_PCH_P
C 81 24 OUT XDP_PCH_TDO H1 JTAG_TDO
SATA5RXN
SATA5RXP
Y3
Y1
NC_SATA_F_D2RN
NC_SATA_F_D2RP
91

91
2 201
PLACE_NEAR=U1800.Y11:2.54mm
91

91
NC_PCIE_8_D2RN
NC_PCIE_8_D2RP
BE38
BC38
PERN8
PERP8
IN 17 84
C
SATA5TXN AB3 NC_SATA_F_R2D_CN 91 91 NC_PCIE_8_R2D_CN AW38 PETN8 CLKIN_DOT_96N G24 PCH_CLK96M_DOT_N 17 84
IN
SATA5TXP AB1 NC_SATA_F_R2D_CP 91 91 NC_PCIE_8_R2D_CP AY38 PETP8 CLKIN_DOT_96P E24 PCH_CLK96M_DOT_P 17 84
IN
T3 PP3V3_S0 650 51 52 53 57 58 60 61 62 67
7 13 17 18 19 20 21 23 24 27
84 48 SPI_CLK_R SPI_CLK 83 PCH_SATAICOMP 30 31 34 37 38 39 40 41 47 49
OUT
SATAICOMPO Y11 71 72 73 74 76 77 79 89 91
84 37 PCIE_CLK100M_ENET_N Y40 CLKOUT_PCIE0N
Y14
1
R1879 OUT
CLKIN_SATA_N AK7 PCH_CLK100M_SATA_N IN 17 84
84 48 SPI_CS0_R_L SPI_CS0* SATAICOMPI Y10 84 37 PCIE_CLK100M_ENET_P Y39 CLKOUT_PCIE0P
OUT 10K OUT
CLKIN_SATA_P AK5 PCH_CLK100M_SATA_P
SPI

IN 17 84
T1 5% AB49
TP_SPI_CS1_L SPI_CS1* 1/20W PP1V05_S0_PCH 7 17 18 21 23 50 84 35 PCIE_CLK100M_AP_N CLKOUT_PCIE1N
SATALED* P3 PCH_SATALED_L OUT
17 MF AB47
V4 2 201 84 35 OUT PCIE_CLK100M_AP_P CLKOUT_PCIE1P
84 48 SPI_MOSI_R SPI_MOSI 1
R1831 REFCLK14IN K45 PCH_CLK14P3M_REFCLK 17 84
SATA0GP/GPIO21 V14
OUT DP_AUXCH_ISOL IN
(T29) OUT 77
49.9 PCIE_CLK100M_FW_N AA48
U3 84 39 OUT CLKOUT_PCIE2N
91 84 48 IN SPI_MISO SPI_MISO SATA1GP/GPIO19 P1 SATARDRVR_EN 17 1% AA47
(IPU) 1/20W 84 39 PCIE_CLK100M_FW_P CLKOUT_PCIE2P
CLKIN_PCILOOPBACK H45
OUT PCH_CLK33M_PCIIN
MF IN 27 84

SATA3COMPI AB13 2 201 PLACE_NEAR=U1800.AB12:2.54mm 17 FW_CLKREQ_L V10 PCIECLKRQ2*/GPIO20

DOES THIS NEED LENGTH MATCH???

39 IN
SATA3RCOMP0 AB12 83 PCH_SATA3COMP Y37
91 NC_PCIE_CLK100M_EXCARDN CLKOUT_PCIE3N XTAL25_IN V47 PCH_CLK25M_X1 26
SATA3RBIAS AH1 PCH_SATA3RBIAS Y36
IN
91 NC_PCIE_CLK100M_EXCARDP CLKOUT_PCIE3P XTAL25_OUT V49 PCH_CLK25M_X2 OUT 26

84 74 PCIE_CLK100M_T29_N Y43 CLKOUT_PCIE4N

OUT
76 75 74 26 20 PP3V3_T29 Y45
84 74 OUT PCIE_CLK100M_T29_P CLKOUT_PCIE4P XCLK_RCOMP Y47 PCH_XCLK_RCOMP
91
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 R18321 V45
47 41 40 39 38 37 34 31 30 27
89 79 77 76 74 73 72 71 67
750 91 NC_PCIE_CLK100M_PE5N CLKOUT_PCIE5N
1% PLACE_NEAR=U1800.AH1:2.54mm V46
R18431 R18451 R18781 R18691 R18761 1/20W NC_PCIE_CLK100M_PE5P CLKOUT_PCIE5P CLKOUTFLEX0/GPIO64 K43 NC_PCH_GPIO64_CLKOUTFLEX0

CLOCK
91 91

FLEX
MF
PP3V3_S5 10K 10K 4.7K 10K 10K 201 2
PCIECLKRQ5_L_GPIO44 L14
27 25 24 23 21 20 19 18 17 6 5% 5% 5% 5% 5% 17 PCIECLKRQ5*/GPIO44
91 89 78 62 61 59 28 1/20W 1/20W 1/20W 1/20W 1/20W CLKOUTFLEX1/GPIO65 F47 NC_PCH_GPIO65_CLKOUTFLEX1 91
MF MF MF MF MF AB42
201 2 201 2 201 2 201 2 201 2 91 NC_PCIE_CLK100M_PEBN CLKOUT_PEG_B_N
91 NC_PCIE_CLK100M_PEBP AB40 CLKOUT_PEG_B_P CLKOUTFLEX2/GPIO66 H47 NC_PCH_GPIO66_CLKOUTFLEX2 91
1 1 1 1 1
R1848 R1846 R1844 R1842 R1877 J2
10K 10K 10K 10K 4.7K 37 17 ENET_CLKREQ_L PCIECLKRQ0*/GPIO73
CLKOUTFLEX3/GPIO67 K49
B 5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
35 17
IN
IN AP_CLKREQ_L M1
A8
PCIECLKRQ1*/GPIO18
NC_PCH_GPIO67_CLKOUTFLEX3 91
B
2 201 2 201 2 201 2 201 2 201 JTAG_T29_TMS OUT 17 74 17 IN EXCARD_CLKREQ_L PCIECLKRQ3*/GPIO25
L12 CLKOUT_ITPXDP_N AK14 ITPXDP_CLK100M_N OUT 17 24 81
PCH_SPKR 17 76 17 T29_CLKREQ_L PCIECLKRQ4*/GPIO26
CLKOUT_ITPXDP_P AK13
IN ITPXDP_CLK100M_P OUT 17 24 81
FW_CLKREQ_L OUT 17 39 M10
17 IN PEG_CLKREQ_L PEG_A_CLKRQ*/GPIO47
AP_CLKREQ_L OUT 17 35
E6
17 PEG_B_CLKRQ_L_GPIO56 PEG_B_CLKRQ*/GPIO56
91 27 21 18 6 PP3V3_G3_RTC PCH_SATALED_L 17

EXCARD_CLKREQ_L 17
CLKIN_GND1_N BJ30 PCH_CLKIN_GNDN1
R18021 1
R1803 T29_CLKREQ_L OUT 17 76
CLKIN_GND1_P BG30 PCH_CLKIN_GNDP1
20K 20K PEG_CLKREQ_L 17
1% 1%
1/20W 1/20W ENET_CLKREQ_L OUT 17 37 CL_CLK1 M7 NC_CLINK_CLK 91
MF MF
201 2 2 201 PEG_B_CLKRQ_L_GPIO56 17
91 72 71 53 39 23 21 7 PP1V5_S0 CL_DATA1 T11 NC_CLINK_DATA 91
1 1
R1800 R1801 NOSTUFF
1 NOSTUFF
1 CL_RST1* P10 NC_CLINK_RESET_L 91
330K 1M 91
R1866 R1849
5% 5%
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 NOSTUFF
1/20W 1/20W
RTC_RESET_L
47 41 40 39 38 37 34 31 30 27
ITPXDP_CLK100M_N R1840 2 0 1 5%1/20W ITPCPU_CLK100M_N 10K 10K
MF MF 17
89 79 77 76 74 73 72 71 67
NOSTUFF 81 24 17 MF 11 81 5% 5%
201 2 2 201 1/20W 1/20W
PCH_SRTCRST_L 17 R18331 201
NOSTUFF
MF
201 2
MF
201 2 R1849 cannot be used w/ VCCSUSHDA on S0
R18701 1
R1871
PCH_INTRUDER_L 17 10K R1841 2 0 1 5%1/20W 10K 10K
5% 81 24 17 ITPXDP_CLK100M_P MF ITPCPU_CLK100M_P 11 81 5% 5%
PCH_INTVRMEN_L 17 1/20W HDA_SYNC_R 17 84 1/20W 1/20W
MF 201 MF MF
201 2 HDA_SDOUT_R 17 84 201 2 2 201
C1802 1 1 C1803
1UF 1UF SATARDRVR_EN 17 PLACE_NEAR=U1800.N34:1.27mm
10% 10% 27 25 24 23 21 20 19 18 17 6 PP3V3_S5
10V 2 10V
X5R
402-1
2 X5R
402-1
91 89 78 62 61 59 28
R1810
1 HDA_BIT_CLK_R 33
R1847 84 17 1 2 HDA_BIT_CLK OUT 53 84

10K 5%
5% 1/20W PLACE_NEAR=U1800.L34:1.27mm 27 25 24 23 21 20 19 18 17 6 PP3V3_S5
1/20W MF R1811 91 89 78 62 61 59 28
PCH_CLK14P3M_REFCLK 201
A 84 17

84 17 PCIE_CLK100M_PCH_N
MF
201 2
84 17 HDA_SYNC_R 1
33 2 HDA_SYNC OUT 53 84 SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
1
84 17 PCIE_CLK100M_PCH_P PCIECLKRQ5_L_GPIO44 17
PLACE_NEAR=U1800.K34:1.27mm
5%
1/20W R1853 1R1854 1R1855 PAGE TITLE

84 17 PCH_CLK100M_SATA_N R1812 MF
201
10K
5% 5%
10K 10K
5%
PCH SATA/PCIE/CLK/LPC/SPI
84 17 PCH_CLK100M_SATA_P 33 1/20W 1/20W 1/20W DRAWING NUMBER SIZE
HDA_RST_R_L 1 2 HDA_RST_L MF MF MF
84 17 PCH_CLK96M_DOT_N 1
84 17 OUT 53 84
2 201 2 201 2 201 Apple Inc. 051-8768 D
84 17 PCH_CLK96M_DOT_P R1897 5%
1/20W PLACE_NEAR=U1800.A36:1.27mm 17 PCH_GPIO11 REVISION
10K MF R1813 R
1 5% 201 17 SML_PCH_0_ALERT_L 9.0.0
R1891 1R1892 1R1893 1R1894 1R1895 1R1896 1/20W
MF 84 17 HDA_SDOUT_R 1
33 2 HDA_SDOUT OUT 53 84 17 SML_PCH_1_ALERT_L NOTICE OF PROPRIETARY PROPERTY: BRANCH
10K 10K 10K 10K 10K 10K 2 201
5% 5% 5% 5% 5% 5% 5% THE INFORMATION CONTAINED HEREIN IS THE
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
MF MF MF MF MF MF MF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
2 201 2 201 2 201 2 201 2 201 2 201 201 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
18 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
UNUSED clock terminations for FCIM MODE IV ALL RIGHTS RESERVED 17 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
PP3V3_S5 6 17 18 19 20 21 23 24 25 27 28
59 61 62 78 89 91

PP1V05_S0_PCH 7 17 21 23 50

1
R1905 1
R1900
10K
5% 49.9
1/20W 1% PLACE_NEAR=U1800.BJ24:12.7mm
MF 1/20W
2 201 MF
2 201
81 10 IN DMI_N2S_N<0> BC24 DMI0RXN U1800 FDI_RXN0 BJ14 FDI_DATA_N<0> IN 8 81
NC
AT1 RSVD U1800 SDVO_TVCLKINN AP43 NC_SDVO_TVCLKINN 91
BE20 COUGAR-POINT AY14 AT3 COUGAR-POINT
81 10 IN DMI_N2S_N<1> DMI1RXN MOBILE FDI_RXN1 FDI_DATA_N<1> IN 8 81
NC RSVD SDVO_TVCLKINP AP45 NC_SDVO_TVCLKINP 91
MOBILE
D 81 10

81 10
IN
IN
DMI_N2S_N<2>
DMI_N2S_N<3>
BG18
BG20
DMI2RXN
DMI3RXN
FCBGA
(3 OF 10)
FDI_RXN2
FDI_RXN3
BE14
BH13
FDI_DATA_N<2>
FDI_DATA_N<3>
IN
IN
8 81

8 81
NC
AT4
NC AT5RSVD
RSVD
FCBGA
(4 OF 10)
SDVO_STALLN AM42 NC_SDVO_STALLN 91 D
BC12 AT8 SDVO_STALLP AM40 NC_SDVO_STALLP 91
BE24 OMIT FDI_RXN4 FDI_DATA_N<4> IN 8 81
NC RSVD OMIT
81 10 IN DMI_N2S_P<0> DMI0RXP BJ12 AT10
BC20 FDI_RXN5 FDI_DATA_N<5> IN 8 81
NC RSVD SDVO_INTN AP39 NC_SDVO_INTN 91
81 10 DMI_N2S_P<1> DMI1RXP BG10 AT12 SDVO_INTP AP40
IN FDI_DATA_N<6> NC_SDVO_INTP
BJ18 FDI_RXN6 IN 8 81
NC RSVD 91
81 10 IN DMI_N2S_P<2> DMI2RXP BG9 AU2
BJ20 FDI_RXN7 FDI_DATA_N<7> IN 8 81
NC RSVD
81 10 IN DMI_N2S_P<3> DMI3RXP AU3
BG14 NC RSVD SDVO_CTRLCLK P38 =IG_DP_EXTA_DDC_CLK BI 8
FDI_RXP0 FDI_DATA_P<0> 8 81
AV1
AW24 BB14
IN
NC RSVD SDVO_CTRLDATA M39 =IG_DP_EXTA_DDC_DATA BI 8
81 10 OUT DMI_S2N_N<0> DMI0TXN FDI_RXP1 FDI_DATA_P<1> IN 8 81 AV3
AW20 BF14 NC AV5RSVD
81 10 OUT DMI_S2N_N<1> DMI1TXN FDI_RXP2 FDI_DATA_P<2> IN 8 81 DDPB_AUXN AT49 =IG_DP_EXTA_AUXCH_C_N BI 8
BB18 BG13 NC RSVD
81 10 OUT DMI_S2N_N<2> DMI2TXN FDI_RXP3 FDI_DATA_P<3> IN 8 81 AV7 DDPB_AUXP AT47 =IG_DP_EXTA_AUXCH_C_P BI 8
AV18 BE12 NC RSVD
81 10 OUT DMI_S2N_N<3> DMI3TXN FDI_RXP4 FDI_DATA_P<4> IN 8 81
AV10 DDPB_HPD AT40 =IG_DP_EXTA_HPD IN 8
RSVD

DMI
FDI
BG12 FDI_DATA_P<5> NC AY3

DIGITAL DISPLAY INTERFACE

AY24 FDI_RXP5 IN 8 81 AV42
81 10 OUT DMI_S2N_P<0> DMI0TXP BJ10 NC RSVD DDPB_0N =IG_DP_EXTA_ML_C_N<0> OUT 8
AY20 FDI_RXP6 FDI_DATA_P<6> IN 8 81
AY5 AV40
81 10 OUT DMI_S2N_P<1> DMI1TXP BH9 NC RSVD DDPB_0P =IG_DP_EXTA_ML_C_P<0> OUT 8
AY18 FDI_RXP7 FDI_DATA_P<7> IN 8 81 AY7 AV45
81 10 OUT DMI_S2N_P<2> DMI2TXP NC RSVD DDPB_1N =IG_DP_EXTA_ML_C_N<1> OUT 8

DMI_S2N_P<3> AU18 DMI3TXP BA2RSVD DDPB_1P AV46 =IG_DP_EXTA_ML_C_P<1>

81 10 OUT
FDI_INT AW16 FDI_INT 8 81
NC OUT 8
OUT BA3RSVD DDPB_2N AU48 =IG_DP_EXTA_ML_C_N<2>
NC AU47 OUT 8

PCH_DMI2RBIAS BH21 DMI2RBIAS FDI_FSYNC0 AV12 FDI_FSYNC<0> BB1RSVD DDPB_2P =IG_DP_EXTA_ML_C_P<2>

OUT 8 81
NC OUT 8

PLACE_NEAR=U1800.BH21:2.54mm FDI_FSYNC1 BC10 FDI_FSYNC<1> OUT 8 81

NC
BB3RSVD DDPB_3N AV47 =IG_DP_EXTA_ML_C_N<3> OUT 8
1 BB5 AV49 =IG_DP_EXTA_ML_C_P<3>
R1920 PCH_DMI_COMP BJ24 DMI_ZCOMP FDI_LSYNC0 AV14 FDI_LSYNC<0> OUT 8 81
NC BB7RSVD DDPB_3P OUT 8

750 BG25 NC RSVD

1% DMI_IRCOMP FDI_LSYNC1 BB10 FDI_LSYNC<1> 8 81 BC8
1/20W OUT
NC RSVD DDPC_CTRLCLK P46 =IG_DP_T29SNK0_CTRL_CLK BI 8
MF BD4
2 201 NC BE8RSVD DDPC_CTRLDATA P42 =IG_DP_T29SNK0_CTRL_DATA BI 8

SYSTEM POWER
PM_SYSRST_L K3 SYS_RESET* WAKE* B9 PCIE_WAKE_L RSVD
46 27 IN IN 18 35 38 77 91
NC DDPC_AUXN AP47 =IG_DP_T29SNK0_AUXCH_C_N 8

MANAGEMENT
BF3RSVD BI
27 24 IN PM_PCH_SYS_PWROK P12 SYS_PWROK CLKRUN*/GPIO32 N3 PM_CLKRUN_L BI 18 46 48
NC DDPC_AUXP AP49 =IG_DP_T29SNK0_AUXCH_C_P BI 8
BF6RSVD
NC DDPC_HPD AT38 =IG_DP_T29SNK0_HPD
PM_PCH_PWROK L22 PWROK BG4RSVD IN 8
27 20 18 IN NC
C 81 28 11 OUT PM_MEM_PWRGD B13 DRAMPWROK SUS_STAT*/GPIO61 G8 LPC_PWRDWN_L OUT 46 48
DDPC_0N
DDPC_0P
AY47
AY49
=IG_DP_T29SNK0_ML_C_N<0>
=IG_DP_T29SNK0_ML_C_P<0>
OUT 8

8
C
OUT
E22 DPWROK SUSCLK/GPIO62 N14 PM_CLK32K_SUSCLK_R 47 DDPC_1N AY43 =IG_DP_T29SNK0_ML_C_N<1> 8
OUT OUT
DDPC_1P AY45 =IG_DP_T29SNK0_ML_C_P<1> 8
27 20 18 PM_PCH_PWROK L10 APWROK SLP_S5*/GPIO63 D10 PM_SLP_S5_L 18 46 62 91
OUT
IN OUT
DDPC_2N BA47 =IG_DP_T29SNK0_ML_C_N<2> 8
OUT
46 PM_RSMRST_L C21 RSMRST* SLP_S4* H4 PM_SLP_S4_L 18 28 46 62 91 DDPC_2P BA48 =IG_DP_T29SNK0_ML_C_P<2> 8
IN OUT OUT
DDPC_3N BB47 =IG_DP_T29SNK0_ML_C_N<3> 8
18 SUSWARN_L K16 SUSWARN*/SUSPWRDNACK/GPIO30 SLP_S3* F4 PM_SLP_S3_L 18 28 46 51 62 91
OUT
OUT OUT
DDPC_3P BB49 =IG_DP_T29SNK0_ML_C_P<3> 8
OUT
46 24 18 PM_PWRBTN_L E20 PWRBTN* SLP_A* G10 TP_PM_SLP_A_L PP1V8_S0 7 15 21 23 26 71
IN
PD on SMC page DDPD_CTRLCLK M43 =IG_HDMI_LS_SCL 8
TP23 AY16
SMC_ADAPTER_EN TP_PCH_TP23 1 BI
47 46 IN H20 ACPRESENT/GPIO31 R1981 DDPD_CTRLDATA M36 =IG_HDMI_LS_SDA BI 8
E10 2.2K
46 PM_BATLOW_L BATLOW*/GPIO72 PMSYNCH AP14 PM_SYNC 11 81 5% 91 NC_CRT_IG_BLUE N48 CRT_BLUE
DDPD_AUXN AT45
IN OUT NC_IG_D_AUXN
1/20W P49 91
A10 MF 91 NC_CRT_IG_GREEN CRT_GREEN
PCH_RI_L RI* SLP_LAN*/GPIO29 K14 GPIO29_SLP_LAN_L 18
2 201 T49 DDPD_AUXP AT43 NC_IG_D_AUXP 91
91 NC_CRT_IG_RED CRT_RED
DDPD_HPD BH41 =IG_HDMI_LS_HPD IN 8
R1980 2 1K

CRT
1 DF_TVS AY1 PCH_DF_TVS 1 1%1/20W MF CPU_PROC_SEL_L
R1909 201
11 81
91 NC_CRT_IG_DDC_CLK T39 CRT_DDC_CLK DDPD_0N BB43 =IG_HDMI_DATA_C_N<2> OUT 8
100K 91 NC_CRT_IG_DDC_DATA M40 CRT_DDC_DATA DDPD_0P BB45 =IG_HDMI_DATA_C_P<2> OUT 8
5%
1/20W DDPD_1N BF44 =IG_HDMI_DATA_C_N<1> 8
DSWVRMEN A18
MF PCH_DSWVRMEN OUT
201 2 PP3V3_G3_RTC 6 17 21 27 91 91 NC_CRT_IG_HSYNC M47 CRT_HSYNC DDPD_1P BE44 =IG_HDMI_DATA_C_P<1> 8
OUT
G16 M49 BF42
SLP_SUS* TP_PM_SLP_SUS_L 1 91 NC_CRT_IG_VSYNC CRT_VSYNC DDPD_2N =IG_HDMI_DATA_C_N<0> OUT 8
R1915 DDPD_2P BE42 =IG_HDMI_DATA_C_P<0> 8
SUSACK* C12 PCH_SUSACK_L IN 18 390K T43 BJ42
OUT
5% PCH_DAC_IREF DAC_IREF DDPD_3N =IG_HDMI_CLK_C_N OUT 8
1/20W T42 BG42
MF CRT_IRTN DDPD_3P =IG_HDMI_CLK_C_P OUT 8
2 201 1
DF_TVS:DMI & FDI Term Voltage R1951
Set to Vss when Low 1K
Set to Vcc when High 1%
1/20W
MF
B 2 201
PLACE_NEAR=U1800.T43:2.54mm
B
SUSWARN_L R1986 2 0 1 5%1/20W MF PCH_SUSACK_L
18 18

201

67 62 61 60 58 57 53 52 51 50
27 24 23 21 20 19 17 13 7 6 PP3V3_S0
49 47 41 40 39 38 37 34 31 30
91 89 79 77 76 74 73 72 71

R19911
8.2K
5%
1/20W
MF
201 2

PM_CLKRUN_L OUT 18 46 48
27 25 24 23 21 20 19 18 17 6 PP3V3_S5
91 89 78 62 61 59 28
27 25 24 23 21 20 19 18 17 6 PP3V3_S5
91 89 78 62 61 59 28

91 62 51 46 28 18 OUT PM_SLP_S3_L
R19251 R19851 R19821 R19831 91 62 46 28 18 OUT PM_SLP_S4_L
1K 1K 10K 10K
1% 1% 5% 5%
PM_SLP_S5_L
A 1/20W
MF
201 2
1/20W
MF
201 2
1/20W
MF
201 2
1/20W
MF
201 2
91 62 46 18 OUT
A
PAGE TITLE
SUSWARN_L 18 R19221 R19211 R19241 PCH DMI/FDI/GRAPHICS
GPIO29_SLP_LAN_L 18
100K 100K 100K DRAWING NUMBER SIZE
5% 5% 5%
PM_PWRBTN_L OUT 18 24 46
1/20W
MF
1/20W
MF
1/20W
MF Apple Inc. 051-8768 D
201 2 201 2 201 2 REVISION
R
PCIE_WAKE_L OUT 18 35 38 77 91 9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
19 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 18 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

67 62 61 60 58 57 53 52 51 50
27 24 23 21 20 18 17 13 7 6 PP3V3_S0
49 47 41 40 39 38 37 34 31 30
91 89 79 77 76 74 73 72 71
R2010 10K 1 2 PCI_INTA_L K40 PIRQA* U1800 USBP0N C24 USB_HUB1_UP_N BI 25 83
R2011 10K 5% 1/20W MF 201 K38 COUGAR-POINT
1 2 PCI_INTB_L PIRQB* MOBILE USBP0P A24 USB_HUB1_UP_P BI 25 83
USB HUB 1

R2012 10K 5% 1/20W MF 201 H38

1 2 PCI_INTC_L PIRQC* FCBGA
5% 1/20W MF 201 USBP1N C25 NC_USB_1N
R2013 10K 1 2 PCI_INTD_L G38 PIRQD* (5 OF 10) 91
Unused
5% 1/20W MF 201 USBP1P B25 NC_USB_1P 91
OMIT
R2016 10K C46 USBP2N C26 NC_USB_2N 91
1 2 JTAG_GMUX_TMS REQ1*/GPIO50 Unused

R2017 10K 5% 1/20W MF 201 C44 USBP2P A26 NC_USB_2P 91

1 2 PCH_GPIO52 REQ2*/GPIO52
D R2018 10K 1 2 5%
5%
1/20W
1/20W
MF
MF
201
201
PCI_REQ3_L E40 REQ3*/GPIO54 USBP3N K28 NC_USB_3N 91
Unused
D
USBP3P H28 NC_USB_3P 91

19 PCH_PCI_GNT1_L D47 GNT1*/GPIO51 USBP4N E28 NC_USB_4N 91

Unused

19 PCH_PCI_GNT2_L E42 GNT2*/GPIO53 USBP4P D28 NC_USB_4P 91

19 PCH_PCI_GNT3_L F46 GNT3*/GPIO55

USBP5N C28 NC_USB_5N 91 Unused
R2030 10K 1 2 PCI_INTE_L G42 PIRQE*/GPIO2 USBP5P A28 NC_USB_5P 91
5% 1/20W MF 201
R2014 10K 1 2 58 AUD_IP_PERIPHERAL_DET G40 PIRQF*/GPIO3
R2031 10K 5% 1/20W MF 201 C42 USBP6N C29 NC_USB_6N 91 Unused
1 2 77 T29_MCU_INT_L PIRQG*/GPIO4

PCI
5% 1/20W MF 201 D44 USBP6P B29 NC_USB_6P 91
58 AUD_I2C_INT_L PIRQH*/GPIO5
K10 USBP7N N28 NC_USB_7N 91 Unused
91 NC_PCI_PME_L PME*
USBP7P M28 NC_USB_7P 91

27 PLT_RESET_L C6 PLTRST*
OUT
USBP8N L30 USB_HUB2_UP_N BI 25 83
H49 USB HUB 2
84 27 OUT LPC_CLK33M_SMC_R CLKOUT_PCI0 USBP8P K30 USB_HUB2_UP_P BI 25 83

84 27 LPC_CLK33M_LPCPLUS_R H43 CLKOUT_PCI1

OUT
J48 USBP9N G30 NC_USB_9N 91
TP_LPC_CLK33M_GMUX_R CLKOUT_PCI2 PP3V3_S4
USBP9P E30
6 20 25 28 33 34 35 38 47 49 50
K42 NC_USB_9P 91
Camera 61 77 78 91
TP_PCI_CLK33M_OUT3 CLKOUT_PCI3
27 PCH_CLK33M_PCIOUT H40 CLKOUT_PCI4 USBP10N C30 NC_USB_10N 91 PP3V3_S5 6 17 18 20 21 23 24 25 27 28 59
OUT 61 62 78 89 91
USBP10P A30 NC_USB_10P 91
AN48 Unused
91 NC_LVDS_IG_A_DATAN<0> LVDSA_DATA0*
AM47 USBP11N L32 NC_USB_11N 91
91 NC_LVDS_IG_A_DATAN<1> LVDSA_DATA1*
USBP11P K32 NC_USB_11P 1
R2061 1
R2064 1
R2067 1
R2068

USB
91
91 NC_LVDS_IG_A_DATAN<2> AK47 LVDSA_DATA2* Unused
AJ48 10K 10K 10K 10K
91 NC_LVDS_IG_A_DATAN<3> LVDSA_DATA3* USBP12N G32 NC_USB_12N 91 5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W
AN47 USBP12P E32 NC_USB_12P 91 MF MF MF MF
91 NC_LVDS_IG_A_DATAP<0> LVDSA_DATA0 Unused 2 201 2 201 2 201 2 201
91 NC_LVDS_IG_A_DATAP<1> AM49 LVDSA_DATA1 USBP13N C32 NC_USB_13N 91

NC_LVDS_IG_A_DATAP<2> AK49 USBP13P A32 NC_USB_13P

C 91

91 NC_LVDS_IG_A_DATAP<3> AJ47
LVDSA_DATA2
LVDSA_DATA3
91
Unused R20601
10K
R20621
10K
R20651
10K
R20691
10K
C
AK39 USBRBIAS* C33 83 PCH_USB_RBIAS 5% 5% 5% 5%
91 NC_LVDS_IG_A_CLKN LVDSA_CLK* 1/20W 1/20W 1/20W 1/20W
USBRBIAS B33 MF MF MF MF

LVDS
91 NC_LVDS_IG_A_CLKP AK40 LVDSA_CLK 201 2 201 2 201 2 201 2

91 NC_LVDS_IG_B_DATAN<0> AH45 LVDSB_DATA0*

OC0*/GPIO59 A14 AP_PWR_EN
91 NC_LVDS_IG_B_DATAN<1> AH47 LVDSB_DATA1* OUT 24 35 62

OC1*/GPIO40 K20 USB_HUB_SOFT_RESET_L 24 25

91 NC_LVDS_IG_B_DATAN<2> AF49 LVDSB_DATA2*
OUT
OC2*/GPIO41 B17 T29_DP_PORTA_PWR_EN 24 78
NC_LVDS_IG_B_DATAN<3> AF45 OUT
91 LVDSB_DATA3* C16
OC3*/GPIO42 ENET_PWR_EN OUT 24

91 NC_LVDS_IG_B_DATAP<0> AH43 LVDSB_DATA0 OC4*/GPIO43 L16 PCH_GPIO43_OC4_L 24

IN
91 NC_LVDS_IG_B_DATAP<1> AH49 LVDSB_DATA1 OC5*/GPIO9 A16 SDCONN_STATE_CHANGE 24 34
IN
91 NC_LVDS_IG_B_DATAP<2> AF47 LVDSB_DATA2 OC6*/GPIO10 D14 PCH_GPIO10_OC6_L 24
IN
91 NC_LVDS_IG_B_DATAP<3> AF43 LVDSB_DATA3 OC7*/GPIO14 C14 PCH_GPIO14_OC7_L 24
IN

91 NC_LVDS_IG_B_CLKN AF40 LVDSB_CLK*

91 NC_LVDS_IG_B_CLKP AF39 LVDSB_CLK

91 NC_PCH_LVDS_IBG AF37 LVD_IBG R20701

NC_PCH_LVDS_VBG AF36 22.6
91 LVD_VBG 1%
1/20W
AE48 MF PLACE_NEAR=U1800.B33:2.54mm
91 NC_LVDS_IG_VREFH LVD_VREFH 201 2
91 NC_LVDS_IG_VREFL AE47 LVD_VREFL

91 NC_LVDS_IG_BKL_PWM P45 L_BKLTCTL

91 NC_LVDS_IG_BKL_ON J47 L_BKLTEN
91 NC_LVDS_IG_PANEL_PWR M45 L_VDD_EN
91 NC_LVDS_IG_CTRL_CLK T45 L_CTRL_CLK
91 NC_LVDS_IG_CTRL_DATA P39 L_CTRL_DATA
T40
B 91

91
NC_LVDS_IG_DDC_CLK
NC_LVDS_IG_DDC_DATA K47
L_DDC_CLK
L_DDC_DATA
B

19 PCH_PCI_GNT3_L
19 PCH_PCI_GNT2_L
19 PCH_PCI_GNT1_L

NOSTUFF NOSTUFF NOSTUFF www.teknisi-indonesia.com

R20521 R20531 R20541
10K 10K 10K
5% 5% 5%
1/20W 1/20W 1/20W
MF MF MF
201 2 201 2 201 2

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

PCH PCI/FLASHCACHE/USB
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
20 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 19 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

T7 U1800 PP3V3_S0 50 51 52 53 57 58 60 61 62 67
6 7 13 17 18 19 20 21 23 24 27
20 IN PCH_GPIO0 BMBUSY*/GPIO0 CLKOUT_PCIE6N V40 NC_PCIE_CLK100M_PE6N 91 30 31 34 37 38 39 40 41 47 49
COUGAR-POINT 71 72 73 74 76 77 79 89 91

D 39 20 IN FW_PME_L A42 TACH1/GPIO1 MOBILE

FCBGA
CLKOUT_PCIE6P V42 NC_PCIE_CLK100M_PE6P 91
R21501 D
H36 10K
91
20 IN GMUX_INT TACH2/GPIO6 (6 OF 10) CLKOUT_PCIE7N V38 NC_PCIE_CLK100M_PE7N 91 5%
1/20W
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 E38 OMIT CLKOUT_PCIE7P V37 NC_PCIE_CLK100M_PE7P 91 MF
47 41 40 39 38 37 34 31 30 27
89 79 77 76 74 73 72 71 67
46 20 IN SMC_RUNTIME_SCI_L TACH3/GPIO7 201 2 R21551
10K
74 20 JTAG_ISP_TCK (IPU) NC
C10 GPIO8 MISC A20GATE P4 PCH_A20GATE
NOSTUFF
5%
1/20W
OUT
20 ODD_PWR_EN_L R2190 1 20 PCH_GPIO12 C4 LAN_PHY_PWR_CTRL/GPIO12 R2170 MF
201 2
43
20 GMUX_INT 100K (IPU) G2 PECI AU16 PCH_PECI 1 2 CPU_PECI BI 11 46 81
5% 24 20 PCH_GPIO15 GPIO15 1/20W MF
1/20W PD on audio page 5%
MF 201

CPU
1 1 1 AUD_IPHS_SWITCH_EN_PCH U2 RCIN* P5 PCH_RCIN_L
R2111 R2112 R2113 201 2 20 OUT SATA4GP/GPIO16
R2140
20K 10K 10K LPCPLUS_GPIO D40
1% 5% 5% 48 TACH0/GPIO17 0
1/20W 1/20W 1/20W BI
PROCPWRGD AY11 PCH_PROCPWRGD 1 2 CPU_PWRGD OUT 11 24 81
MF MF MF T5 1/20W MF R2156
201 2 201 2 201 2 20 OUT ODD_PWR_EN_L SCLOCK/GPIO22 5%
201 390
E8 THRMTRIP* AY10 47 PM_THRMTRIP_L_R 1 2 PM_THRMTRIP_L IN 11 81
(PU necessary?) 20 PCH_GPIO24 GPIO24/MEM_LED
5%
E16 1/20W
46 20 SMC_SCI_L GPIO27 MF
IN
TP1 BG26
NC ALL RSVD TPs NC-ed per INTEL approval 201
28 ISOLATE_CPU_MEM_L P8 GPIO28
OUT
TP2 BJ26

GPIO
NC
76 20 T29_SW_RESET_L K1 STP_PCI*/GPIO34
OUT
TP3 BH25
NC
(NC-ed per Intel chklist) 91 NC_GPIO35 K4 GPIO35 C2150
TP4 BJ16
NC 0.1UF
20 PCH_GPIO36_SATA2GP V8 SATA2GP/GPIO36 47 38 35 34 33 28 25 20 19 6 PP3V3_S4 1 2
OUT
TP5 BG16
NC
91 78 77 61 50 49
25 24 23 21 20 19 18 17 6 PP3V3_S5 M5
91 89 78 62 61 59 28 27 74 20 OUT JTAG_ISP_TCK SATA3GP/GPIO37 10%
TP6 AH38
NC
16V
X7R-CERM
74 20 JTAG_ISP_TDO N2 SLOAD/GPIO38 402
IN
TP7 AH37
NC
R21931 R21921 R21941 74 20 OUT JTAG_ISP_TDI M3 SDATAOUT0/GPIO39
10K 10K 10K TP8 AK43 5 MC74VHC1G08
C 5%
1/20W
5%
1/20W
5%
1/20W 62 20 OUT WOL_EN T13 PCIECLKRQ6*/GPIO45
NC
TP9 AK45
20 ENET_LOW_PWR_PCH 1 SC70-HF
ENET_LOW_PWR
C
MF
201 2
MF
201 2
MF
201 2
PCH_GPIO46 K12
NC
PM_PCH_PWROK 2
U2150 4 OUT 34 37

20 OUT PCIECLKRQ7*/GPIO46 27 20 18 IN
TP10 C18 NC
20 FW_PWR_EN V13 SDATAOUT1/GPIO48 3
OUT
TP11 N30 NC
20 ENET_LOW_PWR_PCH V3 SATA5GP/GPIO49
PCH_GPIO12 20 TP12 H3 NC
PCH_GPIO24 20 SPIROM_USE_MLB D6
91 59 48 20 BI GPIO57
TP13 AH12
NC
C2151
SPIROM_USE_MLB OUT 20 48 59 91 C40 0.1UF
20 PCH_GPIO68_TACH4 TACH4/GPIO68
(PUs necessary?) TP14 AM4 NC 47 38 35 34 33 28 25 20 19 6
91 78 77 61 50 49
PP3V3_S4 1 2

20 PCH_GPIO69_TACH5 B41 TACH5/GPIO69

TP15 AM5 NC 10%
16V
20 PCH_GPIO70_TACH6 C41 TACH6/GPIO70 X7R-CERM
TP16 Y13 NC 402

20 PCH_GPIO71_TACH7 A40 TACH7/GPIO71

TP17 K24 NC 5
AUD_IPHS_SWITCH_EN_PCH 1 MC74VHC1G08
A4 20 SC70-HF
TP18 L24 NC

RSVD
76 75 74 26 20 17 PP3V3_T29 VSS_NCTF
A44 U2151 4 AUD_IPHS_SWITCH_EN OUT 58
VSS_NCTF
91
A45 TP19 AB46
NC 27 20 18 IN PM_PCH_PWROK 2
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 VSS_NCTF
47 41 40 39 38 37 34 31 30 27
89 79 77 76 74 73 72 71 67 A46 VSS_NCTF TP20 AB45 3
NC
A5 VSS_NCTF
A6 TP21 B21 NC
VSS_NCTF
B3 TP22 M20 NC
R21601 R21841 R21851 R21861 B47
VSS_NCTF
C2152
10K 10K 10K 10K VSS_NCTF
5% 5% 5% 5% BD1 TP24 BG46
NC 0.1UF
1/20W 1/20W 1/20W 1/20W VSS_NCTF
MF MF MF MF BD49 47 38 35 34 33 28 25 20 19 6 PP3V3_S4 1 2
201 2 201 2 201 2 201 2 VSS_NCTF TP25 BE28
NC
91 78 77 61 50 49

BE1 VSS_NCTF 10%

BE49 TP26 BC30
NC
16V
X7R-CERM
VSS_NCTF
B BF1
BF49
VSS_NCTF TP27 BE32
NC
402
B
VSS_NCTF
BG2 TP28 BJ32
NC
5 MC74VHC1G08
JTAG_ISP_TDO 20 74 VSS_NCTF 17 IN T29_PWR_EN_PCH 1 SC70-HF

NCTF
FW_PME_L BG48 TP29 BC28 T29_PWR_EN
FW_PWR_EN
OUT 20 39
BH3
VSS_NCTF NC
PM_PCH_PWROK 2
U2152 4 OUT 76

20 VSS_NCTF 27 20 18 IN
BH47 TP30 BE30
NC
PCH_GPIO0 OUT 20 VSS_NCTF 3
BJ4 VSS_NCTF TP31 BF32
NC
BJ44 VSS_NCTF
BJ45 TP32 BG32
NC
VSS_NCTF
BJ46 VSS_NCTF TP33 AV26
NC 76 75 74 26 20 17 PP3V3_T29
62 20 WOL_EN BJ5 VSS_NCTF
27 25 24 23 21 20 19 18 17 6 PP3V3_S5 BJ6 TP34 BB26
NC
91 89 78 62 61 59 28 VSS_NCTF
C2 TP35 AU28
NOSTUFF NOSTUFF
C48
VSS_NCTF NC R21991
R21141 R21151 R21171 D1
VSS_NCTF
TP36 AY30
NC
10K
5%
10K 10K 10K VSS_NCTF 1/20W
5% 5% 5% D49 MF
1/20W 1/20W 1/20W VSS_NCTF NC_1 P37 NC 201 2
MF MF MF E1
201 2 201 2 201 2 VSS_NCTF
PCH_GPIO15 20 24
E49 VSS_NCTF INIT3_3V* T14 PD_PCH_INIT3V3_L JTAG_ISP_TDI 20 74

PCH_GPIO46 20
F1 VSS_NCTF PCH_GPIO36_SATA2GP 20
OUT AY26 OUT
F49 TP38 NC
VSS_NCTF AU26 NOSTUFF ENET_LOW_PWR_PCH OUT 20

PP3V3_S5 TP37 NC 1 1 NOSTUFF AUD_IPHS_SWITCH_EN_PCH OUT

27 25 24 23 21 20 19 18 17 6
91 89 78 62 61 59 28 AH8 TS_VSS1 TP39 AV28
NC
R2130 R2198 R21161 NOSTUFF
20
91 89
AK11 AW30 1K 10K
61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27
PP3V3_S0
AH10
TS_VSS2 TP40 NC 1%
1/20W
5%
1/20W
10K
5% R21181
79 77 76 74 73 72 71 67 62
TS_VSS3 MF MF 1/20W 10K
R21911 AK10 TS_VSS4
201 2 201 2 MF
201
5%
1/20W
R21751 R21741 R21731 R21721 10K
5% U47
2 MF
201 2
10K 10K 10K 10K
A 5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
1/20W
MF
201 2
VSSADAC

INIT3_3V HAS INTERNAL PULL UP AND SHOULD NOT PULLED LOW.

SYNC_MASTER=REFERENCE_MLB SYNC_DATE=12/07/2010 A
201 2 201 2 201 2 201 2 PAGE TITLE
SMC_SCI_L THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.
OUT 20 46
91
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 PCH MISC
47 41 40 39 38 37 34 31 30 27 DRAWING NUMBER SIZE
89 79 77 76 74 73 72 71 67

NOSTUFF Apple Inc. 051-8768 D

PCH_GPIO68_TACH4 1 1
20 R2196 R2197 R
REVISION
PCH_GPIO69_TACH5 20 10K
5%
10K
5%
9.0.0
PCH_GPIO70_TACH6 20 1/20W 1/20W NOTICE OF PROPRIETARY PROPERTY: BRANCH
MF MF
PCH_GPIO71_TACH7 20 201 2 201 2 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
T29_SW_RESET_L
SMC_RUNTIME_SCI_L
20 76

20 46
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
21 OF 512
OUT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 20 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

VCCACLK pin left as NC per DG

AD49 VCCACLK
NC
U1800
COUGAR-POINT
27 25 24 23 21 20 19 18 17 6 PP3V3_S5 T16 VCCDSW3_3 MOBILE
91 89 78 62 61 59 28 V5REF P34 PP5V_S0_PCH_V5REF 23
FCBGA
TP_PPVOUT_PCH_DCPSUSBYP V12 DCPSUSBYP (8 OF 10)
OMIT VCCSUS3_3_5_GPIO N20 PP3V3_S5 6 17 18 19 20 21 23 24 25 27 28
59 61 62 78 89 91
23 PP3V3_S0_PCH_VCC3_3_CLK_F T38 VCC3_3_4_CLK VCCSUS3_3_6_GPIO N22
VCCSUS3_3_7_GPIO P20
VCCAPLLDMI2 pin left as NC per DG
BH23 VCCAPLLDMI2
NC VCCSUS3_3_8_GPIO P22

PCI/GPIO/
PP1V05_S0_PCH AL29 VCCIO_12_PLLCLK
50 23 21 18 17 7
VCC3_3_2_GPIO AA16 PP3V3_S0 50 51 52 53 57 58 60 61 62 67
6 7 13 17 18 19 20 21 23 24 27 50 23 21 18 17 7 PP1V05_S0_PCH AA23 VCCCORE U1800

LPC
30 31 34 37 38 39 40 41 47 49
AL24 left as NC per DG
AL24 DCPSUS_0_CLK VCC3_3_3_GPIO W16 71 72 73 74 76 77 79 89 91
1.44 A Max, 474mA Idle
AC23 VCCCORE COUGAR-POINT
NC MOBILE CKPLUS_WAIVE
VCC3_3_1_GPIO T34 AD21 VCCCORE VCCALVDS AK36 GROUND WHEN LVDS NOT USED.
50 23 21 18 17 7 PP1V05_S0_PCH AA19 VCCASW_3_CLK FCBGA
AD23 VCCCORE (7 OF 10)
AA21 VCCASW_4_CLK VSSALVDS AK37
VCC3_3_0_SATA AJ2 PP3V3_S0 50 51 52 53 57 58 60 61 62 67
6 7 13 17 18 19 20 21 23 24 27
AF21 VCCCORE OMIT
AA24 VCCASW_5_CLK 30 31 34 37 38 39 40 41 47 49
71 72 73 74 76 77 79 89 91 AF23 VCCCORE CKPLUS_WAIVE
AA26 VCCASW_6_CLK VCCIO_5_PLLSATA AF13 VCCTX_LVDS AM37
AG21

VCC CORE
AA27 VCCCORE CKPLUS_WAIVE
AM38 GROUND WHEN LVDS NOT USED.
VCCASW_7_CLK VCCTX_LVDS

LVDS
VCCIO_15_SATA3 AH13 PP1V05_S0_PCH 7 17 18 21 23 50
AG23 VCCCORE CKPLUS_WAIVE
AA29 VCCASW_8_CLK VCCTX_LVDS AP36
VCCIO_16_SATA3 AH14 AG24 VCCCORE CKPLUS_WAIVE
AA31 VCCASW_9_CLK VCCTX_LVDS AP37
AG26 VCCCORE
AC26 VCCASW_10_CLK VCCIO_9_PLLSATA3 AF14 AG27 VCCCORE

HVCMOS
AC27 VCCASW_11_CLK VCC3_3_6_HVCMOS V33 PP3V3_S0 50 51 52 53 57 58 60 61 62 67
6 7 13 17 18 19 20 21 23 24 27
VCCAPLLSATA AK1 NC AG29
C AC29 VCCASW_12_CLK
VCCAPLLSATA pin left as NC per DG
AJ23
VCCCORE
VCC3_3_7_HVCMOS V34
30 31 34 37 38 39 40 41 47 49
71 72 73 74 76 77 79 89 91
C

CLK/MISC
AC31 VCCCORE
VCCASW_13_CLK VCCVRM_1_SATA AF11 PP1V8_S0

SATA
7 15 18 21 23 26 71
AJ26 VCCCORE
AD29 VCCASW_14_CLK VCCVRM_3_DMI AT16 PP1V8_S0 7 15 18 21 23 26 71
AD31 VCCIO_6_SATA AC16 PP1V05_S0_PCH 7 17 18 21 23 50
AJ27 VCCCORE
VCCASW_15_CLK

DMI
W21 VCCIO_7_SATA AC17 AJ29 VCCCORE VCCDMI_1_DMI AT20 PP1V05_S0_PCH 7 17 18 21 23 50
VCCASW_16_CLK
W23 VCCIO_8_SATA AD17 AJ31 VCCCORE
VCCASW_17_CLK VCCCLKDMI AB36 PP1V05_S0_PCH_VCCCLKDMI_F 23
W24 VCCASW_18_CLK
W26
MISC VCCASW_2_MISC T21 PP1V05_S0_PCH 7 17 18 21 23 50 50 23 21 18 17 7 PP1V05_S0_PCH AN19 VCCIO_11_PLLPCIE
AG16
VCCASW_19_CLK VCCDFTERM PP1V8_S0 7 15 18 21 23 26 71
W29 VCCASW_1_MISC V21
TP_1V05_S0_PCH_VCCAPLLEXP BJ22 AG17

DFT/SPI
VCCASW_20_CLK VCCAPLLEXP VCCDFTERM
W31 VCCASW_0_MISC T19 AJ16
VCCASW_21_CLK AN16 VCCIO_17_FDI VCCDFTERM
W33 50 23 21 18 17 7 PP1V05_S0_PCH AJ17
VCCASW_22_CLK N26 AN17 VCCIO_18_FDI VCCDFTERM
PCH output, for decoupling only VCCIO_0_USB PP1V05_S0_PCH 7 17 18 21 23 50

PPVOUT_G3_PCH_DCPRTC N16 DCPRTC VCCIO_1_USB P26 VCCSPI V1 PP3V3_S5 6 17 18 19 20 21 23 24 25 27 28

MIN_NECK_WIDTH=0.2
MIN_LINE_WIDTH=0.2
mm mm AN21 VCCIO_19_PCIE 59 61 62 78 89 91
VOLTAGE=3.3V VCCIO_2_USB P28
USB

1 C2210 PP1V8_S0 Y49 VCCVRM_0_CLK AN26 VCCIO_20_PCIE

VCCIO
71 26 23 21 18 15 7
T27 VCCADAC U48

CRT
0.1UF VCCIO_3_USB AN27 PP3V3_S0_PCH_VCCA_DAC_F 23
10% VCCIO_21_PCIE
PP1V05_S0_PCH_VCCADPLLA_F BD47 VCCADPLLA VCCIO_4_USB T29
2 16V
23
AP21 VCCIO_22_PCIE
X7R-CERM 23 PP1V05_S0_PCH_VCCADPLLB_F BF47 VCCADPLLB VCCVRM_2_FDI AP16 PP1V8_S0 7 15 18 21 23 26 71
402 VCCSUS3_3_1_USB T23 PP3V3_S5 6 17 18 19 20 21 23 24 25 27 28
AP23 VCCIO_23_PCIE
59 61 62 78 89 91
AF17 VCCIO_13_CLK T24 AP24 VCCAFDIPLL BG6NC

FDI
50 23 21 18 17 7 PP1V05_S0_PCH VCCSUS3_3_2_USB VCCIO_24_PCIE VCCAFDIPLL pin left as NC per DG

VCCSUS3_3_3_USB V23 AP26 VCCIO_25_PCIE

PLACE_NEAR=U1800.N16:2.54mm 50 23 21 18 17 7 PP1V05_S0_PCH AF33 VCCDIFFCLKN_0 VCCIO_10_PLLFDI AP17 PP1V05_S0_PCH 7 17 18 21 23 50
55mA Max, 5mA Idle VCCSUS3_3_4_USB V24 AT24 VCCIO_26_PCIE
AF34 VCCDIFFCLKN_1
VCCSUS3_3_9_USB P24 VCCDMI_0_FDI AU20 PP1V05_S0_PCH 7 17 18 21 23 50
AG34 VCCDIFFCLKN_2 AN33 VCCIO_27_DP

AG33 VCCSSC VCCIO_14_PLLUSB T26 PP1V05_S0_PCH 7 17 18 21 23 50

AN34 VCCIO_28_DP
50 23 21 18 17 7 PP1V05_S0_PCH 91

V16 DCPSST V5REF_SUS M26 PP5V_SUS_PCH_V5REFSUS 23

62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 BH29 VCC3_3_5_PCI
PPVOUT_S0_PCH_DCPSST 47 41 40 39 38 37 34 31 30 27
89 79 77 76 74 73 72 71 67
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V
T17 DCPSUS_1_CLK DCPSUS_3_SUS AN23
NC NC-ed per DG
1 C2222 NC
B 0.1UF
10%
NC-ed per DG
NC
V19 DCPSUS_2_CLK VCCSUS3_3_0_SUS AN24 PP3V3_S5 6 17 18 19 20 21 23 24 25 27 28
59 61 62 78 89 91 B
2 16V
CPU

X7R-CERM 50 23 21 18 17 7 PP1V05_S0_PCH BJ8 V_PROC_IO VCCSUSHDA P32 PP1V5_S0 7 17 23 39 53 71 72 91

402
HDA

10 mA Max, 1mA Idle

A22 VCCRTC
RTC

91 27 18 17 6 PP3V3_G3_RTC
PLACE_NEAR=U1800.V16:2.54mm

1 C2231 1 C2232 1 C2233

1UF 0.1UF 0.1UF
10% 10% 10%
2 10V
X5R 2 16V
X7R-CERM 2 16V
X7R-CERM
402-1 402 402
PLACE_NEAR=U1800.A22:2.54mm
PLACE_NEAR=U1800.A22:2.54mm PLACE_NEAR=U1800.A22:2.54mm

A A
PAGE TITLE

PCH POWER
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
22 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 21 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

AJ3 VSS U1800 VSS AK46

B35 U1800 G48
N24 COUGAR-POINT AK8 VSS VSS
VSS VSS B39 COUGAR-POINT H10
BG29 MOBILE AL16 VSS VSS
VSS VSS B43 MOBILE H12
H5 FCBGA AL17 VSS FCBGA VSS
VSS VSS B7 H16
AA17 (9 OF 10) AL19 VSS (10 OF 10) VSS
VSS VSS
D AA2
AA3
VSS
VSS
OMIT VSS AL2
AL21
BB12
BB16
VSS
VSS
VSS
OMIT
VSS
VSS
H18
H22 D
VSS VSS BB20 H24
AA33 AL23 VSS VSS
VSS VSS BB22 H26
AA34 AL26 VSS VSS
VSS VSS BB24 H30
AB11 AL27 VSS VSS
VSS VSS BB28 H32
AB14 AL31 VSS VSS
VSS VSS BB30 H34
AB39 AL33 VSS VSS
VSS VSS BB38 H46
AB4 AL34 VSS VSS
VSS VSS BB4 K18
AB43 AL48 VSS VSS
VSS VSS BB46 K26
AB5 AM11 VSS VSS
VSS VSS BC14 K39
AB7 AM14 VSS VSS
VSS VSS BC18 K46
AC19 AM36 VSS VSS
VSS VSS BC2 K7
AC2 AM39 VSS VSS
VSS VSS BC22 L18
AC21 AM43 VSS VSS
VSS VSS BC26 L2
AC24 AM45 VSS VSS
VSS VSS BC32 L20
AC33 AM46 VSS VSS
VSS VSS BC34 L26
AC34 AM7 VSS VSS
VSS VSS BC36 L28
AC48 AN2 VSS VSS
VSS VSS BC40 L36
AD10 AN29 VSS VSS
VSS VSS BC42 L48
AD11 AN3 VSS VSS
VSS VSS BC48 M12
AD12 AN31 VSS VSS
VSS VSS BD3 M14
AD13 AP12 VSS VSS
VSS VSS BD46 M18
AD14 AP13 VSS VSS
VSS VSS BD5 M22
AD16 AP19 VSS VSS
VSS VSS BE10 M24
AD19 AP28 VSS VSS
VSS VSS BE22 M30
AD24 AP30 VSS VSS
VSS VSS BE26 M32
AD26 AP32 VSS VSS
C AD27
VSS
VSS
VSS
VSS AP38
BE40
BF10
VSS
VSS
VSS
VSS
M34
M38
C
AD33 VSS VSS AP4
BF12 VSS VSS M4
AD34 VSS VSS AP42
BF16 VSS VSS M42
AD36 VSS VSS AP46
BF20 VSS VSS M46
AD37 VSS VSS AP8
BF22 VSS VSS M8
AD38 VSS VSS AR2
BF24 VSS VSS N18
AD39 VSS VSS AR48
BF26 VSS VSS N47
AD4 VSS VSS AT11
BF28 VSS VSS P11
AD40 VSS VSS AT13
BF30 VSS VSS P16
AD42 VSS VSS AT18
BF38 VSS VSS P18
AD43 VSS VSS AT22
BF40 VSS VSS P30
AD45 VSS VSS AT26
BF8 VSS VSS P40
AD46 VSS VSS AT28
BG17 VSS VSS P43
AD47 VSS VSS AT30
BG21 VSS VSS P47
AD8 VSS VSS AT32
BG22 VSS VSS P7
AE2 VSS VSS AT34
BG24 VSS VSS R2
AE3 VSS VSS AT39
BG33 VSS VSS R48
AF10 VSS VSS AT42
BG41 VSS VSS T12
AF12 VSS VSS AT46
BG44 VSS VSS T31
AF16 VSS VSS AT7
BG8 VSS VSS T33
AF19 VSS VSS AU24
BH11 VSS VSS T36
AF24 VSS VSS AU30
BH15 VSS VSS T37
AF26 VSS VSS AV11
BH17 VSS VSS T4
AF27 VSS VSS AV16
BH19 VSS VSS T46
AF29 VSS VSS AV20
BH27 VSS VSS T47
AF31 VSS VSS AV24
BH31 T8
B AF38
AF4
VSS VSS AV30
AV38
BH33
VSS
VSS
VSS
VSS V11 B
VSS VSS BH35 V26
AF42 AV4 VSS VSS
VSS VSS BH39 V27
AF46 AV43 VSS VSS
VSS VSS BH43 V29
AF5 AV8 VSS VSS
VSS VSS BH7 V31
AF7 AW14 VSS VSS
VSS VSS C22 V36
AF8 AW18 VSS VSS
VSS VSS D12 V39
AG19 AW2 VSS VSS
VSS VSS D16 V43
AG2 AW22 VSS VSS
VSS VSS D18 V7
AG31 AW26 VSS VSS
VSS VSS D22 W17
AG48 AW28 VSS VSS
VSS VSS D24 W19
AH11 AW32 VSS VSS
VSS VSS D26 W2
AH3 AW34 VSS VSS
VSS VSS D3 W27
AH36 AW36 VSS VSS
VSS VSS D30 W34
VSS VSS
www.teknisi-indonesia.com
AH39 VSS VSS AW40
D32 VSS VSS W48
AH40 VSS VSS AW48
D34 VSS VSS Y12
AH42 VSS VSS AY12
D38 VSS VSS Y38
AH46 VSS VSS AY22
D42 VSS VSS Y4
AH7 VSS VSS AY28
D8 VSS VSS Y42
AJ19 VSS VSS AY4
E18 VSS VSS Y46
AJ21 VSS VSS AY42
E26 VSS VSS Y8
AJ24 VSS VSS AY46
F3 VSS VSS V17
AJ33 VSS VSS AY8
F45 VSS VSS AP3
AJ34 VSS VSS B11
G14 VSS VSS AP1
AK12 VSS VSS B15
G18 VSS VSS BE16
AK3 B19
A AK38
VSS
VSS
VSS
VSS B23
G20
G26
VSS
VSS
VSS
VSS
BC16
BG28 SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
AK4 VSS VSS B27 PAGE TITLE
G28 VSS VSS BJ28
AK42 VSS VSS B31
G36 VSS
PCH GROUNDS
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
23 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 22 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
PCH VCCSUS3_3 BYPASS PCH VCCIO BYPASS
L2406 PP1V8_S0 PP1V05_S0_PCH (PCH USB 1.05V PWR)
10UH-100MA (PCH SUSPEND USB 3.3V PWR) 71 26 21 18 15 7 50 23 21 18 17 7
50 23 21 18 17 7 PP1V05_S0_PCH
27 25 24 23 21 20 19 18 17 6 PP3V3_S5
50 23 21 18 17 7
1
PP1V05_S0_PCH 2 PP1V05_S0_PCH_VCCCLKDMI_R
MIN_LINE_WIDTH=0.5MM
PP1V05_S0_PCH_VCCCLKDMI_F
MIN_LINE_WIDTH=0.5MM
21 91 89 78 62 61 59 28 1 C2440 1 C2444 1 C2452
0805 0.1UF 1 C2446
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V R2415 MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V 1 C2484 1 C2413 PLACE_NEAR=U1800.AJ16:2.54mm 10% 1UF 1UF
1UF
1 MAKE_BASE=TRUE 0.1UF 0.1UF 2 16V
X7R-CERM
10% 10% PLACE_NEAR=U1800.P28:2.54mm
1 2 402 2 10V
X5R 2 10V
X5R
10%
10% 10% 2 10V
5% 2 16V
X7R-CERM 2 16V
X7R-CERM
402-1 402-1 X5R
402-1
1/16W
MF-LF
402
1 C2411 402 402
1UF PLACE_NEAR=U1800.P24:2.54mm
PLACE_NEAR=U1800.AH13:2.54mm
10% PLACE_NEAR=U1800.AC17:2.54mm
2 16V
X5R PCH VCCSUSHDA BYPASS
PLACE_NEAR=U1800.AB36:2.54mm

D
402 PLACE_NEAR=U1800.V24:2.54mm
D
91 72 71 53 39 21 17 7 PP1V5_S0
PP3V3_S5
1 C2441 50 23 21 18 17 7 PP1V05_S0_PCH 27 25 24 23 21 20 19 18 17 6
91 89 78 62 61 59 28

PLACE_NEAR=U1800.P32:2.54mm 0.1UF
10%
2 16V 1 C2475
1 C2476
PP1V05_S0_PCH X7R-CERM 1UF
50 23 21 18 17 7 402 1UF 10%
10% 10V
2 X5R
2 10V
X5R PLACE_NEAR=U1800.P22:2.54mm 402-1
PLACE_NEAR=U1800.AG33:2.54mm 402-1
C2416 1 1 C2417 1 C2430
4.7UF 0.1UF 0.1UF
20% 10% 10%
6.3V 2 2 16V 2 16V
PLACE_NEAR=U1800.BJ8:2.54mm
X5R X7R-CERM X7R-CERM
PLACE_NEAR=U1800.BJ8:2.54mm
402 402 402
PLACE_NEAR=U1800.BJ8:2.54mm 27 25 24 23 21 20 19 18 17 6 PP3V3_S5
91 89 78 62 61 59 28

1 C2442
1UF
10%
R2450 PLACE_NEAR=U1800.V1:2.54mm
2 10V
X5R 50 23 21 18 17 7 PP1V05_S0_PCH
91 0 402-1
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 1 2 PP3V3_S0_PCH_VCCA_DAC_F 21 50 23 21 18 17 7 PP1V05_S0_PCH
47 41 40 39 38 37 34 31 30 27 MAKE_BASE=TRUE
89 79 77 76 74 73 72 71 67
5%
1/20W
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM 1 C2434
1 C2469
MF VOLTAGE=3.3V
PCH VCCIO BYPASS
1UF
201 1UF 10%
PLACE_NEAR=U1800.AF34:2.54mm 10%
10V 2 10V
X5R
50 23 21 18 17 7 PP1V05_S0_PCH 2 X5R 402-1
402-1 PLACE_NEAR=U1800.AF17:2.54mm
1 C2419
1UF
C2450 1 C2451 1 C2455 1 10%
10V
2 X5R PP3V3_S5
10UF 0.1UF 0.01UF 402-1
27 25 24 23 21 20 19 18 17 6
91 89 78 62 61 59 28
20% 10% 10%
6.3V 2 16V 50V 2
C X5R
603
X7R-CERM 2
402
X7R
402 C2499 1
0.1UF PCH VCCCORE BYPASS
C
PLACE_NEAR=U1800.T16:2.54mm 10% (PCH 1.05V CORE PWR)
PCH VCC3_3 BYPASS 16V 50 23 21 18 17 7 PP1V05_S0_PCH
PLACE_NEAR=U1800.U48:2.54mm (PCH PCI 3.3V PWR)
X7R-CERM 2
PLACE_NEAR=U1800.U48:2.54mm
402
PLACE_NEAR=U1800.U48:2.54mm
1 C2481 1 C2482 1 C2483 1 C2460
PLACE_NEAR=U1800.AT20:2.54mm
1UF 1UF 1UF 10UF
10% 10% 10% 20%
2 10V
X5R 2 10V
X5R 2 10V
X5R 2 6.3V
X5R
91 402-1 402-1 402-1 603
89 79 77 76 74 73 72 71 67
62 61 60 58 57 53 52 51 50 49
PP3V3_S0
24 23 21 20 19 18 17 13 7
47 41 40 39 38 37 34 31 30
6
27
PP5V_S0
L2451
68 67 64 62 61 48 42 41 24
91 80 71 70
7
69
PCH V5REF Filter & Follower
R2451 10UH-0.12A-0.36OHM PLACE_NEAR=U1800.AD21:2.54mm
PLACE_NEAR=U1800.AG26:2.54mm
1 mA (PCH Reference for 5V Tolerance on PCI)
91 1 1 2 PLACE_NEAR=U1800.AG24:2.54mm
1
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 1 2 PP3V3_S0_PCH_VCC3_3_CLK_R PP3V3_S0_PCH_VCC3_3_CLK_F 21 PLACE_NEAR=U1800.AJ27:2.54mm
R2405 2

5 D2400
47 41 40 39 38 37 34 31 30 27
89 79 77 76 74 73 72 71 67 5%
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.075 MM 0603 MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.075 MM
100 NC 1/16W VOLTAGE=3.3V VOLTAGE=3.3V
5% BAT54DW-X-G MF-LF C2453 1 C2454 1
NC

1/16W SOT-363 402

MF-LF 6 10UF 1UF
402 20% 10%
1 6.3V 2 10V
NEED PWR CONSTRAINT X5R X5R 2
PP5V_S0_PCH_V5REF 21
603 402-1 50 23 21 18 17 7 PP1V05_S0_PCH
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM <1 MA
VOLTAGE=5V
C2439 1 MAKE_BASE=TRUE PLACE_NEAR=U1800.T38:2.54mm
1UF PLACE_NEAR=U1800.T38:2.54mm
PLACE_NEAR=U1800.P34:2.54mm
10%
10V 2
X5R
1 C2426 1 C2456 1 C2496 1 C2428 1 C2420
402-1 1UF 1UF 1UF 22UF 22UF
10% 10% 10% 20% 20%
2 10V
X5R 2 10V
X5R 2 10V
X5R 2 6.3V 6.3V
X5R-CERM1 2 X5R-CERM1
PCH VCCADPLLA Filter 402-1 402-1 402-1 0603 0603
(PCH DPLLA PWR)
L2490 PP1V05_S0_PCH_VCCADPLLA_F
27 25 24 23 21 20 19 18 17 6 PP3V3_S5 R2490 10UH-0.12A-0.36OHM MIN_LINE_WIDTH=0.4 MM
21

91 89 78 62 61 59 28 0 1 2 MIN_NECK_WIDTH=0.2 MM 68 mA
50 23 21 18 17 7 PP1V05_S0_PCH
1 2 PP1V05_S0_PCH_VCCADPLLA_R VOLTAGE=1.05V
61 6 PP5V_S5 PCH V5REF_SUS Filter & Follower MIN_LINE_WIDTH=0.4MM
B 1 mA S0-S5
4
(PCH Reference for 5V Tolerance on USB)
5%
1/16W
MF-LF
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.05V
0603
C2491 1 1
NO STUFF
C2492
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm PLACE_NEAR=U1800.AC27:2.54mm
B
R2404 2

2 D2400
402
220UF 1UF
10%
PLACE_NEAR=U1800.AC27:2.54mm
10 NC CRITICAL 20% 10V
5% BAT54DW-X-G 2.5V 2 2 X5R
NC

1/16W SOT-363 POLY-TANT 402-1

MF-LF 3 CASE-B2-SM1
402 1
NEED PWR CONSTRAINT PLACE_NEAR=U1800.BD47:2.54MM
PLACE_NEAR=U1800.BD47:2.54MM
PP5V_SUS_PCH_V5REFSUS 21
MIN_LINE_WIDTH=0.3MM 50 23 21 18 17 7 PP1V05_S0_PCH
MIN_NECK_WIDTH=0.25MM <1 MA S0-S5
VOLTAGE=5V
C2438 1 MAKE_BASE=TRUE
PCH VCCADPLLB Filter
0.1UF
10% (PCH DPLLB PWR)
PLACE_NEAR=U1800.M26:2.54mm
16V
X7R-CERM 2 L2491 PP1V05_S0_PCH_VCCADPLLB_F 1 C24291 C2414 1 C24071 C2463 1 C2401
402 R2491 10UH-0.12A-0.36OHM MIN_LINE_WIDTH=0.4 MM
21
1UF 1UF 1UF 1UF 10UF
0 MIN_NECK_WIDTH=0.2 MM
1 2 PP1V05_S0_PCH_VCCADPLLB_R1 2 VOLTAGE=1.05V 69 mA 10% 10% 10% 10% 20%
MIN_LINE_WIDTH=0.4MM 0603 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 6.3V
X5R
5%
1/16W
MIN_NECK_WIDTH=0.2MM NO STUFF 402-1 402-1 402-1 402-1 603
VOLTAGE=1.05V
MF-LF
402 C2493 1 1 C2494
220UF 1UF
CRITICAL 20% 10%
2.5V 2 2 10V
X5R
91 POLY-TANT 402-1
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 91
CASE-B2-SM1
47 41 40 39 38 37 34 31 30 27 PLACE_NEAR=U1800.BF47:2.54MM PLACE_NEAR=U1800.AN27:2.54mm
89 79 77 76 74 73 72 71 67 62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 PLACE_NEAR=U1800.AN27:2.54mm
47 41 40 39 38 37 34 31 30 27 PLACE_NEAR=U1800.BF47:2.54MM PLACE_NEAR=U1800.AN27:2.54mm PLACE_NEAR=U1800.AN27:2.54mm
89 79 77 76 74 73 72 71 67
PLACE_NEAR=U1800.AN27:2.54mm
1 C2421 1 C2423
0.1UF
10%
16V
0.1UF
2 X7R-CERM 10%
402 2 16V
X7R-CERM
PLACE_NEAR=U1800.AJ2:2.54mm 402
PLACE_NEAR=U1800.BH29:2.54mm

A 91
SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 PAGE TITLE
47 41 40 39 38 37 34 31 30 27
89 79 77 76 74 73 72 71 67
PCH DECOUPLING
1 C2424 91
62 61 60 58 57 53 52 51 50 49
PP3V3_S0 DRAWING NUMBER SIZE
0.1UF 24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27 051-8768 D
10%
2 16V
89 79 77 76 74 73 72 71 67
Apple Inc. REVISION
X7R-CERM
402
1 C2486 1 C2485 R
9.0.0
PLACE_NEAR=U1800.V33:2.54mm 0.1UF 0.1UF
10% 10% NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 25V
X5R 2 25V
X5R
402 402 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PLACE_NEAR=U1800.T34:2.54mm
PLACE_NEAR=U1800.AA16:2.54mm
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
24 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 23 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Mini-XDP Connector DESIGN NOTE:

NOTE: This is not the standard XDP pinout.

ODT AVAILABLE ON JTAG
USE WITH 920-0620 ADAPTER BOARD TO SUPPORT CPU, PCH DEBUGGING. PP1V05_S0 7 24 46 50 62 70 76

PLACEMENT NOTE:
76 70 62 50 46 24 7 PP1V05_S0
PLACE TDO TERM NEAR

67 62 61 60 58 57 53 52 51 50
27 23 21 20 19 18 17 13 7 6 PP3V3_S0 SNB XDP CONN

49 47 41 40 39 38 37 34 31 30
91 89 79 77 76 74 73 72 71
CRITICAL R25101 R25111 R25121
NOSTUFF
1 51 51 10K
R2540 XDP_CONN 5% 5% 5%
1/16W 1/16W 1/16W
1K J2500 MF-LF MF-LF MF-LF
5% 402 2 402 2 402 2
1/16W ASP-129667-02
MF-LF F-ST-SM PLACE_NEAR=J2500:5MM PLACE_NEAR=U1000.M60:5MM PLACE_NEAR=U1000.L55:5MM
402 2
D 2
4
1
3
81 24 11 XDP_CPU_TDO D
81 11 BI XDP_CPU_PREQ_L OBSFN_A0 OBSFN_C0 NC_OBSFN_C0 91 81 24 11 XDP_CPU_TDI
81 11 XDP_CPU_PRDY_L OBSFN_A1
6 5 OBSFN_C1 PCH_GPIO15 20 81 24 11 XDP_CPU_TMS
IN IN
8 7 81 24 11 XDP_CPU_TCK
81 11 XDP_BPM_L<0> OBSDATA_A0
10 9 OBSDATA_C0 AP_PWR_EN 19 35 62 81 24 11 XDP_CPU_TRST_L
IN IN
81 11 XDP_BPM_L<1> OBSDATA_A1
12 11 OBSDATA_C1 USB_HUB_SOFT_RESET_L 19 25
IN IN
14 13 PLACE_NEAR=U1000.J58:5MM PLACE_NEAR=U1000.L56:5MM

16 15
81 11 IN XDP_BPM_L<2> OBSDATA_A2

18 17
OBSDATA_C2 T29_DP_PORTA_PWR_EN IN 19 78
R25131 R25141
81 11 IN XDP_BPM_L<3> OBSDATA_A3 OBSDATA_C3 ENET_PWR_EN 19 51 51
20 19 5% 5%
1/16W 1/16W
22 21 MF-LF MF-LF
91 NC_OBSFN_B0 OBSFN_B0 OBSFN_D0 NC_OBSFN_D01 91 402 2 402 2
PLACEMENT NOTE:
91 NC_OBSFN_B1 OBSFN_B1
24 23 OBSFN_D1 NC_OBSFN_D11 91
PLACE TCK/TDI/TMS/TRST*
26 25 TERM NEAR CPU

81 11 XDP_BPM_L<4> OBSDATA_B0
28 27 OBSDATA_D0 PCH_GPIO43_OC4_L 19
IN IN
81 11 XDP_BPM_L<5> OBSDATA_B1
30 29 OBSDATA_D1 SDCONN_STATE_CHANGE 19 34
IN IN
32 31
81 11 XDP_BPM_L<6> OBSDATA_B2
34 33 OBSDATA_D2 PCH_GPIO10_OC6_L 19
IN IN
81 11 XDP_BPM_L<7> OBSDATA_B3
36 35 OBSDATA_D3 PCH_GPIO14_OC7_L 19 XDP
IN IN
38 37 R2515
XDP 40 39 0
PLACE_NEAR=U1000.B46:1MM
R2500 81 XDP_CPU_PWRGD PWRGD/HOOK0 ITPCLK/HOOK4 81 XDP_CPU_CLK100M_P 1 2 ITPXDP_CLK100M_P IN 17 81

1K 81 XDP_CPU_PWRBTN_L HOOK1
42 41 ITPCLK#/HOOK5 81 XDP_CPU_CLK100M_N 5% 1/16W MF-LF 402
PLACE_NEAR=R1841.1:2.54MM

81 20 11 IN CPU_PWRGD 5% 1 21/16W
44 43
MF-LF
VCC_OBS_AB VCC_OBS_CD XDP
402 XDP 81 XDP_CPU_CFG<0> HOOK2
46 45 RESET#/HOOK6 81 XDP_CPURST_L R2516
PLACE_NEAR=U4900.D10:2.54MM
R2502 81 XDP_VR_READY 48 47 XDP_DBRESET_L 1 2
0 ITPXDP_CLK100M_N
HOOK3 DBR#/HOOK7 OUT 11 27 81 IN 17 81
0 50 49
46 18 OUT PM_PWRBTN_L 5% 1 21/16W NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28 5% 1/16W MF-LF 402
PLACE_NEAR=R1840.1:2.54MM

MF-LF 49 =SMBUS_XDP_SDA SDA

52 51 TDO XDP_TDO 24 81 XDP
402 BI IN
XDP =SMBUS_XDP_SCL 54 53 XDP_CPU_TRST_L R2505 PLACE_NEAR=R1125.1:2.54MM

C PLACE_NEAR=U1000.B50:2.54MM
R2501
1K
81 24 17
49 IN
OUT XDP_PCH_TCK
SCL

TCK1
56 55
TRSTn

TDI XDP_TDI
OUT
OUT
11 24 81

24 81 1
1K 2 CPU_RESET_L IN 11 27
C
81 10 CPU_CFG<0> 5% 1 21/16W 81 24 11 XDP_CPU_TCK TCK0
58 57 TMS XDP_TMS 24 81 5%
OUT OUT OUT 1/16W
MF-LF 60 59 XDP_PRESENT# XDP_PRESENT_L 24 81 MF-LF
402 XDP 402 27 25 24 23 21 20 19 18 17 6 PP3V3_S5
R2504 XDP XDP 91 89 78 62 61 59 28

PM_PCH_SYS_PWROK 1% 1
332 21/16W C2500 1 1 C2501 XDP
27 18 OUT 0.1UF 516S0852 0.1UF
MF-LF 10%
16V
10% R25301
402 X7R-CERM 2 2 16V
X7R-CERM 10K
402 402 5%
1/16W
MF-LF 2
402 2 XDP
PLACE_NEAR=U2520:5MM.
Q2530
81 XDP_RES_RL 1 BC856BW-X-F
XDP 65V-100MA
SOT323
R25311 3 PLACE_NEAR=U2520:5MM.

10K
5% XDP_SEL 24
1/16W
MF-LF 1XDP
402 2 R2532
R2520 27 25 24 23 21 20 19 18 17 6 PP3V3_S5 PLACE_NEAR=U2520:5MM. 10K
91 89 78 62 61 59 28 5%
XDP_TDI 1
0 2 XDP_PCH_TDI XDP_PRESENT_L 1/16W
81 24 OUT 17 24 81 81 24 MF-LF
5% 2 402
1
1/16W
MF-LF Q2550 R2553 PLACE_NEAR=U2520:5MM.

402
PCH 21.5K

1
PLACE_NEAR=J2500:10MM
27 25 24 23 21 20 19 18 17 6 PP3V3_S5 PLACE_NEAR=J2500:10MM (TCK) 24 17 OUT XDP_PCH_TMS 67 64 62 61 48 42 41 24 23 7 PP5V_S0 SSM3K15FV 1%
91 89 78 62 61 59 28 XDP 81 91 80 71 70 69 68 1/16W

G
U2520 SOD-VESM-HF MF-LF
PLACE_NEAR=U1800:10MM
2 402
14SN74LV4066A
QFN1
PLACE_NEAR=U1800:5MM

D
A 1
S5 RAIL 76 70 62 50 46 24 7 PP1V05_S0 PP1V05_S5_PCH
VOLTAGE=1.05V

3
2
24 XDP_SEL 13 S MIN_LINE_WIDTH=0.2 MM
B 2 XDP_PCH_TDO IN 17 24 81 MIN_NECK_WIDTH=0.1 MM

B 7 15
3 D
1
R2557 1 C2557 B
XDP_NOT 10K 0.1UF
10%
1
R2521 Q2520 1%
1/16W 2 16V
X7R-CERM
0 SSM3K15FV MF-LF 402
5% SOD-VESM-HF 2 402
PLACE_NEAR=U1800:5MM
PLACE_NEAR=U1800:5MM

XDP 1/16W PLACE_NEAR=U1000:10MM

U2520 MF-LF
2 402
2 S G 1
CKPLUS_WAIVE
14SN74LV4066A
QFN1
PLACE_NEAR=U2520:5MM
PP5V_S0 7 23 24 41 42 48 61 62 64 67 68
69 70 71 80 91

ICT_SEL 5 A 4
24 S 3 XDP_CPU_TDI
B OUT 11 24 81
PP1V05_S0
76 70 62 50 46 24 7

CKPLUS_WAIVE
7 15
CKPLUS_WAIVE

R2524
XDP
U2520
(TCK) CPU 24 11
81 OUT XDP_CPU_TMS 1
5%
0 2 XDP_TMS IN 24 81 PLACEMENT NOTE:

CKPLUS_WAIVE
14SN74LV4066A 1/16W
PLACE TDO TERM NEAR

QFN1 PCH XDP CONN

A 11 R2522 S0 RAIL MF-LF

24 XDP_SEL 12 S 10 0
402
PLACE_NEAR=U1000:5MM
R25501 R25511 R25521
B 1 2 XDP_CPU_TDO IN 11 24 81 10K 51 51
5% 5% 5%
5% 1/16W 1/16W 1/16W
7 15 1/16W MF-LF MF-LF MF-LF
CKPLUS_WAIVE CKPLUS_WAIVE MF-LF 402 2 402 2 402 2
402
PLACE_NEAR=J2500:10MM PLACE_NEAR=U2520:5MM. PLACE_NEAR=U1800.H7:2.54MM
81 24 XDP_TDO PLACE_NEAR=U1800.K5:2.54MM

81 24 17 XDP_PCH_TDO
81 24 17 IN XDP_PCH_TCK 81 24 17 XDP_PCH_TDI
XDP 81 24 17 XDP_PCH_TMS
U2520 XDP_NOT 81 24 17 XDP_PCH_TCK
CKPLUS_WAIVE
14SN74LV4066A 1
QFN1 R2523
A 24 ICT_SEL 6 S
A 8
9
0
5%
ICT_SEL 24
SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/30/2010 A
B 1/16W
MF-LF XDP R25561 PAGE TITLE
2 402 51
CKPLUS_WAIVE
7 15
CKPLUS_WAIVE
PLACE_NEAR=U2520:5MM
1
R2526 ICT NEEDS TO DRIVE THIS HIGH 5%
1/16W
CPU & PCH XDP
1K TO ENABLE SERIAL JTAG. MF-LF DRAWING NUMBER SIZE
5% 402 2
81 24 11 IN XDP_CPU_TCK 1/16W
MF-LF PLACE_NEAR=U1800.J3:2.54MM Apple Inc. 051-8768 D
2 402 R
REVISION
PLACE_NEAR=U2520:5MM
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
PLACEMENT NOTE: THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
PLACE TCK/TDI/TMS/TRST* THE POSESSOR AGREES TO THE FOLLOWING: PAGE
TERM NEAR PCH
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
25 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 24 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

BYPASS=U2600.5::5mm
35 34 33 28 25 20 19 6 PP3V3_S4 BYPASS=U2600.34::2mm
91 78 77 61 50 49 47 38
BYPASS=U2600.23::2mm
BOM TABLE
C2602 1 C2603 1 C2611 1 C2612 1 BYPASS=U2600.15::2mm PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_HEAD

4.7UF 0.1UF 0.1UF 0.1UF

10% 10% 10% 10% TABLE_5_ITEM

6.3V 16V 16V 16V 338S0824 2 SMSC USB2514B U2600,U2650 CRITICAL USBHUB_2514B
X5R-CERM 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM 2
603 402 402 402 TABLE_5_ITEM

338S0923 2 SMSC USB2513B U2600,U2650 CRITICAL USBHUB_2513B

D
BYPASS=U2600.23::5mm
BYPASS=U2600.29::2mm
BYPASS=U2600.5::2mm
D
BYPASS=U2600.10::2mm
C2607 1 C2608 1 C2609 1 C2610 1 PPUSB_HUB1_CRFILT
MIN_LINE_WIDTH=0.4MM
4.7UF 0.1UF 0.1UF 0.1UF MIN_NECK_WIDTH=0.2MM
10% 10% 10% 10% VOLTAGE=1.8V
6.3V
X5R-CERM 2
16V
X7R-CERM 2
16V
X7R-CERM 2
16V
X7R-CERM 2 PPUSB_HUB1_PLLFILT
1 C2617 1 C2618
603 402 402 402 MIN_LINE_WIDTH=0.4MM 0.1UF 1UF
MIN_NECK_WIDTH=0.2MM 10% 10%

10
15
23
29
36

14

34
2 16V 2 16V

5
VOLTAGE=1.8V
CRITICAL
1 C2615 1 C2616 X7R-CERM
402
X5R
402
0.1UF 1UF

CRFILT

PLLFILT
VDD33 10% 10%
Y2600 16V
2 X7R-CERM 16V
2 X5R
24.000M-60PPM-16PF 402 402
1 2
CRITICAL CRITICAL SYM VER 1

C2619 1
5X3.2X1.4-SM
1 C2620 U2600
18PF R2630 18PF USB2513B
5%
50V 1M 5% R2605 QFN PP3V3_S4
CERM 2 1 2 2 50V
CERM 100 11 OMIT_TABLE 6 19 20 25 28 33 34 35 38 47 49
NOSTUFF 402 402 1 2 USB_HUB1_TEST TEST USBDM_DN1/PRT_DIS_M1 1 USB_IR_N BI 44 83 50 61 77 78 91
5% IR Receiver
1/16W 5% USBDP_DN1/PRT_DIS_P1 2 USB_IR_P BI 44 83
R26011 1
R2603 MF-LF
402
1/16W
MF-LF
25 USB_HUB_RESET_L 26 RESET* CRITICAL
10K 10K 402 33 USBDM_DN2/PRT_DIS_M2 3 USB_EXTC_N BI 43 83
1
R2621 1
R2622
5% 5% CRITICAL USB_HUB1_XTAL1 XTALIN/CLKIN External C
1/16W 1/16W 32 USBDP_DN2/PRT_DIS_P2 4 USB_EXTC_P BI 43 83 10K 10K
MF-LF MF-LF USB_HUB1_XTAL2 XTALOUT 5% 5%
402 2 2 402 6 1/16W 1/16W
28 USBDM_DN3/PRT_DIS_M3 USB_EXTB_N BI 43 83 MF-LF MF-LF
USB_HUB1_NONREM0 SUSP_IND/LOCAL_PWR/NON_REM0 7 External B 2 402 2 402
USBDP_DN3/PRT_DIS_P3 USB_EXTB_P BI 43 83

USB_HUB1_NONREM1 22 SDA/SMBDATA/NON_REM1
NC 8 PU_USB1_PRT4N
USB_HUB1_CFG_SEL0 24 SCL/SMBCLK/CFG_SEL0 NC 9 PU_USB1_PRT4P
NOSTUFF DISABLE PORT ON 4 PORT HUB.
R26021 1
R2604 USB_HUB1_CFG_SEL1 25 HS_IND/CFG_SEL1 PRTPWR1/BC_EN1* 12
16
TP_USB_HUB1_PRTPWR1
10K 10K PRTPWR2/BC_EN2* TP_USB_HUB1_PRTPWR2
C 5%
1/16W
MF-LF
5%
1/16W
MF-LF 1
R2606 1R2607
PRTPWR3/BC_EN3* 18
20
TP_USB_HUB1_PRTPWR3 PP3V3_S4 6 19 20 25 28 33 34 35 38 47 49
50 61 77 78 91
C
402 2 2 402 NC TP_USB_HUB1_PRTPWR4
10K 10K
5% 5% 13
1/16W 1/16W OCS1* TP_USB_HUB1_OCS1 1
MF-LF
2 402
MF-LF
2 402
IPU
OCS2* 17 USB_EXTC_OC_L IN 43
R2620
IPU
19 10K
IPU
OSC3* USB_EXTB_OC_L IN 43 5%
21 1/16W
NC TP_USB_HUB1_OCS4 MF-LF
IPU
2 402 47 38 35 34 33 28 25 20 19 6PP3V3_S4
91 78 77 61 50 49
RBIAS 35 USB_HUB1_RBIAS R2640
20K
VBUS_DET 27 USB_HUB1_VBUS_DET 28 27 24 23 21 20 19 18 17 6PP3V3_S5
91 89 78 62 61 59
1 2
CKPLUS_WAIVE
CRITICAL 5%
BYPASS=U2650.5::5mm USBDM_UP 30 USB_HUB1_UP_N BI 19 83
1
R2600 1/16W
MF-LF
35 34 33 28 25 20 19 6PP3V3_S4 BYPASS=U2650.23::2mm USBDP_UP 31 USB_HUB1_UP_P BI 19 83 12K 402 1
R2641
91 78 77 61 50 49 47 38 1%
BYPASS=U2650.34::2mm THRM_PAD 1/16W 10K
MF 1 5%
BYPASS=U2650.15::2mm 2 402 R2642 NOSTUFF 1/16W
C2652 1 C2653 1 C2661 1 C2662 1

37
MF-LF
4.7UF 0.1UF 0.1UF 0.1UF 100K
5%
1 C2641 2 402
10%
6.3V
10%
16V
10%
16V
10%
16V 1/16W 100PF
5%
X5R-CERM 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM 2 MF-LF
402 2 2 50V
603 402 402 402 CERM USB_HUB_RESET
402 USB_HUB_RESET_L 25
6
3
D
BYPASS=U2650.23::5mm
BYPASS=U2650.10::2mm
Q2640 D
Q2640
2
2N7002DW-X-G
P3V3S3_EN_RC G S SOT-363 5 G
2N7002DW-X-G
BYPASS=U2650.29::2mm S SOT-363
BYPASS=U2650.5::2mm
1
C2657 1 C2658 1 C2659 1 C2660 1 PPUSB_HUB2_CRFILT
MIN_LINE_WIDTH=0.4MM 1 C2640 4
4.7UF 0.1UF 0.1UF 0.1UF MIN_NECK_WIDTH=0.2MM
10% 10% 10% 10% VOLTAGE=1.8V 0.47UF
6.3V
X5R-CERM 2
16V
X7R-CERM 2
16V
X7R-CERM 2
16V
X7R-CERM 2 PPUSB_HUB2_PLLFILT
1 C2667 1 C2668 10%
2 6.3V
B 603 402 402 402 MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
0.1UF
10%
1UF
10%
CERM-X5R
402 B
10
15
23
29
36

14

34
2 16V 2 16V
5

VOLTAGE=1.8V
CRITICAL
1 C2665 1 C2666 X7R-CERM
402
X5R
402
CRFILT
0.1UF 1UF

PLLFILT
VDD33 10% 10%
Y2650 2 16V
X7R-CERM 2 16V
X5R D2600
24.000M-60PPM-16PF 402 402 SOD-523
1 2
CRITICAL CRITICAL SYM VER 1 24 19 USB_HUB_SOFT_RESET_L 2 1
IN

C2669 1
5X3.2X1.4-SM
1 C2670 U2650
USB2513B BAT54XV2T1
18PF
5%
R2680 5%
18PF
R2655
50V 1M 50V QFN PP3V3_S4
CERM 2 1 2 2 CERM 100 11 OMIT_TABLE 6 19 20 25 28 33 34 35 38 47 49
NOSTUFF 402 402 1 2 USB_HUB2_TEST TEST USBDM_DN1/PRT_DIS_M1 1 USB_BT_N BI 35 83 50 61 77 78 91
5% Bluetooth
1 1
1/16W 5%
26 USBDP_DN1/PRT_DIS_P1 2 USB_BT_P BI 35 83
R2651 R2653 MF-LF 1/16W 25 USB_HUB_RESET_L RESET* CRITICAL
402 MF-LF
10K 10K 402 33 USBDM_DN2/PRT_DIS_M2 3 USB_EXTD_N BI 43 83
1
R2671 1
R2672
5% 5% CRITICAL USB_HUB2_XTAL1 XTALIN/CLKIN EXTERNAL D
1/16W 1/16W 32 USBDP_DN2/PRT_DIS_P2 4 USB_EXTD_P BI 43 83 10K 10K
MF-LF MF-LF USB_HUB2_XTAL2 XTALOUT 5% 5%
402 2 2 402 1/16W 1/16W
28 USBDM_DN3/PRT_DIS_M3 6 USB_EXTA_N BI 43 83 MF-LF MF-LF
USB_HUB2_NONREM0 SUSP_IND/LOCAL_PWR/NON_REM0 External A
2 402 2 402
USBDP_DN3/PRT_DIS_P3 7 USB_EXTA_P BI 43 83

USB_HUB2_NONREM1 22 SDA/SMBDATA/NON_REM1
NC 8 PU_USB2_PRT4N
USB_HUB2_CFG_SEL0 24 SCL/SMBCLK/CFG_SEL0 NC 9 PU_USB2_PRT4P
NOSTUFF DISABLE PORT ON 4 PORT HUB.
R26521 1
R2654 USB_HUB2_CFG_SEL1 25 HS_IND/CFG_SEL1 PRTPWR1/BC_EN1* 12
16
TP_USB_HUB2_PRTPWR1
10K 10K PRTPWR2/BC_EN2* TP_USB_HUB2_PRTPWR2
5% 5% 18 PP3V3_S4
1/16W 1/16W 1 PRTPWR3/BC_EN3* TP_USB_HUB2_PRTPWR3 6 19 20 25 28 33 34 35 38 47 49
MF-LF
402 2
MF-LF
2 402
R2656 1R2657 NC 20 TP_USB_HUB2_PRTPWR4
50 61 77 78 91

10K 10K
5% 5% 13
1/16W 1/16W OCS1* TP_USB_HUB2_OCS1 1
MF-LF
2 402
MF-LF
2 402
IPU
OCS2* 17 USB_EXTD_OC_L IN 43
R2670
A IPU

IPU OSC3* 19
21
USB_EXTA_OC_L IN 43
10K
5%
1/16W SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
IPU
NC TP_USB_HUB2_OCS4 MF-LF PAGE TITLE
2 402
NONREM MEANS NOT CUSTOMER REMOVABLE. RBIAS 35 USB_HUB2_RBIAS USB HUBS
THIS IS A DESIGNATION FOR SOFTWARE USE ONLY. DRAWING NUMBER SIZE
VBUS_DET 27 USB_HUB2_VBUS_DET 051-8768 D
CKPLUS_WAIVE
CRITICAL Apple Inc.
NON_REM1 NON_REM0 DESCRIPTION USBDM_UP 30 USB_HUB2_UP_N BI 19 83
1
R2650 R
REVISION

USBDP_UP 31 USB_HUB2_UP_P BI 19 83 12K 9.0.0

0 0 All ports are removable 1% NOTICE OF PROPRIETARY PROPERTY: BRANCH
THRM_PAD 1/16W
0 1 Port 1 is non removable MF THE INFORMATION CONTAINED HEREIN IS THE
2 402 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
37

1 0 Port 1 and 2 are non removable THE POSESSOR AGREES TO THE FOLLOWING: PAGE
1 1 Port 1, 2, and 3 are non removable I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
26 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 25 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

System 25MHz Clock Generator

Low-Power 32kHz Source (not used)
Normal-Power 32kHz Source (not used) COUGAR POINT (PCH) 25MHZ CRYSTAL INPUT
D GreenClk 25MHz Power 91 62 38 37 26 6 PP3V3_ENET
VDD_25M must be powered if any VDDIO is.
D
No bypass necessary on +V3.3A & VBAT
ENET > S0 > T29, so ENET is used here. I571
Ethernet XTAL Power 91 62 38 37 26 6 PP3V3_ENET TP_PCH_CLK25M_X2 PCH_CLK25M_X2 IN 17
MAKE_BASE=TRUE

+3.42V 13
PP1V8_S0

VDD_25M 5

+V3.3A 2
SB XTAL Power 71 23 21 18 15 7

T29 XTAL Power 76 75 74 20 17 PP3V3_T29 R2740

VBAT and +V3.3A are
1
604 2 PCH_CLK25M_X1
internally ORed to OUT 17

create VDD_RTC_OUT. 1%
C2724 1 C2722 1 C2720 1 1 C2702 1/16W
1
0.1UF
10%
0.1UF
10%
0.1UF
10%
1UF
10% U2700
MF-LF
402 R2741
16V 16V 16V 1K
X7R-CERM 2 X7R-CERM 2 X7R-CERM 2 2 10V
X5R SLG3NB148V 1%
402 402 402 402-1 TQFN 1/16W
MF-LF
CRITICAL 2 402
11 VDDIO_25M_A 32KHZ_A 12 NC
6 VDDIO_25M_B
14 25MHZ_A 9 SYSCLK_CLK25M_SB
C2705 R2705
VDDIO_25M_C
12PF 25MHZ_B 8 SYSCLK_CLK25M_ENET_SR
2 1 0 3
SYSCLK_CLK25M_X2 1 2 SYSCLK_CLK25M_X2_R X2 25MHZ_C 15 SYSCLK_CLK25M_T29_SR
5%
50V
5%
1/16W
NO STUFF
1
4 X1 CAESAR IV (ENET) 25MHZ CRYSTAL INPUT
CRITICAL MF-LF R2706 VDD_RTC_OUT 1

1
CERM 402 NC
402 2 4 Y2705 1M
5% GND THRM I574
25.000MHZ-12PF-20PPM 1/16W PAD TP_ENET_CLK25M_XTALO BCM5764_CLK25M_XTALO 37 85
IN
C2706 MF-LF MAKE_BASE=TRUE

10
16

17
3
R2743

7
SM-3.2X2.5MM 2 402
12PF I577
1 2 33
SYSCLK_CLK25M_X1 1 2 SYSCLK_CLK25M_ENET BCM5764_CLK25M_XTALI OUT 37 85
MAKE_BASE=TRUE
NOTE: 30 PPM crystal required 5%
5% 1/16W
50V MF-LF
CERM 402
402

C J40 NOTE: WILL NOT BE USING RTC POWER OR CLK FEATURES OF THIS CHIP DUE TO EXTRA COIN CELL LOAD
Working with Silego on a simplified version without this support
C
R2745
47
1 2 SYSCLK_CLK25M_T29 OUT 74

5%
1/16W

GREEN CLK MF-LF

402

B B

A SYNC_MASTER=J40S SYNC_DATE=11/23/2010 A
PAGE TITLE

CLOCKS, CRYSTALS
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
27 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 26 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
RTC Power Sources
Platform Reset Connections
D2800
BAT54DW-X-G
SOT-363 Unbuffered
91 65 61 48 47 46 45 43 6 PP3V3_G3H PP3V3_G3_RTC 6 17 18 21 91
1 6 MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
Coin-Cell Holder R2800 VOLTAGE=3.3V
1K 3
6 PPVBATT_G3_RTC 2 1 PPVBATT_G3_RTC_R 4 19 PLT_RESET_L
IN
MIN_LINE_WIDTH=0.3 mm MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm 5% MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V 1/16W VOLTAGE=3.3V
MF-LF
NC
5 NC NC 2 NC
402
1 J2800
D 2 SM
BB10201-C1403-7H R28791
100K
1
R2877
33
D
5% 5%
511S0054
1/16W
MF-LF
1/16W
MF-LF R2875
NOTE: R2800 and D2800 form the double- 402 2 2 402 33
PLACE_NEAR=U2840.4:5MM 1 2 ENET_RESET_L OUT 34 85
fault protection for RTC battery. PLACE_NEAR=U1800.C6:5MM PLACE_NEAR=U1800.C6:5MM
5%
1/16W
MF-LF
R2876 402
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION PLT_RESET2_L OUT 28 33
1 2 FW_RESET_L OUT 39

742-0062 1
BAT,COIN,LI/MAG,BR2032,3V,190MAH BAT CRITICAL 5%
1/16W
PLACE_NEAR=U2840.4:5MM MF-LF
TABLE_ALT_HEAD
402 R2888
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: 33
PART NUMBER PLACE_NEAR=U2840.4:5MM 1 2 AP_RESET_L OUT 35
TABLE_ALT_ITEM

5%
511S0074 511S0054 ? ? BATTERY HOLDER WITHOUT ALIGNMENT PEGS 1/16W
MF-LF
R2871 402
33
PLACE_NEAR=U2840.4:5MM 1 2 PCA9557D_RESET_L OUT 33

5%
1/16W
MF-LF
402 R2883
33
PLACE_NEAR=U2840.4:5MM 1 2 SMC_LRESET_L OUT 46

PCH RTC Crystal R2881

5%
1/16W
MF-LF
91 33 402
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 PLACE_NEAR=U2840.4:5MM 1 2 LPCPLUS_RESET_L OUT 48 84
PLACE C2810 CLOSE TO Y2810 47 41 40 39 38 37 34 31 30 27
89 79 77 76 74 73 72 71 67
CRITICAL 5%
MAKE_BASE=TRUE
R2810 C2810 5 U2840 1/16W
0 12pF MF-LF
PCH_CLK32K_RTCX2 1 2 PCH_CLK32K_RTCX2_R 1 2 74LVC1G17DRL 402
17 IN SOT-553
5% 2 4 PLT_RST_BUF_L =PLT_RST_T29_GPU 76
1/16W 5% MAKE_BASE=TRUE
1 CRITICAL 50V
C R2811 MF-LF CERM NC C

3
402 402 1
10M

2 4
5% Y2810 1 3 R2840
1/16W 32.768K C2840 1 NC 100K
MF-LF SM-2 C2811 0.1UF 5%

1
402 2 10% 1/16W
12pF 16V MF-LF
17 PCH_CLK32K_RTCX1 1 2 X7R-CERM 2 2 402
OUT 402
PLACE Y2810 CLOSE TO U1800 5%
50V
CERM
402
PLACE C2811 CLOSE TO Y2810 91
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27
PP3V3_S0 Buffered
89 79 77 76 74 73 72 71 67
CRITICAL
5 U2880
74LVC1G07
SC70
2 4 PLT_RST_CPU_BUF_L CPU_RESET_L 11 24
OUT
OD MAKE_BASE=TRUE
NC OPEN DRAIN WITH PULL UP AT CPU
1
1 3 R2880
C2880 1 NC 100K
5%
0.1UF 1/16W
10% MF-LF
16V
X7R-CERM 2 2 402
402

R2827
PLACE_NEAR=U1800.H49:5.1mm 22
84 19 IN LPC_CLK33M_SMC_R 1 2 LPC_CLK33M_SMC OUT 46 84

5%
1/16W
B MF-LF
402
PLACE_NEAR=U1800.H43:5.1mm
R2826
22
B
84 19 IN LPC_CLK33M_LPCPLUS_R 1 2 LPC_CLK33M_LPCPLUS OUT 48 84

5%
1/16W
MF-LF
402

R2829
PLACE_NEAR=U1800.H40:2.54MM:5.1mm 22
19 IN PCH_CLK33M_PCIOUT 1 2 PCH_CLK33M_PCIIN OUT 17 84

5%
1/16W
MF-LF
402

NO STUFF
PCH S0 PWRGD R2863
1
0 2
27 25 24 23 21 20 19 18 17 6 PP3V3_S5 5%
91 89 78 62 61 59 28 1/16W
91
MF-LF
402
PCH Reset Button
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 91
47 41 40 39 38 37 34 31 30 27
89 79 77 76 74 73 72 71 67 PP3V3_S5 62 61 60 58 57 53 52 51 50 49
PP3V3_S0
R28501 1 C2850 6 17 18 19 20 21 23 24 25 27 28
59 61 62 78 89 91
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27
89 79 77 76 74 73 72 71 67
1K 0.1UF
5%
1/16W
10%
16V
2 X7R-CERM
1 C2860 1
R2895
MF-LF 0.1UF 10K
402 2 402 10% 5%
2 16V
X7R-CERM XDP 1/16W
402 MF-LF
R2896 2 402
5 XDP_DBRESET_L 1
0 2 PM_SYSRST_L
MC74VHC1G08
A 62 46 IN ALL_SYS_PWRGD 1 SC70-HF
4 PM_S0_PGOOD 1
5 MC74VHC1G08 R2862
81 24 11 IN
5%
1/16W
BI 18 46

SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/30/2010 A
PM_PGOOD_PVCORE_CPU 2
U2850 SC70-HF
4 SYS_PWROK_R 1
1K 2 PM_PCH_SYS_PWROK
MF-LF
402
PAGE TITLE
67 62 IN
2
U2860 OUT 18 24
OMIT RTC SUPPORT, RESETS
3 5% PLACE_NEAR=U1800.L22:5.54mm
1
1/16W
MF-LF NO STUFF R2897 DRAWING NUMBER SIZE
3 402 1
R2861 5%
0
Apple Inc. 051-8768 D
0 1/16W REVISION
5% MF-LF R
1/16W
MF-LF 2 402 9.0.0
2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R2860 SILK_PART=SYS RESET
THE INFORMATION CONTAINED HEREIN IS THE
0 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
46 SMC_DELAYED_PWRGD 1 2 PM_PCH_PWROK OUT 18 20 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MAKE_BASE=TRUE
5%
1/16W
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
28 OF 512
MF-LF SHEET
402 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 27 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

D WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
D
WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

1V5 S0 "PGOOD" for CPU
MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L 27 25 24 23 21 20 19 18 17 6PP3V3_S5

91 62 46 18 IN PM_SLP_S4_L 91 89 78 62 61 59

CPUMEM:S0
1 PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page
R2905
10K
5% 62 50 32 31 16 13 11 7 PP1V5_VDDQ_CPU
1/16W 1
PM_MEM_PWRGD OUT 11 18 81
MF-LF
2 402
R2922
10K
5%
P1V5CPU_EN OUT 61 1/16W CRITICAL 6
MF-LF
47 38 35 34 33 28 25 20 19 6 PP3V3_S4 2 402
91 78 77 61 50 49 CPUMEM:S0 R29201 D Q2920
CPUMEM:S0 Q2905 D 6 27.4K DMB53D0UV
1 SSM6N37FEAPE 1% SOT-563
R2901 SOT563 1/16W
MF-LF PM_MEM_PWRGD_L 2 G
100K 402 2
5%
1/16W
MF-LF
402 2 2 G S 1 R2923 3 CRITICAL
0
P1V5CPU_EN_L 61 IN P1V5VDDQCPU_RAMP_DONE 1 2
P1V5_S0_DIV 5 Q2920 S
5% DMB53D0UV 1
1/16W SOT-563
CPUMEM:S0 CPUMEM:S0 MF-LF
402
D 3 3 D 4
Q2900 Q2905
SSM6N37FEAPE SSM6N37FEAPE R29211 C2920 1
SOT563 SOT563 33.2K 0.01UF
1% 10%
C 5 G
1/16W
MF-LF
402 2
50V 2
X7R
402
C
S 4 4 S G 5
20 IN ISOLATE_CPU_MEM_L PM_SLP_S3_L IN 18 46 51 62 91

100NS DELAY REQUIRED.

PCH HANDLES TIMING FOR S5 TO S0,
CPUMEM:S0 BUT NOT S3/S4 TO S0.
1
R2910
10K
5%
1/16W
MF-LF
2 402
MEMVTT_EN OUT 28 66
47 38 35 34 33 28 25 20 19 6 PP3V3_S4
91 78 77 61 50 49
CPUMEM:S0 MEMVTT Clamp
CPUMEM:S0 Q2910 D 6
1 SSM6N37FEAPE Ensures CKE signals are held low in S3
R2902 SOT563
100K
5%
1/16W
MF-LF
402 2 2 G S 1 91 66 31 30 7 PP0V75_S0_DDRVTT
MEMVTT_EN_L CPUMEM:S0
R29501
CPUMEM:S0 CPUMEM:S0 10 75MA MAX LOAD @ 0.75V
D 6 3 D 5%
Q2900 Q2910 1/10W
MF-LF
60MW MAX POWER
SSM6N37FEAPE SSM6N37FEAPE 603 2
SOT563 SOT563
VTTCLAMP_L
91 78 66 65 61 45 44 43 28 6 PP5V_S4
2 G S 1 4 S G 5 CPUMEM:S0
Q2950 D 6
B PLT_RESET2_L IN 27 CPUMEM:S0
R29511 SSM6N37FEAPE B
SOT563
100K
5%
1/16W
PP5V_S4 6 28 43 44 45 61 65 66 78 91 MF-LF
CPUMEM:S0 402 2 2 G S 1
CPUMEM:S0
Q2915 1 VTTCLAMP_EN
SSM6N37FEAPE R2915
100K
2

47 38 35 34 33 28 25 20 19 6 PP3V3_S4 SOT563 5% CPUMEM:S0 PP1V5_S3 6 30 31 32 61 66 72 91 CPUMEM:S0

91 78 77 61 50 49 1/16W NO STUFF
G

MF-LF Q2915 CPUMEM:S0 Q2950 D 3

2 402 SSM6N37FEAPE 1 CPUMEM:S0 SSM6N37FEAPE C2951 1
R2916 1 C2916 SOT563 0.001UF
S

MEMRESET_ISOL_LS5V_L SOT563 20K 10%

5% 0.1UF 50V
CERM 2
6

G
1

1/16W 10%
MF-LF 2 16V
X7R-CERM
402
3.3V TO 5V LEVEL SHIFTER 2 402 402 5 G S 4
S

3 D

66 28 MEMVTT_EN
4

IN
CPU_MEM_RESET_L CPUMEM:S3 MEM_RESET_L
11 IN OUT 30 31
R2917
1
0 2
5%
1/16W
MF-LF
402

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

S0 0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

1 0 1 1 1 1 1 1 1

to 2 0 0 1 1 1 1 0 1

A S3
3

4
0

0
0

0
0

1
1

1
X

X
1

1
0

0
0

1
SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

to
5

6
0

0
1

1
1

1
1

1
0 (*)

1
1

1
1

1
1

1
CPU Memory S3 Support
DRAWING NUMBER SIZE
7 1 1 1 1 1 CPU_MEM_RESET_L 1 1
S0
Apple Inc. 051-8768 D
REVISION
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO. R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
29 OF 512
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L. III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 28 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Host Partition A 0 -> SO-DIMM A 0 Host Partition B 0 -> SO-DIMM B 0
82 12 BI MEM_A_DQS_P<0> =MEM_A_DQS_P<7> BI 30 82 12 BI MEM_B_DQS_P<0> =MEM_B_DQS_P<7> BI 31

82 12 BI MEM_A_DQS_N<0> MAKE_BASE=TRUE =MEM_A_DQS_N<7> BI 30 82 12 BI MEM_B_DQS_N<0> MAKE_BASE=TRUE =MEM_B_DQS_N<7> BI 31

MAKE_BASE=TRUE MAKE_BASE=TRUE
SANDYBRIDGE CPU DOES NOT USE DATA MASK (DM) BITS. =MEM_A_DM<7> OUT 30 =MEM_B_DM<7> OUT 31
PER PDG, TIE DM BITS TO GND.
82 12 BI MEM_A_DQ<0> =MEM_A_DQ<63> BI 30 82 12 BI MEM_B_DQ<0> =MEM_B_DQ<63> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<1> =MEM_A_DQ<62> BI 30 82 12 BI MEM_B_DQ<1> =MEM_B_DQ<62> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<2> =MEM_A_DQ<60> BI 30 82 12 BI MEM_B_DQ<2> =MEM_B_DQ<60> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<3> =MEM_A_DQ<61> BI 30 82 12 BI MEM_B_DQ<3> =MEM_B_DQ<61> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<4> =MEM_A_DQ<59> BI 30 82 12 BI MEM_B_DQ<4> =MEM_B_DQ<59> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<5> =MEM_A_DQ<58> BI 30 82 12 BI MEM_B_DQ<5> =MEM_B_DQ<58> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<6> =MEM_A_DQ<57> BI 30 82 12 BI MEM_B_DQ<6> =MEM_B_DQ<57> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
D 82 12 BI MEM_A_DQ<7>
MAKE_BASE=TRUE
=MEM_A_DQ<56> BI 30 82 12 BI MEM_B_DQ<7>
MAKE_BASE=TRUE
=MEM_B_DQ<56> BI 31
D
Host Partition A 1 -> SO-DIMM A 1 Host Partition B 1 -> SO-DIMM B 2
82 12 BI MEM_A_DQS_P<1> =MEM_A_DQS_P<6> BI 30 82 12 BI MEM_B_DQS_P<1> =MEM_B_DQS_P<6> BI 31

82 12 BI MEM_A_DQS_N<1> MAKE_BASE=TRUE =MEM_A_DQS_N<6> BI 30 82 12 BI MEM_B_DQS_N<1> MAKE_BASE=TRUE =MEM_B_DQS_N<6> BI 31

MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DM<6> OUT 30 =MEM_B_DM<6> OUT 31

82 12 BI MEM_A_DQ<8> =MEM_A_DQ<55> BI 30 82 12 BI MEM_B_DQ<8> =MEM_B_DQ<55> BI 31

MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<9> =MEM_A_DQ<54> BI 30 82 12 BI MEM_B_DQ<9> =MEM_B_DQ<54> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<10> =MEM_A_DQ<53> BI 30 82 12 BI MEM_B_DQ<10> =MEM_B_DQ<53> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<11> =MEM_A_DQ<52> BI 30 82 12 BI MEM_B_DQ<11> =MEM_B_DQ<52> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<12> =MEM_A_DQ<51> BI 30 82 12 BI MEM_B_DQ<12> =MEM_B_DQ<51> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<13> =MEM_A_DQ<50> BI 30 82 12 BI MEM_B_DQ<13> =MEM_B_DQ<50> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<14> =MEM_A_DQ<49> BI 30 82 12 BI MEM_B_DQ<14> =MEM_B_DQ<49> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<15> =MEM_A_DQ<48> BI 30 82 12 BI MEM_B_DQ<15> =MEM_B_DQ<48> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
Host Partition A 2 -> SO-DIMM A 2 Host Partition B 2 -> SO-DIMM B 3
82 12 BI MEM_A_DQS_P<2> =MEM_A_DQS_P<5> BI 30 82 12 BI MEM_B_DQS_P<2> =MEM_B_DQS_P<5> BI 31

82 12 BI MEM_A_DQS_N<2> MAKE_BASE=TRUE =MEM_A_DQS_N<5> BI 30 82 12 BI MEM_B_DQS_N<2> MAKE_BASE=TRUE =MEM_B_DQS_N<5> BI 31

MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DM<5> OUT 30 =MEM_B_DM<5> OUT 31

82 12 BI MEM_A_DQ<16> =MEM_A_DQ<47> BI 30 82 12 BI MEM_B_DQ<16> =MEM_B_DQ<47> BI 31

MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<17> =MEM_A_DQ<46> BI 30 82 12 BI MEM_B_DQ<17> =MEM_B_DQ<46> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<18> =MEM_A_DQ<45> BI 30 82 12 BI MEM_B_DQ<18> =MEM_B_DQ<45> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<19> =MEM_A_DQ<44> BI 30 82 12 BI MEM_B_DQ<19> =MEM_B_DQ<44> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<20> =MEM_A_DQ<43> BI 30 82 12 BI MEM_B_DQ<20> =MEM_B_DQ<43> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<21> =MEM_A_DQ<42> BI 30 82 12 BI MEM_B_DQ<21> =MEM_B_DQ<42> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<22> =MEM_A_DQ<41> BI 30 82 12 BI MEM_B_DQ<22> =MEM_B_DQ<41> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<23> =MEM_A_DQ<40> BI 30 82 12 BI MEM_B_DQ<23> =MEM_B_DQ<40> BI 31

C MAKE_BASE=TRUE
Host Partition A 3 -> SO-DIMM A 3
MAKE_BASE=TRUE
Host Partition B 3 -> SO-DIMM B 1 C
82 12 BI MEM_A_DQS_P<3> =MEM_A_DQS_P<4> BI 30 82 12 BI MEM_B_DQS_P<3> =MEM_B_DQS_P<4> BI 31

82 12 BI MEM_A_DQS_N<3> MAKE_BASE=TRUE =MEM_A_DQS_N<4> BI 30 82 12 BI MEM_B_DQS_N<3> MAKE_BASE=TRUE =MEM_B_DQS_N<4> BI 31

MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DM<4> OUT 30 =MEM_B_DM<4> OUT 31

82 12 BI MEM_A_DQ<24> =MEM_A_DQ<39> BI 30 82 12 BI MEM_B_DQ<24> =MEM_B_DQ<39> BI 31

MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<25> =MEM_A_DQ<38> BI 30 82 12 BI MEM_B_DQ<25> =MEM_B_DQ<38> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<26> =MEM_A_DQ<37> BI 30 82 12 BI MEM_B_DQ<26> =MEM_B_DQ<37> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<27> =MEM_A_DQ<36> BI 30 82 12 BI MEM_B_DQ<27> =MEM_B_DQ<36> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<28> =MEM_A_DQ<35> BI 30 82 12 BI MEM_B_DQ<28> =MEM_B_DQ<35> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<29> =MEM_A_DQ<34> BI 30 82 12 BI MEM_B_DQ<29> =MEM_B_DQ<34> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<30> =MEM_A_DQ<33> BI 30 82 12 BI MEM_B_DQ<30> =MEM_B_DQ<33> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<31> =MEM_A_DQ<32> BI 30 82 12 BI MEM_B_DQ<31> =MEM_B_DQ<32> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
Host Partition A 4 -> SO-DIMM A 4 Host Partition B 4 -> SO-DIMM B 4
82 12 BI MEM_A_DQS_P<4> =MEM_A_DQS_P<3> BI 30 82 12 BI MEM_B_DQS_P<4> =MEM_B_DQS_P<3> BI 31

82 12 BI MEM_A_DQS_N<4> MAKE_BASE=TRUE =MEM_A_DQS_N<3> BI 30 82 12 BI MEM_B_DQS_N<4> MAKE_BASE=TRUE =MEM_B_DQS_N<3> BI 31

MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DM<3> OUT 30 =MEM_B_DM<3> OUT 31

82 12 BI MEM_A_DQ<32> =MEM_A_DQ<31> BI 30 82 12 BI MEM_B_DQ<32> =MEM_B_DQ<31> BI 31

MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<33> =MEM_A_DQ<30> BI 30 82 12 BI MEM_B_DQ<33> =MEM_B_DQ<30> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<34> =MEM_A_DQ<29> BI 30 82 12 BI MEM_B_DQ<34> =MEM_B_DQ<29> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<35> =MEM_A_DQ<28> BI 30 82 12 BI MEM_B_DQ<35> =MEM_B_DQ<28> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<36> =MEM_A_DQ<27> BI 30 82 12 BI MEM_B_DQ<36> =MEM_B_DQ<27> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<37> =MEM_A_DQ<26> BI 30 82 12 BI MEM_B_DQ<37> =MEM_B_DQ<26> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<38> =MEM_A_DQ<25> BI 30 82 12 BI MEM_B_DQ<38> =MEM_B_DQ<25> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<39> =MEM_A_DQ<24> BI 30 82 12 BI MEM_B_DQ<39> =MEM_B_DQ<24> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
B Host Partition A 5 -> SO-DIMM A 5 Host Partition B 5 -> SO-DIMM B 5 B
82 12 BI MEM_A_DQS_P<5> =MEM_A_DQS_P<2> BI 30 82 12 BI MEM_B_DQS_P<5> =MEM_B_DQS_P<2> BI 31

82 12 BI MEM_A_DQS_N<5> MAKE_BASE=TRUE =MEM_A_DQS_N<2> BI 30 82 12 BI MEM_B_DQS_N<5> MAKE_BASE=TRUE =MEM_B_DQS_N<2> BI 31

MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DM<2> OUT 30 =MEM_B_DM<2> OUT 31

82 12 BI MEM_A_DQ<40> =MEM_A_DQ<23> BI 30 82 12 BI MEM_B_DQ<40> =MEM_B_DQ<23> BI 31

MAKE_BASE=TRUE MAKE_BASE=TRUE

www.teknisi-indonesia.com
82 12 BI MEM_A_DQ<41> =MEM_A_DQ<22> BI 30 82 12 BI MEM_B_DQ<41> =MEM_B_DQ<22> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<42> =MEM_A_DQ<21> BI 30 82 12 BI MEM_B_DQ<42> =MEM_B_DQ<21> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<43> =MEM_A_DQ<20> BI 30 82 12 BI MEM_B_DQ<43> =MEM_B_DQ<20> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<44> =MEM_A_DQ<19> BI 30 82 12 BI MEM_B_DQ<44> =MEM_B_DQ<19> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<45> =MEM_A_DQ<18> BI 30 82 12 BI MEM_B_DQ<45> =MEM_B_DQ<18> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<46> =MEM_A_DQ<17> BI 30 82 12 BI MEM_B_DQ<46> =MEM_B_DQ<17> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<47> =MEM_A_DQ<16> BI 30 82 12 BI MEM_B_DQ<47> =MEM_B_DQ<16> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
Host Partition A 6 -> SO-DIMM A 6 Host Partition B 6 -> SO-DIMM B 6
82 12 BI MEM_A_DQS_P<6> =MEM_A_DQS_P<1> BI 30 82 12 BI MEM_B_DQS_P<6> =MEM_B_DQS_P<1> BI 31

82 12 BI MEM_A_DQS_N<6> MAKE_BASE=TRUE =MEM_A_DQS_N<1> BI 30 82 12 BI MEM_B_DQS_N<6> MAKE_BASE=TRUE =MEM_B_DQS_N<1> BI 31

MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DM<1> OUT 30 =MEM_B_DM<1> OUT 31

82 12 BI MEM_A_DQ<48> =MEM_A_DQ<15> BI 30 82 12 BI MEM_B_DQ<48> =MEM_B_DQ<15> BI 31

MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<49> =MEM_A_DQ<14> BI 30 82 12 BI MEM_B_DQ<49> =MEM_B_DQ<14> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<50> =MEM_A_DQ<13> BI 30 82 12 BI MEM_B_DQ<50> =MEM_B_DQ<13> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<51> =MEM_A_DQ<12> BI 30 82 12 BI MEM_B_DQ<51> =MEM_B_DQ<12> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<52> =MEM_A_DQ<11> BI 30 82 12 BI MEM_B_DQ<52> =MEM_B_DQ<11> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<53> =MEM_A_DQ<10> BI 30 82 12 BI MEM_B_DQ<53> =MEM_B_DQ<10> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<54> =MEM_A_DQ<9> BI 30 82 12 BI MEM_B_DQ<54> =MEM_B_DQ<9> BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE
82 12 BI MEM_A_DQ<55> =MEM_A_DQ<8> BI 30 82 12 BI MEM_B_DQ<55> =MEM_B_DQ<8> BI 31

A MAKE_BASE=TRUE
Host Partition A 7 -> SO-DIMM A 7
MAKE_BASE=TRUE
Host Partition B 7 -> SO-DIMM B 7 SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
82 12 BI MEM_A_DQS_P<7> =MEM_A_DQS_P<0> BI 30 82 12 BI MEM_B_DQS_P<7> =MEM_B_DQS_P<0> BI 31
PAGE TITLE

82 12 BI MEM_A_DQS_N<7> MAKE_BASE=TRUE =MEM_A_DQS_N<0> BI 30 82 12 BI MEM_B_DQS_N<7> MAKE_BASE=TRUE =MEM_B_DQS_N<0> BI 31 SO-DIMM Pinswaps

MAKE_BASE=TRUE MAKE_BASE=TRUE
=MEM_A_DM<0> OUT 30 =MEM_B_DM<0> OUT 31 DRAWING NUMBER SIZE

82 12 MEM_A_DQ<56> =MEM_A_DQ<7> 30 82 12 MEM_B_DQ<56> =MEM_B_DQ<7> 31 Apple Inc. 051-8768 D

BI BI BI BI
MAKE_BASE=TRUE MAKE_BASE=TRUE REVISION
82 12 MEM_A_DQ<57> =MEM_A_DQ<6> 30 82 12 MEM_B_DQ<57> =MEM_B_DQ<6> 31 R

82 12
BI
MEM_A_DQ<58> MAKE_BASE=TRUE
=MEM_A_DQ<5>
BI
30 82 12
BI
MEM_B_DQ<58> MAKE_BASE=TRUE
=MEM_B_DQ<5>
BI
31
9.0.0
BI BI BI BI
MEM_A_DQ<59> MAKE_BASE=TRUE
=MEM_A_DQ<4> MEM_B_DQ<59> MAKE_BASE=TRUE
=MEM_B_DQ<4> NOTICE OF PROPRIETARY PROPERTY: BRANCH
82 12 BI BI 30 82 12 BI BI 31
MAKE_BASE=TRUE MAKE_BASE=TRUE THE INFORMATION CONTAINED HEREIN IS THE
82 12 BI MEM_A_DQ<60> =MEM_A_DQ<3> BI 30 82 12 BI MEM_B_DQ<60> =MEM_B_DQ<3> BI 31 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
MAKE_BASE=TRUE MAKE_BASE=TRUE THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MEM_A_DQ<61> =MEM_A_DQ<2> MEM_B_DQ<61> =MEM_B_DQ<2>
82 12

82 12
BI
MEM_A_DQ<62> MAKE_BASE=TRUE
=MEM_A_DQ<1>
BI 30

30
82 12

82 12
BI
MEM_B_DQ<62> MAKE_BASE=TRUE
=MEM_B_DQ<1>
BI 31

31
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
30 OF 512
BI BI BI BI
MAKE_BASE=TRUE MAKE_BASE=TRUE SHEET
82 12 MEM_A_DQ<63> =MEM_A_DQ<0> 30 82 12 MEM_B_DQ<63> =MEM_B_DQ<0> 31
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
BI
MAKE_BASE=TRUE BI BI
MAKE_BASE=TRUE BI
IV ALL RIGHTS RESERVED 29 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
PP0V75_S3_MEM_VREFDQ_A 1A 2A
33 30 10 VREFDQ VSS_0
3A 4A =MEM_A_DQ<4>
VSS_1 DQ4 29

29 =MEM_A_DQ<0> 5A
DQ0 J3100 DQ5
6A =MEM_A_DQ<5> 29

=MEM_A_DQ<1> 7A F-RT-SM 8A
29 DQ1 VSS_2
9A (1 OF 2) 10A =MEM_A_DQS_N<0>
VSS_3 DQS0* 29

DDR3-SODIMM-DUAL
=MEM_A_DM<0> 11A 12A =MEM_A_DQS_P<0>
29
13A
DM0
VSS_4
DQS0
VSS_5
14A
29
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)
=MEM_A_DQ<2> 15A 16A =MEM_A_DQ<6>
29 DQ2 DQ6 29

=MEM_A_DQ<3> 17A 18A =MEM_A_DQ<7> PP1V5_S3

29 DQ3 DQ7 29 91 72 66 61 32 31 30 28 6
19A 20A
VSS_6 VSS_7
=MEM_A_DQ<8> 21A 22A =MEM_A_DQ<12>
29 DQ8 DQ12 29
1 C3100 1 C3101 1 C3110 1 C3111 1 C3112 1 C3113 1 C3114 1 C3115 1 C3116 1 C3117
=MEM_A_DQ<9> 23A 24A =MEM_A_DQ<13>
29 DQ9 DQ13 29
10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
D 29 =MEM_A_DQS_N<1>
25A
27A
VSS_8
DQS1*
VSS_9
DM1
26A
28A =MEM_A_DM<1> 29
20%
2 6.3V
X5R
603
20%
2 6.3V
X5R
603
10%
2 16V
X7R-CERM
402
10%
16V
2 X7R-CERM
402
10%
16V
2 X7R-CERM
402
10%
16V
2 X7R-CERM
402
10%
16V
2 X7R-CERM
402
10%
16V
2 X7R-CERM
402
10%
16V
2 X7R-CERM
402
10%
16V
2 X7R-CERM
402
D
=MEM_A_DQS_P<1> 29A 30A MEM_RESET_L
29 DQS1 RESET* 28 31
31A 32A
VSS_10 VSS_11
=MEM_A_DQ<10> 33A 34A =MEM_A_DQ<14>
29 DQ10 DQ14 29

=MEM_A_DQ<11> 35A 36A =MEM_A_DQ<15>

29 DQ11 DQ15 29
37A 38A
VSS_12 VSS_13
=MEM_A_DQ<16> 39A 40A =MEM_A_DQ<20>
29 DQ16 DQ20 29

=MEM_A_DQ<17> 41A 42A =MEM_A_DQ<21>

29 DQ17 DQ21 29
PP0V75_S3_MEM_VREFDQ_A
43A 44A 33 30 10
VSS_14 VSS_15
=MEM_A_DQS_N<2> 45A 46A =MEM_A_DM<2>
29 DQS2* DM2 29

29 =MEM_A_DQS_P<2> 47A
DQS2 VSS_16
48A 1 C3132 1 C3130 1 C3131
49A
VSS_17 DQ22
50A =MEM_A_DQ<22> 29
33PF 2.2UF 0.1UF
5% 20% 10%
=MEM_A_DQ<18> 51A 52A =MEM_A_DQ<23> 2 50V 2 6.3V 16V
2 X7R-CERM
29 DQ18 DQ23 29 CERM CERM
=MEM_A_DQ<19> 53A 54A 402 402-LF 402
29 DQ19 VSS_18
55A 56A =MEM_A_DQ<28>
VSS_19 DQ28 29

=MEM_A_DQ<24> 57A 58A =MEM_A_DQ<29>

29 DQ24 DQ29 29

=MEM_A_DQ<25> 59A 60A

29 DQ25 VSS_20
61A 62A =MEM_A_DQS_N<3>
VSS_21 DQS3* 29

=MEM_A_DM<3> 63A 64A =MEM_A_DQS_P<3>

29 DM3 DQS3 29
65A 66A
VSS_22 VSS_23
=MEM_A_DQ<26> 67A 68A =MEM_A_DQ<30> PP0V75_S3_MEM_VREFCA_A
29 DQ26 DQ30 29 33 30

=MEM_A_DQ<27> 69A 70A =MEM_A_DQ<31>

29 DQ27 DQ31 29
71A 72A
VSS_24 VSS_25
MEM_A_CKE<0> 73A KEY 74A MEM_A_CKE<1>
1 C3137 1 C3135 1 C3136
82 12
75A
CKE0 CKE1
76A
12 82
33PF 2.2UF 0.1UF
PP1V5_S3 PP1V5_S3 5% 20% 10%
91 72 66 61 32 31 30 28 6 VDD_0 VDD_1 6 28 30 31 32 61 66 72 91
77A 78A 2 50V
CERM 2 6.3V
CERM 2 16V
X7R-CERM
MEM_A_A<15>
C 82 12 MEM_A_BA<2>
NC
79A
NC_0
BA2
A15
A14
80A MEM_A_A<14>
12 82

12 82
402 402-LF 402
C
81A 82A
VDD_2 VDD_3
MEM_A_A<12> 83A 84A MEM_A_A<11>
82 12 A12/BC* A11 12 82

MEM_A_A<9> 85A 86A MEM_A_A<7>

82 12 A9 A7 12 82
87A 88A
VDD_4 VDD_5
MEM_A_A<8> 89A 90A MEM_A_A<6>
82 12 A8 A6 12 82

MEM_A_A<5> 91A 92A MEM_A_A<4>

82 12 A5 A4 12 82
93A 94A
VDD_6 VDD_7 PP0V75_S0_DDRVTT
MEM_A_A<3> 95A 96A MEM_A_A<2> 91 66 31 30 28 7
82 12 A3 A2 12 82

MEM_A_A<1> 97A 98A MEM_A_A<0>

82 12 A1 A0 12 82
99A
VDD_8 VDD_9
100A 1 C3152 1 C3150 1 C3151
82 12 MEM_A_CLK_P<0> 101A
CK0 CK1
102A MEM_A_CLK_P<1> 12 82
33PF 2.2UF 2.2UF
5% 20% 20%
MEM_A_CLK_N<0> 103A 104A MEM_A_CLK_N<1> 2 50V 2 6.3V 6.3V
2 CERM
82 12 CK0* CK1* 12 82 CERM CERM
105A 106A 402 402-LF 402-LF
VDD_10 VDD_11
MEM_A_A<10> 107A 108A MEM_A_BA<1>
82 12 A10_AP BA1 12 82

MEM_A_BA<0> 109A 110A MEM_A_RAS_L

82 12 BA0 RAS* 12 82
111A 112A
VDD_12 VDD_13
MEM_A_WE_L 113A 114A MEM_A_CS_L<0>
82 12 WE* S0* 12 82

MEM_A_CAS_L 115A 116A MEM_A_ODT<0>

82 12 CAS* ODT0 12 82
117A 118A
VDD_14 VDD_15
MEM_A_A<13> 119A 120A MEM_A_ODT<1>
82 12 A13 ODT1 12 82

MEM_A_CS_L<1> 121A 122A

82 12 S1* NC_1 NC
123A 124A
VDD_16 VDD_17
125A 126A PP0V75_S3_MEM_VREFCA_A
NC TEST VREFCA 30 33
127A 128A
VSS_26 VSS_27
=MEM_A_DQ<32> 129A 130A =MEM_A_DQ<36> MEM_A_SA<1>
29 DQ32 DQ36 29 30

B 29 =MEM_A_DQ<33> 131A
133A
DQ33 DQ37
132A
134A
=MEM_A_DQ<37> 29
30 MEM_A_SA<0>
B
VSS_28 VSS_29 91
=MEM_A_DQS_N<4> 135A 136A =MEM_A_DM<4> 62 61 60 58 57 53 52 51 50 49
PP3V3_S0
29 DQS4* DM4 29 24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27
=MEM_A_DQS_P<4> 137A 138A 89 79 77 76 74 73 72 71 67
29 DQS4 VSS_30
139A 140A =MEM_A_DQ<38>
VSS_31 DQ38 29

=MEM_A_DQ<34> 141A 142A =MEM_A_DQ<39>

29 DQ34 DQ39 29
1 1
29 =MEM_A_DQ<35> 143A
DQ35 VSS_32
144A 1 C3140 R3140 R3141
145A 146A 2.2UF 10K 10K
VSS_33 DQ44 =MEM_A_DQ<44> 29
20% 5% 5%
147A 148A 1/16W 1/16W
29 =MEM_A_DQ<40> DQ40 DQ45 =MEM_A_DQ<45> 29 2 6.3V
CERM MF-LF MF-LF
=MEM_A_DQ<41> 149A 150A 402-LF 2 402 2 402
29 DQ41 VSS_34
151A 152A =MEM_A_DQS_N<5>
VSS_35 DQS5* 29

=MEM_A_DM<5> 153A 154A =MEM_A_DQS_P<5>

29 DM5 DQS5 29
155A 156A
VSS_36 VSS_37
=MEM_A_DQ<42> 157A 158A =MEM_A_DQ<46>
29 DQ42 DQ46 29

=MEM_A_DQ<43> 159A 160A =MEM_A_DQ<47>

29 DQ43 DQ47 29
161A 162A
VSS_38 VSS_39
=MEM_A_DQ<48> 163A 164A =MEM_A_DQ<52>
29 DQ48 DQ52 29

=MEM_A_DQ<49> 165A 166A =MEM_A_DQ<53>

29 DQ49 DQ53 29
167A 168A
VSS_40 VSS_41
=MEM_A_DQS_N<6> 169A 170A =MEM_A_DM<6>
29 DQS6* DM6 29

=MEM_A_DQS_P<6> 171A 172A

29 DQS6 VSS_42
173A 174A =MEM_A_DQ<54>
VSS_43 DQ54 29

=MEM_A_DQ<50> 175A 176A =MEM_A_DQ<55>

29 DQ50 DQ55 29

=MEM_A_DQ<51> 177A 178A

29 DQ51 VSS_44
179A 180A =MEM_A_DQ<60>
VSS_45 DQ60 29

=MEM_A_DQ<56> 181A 182A =MEM_A_DQ<61>

A 29

29 =MEM_A_DQ<57> 183A
DQ56
DQ57
DQ61
VSS_46
184A
29

SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
185A 186A =MEM_A_DQS_N<7> PAGE TITLE
VSS_47 DQS7* 29

29 =MEM_A_DM<7> 187A
189A
DM7 DQS7
188A
190A
=MEM_A_DQS_P<7> 29 DDR3 SO-DIMM Connector A-1
VSS_48 VSS_49 DRAWING NUMBER SIZE
29 =MEM_A_DQ<58> 191A
DQ58 DQ62
192A =MEM_A_DQ<62> 29
Apple Inc. 051-8768 D
=MEM_A_DQ<59> 193A 194A =MEM_A_DQ<63> REVISION
29 DQ59 DQ63 29
R
195A
VSS_50 VSS_51
196A 9.0.0
MEM_A_SA<0> 197A 198A MEM_EVENT_L NOTICE OF PROPRIETARY PROPERTY: BRANCH
91
30 SA0 EVENT* 31 46
62 61 60 58 57 53 52 51 50 49
PP3V3_S0 199A 200A =I2C_SODIMMA_SDA THE INFORMATION CONTAINED HEREIN IS THE
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27 VDDSPD SDA 49
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
516S0694 89 79 77 76 74 73 72 71 67 MEM_A_SA<1> 201A 202A =I2C_SODIMMA_SCL THE POSESSOR AGREES TO THE FOLLOWING: PAGE
30 SA1 SCL 49

SPD ADDR=0xA0(WR)/0xA1(RD)
91 66 31 30 28 7 PP0V75_S0_DDRVTT 203A
VTT_0 VTT_1
204A PP0V75_S0_DDRVTT 7 28 30 31 66 91
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
31 OF 512
409 410 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
MTG PIN MTG PIN
IV ALL RIGHTS RESERVED 30 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
PP0V75_S3_MEM_VREFDQ_B 1B 2B
33 31 10 VREFDQ VSS_0
3B 4B =MEM_B_DQ<4>
VSS_1 DQ4 29

29 =MEM_B_DQ<0> 5B
DQ0 J3100 DQ5
6B =MEM_B_DQ<5> 29

=MEM_B_DQ<1> 7B F-RT-SM 8B
29 DQ1 VSS_2
9B (2 OF 2) 10B =MEM_B_DQS_N<0>
VSS_3 DQS0* 29

DDR3-SODIMM-DUAL
=MEM_B_DM<0> 11B 12B =MEM_B_DQS_P<0>
29
13B
DM0
VSS_4
DQS0
VSS_5
14B
29
DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)
=MEM_B_DQ<2> 15B 16B =MEM_B_DQ<6>
29 DQ2 DQ6 29

=MEM_B_DQ<3> 17B 18B =MEM_B_DQ<7> PP1V5_S3

29 DQ3 DQ7 29 91 72 66 61 32 31 30 28 6
19B 20B
VSS_6 VSS_7
=MEM_B_DQ<8> 21B 22B =MEM_B_DQ<12>
29 DQ8 DQ12 29
1 C3200 1 C3201 1 C3210 1 C3211 1 C3212 1 C3213 1 C3214 1 C3215 1 C3216 1 C3217
=MEM_B_DQ<9> 23B 24B =MEM_B_DQ<13>
29 DQ9 DQ13 29
10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
D 29 =MEM_B_DQS_N<1>
25B
27B
VSS_8
DQS1*
VSS_9
DM1
26B
28B =MEM_B_DM<1> 29
20%
2 6.3V
X5R
603
20%
2 6.3V
X5R
603
10%
2 16V
X7R-CERM
402
10%
16V
2 X7R-CERM
402
10%
16V
2 X7R-CERM
402
10%
16V
2 X7R-CERM
402
10%
16V
2 X7R-CERM
402
10%
16V
2 X7R-CERM
402
10%
16V
2 X7R-CERM
402
10%
16V
2 X7R-CERM
402
D
=MEM_B_DQS_P<1> 29B 30B MEM_RESET_L
29 DQS1 RESET* 28 30
31B 32B
VSS_10 VSS_11
=MEM_B_DQ<10> 33B 34B =MEM_B_DQ<14>
29 DQ10 DQ14 29

=MEM_B_DQ<11> 35B 36B =MEM_B_DQ<15>

29 DQ11 DQ15 29
37B 38B
VSS_12 VSS_13
=MEM_B_DQ<16> 39B 40B =MEM_B_DQ<20>
29 DQ16 DQ20 29

=MEM_B_DQ<17> 41B 42B =MEM_B_DQ<21>

29 DQ17 DQ21 29
PP0V75_S3_MEM_VREFDQ_B
43B 44B 33 31 10
VSS_14 VSS_15
=MEM_B_DQS_N<2> 45B 46B =MEM_B_DM<2>
29 DQS2* DM2 29

29 =MEM_B_DQS_P<2> 47B
DQS2 VSS_16
48B 1 C3232 1 C3230 1 C3231
49B
VSS_17 DQ22
50B =MEM_B_DQ<22> 29
33PF 2.2UF 0.1UF
5% 20% 10%
=MEM_B_DQ<18> 51B 52B =MEM_B_DQ<23> 2 50V 2 6.3V 2 16V
29 DQ18 DQ23 29 CERM CERM X7R-CERM
=MEM_B_DQ<19> 53B 54B 402 402-LF 402
29 DQ19 VSS_18
55B 56B =MEM_B_DQ<28>
VSS_19 DQ28 29

=MEM_B_DQ<24> 57B 58B =MEM_B_DQ<29>

29 DQ24 DQ29 29

=MEM_B_DQ<25> 59B 60B

29 DQ25 VSS_20
61B 62B =MEM_B_DQS_N<3>
VSS_21 DQS3* 29

=MEM_B_DM<3> 63B 64B =MEM_B_DQS_P<3>

29 DM3 DQS3 29
65B 66B
VSS_22 VSS_23
=MEM_B_DQ<26> 67B 68B =MEM_B_DQ<30> PP0V75_S3_MEM_VREFCA_B
29 DQ26 DQ30 29 33 31

=MEM_B_DQ<27> 69B 70B =MEM_B_DQ<31>

29 DQ27 DQ31 29
71B 72B
VSS_24 VSS_25
MEM_B_CKE<0> 73B KEY 74B MEM_B_CKE<1>
1 C3237 1 C3235 1 C3236
82 12
75B
CKE0 CKE1
76B
12 82
33PF 2.2UF 0.1UF
PP1V5_S3 PP1V5_S3 5% 20% 10%
91 72 66 61 32 31 30 28 6 VDD_0 VDD_1 6 28 30 31 32 61 66 72 91
77B 78B 2 50V
CERM 2 6.3V
CERM
16V
2 X7R-CERM
MEM_B_A<15>
C 82 12 MEM_B_BA<2>
NC
79B
NC_0
BA2
A15
A14
80B MEM_B_A<14>
12 82

12 82
402 402-LF 402
C
81B 82B
VDD_2 VDD_3
MEM_B_A<12> 83B 84B MEM_B_A<11>
82 12 A12/BC* A11 12 82

MEM_B_A<9> 85B 86B MEM_B_A<7>

82 12 A9 A7 12 82
87B 88B
VDD_4 VDD_5
MEM_B_A<8> 89B 90B MEM_B_A<6>
82 12 A8 A6 12 82

MEM_B_A<5> 91B 92B MEM_B_A<4>

82 12 A5 A4 12 82
93B 94B
VDD_6 VDD_7 PP0V75_S0_DDRVTT
MEM_B_A<3> 95B 96B MEM_B_A<2> 91 66 31 30 28 7
82 12 A3 A2 12 82

MEM_B_A<1> 97B 98B MEM_B_A<0>

82 12 A1 A0 12 82
99B
VDD_8 VDD_9
100B 1 C3252 1 C3250 1 C3251
82 12 MEM_B_CLK_P<0> 101B
CK0 CK1
102B MEM_B_CLK_P<1> 12 82
33PF 2.2UF 2.2UF
5% 20% 20%
MEM_B_CLK_N<0> 103B 104B MEM_B_CLK_N<1> 2 50V 2 6.3V 6.3V
2 CERM
82 12 CK0* CK1* 12 82
CERM CERM
105B 106B 402 402-LF 402-LF
VDD_10 VDD_11
MEM_B_A<10> 107B 108B MEM_B_BA<1>
82 12 A10_AP BA1 12 82

MEM_B_BA<0> 109B 110B MEM_B_RAS_L

82 12 BA0 RAS* 12 82
111B 112B
VDD_12 VDD_13
MEM_B_WE_L 113B 114B MEM_B_CS_L<0>
82 12 WE* S0* 12 82

MEM_B_CAS_L 115B 116B MEM_B_ODT<0>

82 12 CAS* ODT0 12 82
117B 118B
VDD_14 VDD_15
MEM_B_A<13> 119B 120B MEM_B_ODT<1>
82 12 A13 ODT1 12 82

MEM_B_CS_L<1> 121B 122B

82 12 S1* NC_1 NC
123B 124B
VDD_16 VDD_17
125B 126B PP0V75_S3_MEM_VREFCA_B
NC TEST VREFCA 31 33
127B 128B
VSS_26 VSS_27
=MEM_B_DQ<32> 129B 130B =MEM_B_DQ<36>
29 DQ32 DQ36 29

B 29 =MEM_B_DQ<33> 131B
133B
DQ33 DQ37
132B
134B
=MEM_B_DQ<37> 29 31 MEM_B_SA<1> B
VSS_28 VSS_29 31 MEM_B_SA<0>
=MEM_B_DQS_N<4> 135B 136B =MEM_B_DM<4>
29 DQS4* DM4 29
91
=MEM_B_DQS_P<4> 137B 138B 62 61 60 58 57 53 52 51 50 49
PP3V3_S0
29 DQS4 VSS_30 24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27
139B 140B =MEM_B_DQ<38> 89 79 77 76 74 73 72 71 67
VSS_31 DQ38 29

=MEM_B_DQ<34> 141B 142B =MEM_B_DQ<39>

29 DQ34 DQ39 29

=MEM_B_DQ<35> 143B 144B

29 DQ35 VSS_32 1 1
145B
VSS_33 DQ44
146B =MEM_B_DQ<44> 29
1 C3240 R3240 R3241
147B 148B 2.2UF 10K 10K
29 =MEM_B_DQ<40> DQ40 DQ45 =MEM_B_DQ<45> 29
20% 5% 5%
149B 150B 1/16W 1/16W
29 =MEM_B_DQ<41> DQ41 VSS_34 2 6.3V
CERM MF-LF MF-LF
151B
VSS_35 DQS5*
152B =MEM_B_DQS_N<5> 29
402-LF 2 402 2 402
=MEM_B_DM<5> 153B 154B =MEM_B_DQS_P<5>
29 DM5 DQS5 29
155B 156B
VSS_36 VSS_37
=MEM_B_DQ<42> 157B 158B =MEM_B_DQ<46>
29 DQ42 DQ46 29

=MEM_B_DQ<43> 159B 160B =MEM_B_DQ<47>

29 DQ43 DQ47 29
161B 162B
VSS_38 VSS_39
=MEM_B_DQ<48> 163B 164B =MEM_B_DQ<52>
29 DQ48 DQ52 29

29 =MEM_B_DQ<49> 165B
167B
DQ49 DQ53
166B
168B
=MEM_B_DQ<53> 29 DDR3 GROUND RETURN CAPS (MCP SIDE)
VSS_40 VSS_41 62 50 32 28 16 13 11 7 PP1V5_VDDQ_CPU
=MEM_B_DQS_N<6> 169B 170B =MEM_B_DM<6>
29 DQS6* DM6 29

=MEM_B_DQS_P<6> 171B 172B

29 DQS6 VSS_42 1 C3222 1 C3224 1 C3226 1 C3228
173B 174B =MEM_B_DQ<54>
VSS_43 DQ54 29
0.1UF 0.1UF 0.1UF 0.1UF
=MEM_B_DQ<50> 175B 176B =MEM_B_DQ<55> 10% 10% 10% 10%
29 DQ50 DQ55 29
177B 178B 2 16V
X7R-CERM
16V
2 X7R-CERM 16V
2 X7R-CERM 16V
2 X7R-CERM
29 =MEM_B_DQ<51> DQ51 VSS_44 402 402 402 402
179B 180B =MEM_B_DQ<60>
VSS_45 DQ60 29

=MEM_B_DQ<56> 181B 182B =MEM_B_DQ<61>

A 29

29 =MEM_B_DQ<57> 183B
DQ56
DQ57
DQ61
VSS_46
184B
29

SYNC_MASTER=REFERENCE_MLB SYNC_DATE=12/01/2010 A
185B 186B =MEM_B_DQS_N<7> PAGE TITLE
VSS_47 DQS7* 29

29 =MEM_B_DM<7> 187B
189B
DM7 DQS7
188B
190B
=MEM_B_DQS_P<7> 29 DDR3 SO-DIMM Connector A-2
VSS_48 VSS_49 DRAWING NUMBER SIZE
29 =MEM_B_DQ<58> 191B
DQ58 DQ62
192B =MEM_B_DQ<62> 29
Apple Inc. 051-8768 D
=MEM_B_DQ<59> 193B 194B =MEM_B_DQ<63> REVISION
29 DQ59 DQ63 29
R
195B
VSS_50 VSS_51
196B 9.0.0
MEM_B_SA<0> 197B 198B MEM_EVENT_L NOTICE OF PROPRIETARY PROPERTY: BRANCH
91
31 SA0 EVENT* 30 46
62 61 60 58 57 53 52 51 50 49
PP3V3_S0 199B 200B =I2C_SODIMMB_SDA THE INFORMATION CONTAINED HEREIN IS THE
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27 VDDSPD SDA 49
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
89 79 77 76 74 73 72 71 67 MEM_B_SA<1> 201B 202B =I2C_SODIMMB_SCL THE POSESSOR AGREES TO THE FOLLOWING: PAGE
31 SA1 SCL 49
516S0694
SPD ADDR=0xA2(WR)/0xA3(RD)
91 66 31 30 28 7 PP0V75_S0_DDRVTT 203B
VTT_0 VTT_1
204B PP0V75_S0_DDRVTT 7 28 30 31 66 91
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
32 OF 512
411 412 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
MTG PIN MTG PIN
IV ALL RIGHTS RESERVED 31 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

C C

B 91 72 66 61 31 30 28 6 PP1V5_S3
B
1 C3331 1 C3332 1 C3333 1 C3334 1 C3336
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
10% 10% 10% 10% 10%
2 16V
X7R-CERM
16V
2 X7R-CERM 16V
2 X7R-CERM 16V
2 X7R-CERM 16V
2 X7R-CERM
402 402 402 402 402
62 50 31 28 16 13 11 7 PP1V5_VDDQ_CPU

1 C3338 1 C3339 1 C3340 1 C3341 1 C3342

0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
10% 10% 10% 10% 10%
2 16V
X7R-CERM 2 16V
X7R-CERM 2 16V
X7R-CERM
16V
2 X7R-CERM 16V
2 X7R-CERM
402 402 402 402 402

STICHING CAPS.
PLACE ACROSS PLANE SPLIT BETWEEN THESE RAIL
WHERE THE MEMORY ROUTES ARE.
EXTRAS CAN BE DELETED.

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

DDR3 Support
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
33 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 32 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
NOTE: Must not enable more than two SO-DIMM margining

buffers at once or VRef source may be overloaded.

49 47 38 35 34 28 25 20 19 6 PP3V3_S4
91 78 77 61 50

VREFMRGN
OMIT
R3418 91 66 6 PPDDRVREF_S3 R3403
200 PLACE_NEAR=J2900.1:2.54mm
SHORT2 10mA max load 1 2
1 PP3V3_S4_VREFMRGN_DAC
MIN_LINE_WIDTH=0.3 mm 1%
NONE MIN_NECK_WIDTH=0.2 mm VREFMRGN VREFMRGN 1/16W
NONE VOLTAGE=3.3V MF-LF
NONE
402
C3400 1 1 C3401 VREFMRGN
VREFMRGN
402
PP0V75_S3_MEM_VREFDQ_A
2.2UF 0.1UF CRITICAL C3403 1 VREFMRGN MIN_LINE_WIDTH=0.3 mm
10 30
20% 10%
0.1UF
B1 U3402 MIN_NECK_WIDTH=0.2 mm
D
6.3V 2
CERM
402-LF
2 16V
X7R-CERM
402
VREFMRGN
U3400
10%
16V
X7R-CERM 2
A2
V+
MAX4253
UCSP
A1
R3404
133
VOLTAGE=0.75V
D
8
402 VREFMRGN_DQ_SODIMMA_BUF 1 2
VDD 1%
=I2C_VREFDACS_SCL 6 SCL VREFMRGN_SODIMMA_DQ A3 A4 PLACE_NEAR=R3303.2:1mm
49 IN MSOP VOUTA 1 V- 1/16W
MF-LF
B4 402

DAC5574
49 BI =I2C_VREFDACS_SDA 7 SDA VOUTB 2 VREFMRGN_SODIMMB_DQ
9 A0 VOUTC 4 VREFMRGN_SODIMMS_CA
Addr=0x98(WR)/0x99(RD) 10 A1 VREFMRGN_MEMVREG_FBVREF
VOUTD 5 VREFMRGN
NOTE: MEMVREG and FRAMEBUF share R3405
GND
1
200 2 PLACE_NEAR=J3100.1:2.54mm
3 a DAC output, cannot enable VREFMRGN
both at the same time! 1
R3401 1%
1/16W
100K MF-LF
402
5%
1/16W CKPLUS_WAIVE VREFMRGN PP0V75_S3_MEM_VREFDQ_B 10 31
MF-LF B1 U3402 VREFMRGN MIN_LINE_WIDTH=0.3 mm
402 C2 MIN_NECK_WIDTH=0.2 mm
2

V+
MAX4253 R3406 VOLTAGE=0.75V
UCSP
OMIT C1 133
VREFMRGN_DQ_SODIMMB_BUF 1 2
R3419 C3 C4 1% PLACE_NEAR=R3305.2:1mm
SHORT2 V- 1/16W
1 PP3V3_S4_VREFMRGN_CTRL B4
MF-LF
MIN_LINE_WIDTH=0.3 mm 402
NONE MIN_NECK_WIDTH=0.2 mm
NONE
NONE
VOLTAGE=3.3V CRITICAL
VREFMRGN CKPLUS_WAIVE

16
402 VREFMRGN VREFMRGN
C3402 1 VREFMRGN
0.1UF
10%
VCC
1
R3409
R3402 200
16V
X7R-CERM 2 U3401 100K
1 2
PLACE_NEAR=J2900.126:2.54mm

402 PCA9557 5% 1%
QFN 1/16W 1/16W
P0 6 MF-LF MF-LF
(OD)
NC VREFMRGN 402
3 A0 P1 7 VREFMRGN_DQ_SODIMMA_EN 2 402 VREFMRGN PP0V75_S3_MEM_VREFCA_A
C3404 1 VREFMRGN
30

C
C Addr=0x30(WR)/0x31(RD) 4 A1
5 A2
P2
P3
9
10
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_CA_SODIMMA_EN
0.1UF
10%
A2
B1
V+
U3403
MAX4253
UCSP R3410
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
16V 133
P4 11 VREFMRGN_CA_SODIMMB_EN X7R-CERM 2 A1 VREFMRGN_CA_SODIMMA_BUF 1 2
402
P5 12 VREFMRGN_MEMVREG_EN A3 A4 1% PLACE_NEAR=R3309.2:1mm
V- 1/16W
49 IN =I2C_PCA9557D_SCL 1 SCL P6 13 VREFMRGN_FRAMEBUF_EN MF-LF
B4 402
49 BI =I2C_PCA9557D_SDA 2 SDA P7 14
NC
THRM RESET* 15 VREFMRGN
PAD GND
R3411

17

8
1
200 2
PLACE_NEAR=J3100.126:2.54mm

1%
VREFMRGN 1/16W
MF-LF
1
R3407 CKPLUS_WAIVE VREFMRGN
402
PP0V75_S3_MEM_VREFCA_B 31
100K VREFMRGN MIN_LINE_WIDTH=0.3 mm
PCA9557D_RESET_L 5% C2
B1 U3403 MIN_NECK_WIDTH=0.2 mm
27 IN 1/16W
MF-LF V+
MAX4253
UCSP R3412 VOLTAGE=0.75V
2 402 C1 133
RST* on ’platform reset’ so that system VREFMRGN_CA_SODIMMB_BUF 1 2
watchdog will disable margining. C3 C4 1% PLACE_NEAR=R3311.2:1mm
V- 1/16W
MF-LF
NOTE: Margining will be disabled across all B4 402
soft-resets and sleep/wake cycles.
CKPLUS_WAIVE

VREFMRGN
Required zero ohm resistors when no VREF margining circuit stuffed 1
R3408 VREFMRGN
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 100K
5%
1/16W
C3405 1 VREFMRGN
116S0004 2 RES,MTL FILM,0,5%,0402,SM,LF R3403,R3405 VREFMRGN_NOT MF-LF 0.1UF NOSTUFF
2 402
10%
16V C2
B1 U3404
X7R-CERM 2 MAX4253 R3414
116S0004 2 RES,MTL FILM,0,5%,0402,SM,LF R3409,R3411 VREFMRGN_NOT 402 V+ UCSP
B C1 VREFMRGN_MEMVREG_BUF
33.2K2
1 DDRREG_REFIN OUT 66 B
C3 C4 1% PLACE_NEAR=R7315.2:1mm
V- 1/16W
MF-LF
B4 402

Page Notes VREFMRGN

1 VREFMRGN_FRAMEBUF_BUF
Power aliases required by this page: R3413 CKPLUS_WAIVE
VREFMRGN
- =PP3V3_S3_VREFMRGN 100K B1 U3404
5% A2
- =PPVTT_S3_DDR_BUF 1/16W MAX4253
MF-LF V+ UCSP
Signal aliases required by this page: 2 402 A1
- =I2C_VREFDACS_SCL A3 A4
- =I2C_VREFDACS_SDA
V-
B4
- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA CKPLUS_WAIVE

BOM options provided by this page: VREFMRGN

1
VREFMRGN - Stuffs VREF Margining R3415
Circuitry. 100K
5%
VREFMRGN_NOT - Bypasses VREF Margining 1/16W
MF-LF
Circuitry.
2 402

A MEM A VREF DQ MEM B VREF DQ MEM A VREF CA MEM B VREF CA MEM VREG GPU Frame Buffer (1.8V, 70% VRef)
SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

DAC Channel: A B C C D D
FSB/DDR3/FRAMEBUF Vref Margining
DRAWING NUMBER SIZE
PCA9557D Pin: 1 2 3 4 5 6
Apple Inc. 051-8768 D
REVISION
Nominal value 0.75V (DAC: 0x3A) 1.5V (DAC: 0x3A) 1.267V (DAC: 0x8B) R
9.0.0
Margined target: 0.300V - 1.200V (+/- 450mV) 1.998V - 1.002V (+/- 498mV) 1.056V - 1.442V (+/- 180mV) NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
DAC range: 0.000V - 1.501V (0x00 - 0x74) 0.000V - 1.501V (0x00 - 0x74) 0.000V - 3.300V (0x00 - 0xFF) PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
VRef current: +3.4mA - -3.4mA (- = sourced) +33uA - -33uA (- = sourced) +6.0mA - -5.0mA (- = sourced) I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
34 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
DAC step size: 7.69mV / step @ output 8.59mV / step @ output 1.51mV / step @ output
IV ALL RIGHTS RESERVED 33 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

EMI CAPS Caesar IV Support

TPS2065-1 HAS ACTIVE LOAD DISCHARGE SO R3505 IS NOSTUFF.
PLACE NEXT TO J3500
1.0A LIMIT
U3500
TPS2065-1
2 IN0 DGN OUT0 6 MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
3 IN1 VOLTAGE=3.3V
67 62 61 60 58 57 53 52 51 50
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 OUT1 7 MAKE_BASE=TRUE
49 47 41 40 39 38 37 31 30 27
NOSTUFF 91 89 79 77 76 74 73 72 71
OUT2 8 PP3V3_SW_SD_PWR 91

C3511 RESISTER ON FERRITE PADS!! 4 CRITICAL

10PF 37 ENET_CR_PWREN EN NOSTUFF
D 1 2 SDCONN_CMD_R 34 85
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_HEAD

1 C3501 1 C3500 1
R3502 THRM
OC* 5
1 C3507 1 C3505
1
R3505 D
NOSTUFF 5% 10UF 0.1UF GND 10UF 0.1UF 39.2K
C3512 50V
TABLE_5_ITEM

20% 10% 10K PAD

20% 10% 1%
116S0004 3 RES,ZERO OHM,0402 L3540,L3541,L3550 5% 1/16W
10PF CERM 2 6.3V 2 16V 2 6.3V 2 16V

9
402 X5R X7R-CERM 1/16W X5R X7R-CERM MF-LF
1 2
TABLE_5_ITEM

603 402 MF-LF 603 402 2 402

SDCONN_DATA_R<0> 34 85 152S1491 1 IND,WW,43NH,5%,100MA,0402 L3551 2 402
5% NOSTUFF
50V
CERM
C3513
402 10PF
1 2 SDCONN_DATA_R<1> 34 85
PU_SDCONN_OC_L
NOSTUFF 5% RESISTER ON FERRITE PADS!!
C3514 50V RESISTER ON FERRITE PADS!!
10PF CERM PLACE AT SOURCE.
402 PLACE AT CONNECTOR.
1 2 SDCONN_DATA_R<2> 34 85

5% NOSTUFF OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE

50V
CERM
C3515 L3540 L3541 L3550 L3551
402 10PF 10NH-300MA 10NH-300MA 13NH-430MA 68NH-140MA
1 2 SDCONN_DATA_R<3> 34 85
91 85 37 SDCONN_CLK 1 2 85 SDCONNF_CLK_FF 1 2 85 SDCONNF_CLK 1 2 85 SDCONN_CLK_FF 1 2
IN
NOSTUFF 5% 0402 0402 0402 0402
C3516 50V NOSTUFF NOSTUFF NOSTUFF NOSTUFF
10PF CERM
402
1 C3542 1 C3541 1 C3551 1 C3550 CRITICAL
1 2 SDCONN_DATA_R<4> 34 85
15PF 15PF 15PF 22PF
NOSTUFF
1%
2 50V
1%
2 50V
1%
2 50V
5%
2 50V
J3500
5% C0G C0G C0G CERM SD-CARD-K40-K41
50V
CERM
C3517 402 402 402 402
F-RT-TH
402 10PF
1 2 SDCONN_DATA_R<5> 3
34 85 VSS
NOSTUFF 6
5% VSS
C3518 50V
CERM 85 SDCONN_CLK_R 5 CLK
10PF 402 SDCONN_CMD R3555 10 1 2
5% 1/16W MF-LF 402
85 34 SDCONN_CMD_R 2
1 2 SDCONN_DATA_R<6> 91 85 37 BI CMD
34 85
SDCONN_DATA<0> R3560 10 1 2
5% 1/16W MF-LF 402
85 34 SDCONN_DATA_R<0> 7
91 85 37 BI DAT0
5% NOSTUFF SDCONN_DATA<1> R3561 10 1 2
5% 1/16W MF-LF 402
SDCONN_DATA_R<1> 8
C 50V
CERM
402
C3519
10PF
91 85 37

91 85 37
BI
BI SDCONN_DATA<2> R3562 10
10
1 2
5%
5%
1/16W
1/16W
MF-LF
MF-LF
402
402
85 34

85 34 SDCONN_DATA_R<2> 9
DAT1
DAT2
C
R3563
teknisi-indonesia
1 2 SDCONN_DATA_R<7> 34 85 91 85 37 SDCONN_DATA<3> 1 2 85 34 SDCONN_DATA_R<3> 1
BI
10 5% 1/16W MF-LF 402 CD/DAT3
5% 91 85 37 BI SDCONN_DATA<4> R3564 1 2 85 34 SDCONN_DATA_R<4> 10
DAT4
NOSTUFF 50V SDCONN_DATA<5> R3565 10 1 2
5% 1/16W MF-LF 402
SDCONN_DATA_R<5> 11
C3520 CERM
402
91 85 37 BI
R3566 10 5% 1/16W MF-LF 402
85 34
12
DAT5
10PF 91 85 37 BI SDCONN_DATA<6> 1 2 85 34 SDCONN_DATA_R<6> DAT6
1 2 SDCONN_WP SDCONN_DATA<7> R3567 10 1 2
5% 1/16W MF-LF 402
85 34 SDCONN_DATA_R<7> 13
34 37 91 91 85 37 BI DAT7
NOSTUFF 91 34 SDCONN_DETECT 14
5% OUT CARD_DETECT_SW
50V
CERM
C3521 15
CARD_DETECT_GND
(NC SWITCH)
402 10PF SDCONN_WP 16
1 2 SDCONN_DETECT 91 37 34 OUT WRITE_PROTECT_SW
34 91
4
SDCONN DETECT DEBOUNCE. ENET_RESET AND DETECT-CHANGED PCH GPIO PULSE GENERATION. VDD
5%
50V 17
CERM PP3V3_S4 SHLD_PIN
47 38 35 34 33 28 25 20 19 6
402 91 78 77 61 50 49 18
SHLD_PIN
19
SHLD_PIN
CRITICAL
1 C3530 20

1
1UF SHLD_PIN
VDD 10%
2 10V
X5R
U3530 402-1
516-0230
SLG4AP014V
TDFN
R3514
37 20 IN ENET_LOW_PWR 2 LOW_PWR 0
RST RST_OUT* 4 SLG_ENET_RESET_R_L 1 2 CIV_ENET_RESET_L OUT 37
R3511 LOGIC
NOSTUFF 5%
0 R3531 1/16W
85 27 IN ENET_RESET_L 1 2 SLG_ENET_RESET_L 3 RST_IN* MF-LF
0 402
5% 1 2 SDCONN_STATE_CHANGE OUT 19 24
1/16W NOSTUFF SDCONN_DETECT_L 6 DET_IN
DLY (OD) 8 SDCONN_STATE_CHANGE_S1R

XOR
-> FROM PCH GPIO MF-LF 5%
1 (IPU)
402 R3510 1/16W
MF-LF
-> TO PCH GPIO

10K 47 38 35 34 33 28 25 20 19 6 PP3V3_S4 DET_CHNGD*

402
B 5%
1/16W
MF-LF
402 2
91 78 77 61 50 49

D 3
(OD)
DET_OUT
7

*** Need to confirm with SW whether LATCH is required.

ENET_CR_DETECT_L OUT 37

-> TO ENET CHIP

B
R3530 1 Q3530 GND
THRM
PAD (SDCONN_STATE_RST_L will be required with LATCH)
100K SSM3K15FV

9
5%
1/16W SOD-VESM-HF
MF-LF DLY block is 20ms nominal
402 2
1 G S 2 When ENET_LOW_PWR deasserts, RST_OUT# deasserts for >80ms, then asserts for 10ms

regradless of RST_IN# state. Otherwise RST_OUT# follows RST_IN#

91 34 SDCONN_DETECT
FROM SD CONN ->
NOSTUFF
R35121
CRITICAL
1 C3535 0

1
1UF 5%
10% 1/16W
VDD MF-LF
2 10V
X5R 402 2
U3535 402-1
SLG4AP014V
TDFN
2 LOW_PWR
RST RST_OUT* 4
LOGIC NC
3 RST_IN*

6
R3535
DET_IN
DLY (OD) 8 SDCONN_STATE_CHANGE_S2R 1
0 2
XOR

(IPU)
DET_CHNGD* 5%
1/16W
(OD) 7 MF-LF
NC 402
DET_OUT

THRM WE WANT SDCONN_STATE_CHANGE TO WORK THE SAME IN S0 AS IN S3/4.

GND PAD
A COPY CIRCUIT BUT TIE THE RST_IN* LOW. A
5

SYNC_MASTER=REFERENCE_MLB SYNC_DATE=12/03/2010
WE CAN SWITCH BACK TO SINGLE PART WHEN THE PART IS CHANGED. PAGE TITLE

SD CARD READER
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
35 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 34 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

AIRPORT
D D
PCIE_AP_D2R_P OUT 17 84 91

PCIE_AP_D2R_N OUT 17 84 91
PP3V3_WLAN 35 47 91

1 CRITICAL CRITICAL
R3601 J3601 L3601
10K 90-OHM-100MA
5% 500913-0302 DLP11S
1/16W F-ST-SM SYM_VER-1

MF-LF 32 4 3
2 402
31 PCIE_CLK100M_AP_P IN 17 84

WHERE SHOULD THIS GO?

91 WLAN_THROTTLE_L 2 1
1 2 PCIE_CLK100M_AP_N 17 84
4 3 IN
RESET#
PLACE_NEAR=J3601.11:2.54 MM
91 77 38 18 PCIE_WAKE_L WAKE# 6 5
OUT
8 PLACE_NEAR=J3601.15:5 MM
CLKREQ# 7 3.3V S3 WLAN FET
10 9 91 84 PCIE_CLK100M_AP_CONN_P C3631
12 11 91 84 PCIE_CLK100M_AP_CONN_N 0.1UF MOSFET TPCP8102
NC 1 2 PCIE_AP_R2D_C_P IN 17 84
14 13
NC
16
C3630 10%
X7R-CERM
16V 402
CHANNEL P-TYPE
15 91 84 PCIE_AP_R2D_P 0.1UF
18 17 91 84 PCIE_AP_R2D_N 1 2 PCIE_AP_R2D_C_N CRITICAL RDS(ON) 20-30 mOhm @2.5V
IN 17 84
20 19 10%
X7R-CERM Q3650 LOADING 1.1 A (EDP)

ANTENNA CABLE 22 21 91 83 USB_BT_CONN_P

16V 402
PLACE_NEAR=J3601.17:5 MM
TPCP8102
23V1K-SM
CLIPS 24
26
23
25
91 83 USB_BT_CONN_N
CRITICAL
PP3V3_WLAN_FET
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
PP3V3_S4 6 19 20 25 28 33 34 35 38 47 49
50 61 77 78 91

5 6 7 8
VOLTAGE=3.3V 1.1 A PEAK
L3603
28 27 PP3V3_S4_BT_F
BLUETOOTH

1 2 3
91

30 29 MIN_LINE_WIDTH=0.4 mm 90-OHM 606 mA nominal max

S
DLP0NS

D
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V SYM_VER-1
1
CL3601
CLIP-ANT
1 C3632 C3633
1 4 3 USB_BT_P R3651
34 33 BI 25 83
C3651 1 10K

4 G
1 0.01UF 1UF
C CLIP-SM-K40
516S0582
10%
2 50V
X7R
10%
10V 2
X5R 1 2 USB_BT_N
0.033UF
10%
16V 2
5%
1/16W
MF-LF
C
402 402-1 BI 25 83
C3650 X5R
402 R3650 2 402
PLACE_NEAR=J3601.27:2.54 MM 0.1UF
FLEX SIDE = 516S0573 1 2 33.2K2
P3V3WLAN_SS 1 PM_WLAN_EN_L IN 62
CL3602
CLIP-ANT L3606 10%
1%
FERR-120-OHM-1.5A 16V 1/16W
1 MF-LF
X7R-CERM 402
CLIP-SM-K40 2 1 PP3V3_S4 6 19 20 25 28 33 34 35 38 47 49
402
50 61 77 78 91
0402
PLACE_NEAR=J3601.27:2.54 MM

CL3603
CLIP-ANT L3604
1 FERR-120-OHM-3A
CLIP-SM-K40 PLACE_NEAR=J3601.27:2.54 MM
91 47 35 PP3V3_WLAN 1 2
MIN_LINE_WIDTH=0.6 mm 0603
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
1 C3622 1 C3623 1 C3624 C3621 1 1 C3620
CL3604 CL3614 0.01UF 0.01UF 1UF
10% 10% 10% 0.1UF 10UF
CLIP-ANT CLIP-ANT 2 50V 2 50V 2 10V 10% 10%
1 1 X7R X7R X5R 16V 16V
402 402 402-1 X7R-CERM 2 2 X5R-CERM
CLIP-SM-K40 CLIP-SM-K40 402 0805

CL3615
CLIP-ANT
1
CLIP-SM-K40 Supervisor & CLKREQ# Isolation
PP3V3_S4 6 19 20 25 28 33 34 35 38 47 49
50 61 77 78 91
CL3606 CL3616
B 1
CLIP-ANT
1
CLIP-ANT B
CRITICAL 1 C3640

1
CLIP-SM-K40 CLIP-SM-K40
R36401 1
R3653 VDD 0.1UF
10%
100K 232K
5% 1% U3640 2 16V
X7R-CERM
1/16W 1/16W 402
MF-LF MF-LF SLG4AP016V
CL3617
CLIP-ANT
402 2 2 402 TDFN
1 WF: Need pull-up? P3V3WLAN_VMON 2 SENSE
+
CLIP-SM-K40 0.7V -

DLY
CL3608 CL3618 91 AP_RESET_CONN_L 4 RESET*
CLIP-ANT CLIP-ANT MR* 3 AP_RESET_L IN 27
1 1
CLIP-SM-K40 CLIP-SM-K40 EN 6 AP_PWR_EN 19 24 62
IN
OUT 8 AP_CLKREQ_L OUT 17
91 AP_CLKREQ_Q_L 7 IN (OD)

THRM
1 PAD GND
R3654

5
100K
1%
1/16W
MF-LF
2 402

806-0444
STANDOFFS FOR X28 CARD
A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

WIRELESS,BT CONNECTOR
DRAWING NUMBER SIZE

SDF3600 SDF3601 SDF3602 Apple Inc. 051-8768 D

REVISION
STDOFF-3.85OD4.5H-1.3-TH STDOFF-3.85OD4.5H-1.3-TH STDOFF-3.85OD4.5H-1.3-TH R

1 1 1
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
860-1277 860-1277 860-1277 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 36 OF 512
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 35 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

PLACE ONE CAP NEAR EACH PINS 3 AND 4 OF T3801 AND T3802
ENET_CONN_CTAP

C3800 1 C3801 1 C3802 1 C3803 1

0.1UF 0.1UF 0.1UF 0.1UF
10% 10% 10% 10%
16V 16V 16V 16V
X7R-CERM 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM 2
402 402 402 402

ETHERNET CONNECTOR
CRITICAL
T3801
85 37 BI ENET_MDI_N<2> 1 SM 12 85 ENET_MDI_TRAN_N<2>

85 37 BI ENET_MDI_P<2> 2 11 85 ENET_MDI_TRAN_P<2>
CRITICAL
3 10 ENET_CENTER_TAP<1>
C TX
85 J3800
RJ45-J40 C
F-R-TH
TLA-6T213HF ENET_MDI
4 9 ENET_CENTER_TAP<3> 85 1
TRAN_P0
2
TRAN_N0
85 37 BI ENET_MDI_P<1> 5 8 85 ENET_MDI_TRAN_P<1> 3
TRAN_P1 *
4
TRAN_P2 *SPLIT PAIR
85 37 BI ENET_MDI_N<1> 6 7 85 ENET_MDI_TRAN_N<1> 5
TRAN_N2
RX 6 *
TRAN_N1
7
TRAN_P3
8
CRITICAL TRAN_N3

T3802 9
85 37 BI ENET_MDI_P<0> 1 SM 12 85 ENET_MDI_TRAN_P<0> 10
SHIELD
11 PINS
85 37 BI ENET_MDI_N<0> 2 11 85 ENET_MDI_TRAN_N<0> 12

3 85 10 ENET_CENTER_TAP<2>
TX
TLA-6T213HF 514-0785
4 9 85 ENET_CENTER_TAP<0>

85 37 BI ENET_MDI_N<3> 5 8 85 ENET_MDI_TRAN_N<3>

85 37 BI ENET_MDI_P<3> 6 7 85 ENET_MDI_TRAN_P<3>
RX

B TRANSFORMERS SHOULD BE B
MIRRORED ON OPPOSITE
SIDES OF BOARD.

6 5 7 4 9 2 10 1 6 5 7 4 9 2 10 1
1
R3800 1
R3801 1
R3802 1
R3803 REQUIRES 1200V ISOLATION!
75 75 75 75
1% 1% 1% 1%
NC
IO
NC
IO
NC
IO
NC
IO

NC
IO
NC
IO
NC
IO
NC
IO

1/16W 1/16W 1/16W 1/16W

MF-LF MF-LF MF-LF MF-LF
D3800.1: PLACE_NEAR=T3800.2:4 MM 2 402 2 402 2 402 2 402
D3800.5: PLACE_NEAR=T3800.6:4 MM 85 ENET_CMODE_REF
CRITICAL
D3801.1: PLACE_NEAR=T3800.8:4 MM
D3800 D3801 1 C3810
GND

GND

D3801.5: PLACE_NEAR=T3800.12:4 MM 1000PF

RCLAMP0524P RCLAMP0524P 10%
SLP2510P8 SLP2510P8 2 2KV
CERM
3 3 1206
NOSTUFF NOSTUFF
CRITICAL CRITICAL

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

ETHERNET CONNECTOR
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
38 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 36 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.

If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.

IF ENABLED: SR_VDD/SR_VDDP CONNECT TO PP3V3_ENET (ADD BYPASSING), LX CONNECTS TO INDUCTOR.

SPECIAL STAR ROUTING NEEDED ON THESE PINS. DECOUPLING ON PG 40.

PP1V2_ENET 6 38 91

???mA (1000base-T, Caesar V)

91 62 38 37 26 6 PP3V3_ENET
281mA (1000base-T max power, Caesar IV)
SEE CAPS ON NEXT PAGE FOR THESE PINS.
VDD for Card Reader I/O

37 PP3V3R1V8_ENET_LR_OUT
CRITICAL ENET_SR_LX 38

L3900 ENET_SR_VFB CRITICAL

FERR-600-OHM-0.5A 38

1 2
L3920
PP3V3_ENET_PHY_XTALVDDH FERR-600-OHM-0.5A
D SM MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V C3900 1 PP1V2_ENET_PHY_AVDDL 1 2 D
MIN_LINE_WIDTH=0.4 mm SM
0.1UF MIN_NECK_WIDTH=0.2 mm
10% VOLTAGE=1.2V
16V
X7R-CERM 2
402
C3921 1 1 C3920
CRITICAL 0.1UF 4.7UF
10% 10%
L3905 16V
X7R-CERM 2 2 6.3V
X5R-CERM CRITICAL
FERR-600-OHM-0.5A
1 2
402 603 L3925
PP3V3_ENET_PHY_BIASVDDH FERR-600-OHM-0.5A
SM MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm PP1V2_ENET_PHY_PCIEPLL 1 2
VOLTAGE=3.3V 1 C3905 MIN_LINE_WIDTH=0.4 mm SM
0.1UF MIN_NECK_WIDTH=0.2 mm
10% VOLTAGE=1.2V
2 16V
X7R-CERM C3926 1 1 C3925
CRITICAL 402 0.1UF 4.7UF
10% 10%
L3910 16V
X7R-CERM 2 2 6.3V
X5R-CERM CRITICAL
FERR-600-OHM-0.5A
1 2
402 603 L3930
PP3V3_ENET_PHY_AVDDH FERR-600-OHM-0.5A
SM MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm PP1V2_ENET_PHY_GPHYPLL 1 2
VOLTAGE=3.3V R39101 1 C3910 1 C3911 MIN_LINE_WIDTH=0.4 mm SM
4.7K 0.1UF 0.1UF MIN_NECK_WIDTH=0.2 mm
5% 10% 10% VOLTAGE=1.2V
1/16W 2 16V
X7R-CERM 2 16V
X7R-CERM C3931 1 1 C3930
MF-LF 402 402
402 2 0.1UF 4.7UF
10% 10%
16V 2 6.3V
X7R-CERM 2 X5R-CERM
402 603

R39401 1
R3941 C3915 1 1 C3916
4.7K 4.7K 4.7UF 0.1UF

42
48

BIASVDDH 37

XTALVDDH 17

20
56
62

SR_VDD 14

SR_VDDP 15

SR_LX 16

SR_VFB 13
39
45
51

29
32

GPHY_PLLVDDL 36
35
61
10% 10% C3936 1 1 C3935

7
5% 5% 6.3V
1/16W 1/16W X5R-CERM 2 2 16V
X7R-CERM 0.1UF 10UF
C 67 62 61 60 58 57 53 52 51 50
PP3V3_S0 MF-LF
402 2
MF-LF
2 402
603 402 10% 10% C

PCIE_PLLVDDL
24 23 21 20 19 18 17 13 7 6 AVDDH VDDO AVDDL VDDC 16V
49 47 41 40 39 38 34 31 30 27
91 89 79 77 76 74 73 72 71 X7R-CERM 2 2 16V
X5R-CERM LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for
402 0805 the card reader on-chip I/O.
1
C3950 R3942 Connect only to U3900 pin 20.
1K
0.1UF 5% Current CRITICAL
1 2 1/16WLimiting
84 17 OUT PCIE_ENET_D2R_N MF-LF
2 402 Resistor U3900 PP3V3R1V8_ENET_LR_OUT 37
10% MIN_LINE_WIDTH=0.3 mm
16V
X7R-CERM
C3951 BCM57765_VMAIN_PRSNT 58 VMAIN_PRSNT (IPD) BCM57765B0 TRD0_P 40 ENET_MDI_P<0> BI 36 85
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V
402 0.1UF QFN-8X8 41 ENET_MDI_N<0> MAKE_BASE=TRUE
1 2 TRD0_N BI 36 85
PCIE_ENET_D2R_P
84 17 OUT 84 PCIE_ENET_D2R_C_N 27 PCIE_TXD_N TRD1_P 44 ENET_MDI_P<1> BI 36 85
1 C3970 1 C3971 1 C3972
10% 84 PCIE_ENET_D2R_C_P 28 PCIE_TXD_P 343S0534 TRD1_N 43 ENET_MDI_N<1> BI 36 85
4.7UF 0.1UF 0.1UF
16V 10% 10% 10%
C3955 X7R-CERM
402 TRD2_P 46 ENET_MDI_P<2> BI 36 85 2 6.3V 16V 16V
X5R-CERM 2 X7R-CERM 2 X7R-CERM
84 PCIE_ENET_R2D_P 33 PCIE_RXD_P
603 402 402
0.1UF TRD2_N 47 ENET_MDI_N<2> BI 36 85
1 2
84 PCIE_ENET_R2D_N 34 PCIE_RXD_N
84 17 IN PCIE_ENET_R2D_C_P TRD3_P 50 ENET_MDI_P<3> BI 36 85

10% 84 17 IN PCIE_CLK100M_ENET_P 31 PCIE_REFCLK_P TRD3_N 49 ENET_MDI_N<3> BI 36 85

16V
X7R-CERM
C3956 84 17 IN PCIE_CLK100M_ENET_N 30 PCIE_REFCLK_N
402 0.1UF ENET_ASF_GPIO_R R3930 3.3K ENET_ASF_GPIO
1 2 GPIO_0/CR_ACT_LED* 5 1 2 OUT 46
PCIE_ENET_R2D_C_N CIV_ENET_RESET_L 11 PERST*

(IPD)
84 17 IN 34 IN (IPD) 5% 1/16W MF-LF 402
GPIO_1/LR_OUT 8
10% ENET_CLKREQ_L 12 CLKREQ* GPIO_2/MEDIA_SENSE 9 ENET_MEDIA_SENSE
R3943 16V
X7R-CERM
17 OUT (OD) OUT 38

ENET_WAKE_L 1
0 2 402 BCM57765_WAKE_R_L 3 WAKE* NOTE: "IPx" == Programmable pull-up/down
38 OUT (OD)
(IPx) SD_DETECT o 1 ENET_CR_DETECT_L IN 34
(See note) 5%
1/16W SD_DETECT can only be used active low due to errata.
MF-LF
402
34 20 IN ENET_LOW_PWR 4 LOW_PWR (IPD) (IPU) CR_CMD 26 85 ENET_CR_CMD R3974 33 1 2 SDCONN_CMD IN 34 85 91
WAKE# PLACE_NEAR=U3900.26:3 MM 5% 1/16W MF-LF 402

ENET_ASF_SMB_CLK 6 SMB_CLK CR_CLK 21 85 ENET_CR_CLK R3971 33 1 2 SDCONN_CLK OUT 34 85 91

Must isolate from PCIe WAKE# if PHY 87 49 BI PLACE_NEAR=U3900.21:3 MM 5% 1/16W MF-LF 402
is powered-down in S3/S5. Standard 87 49 BI ENET_ASF_SMB_DATA 10 SMB_DATA (IPD) CR_DATA0 25 85 ENET_CR_DATA<0> R3950 33 1 2 SDCONN_DATA<0> BI 34 85 91
R3951 33 5% 1/16W MF-LF 402
N-channel FET isolation suggested. CR_DATA1 24 85 ENET_CR_DATA<1> 1 2 SDCONN_DATA<1> BI 34 85 91
BCM57765_SCLK 66 SCLK_SPD1000LED* 5% 1/16W MF-LF 402
B If PHY is always powered then alias
37 BI
BCM57765_MISO 64 CR_DATA2 23 85 ENET_CR_DATA<2> R3952 33 1 2 SDCONN_DATA<2> BI 34 85 91
B
37 IN SI/EEDATA R3953 33 5% 1/16W MF-LF 402
=ENET_WAKE_L to PCIE_WAKE_L. CR_DATA3 22 85 ENET_CR_DATA<3> 1 2 SDCONN_DATA<3>

(IPU)
BI 34 85 91
BCM57765_MOSI 65 SO_LINKLED* 5% 1/16W MF-LF 402
37 BI
BCM57765_CS_L 63 CR_DATA4 52 85 ENET_CR_DATA<4> R3975 33 1 2 SDCONN_DATA<4> BI 34 85 91
CS*/EECLK 5% 1/16W MF-LF 402
37 BI
CR_DATA5 53 85 ENET_CR_DATA<5> R3976 33 1 2 SDCONN_DATA<5> BI 34 85 91
R3977 33 5% 1/16W MF-LF 402

(IPU)
TP_BCM57765_SPD100LED_L 2 SPD100LED*/SERIAL_DO (OD) CR_DATA6 54 85 ENET_CR_DATA<6> 1 2 SDCONN_DATA<6> BI 34 85 91
5% 1/16W MF-LF 402
TP_BCM57765_TRAFFICLED_L 67 TRAFFICLED*/SERIAL_DI (OD) CR_DATA7 55 85 ENET_CR_DATA<7> R3978 33 1 2 SDCONN_DATA<7> BI 34 85 91
5% 1/16W MF-LF 402
NO_TEST=TRUE
MS_INS* 59 NC_BCM57765_CE_L_MS_INS_L 91
BCM5764_CLK25M_XTALI 18 XTALI No MS (Memory Stick) Insert feature needed.

(IPU)
85 26 IN
CR_LED*/CR_BUS_PWR 60 ENET_CR_PWREN OUT 34 Control signal to light LED or control SD bus power.
85 26 OUT BCM5764_CLK25M_XTALO 19 XTALO
CR_WP* 57 SDCONN_WP IN 34 91

BCM57765_RDAC 38 RDAC SR_DISABLE 68 BDM57765_SR_DISABLE R3980 1K 1 2

THRM_PAD 5% 1/16W MF-LF 402

69
PHY Non-Volatile Memory 1
R3965 ENET 1.2V SR IS ENABLED IF SR_DISABLE is PULLed-DOWN.
1.24K
ROM contains MAC address, PCIe config 1%
1/16W ENET_CR Signals
info as well as code for Bonjour proxy. MF-LF
Required for proper PHY operation.
2 402
BCM requests SD CR[0:7], CMD, CLK termination.
(Required ROM size TBD)

91 62 38 37 26 6 PP3V3_ENET
ENET supports both active-levels for WP.
6

1 C3990
VCC 0.1UF
www.teknisi-indonesia.com
10%
U3990 2 16V
X7R-CERM
AT45DB011D 402
SOIC-8S1
37 IN BCM57765_SCLK 2 SCK SI 1 BCM57765_MOSI IN 37
OMIT_TABLE
A 37 BCM57765_CS_L 4 CS* CRITICAL
SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
IN PAGE TITLE
SO 8 BCM57765_MISO OUT
5 WP*
NOSTUFF
37
ETHERNET PHY (CAESAR IV)
1 1 DRAWING NUMBER SIZE
3 RESET* R3990 R3997
GND 4.7K 4.7K Apple Inc. 051-8768 D
5% 5% REVISION
7

1/16W 1/16W R
MF-LF MF-LF 9.0.0
2 402 2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
NOTE: Pull-down on SO plus internal pull-ups on
THE INFORMATION CONTAINED HEREIN IS THE
other 3 SPI pins configures ENET for the PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
Atmel AT45DB011D (1Mbit) ROM. If a different I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 39 OF 512
ROM is used then the straps must change. II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
NOTE: ENETM requires SI pull-down instead of SO.
IV ALL RIGHTS RESERVED 37 OF 104

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

CAESAR IV 1.2V INT.VR CMPTS

CRITICAL
L4020
4.7UH-30%-1.2A-0.21OHM
91 62 38 37 26 6 PP3V3_ENET 1 2 ENET_SR_LX 37
2520 MIN_LINE_WIDTH=0.4MM
PLACE_NEAR=U3900.16:1mm MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
1 C4020 1 C4021 SWITCH_NODE=TRUE
4.7UF 0.1UF DIDT=TRUE
10% 10%
2 6.3V
X5R-CERM 2 16V
X7R-CERM XW4020
SM
603 402
1 2 ENET_SR_VFB 37
MIN_LINE_WIDTH=0.25MM
PLACE_NEAR=C4025.1:1MM MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V

PLACE_NEAR=U3900.14:1mm
PLACE_NEAR=U3900.14:3mm
PP1V2_ENET 6 37 91
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.2MM
1 C4025
10UF
1 C4026
0.1UF
VOLTAGE=1.2V
Ethernet WAKE# Isolation
20% 10%
PLACE_NEAR=L4020.1:1MM 2 6.3V
X5R 2 16V
X7R-CERM
603 402 PP3V3_ENET 6 26 37 38 62 91
PLACE_NEAR=L4020.1:3MM

C 1
C
Q4050 R4050
1 10K
SSM3K15FV 5%
1/16W

G
SOD-VESM-HF MF-LF
2 402

S
91 77 35 18 OUT PCIE_WAKE_L ENET_WAKE_L IN 37
3 2

R4010
B 37 IN ENET_MEDIA_SENSE 2
12K 1 ENET_MEDIA_SENSE_RDIV OUT 17 B
1%
1/16W
1
MF
402 R4019
10K
5%
1/16W
MF-LF
2 402

49 47 35 34 33 28 25 20 19 6
91 78 77 61 50
PP3V3_S4
Q4010 D 3

R40111 SSM6N37FEAPE
SOT563
100K
5%
1/16W
MF-LF
402 2 5 G S 4
ENET_MSNS_EN_L

Q4010 D 6
SSM6N37FEAPE
SOT563
67 62 61 60 58 57 53 52 51 50
24 23 21 20 19 18 17 13 7 6 PP3V3_S0
49 47 41 40 39 37 34 31 30 27
91 89 79 77 76 74 73 72 71
R4012 2 G S 1
0
2 1 ENET_MSNS_EN
5%
1/16W
MF-LF
402
A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/30/2010 A
PAGE TITLE

ETHERNET SUPPORT
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
40 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 38 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
91 PP1V5_S0 7 17 21 23 53 71 72 91
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27
PP3V3_S0
89 79 77 76 74 73 72 71 67

C4100 1 C4101 1 C4102 1 C4103 1 C4104 1 C4105 1 C4124 1 C4123 1 C4122 1 C4121 1 C4120 1
R4125 1 1
R4129
1UF 1UF 1UF 1UF 1UF 1 1K
1UF 1UF 1UF 1UF 1UF 1UF 10% 10% 10% 10% 10% 5% 5%
10% 10% 10% 10% 10% 10% 10V 10V 10V 2 10V 2 10V
10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 X5R 2 X5R 2 X5R X5R X5R 2 1/10W
MF-LF
1/16W
MF-LF
X5R X5R X5R X5R X5R X5R 402-1 402-1 402-1 402-1 402-1 603 2
402-1 402-1 402-1 402-1 402-1 402-1 2 402

PP1V5_FW_VDDA
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
C4106 1 C4107 1 C4108 1 C4128 1 C4127 1 C4126 1 C4125 1
1 1UF 1UF 1UF 1UF
R4110 1UF 1UF 1UF
D 1
5%
10%
10V 2
X5R
10%
10V 2
X5R
10%
10V 2
X5R
10%
10V 2
X5R
402-1
10%
10V 2
X5R
402-1
10%
10V 2
X5R
402-1
10%
10V 2
X5R
402-1
D
1/10W 402-1 402-1 402-1
MF-LF
2 603
PP3V3_FW_AVDD
MIN_LINE_WIDTH=0.3 mm PU_FW_VP
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
1 C4110
1 C4111 1 C4112 1 C4113 1 C4114 1 C4115 1 PP1V96_S0_FW
R4117 1UF
10%
1UF
10%
1UF
10% 10%
1UF 1UF
10%
1UF
10%
40

1 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2

5%
1/10W X5R
402-1
X5R
402-1
X5R
402-1
X5R
402-1
X5R
402-1
X5R
402-1 C4132 1 C4131 1 C4130 1
R4135 1
R41191 MF-LF
2 603
1UF
10%
1UF
10%
1UF
10% 1
1 10V 2 10V 2 10V 2 5%
5% X5R X5R X5R 1/10W
1/10W PP3V3_FW_VDDA 402-1 402-1 402-1 MF-LF
MF-LF MIN_LINE_WIDTH=0.3 mm 603 2
603 2 MIN_NECK_WIDTH=0.2 mm 1
VOLTAGE=3.3V R4190
PP3V3_FW_PLLVDD PP1V96_FW_PLLVDD 4.7
MIN_LINE_WIDTH=0.3 mm MIN_LINE_WIDTH=0.3 mm 5%
MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm 1/16W
VOLTAGE=3.3V FWXIO_VDD15COMB VOLTAGE=1.96V MF-LF
Power Aliases:
C4117 1 C4118 1 C4119 1
FWXIO_VDD33COMB C4135 1
2 402
1UF 1UF 1UF 1UF
10% 10% 10% FWXIO_VDD33COMIO 10% PP1V96_FW_XTAL
FW_FWPHY nets are PHY power, and for 10V 2 10V 2 10V 2 10V 2 MIN_LINE_WIDTH=0.3 mm
X5R X5R X5R X5R

G10
H10
J10

B12

A10

E10
F10

M10

K10

B10

C12

B11

C11
402-1 402-1 402-1 402-1 MIN_NECK_WIDTH=0.2 mm

N7

M7

E3

M5

C8
J3
K3

C3

J9
K9

M4

G3
H3

M6
B8
P7

B9
B7
B5

C9
F3
M9
multi-port systems must come from bus power. VOLTAGE=1.96V
4
FWRS0_FWXIO nets are OHCI/PCIe power, and C4137 1 1 C4138 1 C4139 C4190 1

PLLVDD_3_3

PLLVDD_CORE

VDD_15_COMB

VDD_33_COMB

VDD_33_COM_IO
FWXIO_REF_PCIE VCC 0.22UF
VDD_33 DVDD_3_3 VDDA_33 AVDD_3_3 VDD_15 VDDA_15 DVDD_CORE 1UF 1UF 1UF 10%

(VDD_33_AUX)
can be S0.
NEED 14.53K NOMINAL. 10%
10V 2
10% 10% Y4190 6.3V
CERM-X5R 2
1 1 X5R 2 10V
X5R 2 10V
X5R 98P3040MHZ 402
For single-port systems, all FW power should R4141 R4140 CRITICAL 402-1 402-1 402-1 R4191 SM
be tied together and powered by S0 or by the 232 14.3K 22 3 CRITICAL 1
1% 1% U4100 1 2 85 CLK98M_FW_XI_R OUT TRI-ST/NC
5K pull-down device detect circuit. 1/16W 1/16W
MF-LF MF-LF XIO2211 5%
1/16W
2 402 402 2
MF-LF GND
BGA
C PLACEMENT_NOTE=PLACE C4140 CLOSE TO U1400 (MCP)
PLACEMENT_NOTE=PLACE C4141 NEXT TO C4140.
FWXIO_REF0_PCIE
FWXIO_REF1_PCIE
A13
A12
REF0_PCIE
REF1_PCIE Single-port:
XI
RSVD19
P4
P3
85 CLK98M_FW_XI
TP_FWOHCI_XO
402
2 C
PC[0:2] = ’000’
84 17 IN PCIE_FW_R2D_C_P C4140 1 2
10% 16V X7R-CERM
402
27 IN FW_RESET_L B13 PERST* PC0 E9 FW_PHY_PC0 IN 40 TP_CLK98M_TS_L
0.1UF Multiple-ports: PC1 E8 FLOAT TO ENABLE,
84 PCIE_FW_R2D_P A4 RXP
84 17 IN PCIE_FW_R2D_C_N C4141 1 2
10% 16V X7R-CERM
402 84 PCIE_FW_R2D_N A3 RXN
PC[0:2] = ’100’ PC2 A11 LOW TO DISABLE.
0.1UF PP3V3_S0 50 51 52 53 57 58 60 61 62 67
6 7 13 17 18 19 20 21 23 24 27
Alias =FWPHY_PC0 DS0 N9 FW_PHY_DS0 IN 40 30 31 34 37 38 39 40 41 47 49
PCIE_FW_D2R_C_P A9 TXP PCI EXPRESS R4170 71 72 73 74 76 77 79 89 91
84 17 OUT PCIE_FW_D2R_P C4145 1 2
10% 16V X7R-CERM
402
84

84 PCIE_FW_D2R_C_N A8 TXN
as appropriate DS1 P9 FW_PHY_DS1 IN 40
1K
1
R4171
0.1UF LINKON_L E1 FWOHCI_LINKON_L 1 2 470
5%
84 17 OUT PCIE_FW_D2R_N C4146 1 2 LKON D1 FWPHY_LKON_DS2 5%
1/16W
1/16W
10% 16V X7R-CERM
402 MF-LF DS2 hard-strapped to 1,
0.1UF 17 OUT FW_CLKREQ_L J12 CLKREQ* MF-LF 402
PLACEMENT_NOTE=PLACE C4145 CLOSE TO U4100 LCLK_L G2 FWOHCI_CLK98M_LCLK 402 2
page assumes no more than
PLACEMENT_NOTE=PLACE C4146 NEXT TO C4145.
84 17 IN PCIE_CLK100M_FW_P A1 REFCLK+ LCLK_P H2 2 FW800 connectors
84 17 IN PCIE_CLK100M_FW_N B1 REFCLK-
PCLK_L G1 FWPHY_CLK98M_PCLK Strap DSx high on unused ports.
FWXIO_REFCLK_SEL H13 REFCLK_SEL PCLK_P F1

PINT_L D2 FWPHY_PINT
FWXIO_SCL J13 SCL PINT_P D3
FWXIO_SDA H12 SDA 338S0765 LPS_L C1 FWOHCI_LPS
P1 GPIO0 LPS_P C2
NC
R41501 R41511 1
R4152 NC
N2 GPIO1 1
R4175
1K 220 220 P2 LREQ_L F2 FWOHCI_LREQ
5% 5% 5% NC GPIO2 E2 10K
1/16W 1/16W 1/16W N3 LREQ_P 5%
MF-LF MF-LF MF-LF NC GPIO3 1/16W
402 2 402 2 2 402 N4 (IPU) H1 MF-LF
NC GPIO4 CTL0 NC 2 402
P5 GPIO5 CTL1 J1
NC NC
P6 GPIO6
NC D0 J2
NC
B NC
N6 GPIO7
D1 K2
NC B
20 OUT FW_PME_L P8 OHCI_PME* D2 K1
NC
D3 L1
FWXIO_CYCLEOUT N8 CYCLEOUT NC
D4 L2
NO STUFF NC
TP_FWXIO_GRST_L C13 L3 1
1
R4153
GRST* (IPU) D5
M2
NC R4185
D6 NC 6.34K
47K M3 1%
PPVP_FW_PHY_CPS
5% D7 1/16W
91
62 61 60 58 57 53 52 51 50 49
PP3V3_S0 1/16W TP_FWXIO_JTAG_TMS E12 RSVD0 (JTAG_TMS) 1394B OHCI & PHY NC MF-LF
41

24 23 21 20 19 18 17 13 7 6 MF-LF 2 402
47 41 40 39 38 37 34 31 30 27
2 402 TP_FWXIO_JTAG_TDO F12 RSVD1 (JTAG_TDO) R0 N1 FWPHY_R0 1
89 79 77 76 74 73 72 71 67

1
TP_FWXIO_JTAG_TDI F13 RSVD2 (JTAG_TDI) R1 M1 FWPHY_R1 R4186
R4160 390K
FWXIO_JTAG_TCK G12 RSVD3 (JTAG_TCK)
B3 5%
1K K12 PD 1/16W
5% NC RSVD4 MF-LF
1/16W 2 402
MF-LF NC
L12 RSVD5 CNA A2 TP_FWPHY_CNA
2 402 L13 RSVD6 CPS P12 FWPHY_CPS
NC
FWXIO_SNOOP_EN M8 RSVD7
M11 (IPU) PHY_RESET* B4 FWPHY_RESET_L
(Snoop Enable, for FireBug) NC RSVD8
1 M12
R4162 NC RSVD9 1 C4189
1K NC
M13 RSVD10 TPBIAS0 K13 FW_P0_TPBIAS BI 40
0.22UF
5% 10%
1/16W NC
N10 RSVD11 Unused Ports: RSVD26 G13 NC_FW_P1_TPBIAS 91
1 MF-LF 2 6.3V
CERM-X5R
R4180 2 402 NC
N11 RSVD12 RSVD23 E13 NC_FW_P2_TPBIAS 91 402
N12 TP/NC TPBIASx
1K NC RSVD13
5% N13 TP/NC TPAx_P/TPAx_N TPA0+ K14 FW_P0_TPA_P BI 40
1/16W NC RSVD14
MF-LF P10 Ground TPBx_P/TPBx_N TPA0- L14 FW_P0_TPA_N BI 40
402 2 NC RSVD15
P11 RSVD25 F14 NC_FW_P1_TPAP 91
NC RSVD16
RSVD27 G14 NC_FW_P1_TPAN 91
FWXIO_JTAG_TRST D12 RSVD17 (JTAG_TRST)
R41811 2
R4182 FWXIO_VREG_PD33 D13 RSVD18
RSVD20 B14 NC_FW_P2_TPAP 91

1K 1K C14 NC_FW_P2_TPAN
A 5%
1/16W
MF-LF
5%
1/16W
MF-LF
RSVD21

TPB0+ M14 FW_P0_TPB_P

91

40
SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
FWPHY_BMODE A5 BI PAGE TITLE
402 2 1 402 BMODE
TPB0- N14 FW_P0_TPB_N
FWPHY_TESTM B2 TESTM RSVD28 H14
BI 40
FW LLC/PHY (XIO2211B)
DRAWING NUMBER SIZE
FWPHY_TESTW A6 VREG_PD RSVD29 J14
P13 SE RSVD22 D14 Apple Inc. 051-8768 D
REVISION
R41832 1
R4184 P14 SM RSVD24 E14 R
9.0.0
1K 1K PLLGND GND VSS VSSA VSSA_PCIE
5% 5% NOTICE OF PROPRIETARY PROPERTY: BRANCH
1/16W 1/16W
MF-LF MF-LF THE INFORMATION CONTAINED HEREIN IS THE
402 1 2 402 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
N5

A14
A7

F5
C10
B6

C4
C5
C6
C7
E6
E7
F6
F7
F8
F9
G5
G6
G7
G8
G9
H5
H6
H7
H8
H9
J5
J6
J7
J8
K5
K6
K7
K8

THE POSESSOR AGREES TO THE FOLLOWING: PAGE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
41 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 39 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Termination
PLACE CLOSE TO FIREWIRE PHY (U4100)

39 BI FW_P0_TPBIAS
VOLTAGE=1.86V
MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.08MM

1394 PHY 1.95V SUPPLY 1 C4250

TI PHY requires 1UF, not 0.33uF spec value. 1UF
D
10%
10V
2 X5R
402-1
D
L4250 L4251
U4200 18NH-250MA 18NH-250MA
91 89 79 77
TPS799195 1 2 1 2
58 57 53 52 51 50 49 47
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 SON TI PHY "Peaking Inductors" To improve Data Eye. 0402 0402
41 40 39 38 37 34 31 30 27
76 74 73 72 71 67 62 61 60 6 IN OUT 1 PP1V96_S0_FW 39
4 EN NR 2 P1V95_FW_NR VOLTAGE=1.96V
MIN_LINE_WIDTH=0.5 MM FW_P0_TPA_L_P FW_P0_TPA_L_N
CRITICAL MIN_NECK_WIDTH=0.2 mm 85
VOLTAGE=1.86V VOLTAGE=1.86V
C4200 1 NC
5 NC
THRML
C4201 1 1 C4202 NO_TEST=TRUE NO_TEST=TRUE
1UF GND PAD
10% 0.01UF 2.2UF
10V 2 3 7 10% 20%
X5R
402-1
50V 2
X7R 2 6.3V
CERM
R42501 1
R4251
402 402-LF 56.2 56.2
1% 1%
1/16W 1/16W
MF-LF MF-LF
402 2 2 402

39 BI FW_P0_TPA_P FW_PORT0_TPA_P BI 41 85
MAKE_BASE=TRUE
39 BI FW_P0_TPA_N FW_PORT0_TPA_N BI 41 85
MAKE_BASE=TRUE
39 BI FW_P0_TPB_P FW_PORT0_TPB_P BI 41 85
MAKE_BASE=TRUE
39 BI FW_P0_TPB_N FW_PORT0_TPB_N BI 41 85
MAKE_BASE=TRUE

R42521 1
R4253
56.2 56.2
C 1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
C
2 402

85 FW_P0_TPB_L_N FW_P0_TPB_L_P
VOLTAGE=0V VOLTAGE=0V
NO_TEST=TRUE NO_TEST=TRUE

L4252 L4253
18NH-250MA 18NH-250MA
1 2 1 2
0402 0402

FW_P0_TPA_C

1
R4254
C4254 1 4.99K
1%
220PF 1/16W
10% MF-LF
50V
X7R-CERM 2 2 402
1394 PHY STRAPPING OPTIONS 402

91 89
61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6PP3V3_S0
47 41 40 39 38 37 34 31 30 27

B 79 77 76 74 73 72 71 67 62
B
NOSTUFF
1
R4255 1R4256
1K 1K
5% 5%
1/16W 1/16W
MF-LF MF-LF
2 402 2 402

39 OUT FW_PHY_DS0
MAKE_BASE=TRUE
39 OUT FW_PHY_DS1
MAKE_BASE=TRUE THERE ARE THREE FIREWIRE PORTS, BUT ONLY ONE IS USED.NO STUFF MEANS THAT
IT IS IN BILINGUL MODE PULL-UPS ASSERT/ENABLE DATA STROBE ONLY MODE.

1
R4258
1K
5%
1/16W
MF-LF
2 402

FW_PHY_PC0
A 39 OUT
MAKE_BASE=TRUE
THIS IS NOW ONE PORT ONLY AND HAVE POWER CODE "000" SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
1 PAGE TITLE
R4257
1K
5%
FW: 1394B MISC
1/16W DRAWING NUMBER SIZE
MF-LF
2 402 Apple Inc. 051-8768 D
REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
42 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 40 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
R4320 PLACEMENT_NOTE=PLACE CLOSE TO F4300
1
24.9K2 XW4300
POUR COPPER TO SINK HEAT 1 2 PPVP_FW_PHY_CPS 39
1%
1/16W
Q4301 SM
VOLTAGE=33V
MIN_LINE_WIDTH=0.5MM
MF-LF MMBT2907A CRITICAL MIN_NECK_WIDTH=0.2MM
402 60V-0.5A
SOT23 Q4300
12 VOLTS FW_SNSP 2 3 FDMC4435BZ
NO_TEST=TRUE MLP3.3X3.3
7 WATTS MAX PER PORT FAST NON-RESETABLE FUSE
THIS FUSE WILL NOT BLOW
CRITICAL IT IS HERE FOR SAFETY ONLY
R4300 3
CRITICAL CRITICAL CRITICAL POUR WIDE SHAPES FOR FW POWER

S
1

D
PP12V_G3H 1
0.27 2 P12V_S5_FW_R
2
D4300 F4300 L4300
FERR-250-OHM
78 72 65 60 51 6
5
2512 1%
MIN_LINE_WIDTH=1.7MM 1 B240XG 3AMP-32V
MIN_NECK_WIDTH=0.2MM FW_PORT0_VP_F FW_PORT0_VP
D
MF 1W VOLTAGE=12V P12V_S5_FW_CL 1 2 P33V_S5_FW_D 1 2 1 2 91
D

4 G
MIN_LINE_WIDTH=1.7MM MIN_LINE_WIDTH=1.7MM MIN_LINE_WIDTH=1.7MM SM MIN_LINE_WIDTH=1.7MM

1
MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
VOLTAGE=12V SMB VOLTAGE=33V 603 VOLTAGE=33V VOLTAGE=12V
XW4301
SM
XW4302
SM 2A, 40V
NOTE: PLACE SHORTS FW_FETGATE 1 C4300
2

2
XW4301, XW4302 AT 0.01UF
R4300 TO FORM KELVIN 2 20%
SENSE POINTS. FW_SNSN 2 50V
CERM
NO_TEST=TRUE 603
S
1 Q4305 D4305
R43211 R4323 BSS84 BAV99TXG
499 24.9K SOT-523-3
1% 1% 1 S0T23-3-HF
1/16W 1/16W G
MF-LF MF-LF 2 NC
402 2 2 402 D
3 3
TEMP. COMPENSATION VALUES NOSTUFF TURN OFF INTEGRATOR
R4300
0.15
R4321
7K
C4309 R4322
WHEN FET IS OFF. 1

1UF 49.9K2
0.20 5K 2 1 FW_OC_DR 1 R4310
PP2V2_FW_ESD "Snapback" & "Late VG" Protection
0.27 2.5K FW_P12V_FETPWR 0
0.33 0 1% 1 2

FW_EN_B
41
10% 1/16W CRITICAL
16V MF-LF 5%
X5R
402 402 R43251 CRITICAL DP4310 1/16W
MF-LF
130K
1%
DP4310 BAV99DW-X-G
SOT-363
402
1/16W BAV99DW-X-G
MF-LF
402 2 C4310 1 SOT-363
C4311 1
5 R4312
6 2 0
R4326 0.01UF 0.01UF 3 1 2
D Q4370 1
499K 2 10%
50V 2 6
10%
50V 2 5%
1/16W
PORT 0
2N7002DW-X-G X7R X7R 4
41 FW_CUTOFF 2 G S
SOT-363 FW_FETV 1%
1/16W
402
1
402 MF-LF
402 1394B
1 MF-LF 4
402 NOSTUFF
1
L4310 CRITICAL
Q4302 Q4302 C
C MMDT3906XG
SOT-363
2 5
MMDT3906XG
SOT-363
12-OHM-100MA
TCM1210-4SM
J4300
FWB-K40-K41-PLST-BLK
FW_EN_A SYM_VER-1
F-RT-TH
1 4
6 3 FW_PORT0_TPB_N TPB- TPB(R)
3 85 40 BI 85 FW_PORT0_TPBL_N 1
FW_V_PD 9
D
Q4370 R43241 85 40 BI FW_PORT0_TPB_P 2 3 85 FW_PORT0_TPBL_P 2 TPB+ VP
2N7002DW-X-G 100K NOSTUFF 8
SOT-363
41 FW_PORTPWR_DISABLE_L 5 G S 1%
1/16W
L4311
12-OHM-100MA 7
MF-LF TCM1210-4SM NC SC/NC
4 402 2 SYM_VER-1 6
85 40 BI FW_PORT0_TPA_N 1 4 85 FW_PORT0_TPAL_N 3 TPA- VG

100UA CONSTANT FW_PORT0_TPA_R 5

FW_IREF CURRENT 85 40 BI FW_PORT0_TPA_P 2 3
85 FW_PORT0_TPAL_P 4 TPA+ TPA(R)

3 6 10
PP2V2_FW_ESD
INTEGRATES VOLTAGE DROP ACROSS FET. Q4303 5 2 Q4303 41

CRITICAL R4311 NOSTUFF 11

APPROXIMATES FET TEMPERATURE RISE. MMDT3904-X-G MMDT3904-X-G CRITICAL
SOT-363-LF SOT-363-LF 0 12 CHASSIS

4 1 DP4311 DP4311 1 2
C4332 1 13
GND

41 FW_FET_TEMP BAV99DW-X-G BAV99DW-X-G 5% 0.001UF

FW_REF_A FW_REF_B SOT-363 SOT-363 1/16W 10%
MF-LF 50V
1 402 CERM 2
R4329 R43271 1
R4328 2 5
402
C4305 1 100K
1%
4.99K
1%
4.99K
1% 6 3 R4313 514-0735
2.2UF 1/16W 1/16W 1/16W C4312 1 C4313 1 0
10%
PLACEMENT NOTE: 16V 2
X5R
MF-LF
2 402
MF-LF
402 2
MF-LF
2 402
0.01UF
10%
1 0.01UF
10%
4
1
5%
2

603 50V 2 50V 2

KEEP THESE COMPONENTS CLUSTERED X7R
402
X7R
402
1/16W
MF-LF R43351 1 C4335
CLOSELY TOGETHER. 402 1M 0.1UF
5% 10%
PROTECT NODE FW_FET_TEMP FROM 1/16W
MF-LF 2 50V
X7R
LEAKAGE CURRENTS. 402 2 603-1
ESD Rail B
B
R4390
91 332
62 61 60 58 57 53 52 51 50
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 1 2 PP2V2_FW_ESD 41
49 47 40 39 38 37 34 31 30 27
89 79 77 76 74 73 72 71 67 VOLTAGE=2.4V
1% MIN_LINE_WIDTH=0.38 mm
1/16W MIN_NECK_WIDTH=0.2 MM
MF-LF
[ LATE VG NOTES ] 402

3
CURRENT THROUGH THE BIAS RESISTOR SHOULD BE 5MA FOR A VOLTAGE DROP TO 2.2V CRITICAL
IT IS 2.2V INSTEAD OF 2.7V BECAUSE THE SNAPBACK ESD DIODES HAVE A .5V DROP D4390
SOT23
MMBZ5227BLT1H

1
67 64 62 61 48 42 41 24 23 7 PP5V_S0
91 80 71 70 69 68

67 64 62 61 48 42 41 24 23 7 PP5V_S0
91 80 71 70 69 68

PP2V2_FW_ESD
www.teknisi-indonesia.com
41

R43401 1
1
R4350 1
R4351 1 C4350 1
R4354
301K R4341 10K 24.9K 0.1UF
1% 1% 1% CRITICAL 10% 200K
1/16W 4.99K 1/16W 1/16W 2 16V 1%
MF-LF 1% MF-LF MF-LF X7R-CERM 1/16W
402 2 CRITICAL 1/16W 2 402 2 402 U4300 402 MF-LF
MF-LF 8 2 402
8 U4300 2 402 FW_LATEVG_PP2V4_RC 2 LM393 D4350
SOT323
6 LM393 V+ SOI-HF
41 FW_FET_TEMP 1
V+ SOI-HF FW_LATEVG_L2 FW_PORTPWR_DISABLE_L
41
7 FW_CUTOFF 41 GND
FW_LATEVG_REF 3 3
A 5 GND
4 1 1 C4355 SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
4 NC PAGE TITLE
0.47UF
R4342 1
R4343 1 C4351 1R4352
100PF
BAT54SW-X-G
20%
10V
2 CERM
FIREWIRE CONNECTOR
15.0K 100K 2 5% 40.2K 603 DRAWING NUMBER SIZE
1% FW_FET_TREF 1 1%
1/16W
MF-LF 1%
2 50V
CERM 1/16W
MF-LF Apple Inc. 051-8768 D
402 2 1/16W 402
MF-LF 2 402 REVISION
402 R4353 R
9.0.0
1
1M 2 NOTICE OF PROPRIETARY PROPERTY: BRANCH
5% THE INFORMATION CONTAINED HEREIN IS THE
1/16W PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
MF-LF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
402 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
43 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 41 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

SATA CONNECTOR (HDD1) SATA CONNECTOR (HDD2)

D D
67 64 62 61 48 42 41 24 23 7 PP5V_S0
91 80 71 70 69 68

67 64 62 61 48 42 41 24 23 7 PP5V_S0
91 80 71 70 69 68

CRITICAL
CRITICAL
J4401 J4410
54722-0164
54722-0164 F-ST-SM-J40
F-ST-SM-J40
2 1
2 1 NC
NC 4 3
4 3
91 83 42 SATA_HDD2_D2R_CONN_P 6 5
SATA_HDD1_D2R_CONN_P 6 5
91 83 42

SATA_HDD1_D2R_CONN_N 8 7 1 C4431 91 83 42 SATA_HDD2_D2R_CONN_N 8 7 1 C4441

91 83 42
10 9 0.1UF
10 9 0.1UF 10%
10% 91 83 42 SATA_HDD2_R2D_CONN_N 12 11 2 16V
91 83 42 SATA_HDD1_R2D_CONN_N 12 11 2 16V
X7R-CERM 14 13
X7R-CERM
402
14 13 402 91 83 42 SATA_HDD2_R2D_CONN_P
91 83 42 SATA_HDD1_R2D_CONN_P 16 15
16 15

516S0616
516S0616

C C
NOSTUFF NOSTUFF
NOSTUFF NOSTUFF
R4450 C4400 R4460 C4420
0.01UF 0.01UF
0 1 2 0 1 2
1 2 83 SATA_HDD1_R2D_DF_P 1 2 83 SATA_HDD2_R2D_DF_P
5% 5%
1/20W 10% 1/20W 10%
MF C4450 16V
X5R-CERM MF C4460 16V
X5R-CERM
201 0.01UF 0201 201 0.01UF 0201
83 17 SATA_HDD1_R2D_C_P 1 2 SATA_HDD1_R2D_CONN_P 42 83 91 83 17 SATA_HDD2_R2D_C_P 1 2 SATA_HDD2_R2D_CONN_P 42 83 91
IN IN
10% 10%
16V 16V
X5R-CERM X5R-CERM
0201 0201

C4451 C4461
0.01UF 0.01UF
83 17 SATA_HDD1_R2D_C_N 1 2 SATA_HDD1_R2D_CONN_N 42 83 91 83 17 SATA_HDD2_R2D_C_N 1 2 SATA_HDD2_R2D_CONN_N 42 83 91
IN IN
10% NOSTUFF 10% NOSTUFF
NOSTUFF 16V NOSTUFF 16V
R4451 X5R-CERM
0201
C4401 R4461 X5R-CERM
0201
C4421
0 0.01UF 0 0.01UF
1 2 83 SATA_HDD1_R2D_DF_N 1 2 1 2 83 SATA_HDD2_R2D_DF_N 1 2
5% 10%
5%
10%
1/20W 1/20W
MF 16V MF 16V
201 X5R-CERM 201 X5R-CERM
0201 0201
NOSTUFF NOSTUFF
NOSTUFF NOSTUFF
R4452 C4402 R4462 C4422
0.01UF 0.01UF
0 0
B 1
5%
2 83 SATA_HDD1_D2R_DF_P 1

10%
2 1
5%
2 83 SATA_HDD2_D2R_DF_P 1

10%
2
B
1/20W C4452 16V 1/20W C4462 16V
MF MF
201 0.01UF X5R-CERM 201 0.01UF X5R-CERM
0201 0201
83 17 SATA_HDD1_D2R_P 1 2 SATA_HDD1_D2R_CONN_P 42 83 91 83 17 SATA_HDD2_D2R_P 1 2 SATA_HDD2_D2R_CONN_P 42 83 91
OUT OUT
10% 10%
16V 16V
X5R-CERM X5R-CERM
0201 0201

C4453 C4463
0.01UF 0.01UF
83 17 SATA_HDD1_D2R_N 1 2 SATA_HDD1_D2R_CONN_N 42 83 91 83 17 SATA_HDD2_D2R_N 1 2 SATA_HDD2_D2R_CONN_N 42 83 91
OUT OUT
10% NOSTUFF 10% NOSTUFF
NOSTUFF 16V NOSTUFF 16V
R4453 X5R-CERM
0201
C4403 R4463 X5R-CERM
0201
C4423
0.01UF 0.01UF
1
0 2 83 SATA_HDD1_D2R_DF_N 1 2 1
0 2 83 SATA_HDD2_D2R_DF_N 1 2
5% 10% 5% 10%
1/20W 1/20W
MF 16V MF 16V
201 X5R-CERM 201 X5R-CERM
0201 0201

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

HDD SATA CONNECTORS

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
44 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 42 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

PLACEMENT_NOTE=Place C4606 and C4604 close to U4601 CRITICAL

U4601 CRITICAL
TPS2561DR
SON L4600
91 78 66 65 61 45 44 43 28 6 PP5V_S4 2 IN_0
3 IN_1
OUT1 9
OUT2 8 PP5V_USB2_PORT3
USB/SMC DEBUG MUX FERR-220-OHM-2.5A
1 2 PP5V_USB2_PORT3_F
VOLTAGE=5V 0603 VOLTAGE=5V
10 FAULT1* ILIM 7 MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM
25 OUT USB_EXTC_OC_L U4601_ILIM MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
25 USB_EXTB_OC_L 6 FAULT2*
OUT PP3V3_G3H
91 65 61 48 47 46 45 27 6

D 4 EN1
1
R4601
D
5 EN2
THRM 23.2K
1 C4650 1
R4650
GND PAD 1% 0.1UF 10K
1/16W 10%
2 16V
5% C4605 1

11
MF-LF X7R-CERM 1/16W 0.01UF
CRITICAL 2 402 1 C4612 1 C4603 402 MF-LF 10% CRITICAL
2 402 50V 2
1 C4604 1
C4606 0.1UF 0.1UF X7R
10% 10% CRITICAL 402
0.1UF 150UF 2 16V 2 16V J4600

9
10% 20% X7R-CERM X7R-CERM USB-K40-41
16V
2 X7R-CERM 2 6.3V
POLY-TANT
402 402
VCC L4602
120-OHM F-RT-TH

PORT B
402 CASE-B2-SM 2012-HF 5
48 47 46 SMC_RX_L 5 M+ Y+ 1 SYM_VER-1
BI
SMC_TX_L 4 M- Y- 2 USB_B_MUXED_N 1 4 USB_PORT3_N
48 47 46 BI U4650 83 83
VDD 1 VBUS
PI3USB102ZLE D- 2 D-
83 25 USB_EXTB_P 7 D+ TQFN
BI USB_B_MUXED_P 2 3 USB_PORT3_P 3 D+
6 D-
83 83 D+
83 25 BI USB_EXTB_N 4 GND
CRITICAL CRITICAL GND
8 OE* SEL 10 USB_DEBUGPRT_EN_L 46
D4603
IN 6
SEL=0: CHOOSE SMC 1
GND
SEL=1: CHOOSE USB
3

3
514-0709
NOSTUFF 2
R4651
1
0 2 RCLAMP0502B
SC-75
NOSTUFF 5%
1/16W
R4652 MF-LF
62 IN USB_PWR_EN 0 402
1 2
5%
1/16W
MF-LF
CRITICAL
L4610
C 402
FERR-220-OHM-2.5A C
PP5V_USB2_PORT2 1 2 PP5V_USB2_PORT2_F
VOLTAGE=5V 0603 VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM

CRITICAL
C4615 1 CRITICAL
0.01UF
10%
U4600 CRITICAL
CRITICAL 50V 2
X7R J4610
TPS2561DR 402 USB-K40-41
SON L4620 L4612
120-OHM F-RT-TH

PORT C
65 61 45 44 43 28 6 PP5V_S4 2 IN_0 OUT1 9
FERR-220-OHM-2.5A 2012-HF 5
91 78 66 SYM_VER-1
3 IN_1 OUT2 8 PP5V_USB2_PORT1 1 2 PP5V_USB2_PORT1_F
VOLTAGE=5V VOLTAGE=5V 83 25 USB_EXTC_N 1 4 83 USB_PORT2_N
MIN_LINE_WIDTH=0.6MM 0603 MIN_LINE_WIDTH=0.6MM BI
VDD 1 VBUS
25 USB_EXTA_OC_L 10 FAULT1* ILIM 7 U4600_ILIM MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
OUT 2 D-
6 FAULT2* D-
25 OUT USB_EXTD_OC_L 2 3 3 D+
83 25 BI USB_EXTC_P 83 USB_PORT2_P D+
4 EN1 CRITICAL GND 4 GND
1
5 EN2
THRM
R4600 D4600
GND PAD 23.2K
1%
1 C4632 1 C4623 C4625 1 6
1/16W 0.1UF 0.1UF CRITICAL 1
10% 10% 0.01UF
1

11

MF-LF
2 402 2 16V
X7R-CERM 2 16V
X7R-CERM
10%
50V 2 3
402 402 X7R
402
J4620 514-0709
USB-K40-41 2

PORT D
CRITICAL CRITICAL F-RT-TH
1 C4601 1
C4600 L4622 5
0.1UF 150UF 120-OHM RCLAMP0502B
10% 20% 2012-HF SC-75
16V
2 X7R-CERM 2 6.3V SYM_VER-1
VDD 1 VBUS
POLY-TANT
402 CASE-B2-SM 83 25 USB_EXTD_N 1 4 83 USB_PORT1_N D- 2 D-
BI
D+ 3 D+

B 83 25 BI USB_EXTD_P 2 3 83 USB_PORT1_P CRITICAL

D4601
GND 4 GND
B
6
PLACEMENT_NOTE=Place C4600 and C4601 close to U4600 1

3 514-0709
2

RCLAMP0502B
SC-75

CRITICAL
L4630
FERR-220-OHM-2.5A
PP5V_USB2_PORT0 1 2 PP5V_USB2_PORT0_F
VOLTAGE=5V 0603 VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM

C4635 1 CRITICAL
0.01UF
10%
50V 2
CRITICAL X7R
402
J4630
USB-K40-41
L4632 F-RT-TH

PORT A
120-OHM 5
2012-HF
SYM_VER-1

83 25 USB_EXTA_N 1 4 83 USB_PORT0_N VDD 1 VBUS

BI
D- 2 D-
D+ 3 D+
USB_EXTA_P 2 3 USB_PORT0_P
A 83 25 BI 83

CRITICAL
GND 4 GND
SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/30/2010 A
D4602 6
PAGE TITLE

1 USB EXTERNAL CONNECTORS

DRAWING NUMBER SIZE
3 514-0709
Apple Inc. 051-8768 D
2 REVISION
R
9.0.0
RCLAMP0502B NOTICE OF PROPRIETARY PROPERTY: BRANCH
SC-75 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
46 OF 512
RIGHT MOST LOOKING AT BACK OF SYSTEM III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 43 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

IR Controller
D D

NOSTUFF
R4700
1
0 2
5%
1/16W
MF-LF
402

D4700
SOD-323
PP5V_S4 1 2 PP5V_S4_IR_R MIN_LINE_WIDTH=0.5MM PLACE R4799 AND R4798 VERY CLOSE TO TP4701 AND TP4702
91 78 66 65 61 45 43 28 6 44 MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V Reduce stubs as much as possible
B0520WSXG
R4799
DIODE NEEDED FOR IN-CIRCUIT 0
PROGRAMMING VIA HEADER. 1 2 USB_IR_P BI 25 83

5%
1/16W
MF-LF
402
R4798
0
1 2 USB_IR_N BI 25 83

5%
1/16W
C NOSTUFF 1 C4792 1 C4791 1 C4790
MF-LF
402 C
R4790 0.001UF
10%
0.1UF
10% 10%
1UF
100
47 46 OUT G3_POWERON_L 1 2 G3_POWERON_R_L 2 50V
CERM 2 16V
X7R-CERM 2 10V
X5R
5% 402 402 402-1
TP4700
1/16W
MF-LF
DRIVE AS OPEN COLLECTOR IF USED. 44 PP5V_S4_IR_R 1
A +5V
402 TH-TP30

16
TP4701
1 D+
A
VDD TH-TP30
TP_IRUC_RCVR_PWR_EN_L 7 P0_0 P1_0/D+ 14 83 USB_IR_R_P
6 P0_1 P1_1/D- 15 83 USB_IR_R_N TP4702
1 D-
A
91 NC_IRUC_P02 5 P0_2/INT0 P1_2/VREG 18 IRUC_VREG TH-TP30
91 NC_IRUC_P03 4 P0_3/INT1 P1_3/SSEL 20 NC_IRUC_P13 91 TP4709
1 GND
R4794 91 NC_IRUC_P04 3 P0_4/INT2 P1_4/SCLK 23 NC_IRUC_P14 91
A
100 TH-TP30
91 45 IN IRRCVR_OUT 1 2 IRRCVR_OUT_RC 2 P0_5/TIO0 P1_5/SMOSI 24 NC_IRUC_P15 91

Signal from 5% 91 NC_IRUC_P06 1 P0_6/TIO1 P1_6/MISO 25 NC_IRUC_P16 91

1/16W
IR Receiver MF-LF 32 P0_7 OMIT_TABLE P1_7 26
402 NC NC
U4700 C4793 1
9 P2_0 CY7C63833 P3_0 21 1UF
NC QFN NC 10%
10V 2
8 P2_1 P3_1 22
NC CRITICAL NC X5R
402-1
10 27
NC NC
11 28
NC Cypress NC
12 29
C4794 1 NC NC ’Encore II’ NC NC
17 30
0.001UF NC USB Controller NC
10% 19 31
50V NC NC
CERM 2
402 VSS THRM_PAD
B B

13

33
Place C4794 near U4700

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

IR CONTROLLER
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
47 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 44 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

IR/LED BOARD CONNECTOR

91 65 61 47 6 PP5V_G3H

1 C4801
D
0.1UF
10%
16V
2 X7R-CERM 1 R4805
D
402 R4801 1
R4802 0
100 91 78 66 65 61 44 43 28 6 PP5V_S4 1 2 PPIRRCVR_G3H_LED
1% 100 VOLTAGE=3.3V
1/16W 1% 5% MIN_LINE_WIDTH=0.5MM
MF-LF 1/16W 1/16W
MF-LF
MIN_NECK_WIDTH=0.2MM CRITICAL MIN_NECK_WIDTH=0.2MM
2 402 MF-LF 1 L4810 MIN_LINE_WIDTH=0.5MM
2 402 402 R4808 FERR-220-OHM
VOLTAGE=3.3V
SMC_SYS_LED_IREF_M SMC_SYS_LED_IREF_S 100K
1%
J4800
Q4801 1 4 Q4801 1/16W 1 2 PPIRRCVR_F 78171-0005
91
M-RT-SM
MF-LF 0402 6
MMDT3906XG MMDT3906XG 2 402 NC
SOT-363 2 5 SOT-363

91 44 IRRCVR_OUT 1
OUT
2
6 3
3
4 N
SMC_SYS_LED_IREF 91 SMC_SYS_LED_DR 5 P

1 C4809 1 NC
7
R4800 SETS CONSTANT CURRENT THROUGH THE LED R4800 100PF
- SHOULD HAVE APPROX 4.2V ACROSS IT 1%
2.49K 5%
50V C4800 1 CRITICAL
C4803 1
1/16W CERM 2 0.1UF 100PF
MF-LF 402 10%
16V L4811 5%
50V
2 402 X7R-CERM 2 FERR-220-OHM CERM 2
402 402
SMC_SYS_LED_L
1 2 GND_IR_F
VOLTAGE=0V
518S0588
0402 MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
C4806 1
100PF
5% NOTE: LED TYPE IS 378S0207
50V
CERM 2 - LED Vfwd(min) @ 1.0mA is approximately 2.5V
402 - LED Vfwd(max) @ 5.0ma is approximately 3.1V
C Q4800 C
SSM3K15FV D 3
SOD-VESM-HF

R4803 1 G S 2
SMC_SYS_LED 1
0 2 SMC_SYS_LED_R
46 6 IN
5%
1/16W
MF-LF
402

SIL LED DRIVE CIRCUIT

Power Button Header

B 91 65 61 48 47 46 43 27 6 PP3V3_G3H
B
1
R4820
10K
5%
1/16W
MF-LF
2 402

L4800
1000-OHM-EMI SMC_ONOFF_L 46
OUT
POWER_BTN_P 1 2
J4801 SM
78171-0002
M-RT-SM
3
NC
1 C4802
0.1UF
10%
1 2 16V
X7R-CERM
2 402
R4823
100
4
POWER_BTN_N 1 2
NC 5%
1/16W
MF-LF
NOSTUFF 402
518S0519
Molex 2-pin flat header R4822
1
0 2
5%
1/8W
SILK_PART=PWR BTN
MF-LF JUMP WITH SCREWDRIVER
805
A NOSTUFF
FOR POWER ON
SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE
R4821
0
ONE FOR EACH SIDE OF BOARD.
PLACE IN ACCESSIBLE PART OF BOARD.
IR/LED, PWR BTTN
1 2 DRAWING NUMBER SIZE
5%
1/8W
SILK_PART=PWR BTN
Apple Inc. 051-8768 D
MF-LF REVISION
805 R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
48 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 45 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
91 47 PP3V3_S5_AVREF_SMC
91 65 61 48 47 45 43 27 6 PP3V3_G3H

C4902 1 1 C4903 1 C4904 1 C4905 1 C4906

22UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 10% 10% 10% 10%
6.3V 2 2 16V 16V
2 X7R-CERM 2 16V 16V
2 X7R-CERM
CERM X7R-CERM X7R-CERM
805 402 402 402 402

D R4999 PLACE_NEAR=U4900.M12:3mm
PLACE_NEAR=U4900.M12:3mm
SMC_VCL PLACE_NEAR=U4900.E1:3mm
D
1
4.7 2 PP3V3_S5_SMC_AVCC
5%
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 MM
C4907 1

M12

H10

L11
1/16W VOLTAGE=3.3V 0.47UF

B1
M1

E1
MF-LF
402
C4920 1 10%
6.3V
0.1UF CERM-X5R 2
10% VCL AVREF 402
B12
U4900 L13
16V
X7R-CERM 2
AVCC VCC
91 NC_SMC_P10
A13
P10 DF2117RVPLP20HV P60
K12
SMC_PM_G2_EN OUT 47 62 91
402 U4900 R49091 1
R4901
91 NC_SMC_RSTGATE_L P11 TLP-145V P61 NC NC E5 NC 10K 10K
ALL_SYS_PWRGD A12 K11 DF2117RVPLP20HV 5% 5%
62 27 IN P12 (1 OF 3) P62 NC TLP-145V 1/20W 1/20W
B13 J12 MF MF
62 IN S5_PWRGD P13 OMIT_TABLE P63 NC (3 OF 3) 201 2 2 201
D11 P14 P64 K13 SMC_ADAPTER_EN
NC OUT 18 47
OMIT_TABLE MD1 D1 SMC_MD1 48
PM_RSMRST_L C13 P15 P65 J10 IN
18 OUT NC MD2 H1 SMC_KBC_MDE
27 SMC_DELAYED_PWRGD C12 P16 P66 J11 SMC_PROCHOT_3_3_L 47 48 47 SMC_RESET_L D3 RES*
OUT IN IN
24 18 PM_PWRBTN_L D10 P17 P67 H12 SMC_BIL_BUTTON_L 47
OUT IN SMC_XTAL A3
47 XTAL
91 NC_SMC_P20 D13 P20 AN0 P70 N10 SMC_CPU_VSENSE 50 47 SMC_EXTAL A2 EXTAL NMI E3 SMC_NMI 48
IN IN
E11 P21 AN1 P71 M11 SMC_CPU_ISENSE
NC IN 50
D12 P22 AN2 P72 L10 PSU_TEMP
NC IN 72 91
F11 P23 AN3 P73 N11 PD_SMC_SPARE_SENSE 47
NC ETRST* H3 SMC_TRST_L IN 48
91 NC_SMC_P24 E13 P24 AN4 P74 N12 SMC_GFX_VSENSE 50
IN
E12 P25 AN5 P75 M13 SMC_GFX_ISENSE AVSS L9
NC IN 50
1 1
91 NC_SMC_BMON_MUX_SEL F13 P26 AN6 P76 N13 SMC_P1V5S3_ISENSE IN 50
VSS R4902 R4998
E10 L12 SMC_CPUVCCIO_ISENSE IN 10K 10K
NC P27 AN7 P77 50 5% 5%

D2
L3
F10
B11
C5
1/20W 1/20W
LPC_AD<0> A9 P30 P80 A7 SMC_SCI_L XW4900
SM
MF MF
84 48 17 BI OUT 20
2 201 2 201
LPC_AD<1> D9 P31 P81 B6 2 1
84 48 17 BI NC
84 48 17 LPC_AD<2> C8 P32 P82 C7 PM_CLKRUN_L 18 48
BI OUT
LPC_AD<3> B7 D5 LPC_PWRDWN_L
C 84 48 17

84 48 17
BI
IN LPC_FRAME_L A8
P33
P34
P83
P84 A6 SMC_TX_L
IN
OUT
18 48

43 46 47 48
PLACE_NEAR=U4900.L3:4mm
C
27 SMC_LRESET_L D8 P35 P85 B5 SMC_RX_L 43 46 47 48
IN IN GND_SMC_AVSS
D7 C6 47 50 51
84 27 IN LPC_CLK33M_SMC P36 P86 (OC) SMBUS_SMC_MGMT_SCL BI 49 87

48 17 LPC_SERIRQ D6 P37
BI
P90 J4 SMC_ONOFF_L 45
IN
D4 P40 P91 G3 SMC_BC_ACOK
NC IN 47

91 NC_SMC_P41 A5 P41 P92 H2 SMC_PME_S4_WAKE_L 47

IN
87 49 SMBUS_SMC_MGMT_SDA (OC) B4 P42 P93 G1 PM_SLP_S3_L 18 28 51 62 91
BI IN
91 NC_SMC_P43 A1 P43 P94 H4 PM_SLP_S4_L 18 28 62 91
IN
C2 P44 P95 G4 PM_SLP_S5_L
NC IN 18 62 91
B2 P45 P96 F4 SMC_CLK32K
NC IN 47

73 =SMC_GFX_THROTTLE_L C1 P46 P97 F1 (OC) SMBUS_SMC_0_S0_SDA 49 87

OUT BI
91 NC_SMC_SYS_KBDLED C3 P47

48 47 46 43 SMC_TX_L G2 P50
OUT
48 47 46 43 SMC_RX_L F3 P51
IN
87 49 SMBUS_SMC_0_S0_SCL (OC) E4 P52
BI

N3
U4900 K1
47 SMC_PA0_PU (OC) PA0 DF2117RVPLP20HV PE0 SMC_CASE_OPEN IN 47

91 NC_SPI_DESCRIPTOR_OVERRIDE_L
(OC) N1 PA1 TLP-145V PE1 J3 SMC_TCK 47 48
IN
27 18 PM_SYSRST_L (OC) M3 PA2 (2 OF 3) PE2 K2 SMC_TDI 47 48
OUT IN
USB_DEBUGPRT_EN_L (OC) M2 PA3 PE3 J1 SMC_TDO
43 OUT OMIT_TABLE OUT 47 48

31 30 MEM_EVENT_L (OC) N2 PA4 PE4 K4 SMC_TMS 47 48

BI IN
L1 K5
B 47

47
BI
BI
WIFI_EVENT_L
SYS_ONEWIRE
(OC)
(OC) K3
PA5
PA6
PF0
N5
G3_POWERON_L IN 44 47
B
L2 PF1 SMC_SYS_LED OUT 6 45
18 OUT PM_BATLOW_L (OC) PA7 M6
PF2 SMC_LID IN 47
B8 PB0 PF3 L5 ENET_ASF_GPIO
NC IN 37

SMC_RUNTIME_SCI_L C9 PB1 PF4 M5

20 OUT NC
47 SMC_ODD_DETECT B9 PB2 PF5 N4 NC_SMC_PF5 91
IN
SMC_S4_WAKESRC_EN A10 PB3 PF6 L4
47 OUT NC
SMC_PB4 C10 PB4 PF7 M4
47
NC
B10 PB5
NC PG0 M8
77 47 IN SMC_DP_HPD_L C11 PB6 NC
PG1 N7 SMS_INT_L 47 NOTE: SMS Interrupt can be active high or low, rename net accordingly.
73 SMC_GFX_OVERTEMP A11 PB7 IN
IN
PG2 K8 (OC) =SMBUS_SMC_2_SDA 49 If SMS interrupt is not used, pull up to SMC rail.
BI
60 SMC_FAN_0_CTL G11 PC0 PG3 K7 (OC) =SMBUS_SMC_2_SCL 49
OUT BI
91 NC_SMC_FAN_1_CTL G13 PC1 PG4 K6 (OC) SMBUS_SMC_A_S3_SDA 49 87
BI
91 NC_SMC_FAN_2_CTL F12 PC2 PG5 N6 (OC) SMBUS_SMC_A_S3_SCL 49 87
BI
91 NC_SMC_FAN_3_CTL H13 PC3 PG6 M7 (OC) SMBUS_SMC_B_S0_SDA 49 87
BI
60 SMC_FAN_0_TACH G10 PC4 PG7 L6 (OC) SMBUS_SMC_B_S0_SCL 49 87
IN BI
91 NC_SMC_FAN_1_TACH G12 PC5
H11 PH0 E2 SMC_PROCHOT OUT 47
91 NC_SMC_FAN_2_TACH PC6
J13 PH1 F2 SMC_THRMTRIP OUT 47
91 NC_SMC_FAN_3_TACH PC7 R4910
PH2 J2 NC
M10 43.2 2
50 IN SMC_CPUP1V5_ISENSE PD0 AN8 PECI/PH3 A4 81 CPU_PECI_R 1 CPU_PECI 11 20 81

51 SMC_DCIN_VSENSE N9 PD1 AN9 PEVREF/PH4 B3 PVCCIO_S0_SMC_R 1%

IN 1/16W
51 SMC_DCIN_ISENSE K10 PD2 AN10 PEVSTP/PH5 C4 PM_PECI_PWRGD_R MF-LF
IN 402
50 SMC_VCCSA_VSENSE L8 PD3 AN11
IN
50 IN SMC_VCCSA_ISENSE M9 PD4 AN12 R4911
0
SMC_CPUDDR_HI_ISENSE N8 C4910 1 1 2 PP1V05_S0
A 51

73
IN
IN SMC_GPU_HI_ISENSE K9
PD5
PD6
AN13
AN14 0.1UF
10% 5%
1/16W
7 24 50 62 70 76

SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
SMC_PCH1V05_ISENSE L7 PD7 AN15 16V MF-LF PAGE TITLE
50 IN X7R-CERM 2 402
402 SMC
R4912 DRAWING NUMBER SIZE
0
1 2 PM_PECI_PWRGD 62
Apple Inc. 051-8768 D
5% REVISION
1/16W R
MF-LF
402
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
49 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 46 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
SMC Reset "Button", Supervisor & AVREF Supply SMC FSB to 3.3V Level Shifting
65 61 48 47 46 45 43 27 6 PP3V3_G3H 67 62 61 60 58 57 53 52 51 50
24 23 21 20 19 18 17 13 7 6 PP3V3_S0
91 49 41 40 39 38 37 34 31 30 27
91 65 61 45 6 PP5V_G3H 91 89 79 77 76 74 73 72 71

Desktops: 5V
1 1
Mobiles: 3.42V
1
R5061 R5060
R5000 100K 10K

3
C5020 1 3.3K 5%
1/16W
5%
1/16W
0.47UF V+ VIN
5% MF-LF MF-LF
10%
6.3V
CERM-X5R 2
U5010 1/16W
MF-LF 2 402 2 402 TO SMC
402 VREF-3.3V-VDET-3.0V 2 402 SMC_PROCHOT_3_3_L OUT 46
DFN

D NC
NC
6 MR1* (IPU)
SN0903048
7 MR2* (IPU)
RESET* 5 SMC_RESET_L OUT 46 48

6
D
PP3V3_S5_AVREF_SMC 46 91
MIN_LINE_WIDTH=0.4 mm
SMC_MANUAL_RST_L 4 DELAY CRITICAL REFOUT 8 MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V
D Q5060
OMIT GND
THRM
PAD DMB53D0UV
1 SOT-563
R5001 C5001 1 CPU_PROCHOT_BUF 2 G

9
0
5% 0.01UF C5025 1 1 C5026
1/10W 10% 10uF 0.01UF
50V 2 20% 10%
MF-LF
2 603
X7R
402
6.3V 2
X5R
50V
2 X7R
TO CPU R5062 3

SILK_PART=SMC_RST 603 402 81 67 11 BI CPU_PROCHOT_L 1

3.3K 2 CPU_PROCHOT_L_R 5 Q5060 S
DMB53D0UV
5% SOT-563 1
PLACEMENT_NOTE=Place R5001 on BOTTOM side GND_SMC_AVSS 46 50 51 1/16W
MIN_LINE_WIDTH=0.4 mm MF-LF 4
MIN_NECK_WIDTH=0.1 mm 402
MR1* and MR2* must both be low to cause manual reset. VOLTAGE=0V 6 D
Used on mobiles to support SMC reset via keyboard.
Q5059
SSM6N37FEAPE
SOT563
NOTE: Internal pull-ups are to VIN, not V+.

1 S G 2
SMC_PROCHOT IN 46

20 OUT PM_THRMTRIP_L_R

3 D Q5059
SSM6N37FEAPE
SOT563
teknisi-indonesia
C 4 S G 5
SMC_THRMTRIP 46
C
IN

91 65 61 48 47 46 45 43 27 6 PP3V3_G3H
R5012
PLACE_NEAR=U1800.N14:5.1mm 22
18 IN PM_CLK32K_SUSCLK_R 1 2 SMC_CLK32K OUT 46

5%
1/16W
46 44 G3_POWERON_L R5072 10K 1 2
5% 1/20W MF 201
MF-LF
402
46 SMC_LID R5071 100K 1 2
R5073 10K 5% 1/20W MF 201
48 46 43 SMC_TX_L 1 2
5% 1/20W MF 201
48 46 43 SMC_RX_L R5074 100K 1 2
R5075 10K 5% 1/20W MF 201
PP3V3_S4 6 19 20 25 28 33 34 35 38 47 49 46 SYS_ONEWIRE 1 2
50 61 77 78 91
48 46 SMC_TMS R5077 10K 1 2 5% 1/20W MF 201
1 R5078 10K 5% 1/20W MF 201
R5020 48 46 SMC_TDO 1 2
R5079 10K 5% 1/20W MF 201
100K SMC_TDI 1 2
SMC Crystal Circuit 5%
1/20W
48 46

48 46 SMC_TCK R5080 10K 1 2

5% 1/20W MF 201
MF R5081 10K 5% 1/20W MF 201
C5010 2 201 46 SMC_BIL_BUTTON_L 1 2
R5010 15pF 46 SMC_BC_ACOK R5087 470K 1 2 5% 1/20W MF 201
0 SMC_DP_HPD_L OUT
NOSTUFFR5093 10K
1 2 46 77 5% 1/20W MF 201
46 SMC_XTAL 1 2 SMC_XTAL_R 46 SMS_INT_L 1 2
5% 1/20W MF 201
5% 5%
1/16W
MF-LF
CRITICAL 50V SMC_ODD_DETECT R5092 10K 1 2
402 Y5010 1 CERM
402
46

SMC_PA0_PU R5091 100K 1 2 5% 1/20W MF 201

20.00MHZ 46

B 5X3.2-SM
2 C5011
5% 1/20W MF 201
B
15pF
46 SMC_EXTAL 1 2

5% 91 62 46 SMC_PM_G2_EN R5084 100K 1 2

50V
CERM 46 18 SMC_ADAPTER_EN R5085 10K 1 2 5% 1/20W MF 201
402 R5086 10K 5% 1/20W MF 201
46 SMC_CASE_OPEN 1 2
5% 1/20W MF 201

PP3V3_S4 46 SMC_PB4 R5088 10K 1 2

6 19 20 25 28 33 34 35 38 47 49
R5090 100K 5% 1/20W MF 201
50 61 77 78 91 46 SMC_S4_WAKESRC_EN 1 2
5% 1/20W MF 201
1
R5076 46 PD_SMC_SPARE_SENSE R5095 10K 1 2
5% 1/20W MF 201
100K
5%
1/20W
MF
2 201
91 35 PP3V3_WLAN
47 46 IN SMC_PME_S4_WAKE_L SMC_PME_S4_WAKE_L OUT 46 47
MAKE_BASE=TRUE
46 WIFI_EVENT_L R5089 10K 1 2
5% 1/20W MF 201

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

SMC Support
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
50 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 47 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D MATT CARD D

LPC+SPI Connector
CRITICAL
LPCPLUS
J5100
55909-0374
M-ST-SM
91 65 61 47 46 45 43 27 6 PP3V3_G3H 31 32
68 67 64 62 61 42 41 24 23 7 PP5V_S0
91 80 71 70 69
1 2 LPC_CLK33M_LPCPLUS 27 84
IN
84 46 17 LPC_AD<0> 3 4 LPC_AD<2> 17 46 84
BI BI
84 46 17 LPC_AD<1> 5 6 LPC_AD<3> 17 46 84
BI BI
7 8
48 SPI_ALT_MOSI 9 10 SPIROM_USE_MLB 20 59 91
IN OUT
48 SPI_ALT_MISO 11 12 SPI_ALT_CLK 48
OUT IN
84 46 17 LPC_FRAME_L 13 14 SPI_ALT_CS_L 48
IN IN
46 18 PM_CLKRUN_L 15 16 LPC_SERIRQ 17 46
OUT BI
47 46 SMC_TMS 17 18 LPC_PWRDWN_L 18 46
OUT IN
84 27 LPCPLUS_RESET_L 19 20 SMC_TDI 46 47
IN OUT
47 46 SMC_TDO 21 22 SMC_TCK 46 47
OUT OUT
46 SMC_TRST_L 23 24 SMC_RESET_L 46 47
IN OUT
46 SMC_MD1 25 26 SMC_NMI 46
OUT OUT
C 47 46 43 IN SMC_TX_L 27
29
28
30
SMC_RX_L
LPCPLUS_GPIO
OUT 43 46 47

20
C
OUT

33 34

516S0573

SPI Bus Series Termination

NO_TEST=TRUE SPI_ALT_MISO 48

NO_TEST=TRUE SPI_ALT_MOSI 48

NO_TEST=TRUE SPI_ALT_CLK 48

B LPCPLUS LPCPLUS LPCPLUS

NO_TEST=TRUE
LPCPLUS
SPI_ALT_CS_L 48
B
1 1 1 1
R5128 R5127 R5126 R5125 PLACE_NEAR=J5100.14:5mm
0 47 47 47 PLACE_NEAR=J5100.12:5mm
5% 5% 5% 5% PLACE_NEAR=J5100.9:5mm
1/16W 1/16W 1/16W 1/16W PLACE_NEAR=J5100.11:5mm
MF-LF MF-LF MF-LF MF-LF
2 402 2 402 2 402 2 402

PLACE_NEAR=U1400.E11:5MM R5110 R5120

15 47
84 17 IN SPI_CS0_R_L 1 2 91 84 SPI_CS0_L 1 2 SPI_MLB_CS_L OUT 59

5% 5% PLACE_NEAR=R5125.2:5mm
1/16W 1/16W
PLACE_NEAR=U1400.D7:5MM MF-LF R5111 R5121 MF-LF
402 402
15 47
84 17 IN SPI_CLK_R 1 2 91 84 SPI_CLK 1 2 SPI_MLB_CLK OUT 59

5% 5% PLACE_NEAR=R5126.2:5mm
1/16W 1/16W
PLACE_NEAR=U1400.B8:5MM R5112 MF-LF R5122 MF-LF
402 402
15 47
84 17 IN SPI_MOSI_R 1 2 91 84 SPI_MOSI 1 2 SPI_MLB_MOSI OUT 59

5% 5% PLACE_NEAR=R5127.2:5mm
1/16W 1/16W
MF-LF R5123 MF-LF
402 402
15
91 84 17 OUT SPI_MISO 1 2 SPI_MLB_MISO IN 59

5% PLACE_NEAR=U6400.2:5MM
1/16W
MF-LF
402

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

LPC+ Debug Connector

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
51 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 48 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
PCH SMBus "0" Connections
91
62 61 60 58 57 53 52 51 50 49
PP3V3_S0 SMC "0" SMBus Connections SMC "2" SMBUS CONNECTIONS
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27
89 79 77 76 74 73 72 71 67
91 89
61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0
R52001 1
R5201 47 41 40 39 38 37 34 31 30 27
79 77 76 74 73 72 71 67 62
1K 1K
5% 5%
1/16W 1/16W
Cougar-Point MF-LF
402 2
MF-LF
2 402 SMC R52501 1
R5251 ENET ASF (MINI-LOM)
PULL-UPS ON ENET PAGE
SMC
BALANCED STAR TOPOLOGY 4.7K 4.7K T29 Temp TO 3.3V ENET RAIL.
U1800 R5202 U4900
5%
1/16W
5%
1/16W EMC1414-A:U5535 U3900 H8S_2117RP:U4900
(MASTER) 33 5% MF-LF MF-LF
1/16W 402 2
MF-LF 402 SMB_PCH_STR_SCL 84
(MASTER)
2 402 (WRITE: 0X78 READ: 0X79) (MASTER) (WRITE: 0X?? READ: 0X??)

84 17 SMBUS_PCH_CLK 1 2
MAKE_BASE=TRUE 87 46 SMBUS_SMC_0_S0_SCL =I2C_T29THMSNS_SCL 52 87 37 ENET_ASF_SMB_CLK =SMBUS_SMC_2_SCL 46

D 84 17 SMBUS_PCH_DATA
MAKE_BASE=TRUE 1 2
SMB_PCH_STR_SDA 84

87 46
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA =I2C_T29THMSNS_SDA 52 87 37
MAKE_BASE=TRUE
ENET_ASF_SMB_DATA =SMBUS_SMC_2_SDA 46
D
MF-LF 402
1/16W R5206 MAKE_BASE=TRUE MAKE_BASE=TRUE
33 5% 33 5%
1/16W
R5203 MF-LF 402
1 2 SMB_PCH_DIMM_SCL 84
MAKE_BASE=TRUE
VREFMRGN SMB_PCH_DIMM_SDA 84
R5204 1 2
MF-LF 402
MAKE_BASE=TRUE
33 5% 1/16W
1/16W
MF-LF 402 33 5% SO-DIMM "A"
84 SMB_PCH_VRF_SCL 1 2
R5207
MAKE_BASE=TRUE J2900

84 SMB_PCH_VRF_SDA (Write: 0xA0 Read: 0xA1)

MAKE_BASE=TRUE 1 2
MF-LF 402
1/16W
33 5% =I2C_SODIMMA_SCL 30
VRef DACs
R5205 =I2C_SODIMMA_SDA 30
U3300 VREFMRGN
(Write: 0x98 Read: 0x99)

33 =I2C_VREFDACS_SCL SMC "Management" SMBus Connections

SO-DIMM "B"
33 =I2C_VREFDACS_SDA J3100
47 38 35 34 33 28 25 20 19 6 PP3V3_S4
(Write: 0xA4 Read: 0xA5) 91 78 77 61 50 49

=I2C_SODIMMB_SCL 31

Margin Control SMC R52901 1

R5291
=I2C_SODIMMB_SDA 31 4.7K 4.7K
5% 5%
U3301
R5208 U4900 1/16W
MF-LF
1/16W
MF-LF
(Write: 0x30 Read: 0x31) 33 5%
1/16W
(MASTER) 402 2 2 402
MF-LF 402
33 =I2C_PCA9557D_SCL 1 2 SMB_PCH_MKY_SCL 84 87 46 SMBUS_SMC_MGMT_SCL
C 33 =I2C_PCA9557D_SDA XDP
MAKE_BASE=TRUE
SMB_PCH_MKY_SDA 84
SMC "A" SMBus Connections
87 46
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SDA C
R5212 1 2
MF-LF 402
MAKE_BASE=TRUE MAKE_BASE=TRUE
33 5%
1/16W
1/16W NOTE: SMC RMT bus remains powered and may be active in S3 state

MF-LF 402 33 5%
84 SMB_PCH_XDP_SCL 1 2
R5209 47 38 35 34 33 28 25 20 19 6 PP3V3_S4
MAKE_BASE=TRUE 91 78 77 61 50 49

SMB_PCH_XDP_SDA Mikey
84
MAKE_BASE=TRUE 1 2
MF-LF 402 U6800
1/16W
33 5% (Write: 0x72 Read: 0x73) SMC R52701 1
R5271 RMT TEMP
1K 1K
R5213 =I2C_MIKEY_SCL 58 U4900
5%
1/16W
5%
1/16W LM952141:U5500
XDP Connectors XDP MF-LF MF-LF
(MASTER) 402 2 2 402 (WRITE: 0X30 READ: 0X31)
=I2C_MIKEY_SDA 58
J2500
87 46 SMBUS_SMC_A_S3_SCL =SMBUS_REMOTE_THMSNS_SCL
(MASTER) MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SDA =SMBUS_REMOTE_THMSNS_SDA
24 =SMBUS_XDP_SCL
SDRVI2C:SB SDRVI2C:SB
87 46
MAKE_BASE=TRUE T29 SMBus Connections
=SMBUS_XDP_SDA 1 1
24 R5237 R5236 91 89
33 33 DP SDRV "A" 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0
5% 5% 47 41 40 39 38 37 34 31 30 27
79 77 76 74 73 72 71 67 62
1/16W 1/16W
MF-LF MF-LF U9310
402 2 2 402 (Write: 0x94 Read: 0x95)
T29 IC R52301 1
R5231 T29 Port A MCU
49 I2C_DPSDRVA_SCL =I2C_DPSDRVA_SCL 49 77 4.7K 4.7K
5% 5%
U9000 1/16W 1/16W J9330
49 I2C_DPSDRVA_SDA =I2C_DPSDRVA_SDA 49 77 MF-LF MF-LF
(MASTER) 402 2 2 402 (Write: 0x26 Read: 0x27)

86 74 I2C_T29_SCL =I2C_T29AMCU_SCL 77
MAKE_BASE=TRUE
86 74 I2C_T29_SDA =I2C_T29AMCU_SDA 77
MAKE_BASE=TRUE

B PCH "SMLink 0" Connections

SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
B
91 89
SDRVI2C:MCU SDRVI2C:MCU
61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27
PP3V3_S0 R52341 1
R5235
79 77 76 74 73 72 71 67 62 0 0 DP SDRV "A"
5% 5%
1/16W 1/16W
1 1 MF-LF MF-LF U9310
Cougar-Point R5210 R5211 402 2 2 402 (Write: 0x94 Read: 0x95)
8.2K 8.2K
5% 5%
U1800 1/16W 1/16W 49 I2C_DPSDRVA_SCL =I2C_DPSDRVA_SCL 49 77
MF-LF MF-LF MAKE_BASE=TRUE
(MASTER) 402 2 2 402 49 I2C_DPSDRVA_SDA =I2C_DPSDRVA_SDA 49 77
MAKE_BASE=TRUE
17 SML_PCH_0_CLK
MAKE_BASE=TRUE SMC "B" SMBus Connections
17 SML_PCH_0_DATA 91
MAKE_BASE=TRUE 62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0
47 41 40 39 38 37 34 31 30 27
89 79 77 76 74 73 72 71 67

R52601 1
R5261
4.7K 4.7K
5% 5%
1/16W 1/16W
SMC MF-LF MF-LF
402 2 2 402
PCH "SMLink 1" Connections
U4900
R5262 R5264
(MASTER) 33 5% 33 5%
91 89 1/16W 1/16W
61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 MF-LF 402 MF-LF 402
47 41 40 39 38 37 34 31 30 27
79 77 76 74 73 72 71 67 62
87 46 SMBUS_SMC_B_S0_SCL 1 2 1 2 SMB_SMC_B_TSN_SCL 87
MAKE_BASE=TRUE MAKE_BASE=TRUE
NO STUFF NO STUFF 87 46 SMBUS_SMC_B_S0_SDA SMB_SMC_B_TSN_SDA 87
MAKE_BASE=TRUE 1 2 1 2 MAKE_BASE=TRUE
Cougar-Point R52201 1
R5221 MF-LF 402
1/16W
MF-LF 402
1/16W
8.2K 8.2K R5223 33 5% 33 5%
5% 5% SYSTEM TEMP SENSORS
0 R5263 R5265
A U1800

(Write: 0x90 Read: 0x91)

1/16W
MF-LF
402 2
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
EMC1428: U5500 SYNC_MASTER=J40S SYNC_DATE=11/23/2010 A
402 (WRITE: 0X92 READ: 0X93)
PAGE TITLE
84 17 SML_PCH_1_CLK 1 2 87 SMB_SMC_B_STR_SCL
MAKE_BASE=TRUE MAKE_BASE=TRUE
=I2C_CPUTHMSNS_SCL SMBus Connections
52
84 17 SML_PCH_1_DATA 1 2 87 SMB_SMC_B_STR_SDA DRAWING NUMBER SIZE
MAKE_BASE=TRUE MAKE_BASE=TRUE
R5222 =I2C_CPUTHMSNS_SDA 52
Apple Inc. 051-8768 D
0 REVISION
5% R
1/16W
MF-LF
9.0.0
SMLink 1 is slave port to 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
access PCH & CPU via PECI. PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
52 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 49 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
NOSTUFF
R5304
47 38 35 34 33 28 25 20 19 6 PP3V3_S4 1
0 2 CPU VDDQ CURRENT SENSE FILTER CPU VCORE IMON CURRENT SENSE / FILTER
91 78 77 61 50 49
5%
R5302 1/16W
MF-LF 91
91 0 402 62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 1 2 PP3V3_U5300 47 41 40 39 38 37 34 31 30 27
89 79 77 76 74 73 72 71 67
PLACE_NEAR=U5340.5:3MM
47 41 40 39 38 37 34 31 30 27 VOLTAGE=3.3V
89 79 77 76 74 73 72 71 67
CRITICAL
5%
1/16W
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.1 MM
1 C5340
MF-LF 0.1UF
R5300 402 1 C5300 CRITICAL 10%
2 16V
0.001 0.1UF X7R-CERM
1% 10% U5340 402

3
1W
MF 2 16V
X7R-CERM 67 IN VR_CPU_IMON 8 OPA2333 PLACE_NEAR=U4900.M11:5MM
1206 V+ 402 3 DFN R5341
PP1V5_VDDQ_CPU_R
CPUIMVP_ISUM_IOUT14.53K2
1 2 V+
61 7 IN
U5300 R5301 1 SMC_CPU_ISENSE
D
D 3 4
SIGNAL_MODEL=EMPTY
ISNS_VDDQ_N 5 IN-
INA210
SC70 OUT 6 VDDQ_IOUT 1
4.53K2 SMC_CPUP1V5_ISENSE OUT 46
2 V- 1%
1/16W PLACE_NEAR=U4900.M11:5MM
OUT 46

MF-LF
CRITICAL 1% R5343 THRM
4 402 1 C5341
1/16W 10K 9 0.22UF
ISNS_VDDQ_P 4 IN+ REF 1 MF-LF
402
1 C5301 1 2 CPUIMVP_ISUM_RN 10%
0.22UF 1% 2 6.3V
10% 1/16W CERM-X5R
62 32 31 28 16 13 11 7 OUT PP1V5_VDDQ_CPU GND 2 6.3V
CERM-X5R MF-LF
R5345 402
402 402
GND_SMC_AVSS

2
1
10K 2
46 47 50 51

GND_SMC_AVSS 46 47 50 51
NOSTUFF 1% SIGNAL_MODEL=EMPTY
Place RC close to SMC C5345 1/16W
MF-LF
GAIN:2X
470PF 402
91 1 2 SCALE: ??.??A / V
62 61 60 58 57 53 52 51 50 49
PP3V3_S0 MAX VOUT: 3.3V AT ??.??A
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27
89 79 77 76 74 73 72 71 67
PCH 1.05V CURRENT SENSE FILTER 10% SIGNAL_MODEL=EMPTY
CRITICAL 50V
CERM
R5305 1 C5305 402
CPU Vcore Voltage Sense / Filter
0.001 0.1UF
1% 10%

3
1W 2 16V
MF
1206 V+
X7R-CERM
402 XW5320
SM R5320
PP1V05_S0 1 2 4.53K2
76 70 62 46 24 7 IN
3 4 U5305 R5306 91 68 67 15 13 10 7 PPVCORE_S0_CPU 1 2 CPUVSENSE_IN 1 SMC_CPU_VSENSE OUT 46

SIGNAL_MODEL=EMPTY INA210 4.53K2 PLACE_NEAR=R7510.2:5 MM 1% PLACE_NEAR=U4900.N10:5MM

ISNS_P1V05PCH_N5 IN- SC70 OUT 6 PCH1V05_IOUT 1 SMC_PCH1V05_ISENSE 46 1/16W
CRITICAL 1%
OUT MF-LF
402
1 C5320
1/16W 0.22UF
ISNS_P1V05PCH_P4 IN+ REF 1 MF-LF
402
1 C5306 PLACE_NEAR=U4900.N10:5MM
10%
6.3V
2 CERM-X5R
0.22UF
10% 402
23 21 18 17 7 OUT PP1V05_S0_PCH GND 2 6.3V
CERM-X5R
402 GND_SMC_AVSS 46 47 50 51

2
GND_SMC_AVSS 46 47 50 51

Place RC close to SMC

C C

47 38 35 34 33 28 25 20 19 6 PP3V3_S4
91 78 77 61 50 49
CPU/DDR 1.5V CURRENT SENSE / FILTER GFX/IG VCORE IMON CURRENT SENSE / FILTER
1 C5375
3

V+
0.1UF
10% PLACE_NEAR=U4900.L12:5MM
2 16V
PLACE_NEAR=R7640.4:5MM U5375 X7R-CERM
402 R5376 CRITICAL
INA210 4.53K2 CKPLUS_WAIVE
66 IN P1V5S3_CS_N 5 IN- SC70 OUT 6 P1V5S3_IOUT 1 SMC_P1V5S3_ISENSE OUT 46
U5340
CRITICAL 1%
1/16W
PLACE_NEAR=U4900.L12:5MM 8 OPA2333 PLACE_NEAR=U4900.M13:5MM
66 IN P1V5S3_CS_P 4 IN+ (200V/V) REF 1 Gain: 200x MF-LF 1 C5376 67 IN VR_AXG_IMON 5 DFN R5351
402
0.22UF V+ 7 4.53K2
10%
CPUIMVP_ISUMG_IOUT 1 SMC_GFX_ISENSE OUT 46
GND Scale: 5A / V 6.3V 6 1%
2 CERM-X5R V- PLACE_NEAR=U4900.M13:5MM
Max VOut: 3.3V at 16.5A 1/16W
402 1 C5351
2

MF-LF
SENSE R IS 1MOHM ON VR PAGE R5353 THRM
4 402
0.22UF
GND_SMC_AVSS 46 47 50 51 10K 9
10%
EDP: 17.5A TDP :13.1A 1 2 CPUIMVP_ISUMG_RN
2 6.3V
CKPLUS_WAIVE

1%
CKPLUS_WAIVE CERM-X5R
1/16W 402
91 MF-LF R5355
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27
PP3V3_S0 402
1
10K 2
GND_SMC_AVSS 46 47 50 51
89 79 77 76 74 73 72 71 67
CPU 1.05V VCCIO Current Sense / Filter NOSTUFF 1% SIGNAL_MODEL=EMPTY
1 C5360 C5355 1/16W GAIN:2X
3

MF-LF
V+
0.1UF 470PF 402
10% PLACE_NEAR=U4900.L12:5MM SCALE: ?.??A / V
2 16V 1 2
PLACE_NEAR=R7640.4:5MM U5360 X7R-CERM
402 R5361 MAX VOUT: 3.3V AT ??.??A
B 89 70 IN CPUVCCIOS0_CS_N 5 IN-
INA210
SC70 OUT 6 CPUVCCIO_IOUT 1
4.53K2
SMC_CPUVCCIO_ISENSE OUT 46
10% SIGNAL_MODEL=EMPTY
50V
CERM
B
CRITICAL 1% PLACE_NEAR=U4900.L12:5MM 402
1/16W
89 70 IN CPUVCCIOS0_CS_P 4 IN+ (200V/V) REF 1 Gain: 200x MF-LF
402
1 C5361
0.22UF
GND Scale: 5A / V 10%
2 6.3V
GFX/IG Vcore Voltage Sense / Filter
Max VOut: 3.3V at 16.5A CERM-X5R
402
2

SENSE R IS 1MOHM ON VR PAGE GND_SMC_AVSS 46 47 50 51

XW5330
SM R5330
EDP: 17.5A TDP :13.1A 4.53K2
69 67 16 13 7 PPVAXG_S0_CPU 1 2 GFXVSENSE_IN 1 SMC_GFX_VSENSE OUT 46

PLACE_NEAR=R7550.2:5 MM 1% PLACE_NEAR=U4900.N12:5MM
1/16W
91
62 61 60 58 57 53 52 51 50 49
PP3V3_S0
MF-LF
402
1 C5330
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27 CPU SA CURRENT SENSE / FILTER 0.22UF
89 79 77 76 74 73 72 71 67 10%
PLACE_NEAR=U4900.N12:5MM 2 6.3V
1 C5365 CERM-X5R
3

402
V+
0.1UF
10% PLACE_NEAR=U4900.L12:5MM GND_SMC_AVSS 46 47 50 51
16V
2 X7R-CERM
PLACE_NEAR=R7640.4:5MM U5365 402 R5366
INA210 4.53K2
89 64 IN VCCSAS0_CS_N 5 IN- SC70 OUT 6 VCCSA_IOUT 1 SMC_VCCSA_ISENSE OUT 46

CRITICAL 1%
1/16W
PLACE_NEAR=U4900.L12:5MM
89 64 IN VCCSAS0_CS_P 4 IN+ (200V/V) REF 1 Gain: 200x MF-LF
402
1 C5366
0.22UF
Scale: 5A / V 10%
GND 2 6.3V
CERM-X5R
Max VOut: 3.3V at 16.5A 402
2

Sense R is R7640, 1mOhm GND_SMC_AVSS 46 47 50 51

EDP: 17.5A TDP :13.1A

A CPU SA VOLTAGE SENSE / FILTER SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A

PAGE TITLE

XW5322
SM R5322 Voltage & Load Side Current Sensing
4.53K2 DRAWING NUMBER SIZE
PPVCCSA_S0_CPU 1 2 VCCSAVSENSE_IN 1 SMC_VCCSA_VSENSE
64 16 13 7

PLACE_NEAR=R7510.2:5 MM 1% PLACE_NEAR=U4900.N10:5MM
OUT 46

Apple Inc. 051-8768 D

1/16W REVISION
MF-LF
402
1 C5322 R
9.0.0
0.22UF
10% NOTICE OF PROPRIETARY PROPERTY: BRANCH
PLACE_NEAR=U4900.N10:5MM 2 6.3V
CERM-X5R
402 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
GND_SMC_AVSS 46 47 50 51
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
53 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 50 OF 104

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

J40I, J40S, AND J40

DC-In Voltage Sense Enable & Filter

PSU CURRENT SENSE TURN ON DIVIDER ONLY IN S0.

91
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0
47 41 40 39 38 37 34 31 30 27

D CRITICAL
89 79 77 76 74 73 72 71 67

Max VOut: 3.3V at 19.77V Input

D
R5493 1 C5418 Q5415
0.002 0.1UF DMG1016V
1% CRITICAL 10% DCIN_S5_VSENSE

3
1/4W
MF V+
2 16V
X7R-CERM DCIN current Sense Filter SOT-563
P-CHN 3
1206 402
91 72 6 IN PP12V_G3H_PSU 1
3
2
4 U5403 R5433 D R54131
INA214 27.4K
SIGNAL_MODEL=EMPTY 4.53K2 1%
ISNS_P12VG3H_N 5 IN- SC70 OUT 6 DCIN_IOUT 1 SMC_DCIN_ISENSE OUT 46
G 1/16W PLACE_NEAR=U4900.N9:5MM
5 MF-LF
1% S 402 2 RTHEVENIN = 4573 Ohms
1/16W
ISNS_P12VG3H_P 4 IN+ REF 1
GAIN: 100X
MF-LF
402
1 C5437 SMC_DCIN_VSENSE
0.22UF OUT 46
10% 4 PLACE_NEAR=U4900.N9:5MM
78 72 65 60 51 41 6 PP12V_G3H GND SCALE: 5A / V 6.3V
2 CERM-X5R 78 72 65 60 51 41 6 PP12V_G3H PLACE_NEAR=U4900.N9:5MM
OUT
402 R54141 1 C5414

2
MAX VOUT: 3.3V AT 16.5A
5.49K 0.22UF
GND_SMC_AVSS 46 47 50 51 1% 10%
1/16W
Place RC close to SMC R5411 1 MF-LF 2 6.3V
CERM-X5R
402 2 402
100K
1%
1/16W GND_SMC_AVSS 46 47 50 51
MF-LF
402 2

PDCINVSENS_EN_L_DIV

Q5415 R5412
DMG1016V 100K 2
DCINVSENS_EN_L 1
SOT-563
CPU / DDR HIGH SIDE CURRENT SENSE / FILTER N-CHN 6 1%
1/16W
MF-LF
91 D 402
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27
PP3V3_S0
C CRITICAL
89 79 77 76 74 73 72 71 67

C5401 91 62 46 28 18 IN PM_SLP_S3_L 2 G C
R5400 1
0.1UF ENABLES DC-IN VSENSE
S
0.005 10%
1% 16V DIVIDER IN S0.
3
1W
MF 2 X7R-CERM
402
1
0612 V+
78 72 65 60 51 41 6 PP12V_G3H 1 2 PLACE_NEAR=U4900.N8:5MM
IN
3 4 U5400 R5403
INA213 4.53K2
ISNS_HS_CPUDDR_N 5 IN- SC70 OUT 6 HS_CPUDDR_IOUT 1 SMC_CPUDDR_HI_ISENSE OUT 46
PLACE_NEAR=U4900.N8:5MM
CRITICAL 1%
ISNS_HS_CPUDDR_P 4 IN+ REF 1 Gain: 50x
1/16W
MF-LF 1 C5403
402 0.22UF
10%
Scale: 4A / V 6.3V
70 69 68 66 64 6 OUT PP12V_G3H_CPUDDR GND 2 CERM-X5R
402
Max VOut: 3.3V at 13.2A
2

GND_SMC_AVSS 46 47 50 51

Place RC close to SMC

B B

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

High Side Current Sensing

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
54 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 51 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

91
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27
PP3V3_S0
89 79 77 76 74 73 72 71 67

1
C5500 1 R5500 1R5501 1R5502 CPU_THERMD_P IN 10 52 89

6.81K 10K 20K

16
CRITICAL 1UF 1% 5% 5%
10%
10V 2 1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1 C5510
VDD X5R 0.0022uF
2 402 2 402 2 402
D U5500
EMC1428-7
402-1 10%
50V
2 CERM
402
SIGNAL_MODEL=EMPTY
D
QFN Place C5570 near U5500
89 52 10 IN
CPU_THERMD_P 1 DP1 ALERT* 7 SNS_T1_ALERT_L CPU_THERMD_N IN 10 52 89
CPU BODY CPU_THERMD_N 2
89 52 10 IN DN1
SYS_SHND* 6 SNS_T1_ADDR
52 CPU_PROX_THRM_P 3 DP2/DN3
CPU_PROX_THRM_N 4 SMDATA 11 =I2C_CPUTHMSNS_SDA BI 49 52 CPU_PROX_THRM_P
52 DN2/DP3
SMCLK 12 =I2C_CPUTHMSNS_SCL 3
52 WIFI_PROX_THRM_P 10 DP4/DN5 IN 49
1 C5520
52
WIFI_PROX_THRM_N 9 DN4/DP5 TRIP/SET 5 SNS_T1_TRIPSET 0.0022uF 1 Q5520
10% SIGNAL_MODEL=EMPTY
Set trip point to 125 C. 50V
2 CERM BC846BMXXH
DIMM_PROX_THRM_P 15 DP6/DN7 NC 13 SOT732-3
52
NC 402 2
52
DIMM_PROX_THRM_N 14 DN6/DP7 Place C5570 near U5500
52 CPU_PROX_THRM_N
22 GND THRM_PAD PLACE Q5520 UNDER BODY OF CPU.

17
SM
XW5504 SM XW5505
52 WIFI_PROX_THRM_P
11
3
22
1 C5570
0.0022uF 1 Q5570
10% SIGNAL_MODEL=EMPTY
SM 2 50V BC846BMXXH
XW5500 SM XW5501 EMC1428-7: 6.8K PULL UP: I2C ADDRESS: WRITE: 0x92, READ: 0x93 CERM SOT732-3
402 2
11 Place C5570 near U5500
52 WIFI_PROX_THRM_N
52 PCH_THRMD_N
PLACE Q5570 NEAR AIRPORT CARD
52 PCH_THRMD_P connector on edge of MLB

52 DIMM_PROX_THRM_P
C AMBIENT_THRMD_N
1 C5580
3 C
52
0.0022uF 1 Q5580
52 AMBIENT_THRMD_P 10% SIGNAL_MODEL=EMPTY
2 50V
CERM
BC846BMXXH
402 SOT732-3
2
PLACE C5580 NEAR U5500
52 DIMM_PROX_THRM_N
PLACE Q5580 UNDER SODIMMS.
connector on edge of MLB

ONLY ONE CAP PER BACK-TO-BACK DIODE PAIR NEEDED.

52 PCH_THRMD_P
3

1 Q5560
BC846BMXXH
SOT732-3
2

T29 PROXIMITY THERMAL SENSORS 52 PCH_THRMD_N

PLACE Q5560 NEAR PCH (U1800)

91
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 52 AMBIENT_THRMD_P
47 41 40 39 38 37 34 31 30 27
89 79 77 76 74 73 72 71 67
3
C5535 1 1
R5536 1
R5537 1 Q5590
1UF 33.2K 10K
10%
10V 2 1% 5% BC846BMXXH
B 1
VDD
X5R
402-1
1/16W
MF-LF
2 402
1/16W
MF-LF
2 402
2
SOT732-3
B
U5535 52 AMBIENT_THRMD_N
PLACE Q5590 PER PD
EMC1414-A
MSOP
2 DP1 THERM*/ADDR 7 SNS_T2_ADDR
NC CRITICAL
3 DN1 ALERT* 8 SNS_T2_ALERT_L
NC
4 DP2/DN3 SMDATA 9 =I2C_T29THMSNS_SDA 49
BI
5 DN2/DP3 SMCLK 10 =I2C_T29THMSNS_SCL 49
IN
GND
6
3

Q5540 1 SMT_THRM_SNS3_P
SIGNAL_MODEL=EMPTY
BC846BMXXH
SOT732-3
2 C5540 1
PLACE NEXT TO OR UNDER U9000. 0.0022uF
10%
50V
CERM 2
402
SMT_THRM_SNS3_N
Place C5540 near U5535

EMC1414-A-AIZL: 33K PULL UP: I2C ADDRESS: WRITE: 0x78, READ: 0x79
A SYNC_MASTER=J40S SYNC_DATE=11/23/2010 A
PAGE TITLE

THERMAL SENSORS
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
55 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 52 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
AUDIO CODEC
APPLE P/N 353S3199
91 72 71 39 23 21 17 7 PP1V5_S0

PP3V3_S0 IN
50 51 52 53 57 58 60 61 62 67
6 7 13 17 18 19 20 21 23 24 27
30 31 34 37 38 39 40 41 47 49
CRITICAL 71 72 73 74 76 77 79 89 91

1 C5600 PP4V5_AUDIO_ANALOG IN 53 91
4.7UF CRITICAL CRITICAL
20%
2 6.3V
X5R C5603 1 1
C5604 C5605 1 1 C5606 1 C5608
0306
CRITICAL 0.1UF 10UF 0.1UF 1UF 10UF
D C5602 1
10%
16V
X7R-CERM 2
402
20%
2 16V
TANT-POLY
10%
16V
X7R-CERM 2
402
10%
2 10V
X5R
402-1
20%
10V
2 X5R D
10UF 2012-LLP 0508
20%
16V
TANT-POLY 2

24

46

25
2012-LLP

9
91 53 IN PP4V5_AUDIO_ANALOG
1 VD VA_REF VA_HP VA GND_AUDIO_CODEC 53 54 57 58
R5600 VBIAS_DAC 29 VBIAS_DAC
2.67K
1%
1/16W NC_CS4206_FP 44 VHP_FILT+
HPOUT_L 38 NC_AUD_HP_PORT_L NC 91

MF-LF
91

41 U5600 HPOUT_R 40 NC_AUD_HP_PORT_R NC 91 XW5610

2 402 VHP_FILT- SM
CS4206B HPREF 39 AUD_HPREF 1 2 GND_AUDIO_CODEC 53 54 57 58
QFN
MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM
91 NC NC_AUD_GPIO_0 2 GPIO0/DMIC_SDA1 LINEOUT_L1+ 35
MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM
AUD_LO2_P_L OUT 55

EXT HP AMP CNTRL 55 OUT AUD_GPIO_1 12 GPIO1/DMIC_SDA2

/SPDIF_OUT2
LINEOUT_L1- 34
MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM
AUD_LO2_N_L OUT 55

91 NC_AUD_GPIO_2
NC AUD_GPIO_3
14 GPIO2 LINEOUT_R1+ 36
MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM
AUD_LO2_P_R OUT 55 EXTERNAL HP AMP
SPKR AMP CNTRL 56 OUT 15 GPIO3 LINEOUT_R1- 37 AUD_LO2_N_R OUT 55

58 IN AUD_SENSE_A 13 SENSE_A LINEOUT_L2+ 31 AUD_LO3_P_L OUT 56

LINEOUT_L2- 30 AUD_LO3_N_L 56
SPEAKER AMP
OUT
PP4V5_AUDIO_ANALOG LINEOUT_R2+ 32 NC_AUD_LO3_P_R 91
91 53 45 FLYP
LINEOUT_R2- 33 NC_AUD_LO3_N_R NC 91
43 FLYC NC
42 FLYN CRITICAL
MICBIAS 16 NC_CS4206_MICBIAS 91
NC
3 VL_HD
VCOM 28 CS4206_VCOM
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
NC
1 VL_IF

C 84 17 IN HDA_BIT_CLK 6 BITCLK
LINEIN_L+
LINEIN_C-
21
22 MAKE_BASE=TRUE
AUD_LI_P_L
AUD_LI_N_LR
IN 54

54
C
IN
84 17 IN HDA_SYNC LINEIN_R+ 23 AUD_LI_P_R IN 54

R5601 10 SYNC
22
84 17 OUT HDA_SDIN0 1 2 84 AUD_SDI_R 8 SDI MICIN_L+ 18 AUD_MIC_INP_L IN 58

5% 5 SDO MICIN_L- 17 AUD_MIC_INN_L 58

EXTERNAL MIC INPUT
1/16W IN
MF-LF MICIN_R+ 19 NC_AUD_MIC_INP_R 91

84 17 HDA_SDOUT
402 11 RESET*
MICIN_R- 20 NC_AUD_MIC_INN_R NC 91
IN
84 17 HDA_RST_L NC
IN
57 IN AUD_SPDIF_IN 47 SPDIF_IN
VREF+_ADC 27 CS4206_VREF_ADC
CS4206_SPDIF_OUT 48 SPDIF_OUT MIN_LINE_WIDTH=0.20MM NC
R5602 MIN_NECK_WIDTH=0.15MM
22
57 OUT AUD_SPDIF_OUT 1 2
1 DMIC_SCL 4 TP_AUD_DMIC_CLK
5% R5603 NC
1/16W
MF-LF
100K
1%
402 1/16W DGND THRM_PAD AGND
MF-LF
402 2

49

26
DIFF FSINPUT= 2.45VRMS CRITICAL
CRITICAL
SE FSINPUT= 1.22VRMS
DAC1 FSOUTPUT= 1.34VRMS C5613 1 1
C5614
1UF 10UF
DAC2/3 FSOUTPUTDIFF= 2.67VRMS 10%
20V
20%
16V
DAC2/3 FSOUTPUTSE= 1.34VRMS TANT 2 2 POLY-TANT

teknisi-indonesia
CASE-P3-HF CASE-B2-SM

58 57 54 53 GND_AUDIO_CODEC
B B

CRITICAL
L5651 AUDIO 4.5V REGULATOR
FERR-120-OHM-1.5A APPLE P/N 353S2234
1 2 PP5V_AUDIO_HPAMP 55
0402
VOLTAGE=5V
MIN_LINE_WIDTH=0.60MM
CRITICAL MIN_NECK_WIDTH=0.20MM
L5650 U5601
FERR-120-OHM-1.5A MAX8840-4.5V
PP5V_S0_AUDIO 1 2 AUD_4V5_REG_IN 1 IN UDFN PP4V5_AUDIO_ANALOG
7 OUT 6 53 91
VOLTAGE=5V VOLTAGE=4.5V
R5650 0402 MIN_LINE_WIDTH=0.60MM CRITICAL MIN_LINE_WIDTH=0.2MM
91 89 1.02K2
MIN_NECK_WIDTH=0.20MM
BP 4 C5653 MIN_NECK_WIDTH=0.15MM
61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 1 AUD_REG_SHDN_L 3 SHDN* 0.01UF
47 41 40 39 38 37 34 31 30 27
79 77 76 74 73 72 71 67 62 1% NC 5 MAX8840_BP 1 2
1/20W GND NC MIN_LINE_WIDTH=0.40MM
MF MIN_NECK_WIDTH=0.20MM10% C5654 1
2

201 C5651 1 1 C5652 50V 1UF

1 C5650 1UF 0.001UF X7R 10%
10V 2
10% 10% 402
0.1UF 10V 2 2 50V X5R
A 10%
2 16V
X7R-CERM
X5R
402-1
CERM
402
402-1
SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
402 XW5600 PAGE TITLE
SM
1 2 GND_AUDIO_CODEC 53 54 57 58
AUDIO:CODEC
VOLTAGE=0V DRAWING NUMBER SIZE
MIN_LINE_WIDTH=0.50MM
XW5601
SM
MIN_NECK_WIDTH=0.20MM
NO_TEST=TRUE Apple Inc. 051-8768 D
REVISION
1 2 GND_AUDIO_HPAMP 55 R
VOLTAGE=0V
MIN_LINE_WIDTH=0.60MM
9.0.0
MIN_NECK_WIDTH=0.20MM NOTICE OF PROPRIETARY PROPERTY: BRANCH
NO_TEST=TRUE
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
56 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 53 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

CODEC Nom SE RIN = 20K OHMS

FC = 5 HZ Max
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
D NET RIN = 18K OHMS D
CRITICAL
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM OMIT_TABLE
R5700 C5700
3.3UF
AUD_LI_INL 1
7.87K2 AUD_LI_LF 2 1 AUD_LI_P_L
57 IN OUT 53
MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM 1% MIN_NECK_WIDTH=0.2MM
1/16W 20%
MF-LF 10V
402 POLY-TANT
CASE-M

R57011
21.5K
1%
1/16W
MF-LF
402 2
CRITICAL
OMIT_TABLE
C5702
3.3UF
57 AUD_LI_GND 2 1 AUD_LI_N_LR 53
IN OUT
MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM 1 NOSTUFF MIN_NECK_WIDTH=0.2MM
R5703 1 C5713 20%
10V
10 0.01UF POLY-TANT
1% 10% CASE-M
1/20W 10V
MF 2 X5R
2 201 201
58 57 53 IN GND_AUDIO_CODEC
R57051
21.5K
1%
1/16W
C MF-LF
402 2
MIN_NECK_WIDTH=.2MM
CRITICAL
OMIT_TABLE
C
MIN_LINE_WIDTH=.3MM
R5706 C5703
7.87K2 AUD_LI_RF 3.3UF
57 AUD_LI_INR 1 2 1 AUD_LI_P_R 53
IN OUT
MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM 1% MIN_NECK_WIDTH=0.2MM
1/16W 20%
MF-LF 10V
402 POLY-TANT
CASE-M

TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_ITEM

128S0309 3 CAP,TANT,POLY,4.7UF,20%,10V,SMD C5700,C5702,C5703 CRITICAL ?

B B

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

AUDIO:LINE-IN
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
57 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 54 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

HEADPHONE AMPLIFIER (MAX97220A)

APN:353S3081
VOLTAGE GAIN:-2DB.TO GET 2VRMS FROM 2.67VRMS

D D

PLACE C5801 NEAR U5800 PIN 9 AND 13

53 PP5V_AUDIO_HPAMP

1 C5800 1 C5801
10UF 2.2UF
20% 20%
2 10V
X5R 2 10V
X5R-CERM
0508 402

R5803
7.87K2
1 AUD_HPAMP_OUTL 55 57

1%
1/16W
MF-LF
402
CRITICAL

C AUD_LO2_N_L
C5812
22UF R5801
10K
C
53 IN
1 2 HPAMP_B4GAIN_INL_N 1 2
1%
CRITICAL 20% 1/16W
MF-LF
6.3V
C5813 CASE-P
TANT
R5802
402

AUD_LO2_P_L 22UF
10K

13
HPAMP_B4GAIN_INL_P

9
53
1 2 1 2
IN AUD_HPAMP_OUTL OUT 55 57
1%

PVDD
MIN_LINE_WIDTH=0.40MM

SVDD
SVDD2
20% 1/16W MIN_NECK_WIDTH=0.20MM
1
6.3V
TANT
MF-LF
402 R5804
CASE-P 7.87K AUD_HPAMP_INL_N
1% 14 INL- 12
1/16W OUTL
MF-LF
2 402
AUD_HPAMP_INL_P 15 INL+
GND_AUDIO_HPAMP U5800 BIAS 11 HPAMP_BIAS
55 53
AUD_HPAMP_INR_P MAX97220AETE
7 INR+
1 TQFN OUTR 10
R5807 8 INR-
7.87K 2
CRITICAL 1% AUD_HPAMP_INR_N CRITICAL C1P HPAMP_CN
1/16W
16 SHDN* MIN_LINE_WIDTH=0.40MM
C5814 MF-LF C1N 4 MIN_NECK_WIDTH=0.20MM

17 THM_PAD
R5805 2 402 CRITICAL
22UF
AUD_LO2_P_R 10K 1 C5805 AUD_HPAMP_OUTR

PGND

SGND

PVSS
OUT 55 57
53 IN
1 2 HPAMP_B4GAIN_INR_P 1 2
1UF MIN_LINE_WIDTH=0.40MM
10% MIN_NECK_WIDTH=0.20MM
1% 10V
20% 1/16W 2 X5R
MF-LF

5
6.3V 402-1
TANT CRITICAL 402
HPAMP_CP
CASE-P
C5815 R5806
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
AUD_LO2_N_R 22UF
1 2 HPAMP_B4GAIN_INR_N 1
10K 2
CRITICAL
53 IN
1%
1 C5806
20% 1/16W 1UF
6.3V MF-LF 10%
10V
B TANT
CASE-P
402

R5808
HPAMP_PVSS MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
2 X5R
402-1 B
CRITICAL
7.87K2 AUD_HPAMP_OUTR
1 55 57
1 C5804
1% 1UF
1/16W 10%
MF-LF 2 10V
402 L5801 X5R
402-1 XW5800
SM
FERR-1000-OHM
1 2 AUD_HPAMP_RETURN OUT 57
53 IN AUD_GPIO_1 1 2 AUD_HPAMP_MUTE_L VOLTAGE=0V
0402 MIN_LINE_WIDTH=0.60 MM
MIN_NECK_WIDTH=0.20 MM
NO_TEST=TRUE
R58001
100K
5%
1/20W
MF
201 2

55 53 GND_AUDIO_HPAMP

DAC FILTER: @ 168KHZ

CODEC FILTER STOPBAND:26.256KHZ, ATTENUATION FROM STOPBAND TO 100KHZ IS 102DB
A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

AUDIO:HEADPHONE AMP
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
58 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 55 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

MONO SPEAKER AMPLIFIER

APN 353S2888
GAIN = 3 DB NOM TO ALLOW A LITTLE MORE THAN 1% THD POWER = 2.1W AT 4OHMS.
FC = 470 HZ. RIN AT 3DB IS 28K.

7 PP5V_S0_AUDIO_AMP
C C
L5901 C5951 CRITICAL
CRITICAL
FERR-1000-OHM C5902 1 1
AUD_LO3_N_L 1
0.012UF
C5904 1 0.1UF
C5901
53 IN
2 AUD_SPKRAMP_INR_L 1 2 AUD_SPKRAMP_INR 1UF 10%
47UF
10% 16V 20%
0402 2 10V
10% 10V 2 X7R-CERM 2 TANT
25V X5R 402 1206-LLP
X7R 402-1
402

A1
PVDD
U5900 SPKRAMP_M_P_OUT
L5900 MAX98300 MIN_LINE_WIDTH=0.50MM OUT
57 91

FERR-1000-OHM C5950 A3 IN+

WLP MIN_NECK_WIDTH=0.20MM
0.012UF OUT+ B1
AUD_LO3_P_L
1 2 AUD_SPKRAMP_INL_L AUD_SPKRAMP_INL B3 IN-
53 IN
1 2 OUT- C1
0402
SPKRAMP_M_N_OUT OUT 57 91
10% CRITICAL MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
L5902 25V
X7R
C2 SHDN* GAIN C3 U5900_GAIN
FERR-1000-OHM 402
B2 NC
53 IN AUD_GPIO_31 2 AUD_SPKRAMP_SD_H NC
0402
PGND
PART IS ENABLED IF AUD_GPIO3 IS HIGH

A2
B R59031 B
R59021 100K
5% SETTING GAIN AT 3DB
100K 1/16W
5% MF-LF
1/16W 402 2
MF-LF
402 2

GND_AUDIO_SPKRAMP 9 57
VOLTAGE=0V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MM

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

AUDIO:SPEAKER AMP
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
59 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 56 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

L6000
FERR-1000-OHM
1 2 HS_MIC_LO 58
OUT
0402

AUDIO JACK 1 LO/HP CONNECTOR, SPDIF TX L6001

FERR-1000-OHM
D AUD_CONNJ1_MIC_HI
MIN_LINE_WIDTH=0.40 MM
1
0402
2 HS_MIC_HI OUT 58 D
MIN_NECK_WIDTH=0.20 MM
L6002
FERR-1000-OHM
AUD_CONNJ1_SLEEVEDET 1 2 AUD_J1_SLEEVEDET 58
OUT
MIN_LINE_WIDTH=0.40 MM 0402
MIN_NECK_WIDTH=0.20 MM
L6006 CRITICAL
FERR-120-OHM-1.5A
AUD_CONNJ1_TIP 1 2 AUD_HPAMP_OUTL 55
BI
MIN_LINE_WIDTH=0.40 MM 0402
MIN_NECK_WIDTH=0.20 MM
L6007 CRITICAL
FERR-120-OHM-1.5A
AUD_CONNJ1_RING 1 2 AUD_HPAMP_OUTR
MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.20 MM 0402
BI 55
GROUND STUFF OPTIONS
OMIT_TABLEL6004 RESISTER ON FERRITE PADS!!
FERR-220-OHM-2.5A
PLACE CLOSE TO CONNECTORS
AUD_CONNJ1_SLEEVE 1 2 AUD_HPAMP_RETURN 55
TABLE_5_HEAD

BI
MIN_LINE_WIDTH=0.60 MM 0603 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
MIN_NECK_WIDTH=0.20 MM
L6005
TABLE_5_ITEM

113S0022 2 RES,ZERO OHM,0603 L6004,L6092

FERR-1000-OHM
AUD_CONNJ1_TIPDET 1 2 AUD_J1_TIPDET
APN 514-0761 MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.20 MM 0402
OUT 58
RESISTER ON FERRITE PADS!!
CRITICAL L6003 OMIT_TABLE
FERR-1000-OHM L6092
J6000 AUD_CONNJ1_PERIPHDET 1 2 AUD_J1_PERIPHDET 58
FERR-70-OHM-4A
OUT
MIN_LINE_WIDTH=0.40 MM 0402 2 1
AUDIO-TX-RX-SPDIF-BLK-J40 MIN_NECK_WIDTH=0.20 MM
F-RT-TH 0603
C MIC 5 AUD_SPDIF_OUT IN 53
C
TYPE_DETECT 4
LEFT 1 NOSTUFF
2 2 2 2
RIGHT 2 DZ6000 DZ6002 DZ6004 DZ6006 R6090
GND 3 6.8V-100PF ESDALC5-1BM2 6.8V-100PF ESDALC5-1BM2 2
0 1
402 SOD882 402 SOD882
AUDIO TX 5%
1/16W
GND 6 1 1 1 1 MF-LF
7 402
HP_DETECT
9 2 2 2 NOSTUFF
IPHS_DETECT
GND 8 DZ6001 DZ6003 DZ6005
6.8V-100PF 6.8V-100PF ESDALC5-1BM2 R6091
402 402 SOD882 GND_CHASSIS_AUDIO_JACK 0 GND_AUDIO_CODEC
57 2 1 53 54 58
A VOLTAGE=0V
LED VIN 5%
B 1 1 1 MIN_LINE_WIDTH=0.40MM
VCC MIN_NECK_WIDTH=0.20MM 1/16W
C GND_CHASSIS_AUDIO_JACK MF-LF
GND 57 402
OPERATING VOLTAGE 3.3
POF AUDIO JACK 2 LINE IN CONNECTOR, SPDIF RX
TYPE_DETECT 13 L6054
LEFT 10 FERR-1000-OHM
RIGHT 11 AUD_CONNJ2_TIP 1 2 AUD_LI_INL 54
BI
GND 12 MIN_LINE_WIDTH=0.40 MM 0402
MIN_NECK_WIDTH=0.20 MM
AUDIO RX
TIP_DETECT 15
L6052
FERR-1000-OHM
SPEAKER CONNECTOR
GND 14 AUD_CONNJ2_RING 1 2 AUD_LI_INR OUT 54
APN 518S0519
MIN_LINE_WIDTH=0.40 MM 0402
MIN_NECK_WIDTH=0.20 MM
D CRITICALL6051
SENSOR VDD J6001
B GRD
VOUT
E
F
600-OHM-300MA
1 2
78171-0002
M-RT-SM B
AUD_CONNJ2_SLEEVE AUD_LI_GND OUT 54 3
OPERATING VOLTAGE 3.3 MIN_LINE_WIDTH=0.40 MM 0402
MIN_NECK_WIDTH=0.20 MM
POF
22 91 56 IN SPKRAMP_M_P_OUT 1
SPKRAMP_M_N_OUT 2
SHELL 23 L6053 91 56 IN
24 FERR-1000-OHM
SHIELD 56 9 GND_AUDIO_SPKRAMP 4
PINS 25 AUD_CONNJ2_TIPDET 1 2 AUD_J2_TIPDET_R 58
BI
MIN_LINE_WIDTH=0.40 MM 0402
MIN_NECK_WIDTH=0.20 MM

R6060
1
22 2 AUD_SPDIF_IN
AUD_J2_OPT_OUT OUT 53
91 5% DO NOT PLACE UNDER SD CARD CONNECTOR.
62 61 60 58 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 1/16W
47 41 40 39 38 37 34 31 30 27
89 79 77 76 74 73 72 71 67
MF-LF
402

2
DZ6052
6.8V-100PF
402
1 C6050 1 C6000 2
1UF 1UF DZ6055 1
10% 10%
2 10V
X5R 2 10V
X5R
ESDALC5-1BM2
402-1 402-1 SOD882

NOSTUFF 1 NOSTUFF 2 2
DZ6051
2
1 C6051 DZ6054
2
1 C6054 DZ6050 DZ6053
6.8V-100PF 6.8V-100PF
ESDALC5-1BM2 0.01UF ESDALC5-1BM2 0.01UF 402 402
SOD882 10% SOD882 10%
2 50V 50V
A 1
X7R
402 1
2 X7R
402 1 1
SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

AUDIO:JACKS
DRAWING NUMBER SIZE
GND_CHASSIS_AUDIO_JACK
57
Apple Inc. 051-8768 D
REVISION
R
PLACE ONE DIODE AT EACH CONNECTOR GND PIN, WITH CAP ADJACENT. 9.0.0
ROUTE FROM CONNECTOR PIN TO DIODE AND CAP, THEN TO FERRITE. NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
60 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 57 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
CODEC OUTPUT SIGNAL PATHS
FUNCTION VOLUME/MUTE CONVERTER PIN COMPLEX ~SHDN CONTROL DET ASSIGNMENT
MIKEY RECEIVER CKT
WRITE: 0X72 READ: 0X73 APN 353S2256
HP/LINE OUT 0X03 (3) 0X03 (03) 0X0A (10) GPIO_1 0X0A(D)
SPEAKER 1 0X04 (4) 0X04 (04) 0X0B (11) GPIO_3 N/A
SPDIF OUT N/A 0X08 (08) 0X10 (16) N/A 0X0D(B)
L6180 MIN_LINE_WIDTH=0.15MM
FLP = 8.82 KHZ
FERR-1000-OHM MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V
FHP = 80 HZ
COUGAR POINT OUTPUT SIGNAL PATHS 91 89
61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 1 2 PP3V3_S0_HS_RX
47 41 40 39 38 37 34 31 30 27
FUNCTION VOLUME/MUTE CONVERTER PIN COMPLEX ~SHDN CONTROL DET ASSIGNMENT 79 77 76 74 73 72 71 67 62 0402
HDMI OUT N/A - - N/A N/A CRITICAL
R61861 C6180 1 1 C6187 D
D CODEC INPUT SIGNAL PATHS
10K
5%
10UF
20%
6.3V 2
10%
0.001UF
1/16W 2 50V

A2
MF-LF X5R CERM CRITICAL
FUNCTION GAIN/MUTE CONVERTER PIN COMPLEX VREF DET ASSIGNMENT 402 2 603 402
AVDD KEEP DET TRACE AS SHORT AS POSS
LINE IN 0X05 (5) 0X05 (05) 0X0C (12) N/A 0X0C(C)
EXT MIC IN 0X06 (6) 0X06 (06) 0X0D (13,V22,B,LEFT) MIKEY MIKEY U6106
CD3282A1
SPDIF IN N/A 0X07 (07) 0X0F (15) N/A N/A WCSP
49 =I2C_MIKEY_SCL C3 SCL MICBIAS C1 HS_MIC_BIAS
IN

49 =I2C_MIKEY_SDA B3 SDA DETECT B1 HS_SW_DET

BI
SYSTEM INT AND GPIO LINES
AUD_I2C_INT_L D3 INT* BYPASS D1 HS_RX_BP
FUNCTION 19 OUT
MIKEY ENABLE SATA4GP/GPIO16
MIKEY INTERRUPT PIRQG*/GPIO5 20 IN AUD_IPHS_SWITCH_EN A3 ENABLE
PERIPHERAL DETECT PIRQF*/GPIO3 TIPDET_UNFILT A1 CRITICAL
HDET
58
1 C6181 1
C6182

C2 DGND

D2 AGND
WRITE: 0X72 READ: 0X73 1
R6180 B2 CS 0.01UF
10%
4.7UF
20%
100K 2 50V
X7R 6.3V
2 TANT
5% 402
1/20W 603-HF
PORT B DETECT MF
PORT D DETECT (SPDIF DELEGATE) 2 201
58 53 OUT AUD_SENSE_A 58 57 54 53 GND_AUDIO_CODEC
NOSTUFF 1 1
1
R6181 R6182
R6184 1K 2.2K
5% 5%
0 1/16W 1/16W
5% MF-LF MF-LF
1/20W 2 402 2 402
1 MF
R6106 1
R6105 2 201
5.11K
1% 20K
C 1/20W
MF
2 201
1%
1/20W
MF CRITICAL C
2 201
R6103 C6183 R6185
0.1UF
100K 2 1 2 2.2K 2
58 PP3V3_S0_AUDIO_F 1 AUD_J1_SLEEVEDET_INV 53 OUT AUD_MIC_INP_L HS_MIC_HI_R 1 HS_MIC_HI
IN 57
AUD_PORT_D_DET_L NC AUD_PORT_G_DET_L
NC
5% 10% 5%
1/20W 16V 1/16W
MF D 6 MF-LF NOSTUFF
1
201
Q6100 D 3 Q6101 X7R-CERM
402
1
R6183 1 C6186
402
1 C6185
R6101 Q6101 D 3 SSM6N37FEAPE 100K 0.0082UF 15PF
270K SSM6N37FEAPE SOT563 5%
5% SOT563 SSM6N37FEAPE 1/16W 10% 5%
1/20W SOT563 CRITICAL MF-LF 2 25V
X7R 2 50V
CERM
MF 2 402 402 402
2 201 2 G S 1 C6184
5 G S 4 0.1UF
5 G S 4 1 2
58 57 IN AUD_J1_SLEEVEDET 53 OUT AUD_MIC_INN_L HS_MIC_LO
IN 57
58 57 AUD_J1_SLEEVEDET
10%
1 C6102 16V
X7R-CERM XW6180
0.01UF 402 SM
10%
2 50V
X7R 58 57 54 53 GND_AUDIO_CODEC 1 2
402
58 57 54 53 GND_AUDIO_CODEC
AUD_OUTJACK_INSERT_L

EXTRACTION NOTIFICATION CKT

58 PP3V3_S0_AUDIO_F
Q6100 D 6 58 PP3V3_S0_AUDIO_F
IN
R61001 SSM6N37FEAPE
270K SOT563
1
5% R6161
B 1/20W
MF
201 2 R6102
220K
5%
B
2 G S 1 1/20W
47.5K2 MF 1
57 IN AUD_J1_TIPDET 1 AUD_J1_DET_RC 2 201 R6162
1 100K
1%
1/16W R6164 5%
MF-LF
402
220K 1/20W
5% MF
1 C6101 1/20W 2 201
0.1UF
10%
MF
2 201 Q6103 D 3 R6163
16V SSM6N37FEAPE 0
2 X7R-CERM AUD_PERIPH_DET_R
1 2 AUD_IP_PERIPHERAL_DET
OUT 19
402 SOT563
5%
1/20W
D 6 MF
58 57 54 53 GND_AUDIO_CODEC
5 G S 4
Q6103 201
SSM6N37FEAPE
SOT563
R6160
PORT C DETECT PERIPHDET_FILT
57 AUD_J1_PERIPHDET115.0K2
58 53 AUD_SENSE_A
NOSTUFF 1%
1/16W
2 G S 1

LOW = DIGITAL (PLASTIC)

1
R6114 MF-LF
402
1 C6160
58 PP3V3_S0_AUDIO_F 0 0.1UF AUD_J1_PERIPHDET_INV
5% 10%
HIGH = ANALOG (METAL) 1/20W
MF
2 16V
X7R-CERM
402
2 201
R61131
10K TIPDET_UNFILT 58
1%
1 1/16W
R6111 MF-LF 58 57 54 53 GND_AUDIO_CODEC
402 2
270K
5%
1/20W AUD_INJACK_INSERT_L
MF NC
2 201 Q6102 PLACE L6100/C6100 CLOSE TO Q6100/01/02/03
SSM3K15FV D 3
A AUD_J2_TIPDET_R
R6112
47.5K2
SOD-VESM-HF
L6100 SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
57 1 AUD_J2_DET_RC FERR-1000-OHM PAGE TITLE
IN
1%
1/16W
91 89
61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27
PP3V3_S0 1
0402
2 PP3V3_S0_AUDIO_F
VOLTAGE=3.3V
58 AUDIO:JACK TRANSLATORS
MF-LF 1 G S 2 79 77 76 74 73 72 71 67 62
MIN_LINE_WIDTH=0.20MM DRAWING NUMBER SIZE
402 MIN_NECK_WIDTH=0.10MM
1 C6111 Apple Inc. 051-8768 D
0.1UF REVISION
10%
1 C6100 R
9.0.0
2 16V 0.1UF
X7R-CERM 10% NOTICE OF PROPRIETARY PROPERTY: BRANCH
402 2 16V
X7R-CERM THE INFORMATION CONTAINED HEREIN IS THE
402 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
58 57 54 53 GND_AUDIO_CODEC THE POSESSOR AGREES TO THE FOLLOWING: PAGE
GND_AUDIO_CODEC
58 57 54 53
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
61 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 58 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

C 27 25 24 23 21 20 19 18 17 6
91 89 78 62 61 28
PP3V3_S5 C
1
R6401

8
3.3K
C6400 1 VCC
5% 0.1UF
1/16W 10% CRITICAL
MF-LF 16V
X7R-CERM 2 U6400
2 402 402
64MBIT
SPI_MLB_CLK 6 SCLK SOIC SPI_MLB_MOSI
48 IN SI/SIO0 5 IN 48

MX25L6406E
SPI_MLB_CS_L 1 CS* OMIT_TABLE
48 IN
SO/SIO1 2 SPI_MLB_MISO OUT 48
SPI_WP_L 3 WP*
91 48 20 IN SPIROM_USE_MLB 7 HOLD*

NOTE: If HOLD* is asserted GND

4
ROM will ignore SPI cycles.

B B

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

SPI BOOT ROM

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
64 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 59 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

FAN CONTROL CIRCUIT

D D

CRITICAL MIN_LINE_WIDTH=0.5MM CRITICAL

MIN_NECK_WIDTH=0.2MM
Q6500 VOLTAGE=12V L6510
FDC638P_G 220-OHM-1.4A
SM 1 2
78 72 65 51 41 6 PP12V_G3H PP12V_S0_FAN
6 0603 MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
5 VOLTAGE=12V
4
R65021 1 C6502
2
1
100K 0.033UF
5%
1/16W 10%
1 C6505 1 C6506 1 C6507
MF-LF 2 16V 2.2UF 2.2UF 0.01UF
402 2 X5R 10% 10% 10%
402 3 16V 16V 2 50V
R6501 C6503 2 X5R
603
2 X5R
603
X7R
402
100K 2 0.01UF
FAN_S0_EN_L 1 FAN_S0_EN_L_G 1 2
Q6501 5% 10%
SSM3K15FV D 3 1/16W
MF-LF 50V
SOD-VESM-HF 402 X7R
91 89 402
61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27
PP3V3_S0 CRITICAL
79 77 76 74 73 72 71 67 62
J6500
1 78171-0004
R6506 1 G S 2 M-RT-SM
5
10K
5%
1/16W CRITICAL
MF-LF MIN_NECK_WIDTH=0.2MM
2 402 L6520 MIN_LINE_WIDTH=0.5MM 91 PP12V_S0_FAN0_F 1 12V DC
C 46 SMC_FAN_0_CTL
220-OHM-1.4A
1 2
91

91
FAN0_TACH_F
FAN0_CTL_F
2
3
TACH
PWM
C
0603 4 GND
91 89
61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0
47 41 40 39 38 37 34 31 30 27
79 77 76 74 73 72 71 67 62 C6520 1 6
100PF
5%
1 50V
R6500 CERM 2
402
10K CRITICAL
5%

www.teknisi-indonesia.com
1/16W L6500
R6599 MF-LF
2 402
FERR-220-OHM
46 SMC_FAN_0_TACH 147.5K2 FAN_TACH0 1 2 518S0521
1% 0402
1/16W
MF-LF
402 C6500 1
100PF
5%
NOTE: ADDED TO PROTECT SMC 50V
CERM 2
402

B B

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

Fan Control Circuit

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
65 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 60 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

3.3V S5 FET CRITICAL 3.3V S4 FET CRITICAL

Q6710 Q6700
SIA427DJ SIA427DJ
SC70-6L SC70-6L
PP3V3_S5 6 17 18 19 20 21 23 24 25 27 28

4 7

4 7
91 65 61 48 47 46 45 43 27 6 PP3V3_G3H 59 62 78 89 91 91 65 61 48 47 46 45 43 27 6 PP3V3_G3H

S
D

D
1

1
PP3V3_S4 6 19 20 25 28 33 34 35 38 47 49
50 77 78 91
3.3V S0 FET
1
R6711 C6711 1 1
R6702 C6709 1
D

G
D Q6711 D 3 26.7K
1%
0.1UF
10%
16V
MOSFET SiA427
SSM6N37FEAPE
Q6702 D 6 470K
5%
0.1UF
10%
16V
3.3V S4 FET

3
SSM6N37FEAPE 1/16W X7R-CERM 2 SOT563 1/16W X7R-CERM 2
SOT563 MF-LF 402 CHANNEL P-TYPE 8V/5V MF-LF 402
2 402
R6710 C6710 2 402
R6700 C6700 MOSFET SiA427

20K 0.01UF RDS(ON) 26 mOhm @1.8V

5.1K 2 0.01UF
1 2 1 2 CHANNEL P-TYPE 8V/5V
P3V3S5_EN_L 1 2 P3V3S5_SS 2 G S 1 P3V3S4_EN_L 1 P3V3S4_GATE
5 G S 4 LOADING 3.2 A (EDP)
62 IN P3V3S5_EN 5%
10% 62 IN P3V3S4_EN 5%
10% RDS(ON) 26 mOhm @1.8V
1/16W 50V 1/16W 50V
MF-LF MF-LF
402 X7R 402 X7R LOADING 1.35 A (EDP)
402 402

3.3V S0 FET CRITICAL

Q6730
SIA427DJ
SC70-6L
PP3V3_S0 50 51 52 53 57 58 60 62 67 71
6 7 13 17 18 19 20 21 23 24 27

4 7
91 65 61 48 47 46 45 43 27 6 PP3V3_G3H 30 31 34 37 38 39 40 41 47 49
72 73 74 76 77 79 89 91

1
3.3V S0 FET
1
R6732 C6731 1

G
26.7K 0.1UF MOSFET SiA427
Q6712 D 3 1% 10%
16V

3
SSM6N37FEAPE 1/16W X7R-CERM 2
SOT563 MF-LF 402 CHANNEL P-TYPE 8V/5V
2 402
R6730 C6730
0.01UF RDS(ON) 26 mOhm @1.8V
20K 1 2
P3V3S0_EN_L 1 2 P3V3S0_SS
5 G S 4 LOADING 3.2 A (EDP)
62 IN P3V3S0_EN 5% 10%
1/16W
MF-LF 50V
402 X7R
402

C 5V_S5 FET CRITICAL

C
Q6740
SIA413DJ
SC70-6L

4 7
91 65 47 45 6 PP5V_G3H

1
PP5V_S5 6 23

www.teknisi-indonesia.com
1
R6742 C6741 1

G
Q6722 D 3 470K
5%
0.15UF
10% 5V S5 FET
SSM6N37FEAPE 10V 2

3
SOT563 1/16W X5R
MF-LF 402
2 402
R6740 C6740 MOSFET SIA413
0.01UF
3.3K 2 1 2 CHANNEL P-TYPE 12V/8V
5 G S 4 P5VS5_EN_L 1 P5VS5_SS
62 IN P5VS5_EN 5%
10% RDS(ON) 29 MOHM @4.5V
1/16W
MF-LF 50V
402 X7R LOADING 100? mA (EDP)
402
1.5V S3/S0 FET
91 72 66 32 31 30 28 6 PP1V5_S3
PP5V_S4
91 78 66 65 61 45 44 43 28 6
5.0V S0 FET CRITICAL
Q6760
C6701 1 TPCP8102
0.1UF PP5V_S0 7 23 24 41 42 48 62 64 67 68 69
1

10% 23V1K-SM 70 71 80 91
16V

5 6 7 8
X7R-CERM 2 VCC

1 2 3
402 5 APN 376S0928
91 78 66 65 61 45 44 43 28 6 PP5V_S4
U6701

S
5.0V S0 FET

D
B SLG5AP020
TDFN
D
CRITICAL 1
R6762
B
P1V5CPU_EN 2 ON D 5 Q6701 C6761 1

G
28 IN
CRITICAL R6701 220K 0.15UF
MOSFET TPCP8102

4
3 SHDN* 7 1
0 2 4 G
SI7108DN 5% 10%
G PWRPK-1212-8-HF 1/16W 10V 2 CHANNEL P-TYPE 20V/12V
MF-LF X5R
NO STUFF P1V5S0FET_GATE
5% P1V5S0FET_GATE_R 2 402 C6760
C6702 1 S 6 1/16W
MF-LF
S
R6760402 0.01UF
RDS(ON) 18 MOHM @4.5V

4.7UF 402 1 2 3 10K 1 2

10% PG 8 PP1V5_VDDQ_CPU_R 7 50 P5V0S0_EN_L 1 2 P5V0S0_SS LOADING 1.678 A (EDP)
6.3V THRM 5%
X5R-CERM 2 GND PAD 1/16W 10%
603 MF-LF 50V
4

402 X7R
402
Q6702 D 3
P1V5VDDQCPU_RAMP_DONE OUT 28 1.5V S3/S0 FET SSM6N37FEAPE
SOT563
MOSFET SI7108DN

CHANNEL N-TYPE 5 G S 4
P5VS0_EN
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62 IN
RDS(ON) 6 mOhm @4.5V

LOADING 5 A (EDP)

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=12/13/2010 A
PAGE TITLE

Power FETs
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
67 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 61 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
S5 Rail Enables & PGOOD 3.3V,5V S4 ENABLE
I703
91 46 18 IN PM_SLP_S5_L P5VS4_EN OUT 65
State SMC_PM_G2_ENABLE PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L MAKE_BASE=TRUE
P5VS5_EN OUT 61
Run (S0) 1 1 1 1
R6840
2 R6812 2 R6811
Sleep (S3) 1 1 1 0
0 5.1K
100 5% 5%
91 47 46 IN SMC_PM_G2_EN 1 2 P3V3S5_EN OUT 61 1/16W 1/16W
MAKE_BASE=TRUE MAKE_BASE=TRUE Deep Sleep (S4) 1 1 0 0 1 MF-LF 1 MF-LF
5% 402
1/16W
MF-LF
1 C6842 402
402 0.033UF STANDBY (S5) 1 0 0 0
10%
2 16V
D
X5R
402
NO STUFF
AC POWER (G3HOT) 0 0 0 0 P3V3S4_EN OUT 61 D
USB_PWR_EN OUT 43

NO STUFF
PP3V3_S5
1 C6812 1 C6810
27 25 24 23 21 20 19 18 17 6
91 89 78 62 61 59 28 0.47UF 0.47UF
10% 10%
R6841 1 2 6.3V 2 6.3V
100
3.3V,5V S3 ENABLE CERM-X5R
402
CERM-X5R
402
5%
1/16W I705
MF-LF
402 2 91 46 28 18 IN PM_SLP_S4_L DDRREG_EN OUT 66
MAKE_BASE=TRUE
S5_PWRGD 46
OUT

S5_PWRGD (old name RSMRST_PWRGD)-->SMC S0 ENABLE

SMC-->PM_DSW_PWRGD
R6878
100 (PM_SLP_S3_R_L) PM_SLP_S3_R_L
91 62 51 46 28 18 IN PM_SLP_S3_L1 2
MAKE_BASE=TRUE
5% P5VS0_EN OUT 61
1/16W
MF-LF 1 1
402 1 1 R6888 R6886 P3V3S0_EN OUT 61
R6887 R6881 10K 5.1K
33.2K 20K 5% 5%
1% 5% 1/16W 1/16W
1/16W 1/16W MF-LF MF-LF
S0 Rail PGOOD (BJT Version) MF-LF MF-LF 2 402 2 402
2 402 2 402

27 25 24 23 21 20 19 18 17 6
PP3V3_S5
91 89 78 62 61 59 28 P1V8S0_EN OUT 71
91 89
61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 R68561
47 41 40 39 38 37 34 31 30 27
79 77 76 74 73 72 71 67 62
150K
1 1%
R6851 1/16W P1V5S0_EN OUT 71
MF-LF ALL_SYS_PWRGD 27 46 62
15.0K
C 1%
1/16W
402 2
S0PGD_C 1V05_S0_LDO_EN C
MF-LF
2 402
R6853 CPUVCCIOS0_EN OUT 70

VMON_3V3_DIV 1
1K 2 VMON_Q2_BASE MAKE_BASE=TRUE
6

4
PVCCSA_EN OUT 64
5%
1 1/16W Q6850 CPUVCORE ENABLE
R6852 MF-LF
402 Q1
7.15K 5 ASMCC0179 R6874
1% Q2
1/16W
MF-LF DFN2015H4-8 ALL_SYS_PWRGD 1
0 2 PM_EN_PVCORE_CPU 1 C6887 1 C6881 1 C6888
1 C6886

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8 62 46 27 OUT 67
0.47UF
2 402 R6854 NC 5% 0.47UF 0.47UF 0.47UF 10%
1
1K 2 VMON_Q3_BASE 7
1/16W 10%
6.3V
10%
6.3V
10%
6.3V 2 6.3V
CERM-X5R
Q3 MF-LF 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 402
402
5% 2 CRITICAL R6876 402 402 402
1/16W NC 0
MF-LF 1 2 PM_PECI_PWRGD OUT 46
62 50 32 31 28 16 13 11 7 PP1V5_VDDQ_CPU 402 1
Q4 5% NO STUFF
1/16W
MF-LF
R6855 402 R6875 VFRQ Low: Fix Frequency
1K VMON_Q4_BASE 0 VFRQ High: Variable Frequency
76 70 62 50 46 24 7 PP1V05_S0 1 2 70 62 CPUVCCIOS0_PGOOD 1 2
3

353S2809
5% 5%
1/16W S0PGD_BJT_GND_R 1/16W
MF-LF MF-LF
402 Worst-Case Thresholds: 402
1
R6857
Q2: 0.XXXV 100
5%
Q3: 0.640V 1/16W
MF-LF
3.3V w/Divider: 2.345V 2 402
Q4: 0.660V

3.3V ENET FET

B 91 89
ENET Enable Generation CRITICAL
Q6822
B
61 60 58 57 53 52 51 50 49 "ENET" = "S0" || ("S5" && "WOL_EN")
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27
PP3V3_S0 NTR4101P
79 77 76 74 73 72 71 67 62 SOT-23-HF
R68671
10K PP3V3_S5 2 S D 3 PP3V3_ENET
5% 27 25 24 23 21 20 19 18 17 6 6 26 37 38 91
1/16W 91 89 78 62 61 59 28
MF-LF
402 2
S0 Rail PGOOD Circuitry 1 C6821 G
R6869 R68211 0.033UF
10%
(ISL Version in development) 10K 1
100 5% 2 16V
X5R
66 IN DDRREG_PGOOD 1 2 1/16W 402 C6822
NO STUFF 5%
MF-LF
402 2 R6822 0.01UF
R6868 1/16W 100K 2 2 1
Thresholds: MF-LF PM_ENET_EN_L 1 P3V3ENET_SS
PM_PGOOD_PVCORE_CPU 1
100 2
402
5%
VDD: 2.734V-3.010V 67 27 IN 3 10%
1/16W
50V
V2MON: 2.815V-3.099V
P1V5S0_PGOOD from U7710
5%
1/16W R6866 Q6825 D
MF-LF
402 X7R
402
V3MON: 0.572V-0.630V MF-LF 2N7002DW-X-G
402 100 SOT-363
V4MON: 0.572V-0.630V 71 IN P1V8S0_PGOOD 1 2
5 6
20 IN WOL_EN G S
91
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 R6865
5%
1/16W Q6825 D
47 41 40 39 38 37 34 31 30 27 MF-LF 4 2N7002DW-X-G
89 79 77 76 74 73 72 71 67
S0PGOOD_ISL 100 402 SOT-363
PP1V5_VDDQ_CPU PM_P5V_S4_PG 1 2
62 50 32 31 28 16 13 11 7
1 C6860 78 65 IN
5%
91 62 51 46 28 18 IN PM_SLP_S3_L 2 G S
76
PP1V05_S0 0.1UF 1/16W
91 80 71 70 69
42 41 24 23 7 PP5V_S0 46 24 7
70 62 50 10% MF-LF R6864 1
68 67 64 61 48 2 16V
X7R-CERM 402 100
CPUVCCIOS0_PGOOD 1 2
2
7

S0PGOOD_ISL 402 70 62 IN
1 S0PGOOD_ISL
1 S0PGOOD_ISL
1
R6860 R6870 R6872 VDD
R6863
5%
1/16W
6.04K 10K 6.04K MF-LF
1%
1/16W
1%
1/16W
1%
1/16W
U6860 64 IN PVCCSA_PGOOD 1
100 2
402
PM_WLAN_EN_L OUT 35
MF-LF MF-LF MF-LF ISL88042IRTEZ
5%
A 402 2
P5V_DIV_VMON
402 2 402 2 TDFN
3 V2MON CRITICAL
MR* 1
(IPU)
NC
1/16W
MF-LF
402
Q6821
SSM3K15FV D 3 SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
P1V5_DIV_VMON 5 V3MON SOD-VESM-HF PAGE TITLE
S0PGOOD_ISL8 ALL_SYS_PWRGD_R
P1V05_DIV_VMON 6 V4MON RST*
S0PGOOD_ISL
Power Control 1/ENABLE
S0PGOOD_ISL
1 S0PGOOD_ISL
1 S0PGOOD_ISL
1 GND THRM_PAD R6862 DRAWING NUMBER SIZE
R6861 R6871 R6873 332 051-8768 D
Apple Inc.
4

15.0K 10K 15.0K 353S2310 1 2 ALL_SYS_PWRGD OUT 27 46 62 1 G S 2

1% 1% 1% REVISION
1/16W 1/16W 1/16W 1% 35 24 19 AP_PWR_EN R
MF-LF
402 2
MF-LF
402 2
MF-LF
402 2
1/16W
MF-LF
IN
9.0.0
402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
WLAN Enable Generation THE POSESSOR AGREES TO THE FOLLOWING: PAGE
"WLAN" = ("S4" && "AP_PWR_EN" ) I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
68 OF 512
NOTE: S4 TERM IS GUARANTEED BY S3 PULL-UP ON OPEN-DRAIN AP_PWR_EN SIGNAL. III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 62 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

C C

ROOM FOR MORE?

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B B

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

POWER CONTROL CONT.

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
69 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 63 OF 104
8 7 6 5 4 3 2 1
www.teknisi-indonesia.com
 8 7 6 5 4 3 2 1

R7202 MIN_LINE_WIDTH=0.5 MM R7203

4.7K 1 2.2 PP5V_G3H

VR3V3_G3H_V5V
2 MIN_NECK_WIDTH=0.2 mm 1 2 6 45 47 61 65 91

5% 5%
1/16W 1/10W
MF-LF MF-LF

D
402 603
PP12V_G3H 6 41 51 60 65 72 78 D
C7211 1 CRITICAL
1UF C7202 1 1 C7213 1 C7204 1
C7205
10%
16V 2 0.1UF 0.001UF 0.1UF 39UF
X5R
402
10%
25V 2
1 C7201 10%
2 50V
10%
2 25V
20%
16V
2 POLY-TANT
X5R
402
1UF CERM
402
X5R
402
10% CASED2-SM
2 16V
X5R
402
AGND_3V3_G3H_REG

10
11
30
2

5
8
9

6
V5V

VLDO
91 65 61 48 47 46 45 43 27 6 PP3V3_G3H VIN
R72041 CRITICAL
100K
5%
U7201
1/16W
MF-LF 25 EN_PSV
SC414 7
402 2 VR3V3_G3H_EN BST VR3V3_G3H_BST
MLPQ DIDT=TRUE0.5 MM
PM_P3V3_G3H_PG 22 PGOOD LXBST 12 0.2 MM
0.2 MM SWITCH_NODE 1 C7203 CRITICAL
FOR POWER SEQUENCE? 0.2 MM LX_1 15
1 FB
LX_2 20 10%
0.1UF L7201
16V 3.3UH-6A
VR3V3_G3H_TON 27 TON LX_3 21 VR3V3_G3H_SW 2 402X7R-CERM0.5 MM
0.2 MM 1 2 PP3V3_G3H 6 27 43 45 46 47 48 61 65 91
LXS 24 SWITCH_NODE SWITCH_NODE0.2 MM
NOSTUFF 4 VOUT DIDT=TRUE 0.2 MM MMD-06CZ
31 DIDT=TRUE
LX_5 NO_TEST=TRUE
NO_TEST=TRUE R7208 2
R72141 R72051 10K 2

VR3V3_G3H_FB
23 VR3V3_G3H_ILIM 1 VR3V3_G3H_LXS CRITICAL CRITICAL
4.7K 133K
ILIM
DIDT=TRUE
0.2 MM
1% 1/16W MF-LF 402
SHORT-12L-0.25MM-SM
XW7202 1 C7212 1 C7209 1 C7210
5% 1% 28 0.2 MM 0.001UF 22UF 22UF
1/16W
MF-LF
1/16W
MF-LF
ENL R7209 1 10% 20% 20%
402 2 402 2 40.2K2 PP12V_G3H 2 50V
CERM 2 6.3V
CERM 2 6.3V
CERM
VR3V3_G3H_ENL
1 6 41 51 60 65 72 78 402 805 805
1% 1/16W MF-LF 402
AGND PGND
1
C R7215 C

3
26
29

13
14
16
17
18
19
AGND_3V3_G3H_REG 20.0K
1%
1/16W
MF-LF
2 402 C7208 1 1
R7210
XW7201 220PF
10% 10K
1%
F=300KHZ
SM 50V
X7R-CERM 2 1/16W
MF-LF OCP=9A+/-10%
1 2 402
2 402
AGND_3V3_G3H_REG

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MIN_LINE_WIDTH=0.5 MM 1
MIN_NECK_WIDTH=0.2 mm
R7211
2.94K
NO_TEST=TRUE 1%
0.2 MM 1/16W
VR3V3_G3H_VSEN 0.2 MM MF-LF
NO_TEST=TRUE 2 402
AGND_3V3_G3H_REG

SC414 6A/9A @ 3.3V (S5)

R7251 MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
2.2
91 65 61 47 45 6 PP5V_G3H 2 1 VR5V_G3H_VCC
5%
1/10W
MF-LF
603
B 78 72 65 60 51 41 6 PP12V_G3H 1 C7254
1UF
B
10%
2 16V
X5R
CRITICAL CRITICAL 402 0.5 MM
1
C7251 1 C7252 1 C7253 1 C7250 0.2 MM
39UF 1UF 0.1UF 0.001UF
10% 10% 10%
10

20% SWITCH_NODE
2 16V
POLY 2 35V
X5R 2 25V
X5R 2 50V
CERM DIDT=TRUE
SM 603 402 402
VCC
U7251
1 C7256
0.1UF
IR3859MPBF 10% CRITICAL
2 16V
13
QFN
14 VR5V_S4_BOOT
X7R-CERM
402 L7251
R7254 VIN CRITICAL BOOT
DIDT=TRUE
NO_TEST=TRUE
2.2UH-20%-8A-0.0112OHM
0.5 MM
P5VS4_EN 2
1K 1 VR5V_S4_EN_IC 15 12 VR5V_G3H_SW SWITCH_NODE 0.2 MM 1 2 PP5V_S4
62 IN ENABLE SW 6 28 43 44 45 61 66 78 91
DIDT=TRUE R7256 PIMB065T-SM
5%
16 7 VR5V_S4_OCSET 1 2
11.3K
1/16W SEQ OCSET 1 CRITICAL CRITICAL
MF-LF
402
0.2 MM 0.2 MM
1% 402 R7261 1 C7260 1 C7261 1
C7262
78 62 OUT PM_P5V_S4_PG 8 PGOOD FB 1 VR5V_S4_FB
0.2 MM 0 0.001UF 10UF
0.2 MM 5% 10% 10%
150UF
FOR POWER SEQUENCE VR5V_S4_RT 5 RT COMP 3 1/16W
MF-LF 2 50V 16V
2 X5R-CERM
20%
2 6.3V
0.2 MM CERM POLY-TANT
VR5V_S4_COMP

0.2 MM 2 402 402 0805 CASE-B2-SM

0.2 MM
0.2 MM VR5V_S4_SS 6 SS/SD VSNS 2 C7257 R7257 R7258

VR5V_S4_FB_SNS
0.2 MM 0.0022UF 0.2 MM
0.2 MM 26.7K2 6.98K2
0.2 MM
0.2 MM
0.2 MM 9 1 2 1 1
1 NC SYNC THRM
R7255 C7255 1 GND PGND PAD VR5V_S4_COMP_RC
10% 1% 1%
NO_TEST=TRUE
23.7K 0.047UF 50V
1/16W 1/16W
MF-LF MF-LF
4

11

17

1% 10% CERM
1/16W 16V 2 402 C7258 402 402 C7259
MF-LF X7R 22PF R7259 0.2 MM
2.37K2 0.20.0022UF
402 2 402
1 2 1
MM
1 2 F=600KHZ
XW7251 1% VR5V_S4_FB_RC OCP=60A NOM/30A MIN
A SM AGND_5V_G3H_REG
5%
50V
CERM 1
1/16W
MF-LF
10%
50V
CERM SYNC_MASTER=REFERENCE_MLBSYNC_DATE=11/23/2010 A
1 2 402 R7260 402 402 PAGE TITLE
AGND_5V_G3H_REG MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
NO_TEST=TRUE
1.13K
1%
1/16W
MF-LF
VR - 3.3V S5 AND 5V S4 DRAWING NUMBER SIZE
2 402 051-8768 D
Apple Inc. REVISION
R
AGND_5V_G3H_REG 9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE

IR3859 5A/9A @ 5V (S4) PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
PAGE
72 OF 512
SHEET
IV ALL RIGHTS RESERVED 65 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

CRITICAL
L7302
0.47UH+/-20%-12MOHM-7A
70 69 68 64 51 6 PP12V_G3H_CPUDDR 1 2 PP12V_G3H_DDRS3REG_FILT
PIMB042T-COMBO VOLTAGE=12V
MIN_LINE_WIDTH=0.6 mm
1 C7301 1 C7302 MIN_NECK_WIDTH=0.2 mm
0.01UF 1UF MAX_NECK_LENGTH=3 MM
10% 10% DIDT=TRUE
2 50V
X7R 2 35V
X5R
402 603

CRITICAL CRITICAL
C7331 C7333 1 C7398 1
C7330 1 C7332 1 1
1UF
0.001UF 0.1UF
39UF 39UF 10%
10%
50V
10%
25V 2
20% 20% CERM 2
16V
POLY 2
16V
POLY 2 2 35V
X5R 402
X5R
402
SM SM 603
MIN_LINE_WIDTH=0.5 MM
R7301 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
PP5V_S4 1
2.2 2 PP5V_S4_DDRREG_V5IN
91 78 65 61 45 44 43 28 6
PP1V5_S3
teknisi-indonesia
6 28 30 31 32 61 66 72 91
5%
1/10W 5
MF-LF
603 C7300 1 1 C7355 OMIT_TABLE
2.2UF 10UF D CRITICAL
10% 20%
16V 2
X5R 2 6.3V
X5R 4 G
Q7330
603 603 RJK0225DNS
C MIN_LINE_WIDTH=0.5 MM HVSON-3333 C

2
MIN_NECK_WIDTH=0.2 mm
CRITICAL
VLDOIN
R7330 C7325 S CRITICAL VOLTAGE=1.5V R7340
0.1UF MIN_LINE_WIDTH=0.8 MM 0.001
0SWITCH_NODE MIN_NECK_WIDTH=0.1 MM
12 V5IN VBST 15 DDRREG_VBST
SWITCH_NODEMIN_LINE_WIDTH=0.5
DIDT=TRUE MM
1 2 1 2
1 2 3
L7330 1%
1W
DRVH 14 DDRREG_DRVH MIN_NECK_WIDTH=0.2 mm 5% DDRREG_VBST_R 1.0UH-20A-2.64M-OHM MF-1
28 MEMVTT_EN 17 S3
U7300 SW 13
GATE_NODE
DDRREG_SW
NO_TEST=TRUE
DIDT=TRUE 1/16W 0.5 MM
MF-LF 0.2 MM
10%
16V 1 2 PP1V5_S3_REG 1
0612
2 PP1V5_S3 6 28 30 31 32 61 66 72 91
IN X7R-CERM
DDRREG_EN TPS51916 SWITCH_NODE DIDT=TRUE MIN_LINE_WIDTH=0.5
402 MM 402 PIMB103E-SM-1 CRITICAL 3 4
16 S5 NO_TEST=TRUE DIDT=TRUE
MIN_NECK_WIDTH=0.2 mm
62 IN QFN
DRVL 11 DDRREG_DRVL NO_TEST=TRUE 1
C7340 12A max output

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0.2 mm 0.2 MM DDRREG_1V8_VREF 6 VREF GATE_NODE 5 1
R7331 330UF
CRITICAL PGOOD 20 DDRREG_PGOOD OUT 62 NO_TEST=TRUE DIDT=TRUE OMIT_TABLE 20%
DDRREG_VDDQSNS 2.2 2 2.5V
TANT
0.2 mm 0.2 MM VDDQSNS 9 CRITICAL 5%
33 DDRREG_REFIN 8 REFIN
3 PP0V75_S0_DDRVTT
D 1/10W C7399 1 CASE-B2-SM 1 C7345 P1V5S3_CS_N OUT
VTT 0.2 mm 0.5 MM 7 28 30 31 91
Q7335 MF-LF
2 603
0.001UF CRITICAL 10UF 50

DDRREG_MODE DDRREG_VTTSNS XW7360 10% 20%

<Ra> DDRREG_TRIP
19 MODE
18 TRIP
VTTSNS 1
0.2 MM
SHORT-12L-0.25MM-SM 4 G
MIN_LINE_WIDTH=0.5 MM
RJK0226DNS
HVSON-333 DDRREG_SNUB
50V
CERM 2
402
C7341
330UF
1 2 6.3V
X5R
603 P1V5S3_CS_P OUT 50
R73201 VTTREF 5
0.2 mm 1 2 MIN_NECK_WIDTH=0.2 mm DIDT=TRUE
NO_TEST=TRUE 0.5 MM 20%
10K CRITICAL CRITICAL S 0.2 MM 2.5V
TANT 2
1%
1/16W C7360 1 1 C7361
1 C7321 CASE-B2-SM
MF-LF
VTT THRM 0.001UF
C7305 1 402 2 PGND GND GND PAD 22UF 22UF 1 2 3 10%
0.25 MM 20% 20% 50V
2 CERM
0.1UF 1 6.3V 2 6.3V
R7310
10

21

10% 0.2 mm X5R-CERM1 2 X5R-CERM1 402

16V 200K 0603 0603
X7R-CERM 2 1
402 1%
1/16W R7305
MF-LF 75K
<Rb> 1
402 2 1%
1/16W
MF-LF XW7300 XW7335
R7321 2 402 SM PPDDRVREF_S3 OUT 6 33 91 SHORT-12L-0.25MM-SM
49.9K
1% 1 C7320
2 1 10mA max load MIN_LINE_WIDTH=0.2 mm
1 2
1/16W
MF-LF 0.01UF Vout = VTTREF MIN_NECK_WIDTH=0.2 mm
402 2 10%
2 50V
X7R
1 C7350 Vout = VDDQSNS/2
402 0.22UF
B 10%
16V
2 CERM
402
B
GND_DDRREG_SGND
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
NO_TEST=TRUE

VDDQ = VREFIN = 1.8V * RB / (RA + RB) f = 400 kHz TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_ITEM

376S0979 1 TRA,FET,FAIRCHILD Q7330 CRITICAL FET_SET_A:FAIRCHILD

OCP=27A NOM/19A MIN TABLE_5_ITEM

376S0874 1 TRA,FET,FAIRCHILD Q7335 CRITICAL FET_SET_A:FAIRCHILD

TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_ITEM

376S0964 1 TRA,FET,RENESAS Q7330 CRITICAL FET_SET_A:RENESAS

TABLE_5_ITEM

376S0965 1 TRA,FET,RENESAS Q7335 CRITICAL FET_SET_A:RENESAS

TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_ITEM

085-3109 1 COMP SET,FETS,FAIRCHILD CSET1 CRITICAL FET_SET_A:USE_PHANTOMS

TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

A 085-3110
PART NUMBER

085-3109 FET_SET_A:USE_PHANTOMS CSET1

TABLE_ALT_ITEM

COMP SET,FETS,RENESAS
SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

DDR 1.5V VR DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
73 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 66 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

69 50 16 13 7 PPVAXG_S0_CPU
SM
0.2 mm 0.25 MM R7460
1K
CPU CORE/AXG REG 1.1V/53A
SIGNAL_MODEL=EMPTY
O/P= PPVCORE_S0_CPU_REG
1 2 VR_AXG_VSNS_XW_P 1 2
R7462
VOLTAGE=1.1V
5%
1/16W 1
10 2
XW7420 R7461 MF-LF R7427
0 402 5% SIGNAL_MODEL=EMPTY PP5V_S0 2.2 PP5V_S0_CPU_VCORE_VCC
1 2 VR_AXG_VSNS_R_P
1/16W 68 64 62 61 48 42 41 24 23 7 2 1 67
0.25 MM MF-LF NOSTUFF 91 80 71 70 69
MAX_NECK_LENGTH=2MM
5% 0.2 mm 0.25 MM 402 5%
CPU_AXG_SENSE_P 0.2 mm 1/16W C7455 1 1/8W MIN_NECK_WIDTH=0.2MM
81 13 IN MF-LF MF-LF MIN_LINE_WIDTH=0.5MM
402 0.0022UF 805
VOLTAGE=5V
81 13 CPU_AXG_SENSE_N 10% PP3V3_S0 50 51 52 53 57 58 60 61 62 67
IN SIGNAL_MODEL=EMPTY 50V 6 7 13 17 18 19 20 21 23 24 27
0.25 MM CERM 2 30 31 34 37 38 39 40 41 47 49
R7463 0.2 mm 0.25 MM R7464 402 71 72 73 74 76 77 79 89 91
D
D 0.2 mm
1
0 2 VR_AXG_VSNS_R_N
1
10 2 1
R7495
5%
1/16W
5%
1/16W 1 C7457 10K CPU VCORE
XW7430 MF-LF R7465 MF-LF
1 C7456 5%
1/16W
SM 402
1K
402 0.0022UF
10%
0.0022UF
10%
PP3V3_S0 50 51 52 53 57 58 60 61 62 67
6 7 13 17 18 19 20 21 23 24 27
MF-LF VOUT = VCORE
1 2 VR_AXG_VSNS_XW_N 1 2 2 50V
30 31 34 37 38 39 40 41 47 49 2 402
VOLTAGE=0V 2 50V
CERM CERM 71 72 73 74 76 77 79 89 91
R7457 PEAK = 53A
5% 402 402
1/16W VR_AXG_TM 2
1.47K1
0.2 mm 0.25 MM MF-LF
402 1%
AVG = 36A
0.25 MM 0.25 MM 1/16W
MF-LF
402
C7416 R7428 0.2 mm 0.2 mm
R74051 1
R7406
470PF 0 0
1 2 VR_SEN_R2 1
100 2 5% 5% VR_AXG_PWM

10KOHM-1%
CRITICAL

2
69

RT7403
1/16W 1/16W OUT
10% 0.2 mm 0.2 MM 1%
1/16W
1 C7413 0.2MM MF-LF
402 2
MF-LF
2 402
0.1UF C7409

0603
50V MF-LF 1
CERM 402 10% 0.2 mm
0.1UF
1 C7414
402 2 16V
X7R-CERM 10% 2.2UF
10%
R7408
402 2 16V 422
R7429 X7R-CERM
402
2 16V
X5R 1 2 0.2 mm 0.2 MM
1.58K2 603

1
1 1%
1/16W
1% MF-LF
1/16W
MF-LF
R74891 XW7401 402
LOCAL 5V

35
402 10K SHORT-12L-0.25MM-SM 1 C7400 SIGNAL_MODEL=EMPTY
5%
1/16W
1 2
56PF
1 C7401 1 C7402 VR_AXG_ISNS_P IN 69
MF-LF VCC 5% 0.1UF 220PF
VR_AXG_TMN 10%
402 2 2 50V
CERM 2 16V
10%
50V VR_AXG_ISNS_N
0.2MM X7R-CERM 2 X7R-CERM
C7417 0.2 mm U7400 0.2 MM
0.2 MM
402 402 402
IN 69

R7432 1000PF ISL6364

0.2 mm
0.2 mm
1
12.1K2 1
VR_AXG_COMP_RC 2 QFN
23 TMS PWMS 26
1% 0.2 mm 0.2 MM
1/16W 5% VR_AXG_VSEN20 ISENS+ 24 VR_AXG_ISNS_RP
MF-LF 25V VSENS CRITICAL
ISENS- 25
C 402
C7418
39PF
NP0-C0G
402 R74411
1% 1/16W
2 1.58K
MF-LF 402
VR_AXG_HFREQ_COMP 16
0.2 mm 0.2 MM
HFCOMPS/DVCS
PWM1 38
0.2 mm

0.2 mm
0.2 MM

0.2 MM VR_CPU_PWM1 68
C
OUT
1 2 0.2 mm 0.2 MM 19
VR_AXG_FB FBS ISEN1+ 46 0.2 mm 0.2 MM VR_CPU_ISNS1_P IN 68
SIGNAL_MODEL=EMPTY
5% VR_AXG_RGND 21 ISEN1- 45 0.2 mm 0.2 MM
RGNDS 1 C7403 VR_CPU_ISNS1_N
C7419 R7433CERM
50V
PWM2 36 0.2 mm 0.2 MM 220PF
1 C7404 IN 68

0.0022UF 402 0.2 mm 0.2 MM VR_AXG_COMP 18 COMPS 10% 0.1UF

2 VR_CPU_PSICOMP1 698 ISEN2+ 42 2 50V
10%
1 1 2
13 X7R-CERM 2 16V
X7R-CERM
62 27 OUT PM_PGOOD_PVCORE_CPU VR_RDY ISEN2- 41 402 402
0.2 mm 0.2 MM 1%

www.teknisi-indonesia.com
10% 1/16W
50V MF-LF PP5V_S0_CPU_VCORE_VCC R7440 1 2 953K VR_AXG_TCOMP 30 BTS_DES_TCOMPS PWM3 39 VR_CPU_PWM3
R7456 1NOSTUFF
67
CERM 402 1% 1/16W MF-LF402
402 2 19.6K VR_CPU_SUTH 29 BT_FDVID_TCOMP ISEN3+ 48
MF-LF402 NC VR_CPU_PWM2
R7434 C7420 1% 1/16W R74421 2 28K VR_CPU_N_PSI 28 NPSI_DE_IMAX ISEN3- 47
0.2 mm 0.2 MM OUT 68

390PF 1/16W 1% MF-LF402 0.2 mm 0.2 MM VR_CPU_ISNS2_P

249 1 2
R7443 1 231.6K VR_CPU_FDVID 27 ADDR_DES_FDVID_TMAX SIGNAL_MODEL=EMPTY
IN 68

1 2 VR_CPU_FB_RC 1/16W
1% MF-LF402 CPU_VIDSCLK PWM4 37 VR_CPU_PWM4
1% 0.2 mm 0.2 MM 81 13 IN
12 SVCLK
ISEN4+ 44
1 C7405 1 C7406 VR_CPU_ISNS2_N
1/16W 10% 81 13 OUT
CPU_VIDALERT_L 11 SVALERT* NC 220PF 0.1UF IN 68

MF-LF 50V ISEN4- 43 10% 10%

402 CERM 81 13 BI
CPU_VIDSOUT 10 SVDATA 50V 2 16V
X7R-CERM
402 2 X7R-CERM
(VR_CPU_VSEN) 402
R7435 4 VSEN FSS_DRPS 22 VR_AXG_SW_FREQ 402
1
1.3K 2
(VR_CPU_RGND) 3 0.2 mm 0.2 MM
RGND VR_RDYS 17 PM_PGOOD_PVAXG
1%
1/16W 0.2 mm 0.2 MM VR_CPU_FB 7 FB
MF-LF
VR_CPU_PSICOMP 6 IMONS 14 VR_AXG_IMON
402 0.2 mm 0.2 MM PSICOMP
R7444 1 2 1.5K VR_CPU_HFREQ_COMP 5 FS_DRP 34 VR_CPU_SW_FREQ
HFCOMP
1% 1/16W MF-LF402 0.2 mm 0.2 MM
VR_CPU_COMP 8 RAMP_ADJ 2 VR_CPU_RAMP_ADJ
0.2 mm 0.2 MM COMP
0.2 mm 0.2 MM 32 SICI EN_VTT 40 PM_EN_PVCORE_CPU IN 62
C7422 VR_CPU_IAUTO
82PF 9 EN_PWR_OVP 1 VR_EN_PWR_OVP
1 2 50 OUT 0.2 mm 0.2 MM VR_CPU_IMON IMON

B 5%
50V
81
11
47
CPU_PROCHOT_L R7499
5%
1
1/16W
2 0
MF-LF402
VR_HOT_L
VR_CPU_TM
15
31
VR_HOT*
RSET 33 0.2 MM
0.2 mm
0.2 MM
0.2 mm
0.2 mm 0.2 MM
B
0.2 mm 0.2 MM TM
R7445 CERM
402 C7423 THRM
PP12V_S0_CPU_FLTRD 68 PP5V_S0_CPU_VCORE_VCC
0.0022UF R7452 1 PAD 67
10K 1 2
1 2 VR_CPU_FB2 0 R7449 1R7450 1R7451 1 NOSTUFF

49
1% 0.2 mm 0.2 MM 5%
14.7K 15.4K 499K
1
R7458 R7420 1 1 R7480 1
1/16W 10%
50V
1/16W
MF-LF 1% 1% 1% 255K R7455 1 100K
MF-LF
402 CERM
402
402 2 NOSTUFF 1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1%
1/16W
VR_RSET 165K
1%
143K
1%
R7422 1
R7418 5%
1/16W
R7446 1R7447 1R7448 1 402 2 402 2 402 2 MF-LF 1/16W 1/16W 100K 1.18M MF-LF
5%
110 90.9 54.9 2 402 R7419 1 MF-LF
402 2
MF-LF 1/16W 1% 402 2
5% 1% 1% 2 402 MF-LF 1/16W
MF
67 PP5V_S0_CPU_VCORE_VCC 1/16W 1/16W 1/16W 17.4K 2 402 2 402 1 C7412
MF-LF MF-LF MF-LF 1% OUT 50
402 2 402 2 402 2 1/16W 0.1UF
MF-LF 10%
10KOHM-1%
CRITICAL

2 16V
2

402 2 NOSTUFF
RT7404

R7459 1 C7432 1 PP5V_S0_CPU_VCORE_VCC 1

R7424 1 R7481 X7R-CERM
402 R74261
0.1UF 91 15 13 11 10 7 PP1V05_S0_VCCIO NOSTUFF
67
9.53K 11.3K 1 C7411
0603

1.47K 10K 1%
1%
1/16W
10%
16V R7479 1 FS=300KHZ
1%
1/16W 5% 1/16W 0.1UF
10%
X7R-CERM 2 100K MF-LF 1/16W MF-LF 16V
MF-LF
402 2 402 1 C7426 5% FS=350KHZ 2 402
MF-LF
2 402
402 2 2 X7R-CERM
402
0.1UF 1/16W
XW7402
1

10% MF-LF
0.2 MM
SHORT-12L-0.25MM-SM 2 16V
X7R-CERM
402 2
0.2 MM 1 2 402
VR_CPU_TMN
0.25 MM 0.25 MM
PPVCORE_S0_CPU 0.2 mm 0.2 mm
15 13 10 7
91 68 50
SM 0.2 mm 0.25 MM R7466 R74541
1 2 VR_CPU_VSNS_XW_P 1
1K 2
SIGNAL_MODEL=EMPTY

11.8K
1 C7427
VOLTAGE=1.1V R7467 1% 0.082UF
10%
5% 10 VR_CPU_VSEN 1/16W
1/16W 1 2 MF-LF 2 16V
XW7423 R7468 MF-LF
402 5%
402 2 CERM-X7R
402
A 0.25 MM
1
0 2 VR_CPU_VSNS_R_P
0.2 mm
1/16W
0.25 MM
MF-LF
402
SIGNAL_MODEL=EMPTY

NOSTUFF SYNC_MASTER=J40I SYNC_DATE=11/23/2010 A

5% PAGE TITLE
81 13 IN CPU_VCCSENSE_P 0.2 mm 1/16W C7458 1
CPU_VCCSENSE_N
MF-LF
402 0.0022UF
10%
VR - CPU VCORE & GPU CONTROLLER
81 13 IN 50V
SIGNAL_MODEL=EMPTY DRAWING NUMBER SIZE
CERM 2
0.25 MM R7469 0.2 mm 0.25 MM R7470 402
Apple Inc. 051-8768 D
0.2 mm 1
0 2 VR_CPU_VSNS_R_N
1
10 2 VR_CPU_RGND REVISION
R
5% 5% 9.0.0
XW7433 1/16W
MF-LF
1/16W
MF-LF
1 C7459 1 C7460 NOTICE OF PROPRIETARY PROPERTY: BRANCH
SM 402 R7471 402 0.0022UF 0.0022UF
10% THE INFORMATION CONTAINED HEREIN IS THE
1K 10%
1 2 VR_CPU_VSNS_XW_N1 2
2 50V 2 50V
CERM
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
VOLTAGE=0V CERM 402
5% 402 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 74 OF 512
0.2 mm 0.25 MM 1/16W II NOT TO REPRODUCE OR COPY IT
MF-LF SHEET
402 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 67 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
CRITICAL
L7500
0.47UH-17.5A
70 69 66 64 51 6
PP12V_G3H_CPUDDR 1 2 PP12V_S0_CPU_FLTRD 67 68
MAKE_BASE=TRUE
67 64 62 61 48 42 41 24 23 7
PP5V_S0 PCMB063T-MMD06CZ-SM VOLTAGE=12.0V
MIN_LINE_WIDTH=0.6 mm1
91 80 71 70 69 68

C7580 1 C7581 1 MIN_NECK_WIDTH=0.25 mm C7511 1 C7507 1 C7510

1
C7505 1
C7506 1
C7515 1
C7526
MAX_NECK_LENGTH=3 MM 0.1UF 39UF 39UF 39UF 39UF
0.01UF 1UF 10% 1UF 0.001UF 20% 20% 20% 20%
R7505 1 10%
50V 2
10%
35V 2
DIDT=TRUE 2 25V
X5R
10%
2 35V
10%
2 50V
2 16V
POLY
2 16V
POLY
2 16V
POLY
2 16V
POLY
X7R X5R 402 X5R CERM SM SM SM SM
2.2 402 603 603 402
5% 2
1/10W CRITICAL
MF-LF

D
PHASE 1 603 2
VR_CPU_DRV1_PVCC
0.2 mm 0.5 MM
VR_CPU_BOOT1_RC
0.2 mm 0.5 MM
Q7503
RJK0230DPA
WPAK
CRITICAL
L7501 D
1
1 C7501 0.36UH-20%-40A-0.00075OHM
1UF 1 PPVCORE_S0_CPU

7
10% R7504 DIDT=TRUE
7 1 2 7 10 13 15 50 67 68 91
VCC 2 16V 0 PIMA104E-SM-1
U7501
X5R
402 5% C7503 1 1 2
1/16W
MF-LF 0.22UF R7506 2
ISL6620A 402 2
DIDT=TRUE
10%
16V 6 2.2 XW7501 XW7502
QFN CERM 2 5%
1/10W
SM
SM
VR_CPU_PWM1 VR_CPU_DRV1_BOOT 0.5 MM 402 MF-LF
67 IN 4 PWM BOOT 2 0.2 mm 1
2 603 0.2 mm 0.5 MM 1
CRITICAL VR_CPU_DRV1_UGATE DIDT=TRUE VR_CPU_ISNS1_N_R
9 EN UGATE 1 0.2 mm 0.5 MM 3 4 5 VR_CPU_PH1_SNUB 0.2 mm 0.2 MM VR_CPU_ISNS1_POUT 67
VR_CPU_PHASE1 SWITCH_NODE=TRUE DIDT=TRUE 0.2 mm 0.5 MM 0.2 mm 0.2 MM
PHASE 10 DIDT=TRUE SIGNAL_MODEL=EMPTY
NC 3 NC
VR_CPU_DRV1_LGATE 0.2 mm 0.5 MM DIDT=TRUE
1 C7508 R75011 1 C7509
NC 8 NC LGATE 6 0.001UF 5.76K 0.1UF
10% 1% 10%
THRML 2 50V
CERM
1/16W
MF-LF 2 16V
GND PAD 402 X7R-CERM
402 2 402

11
VR_CPU_ISNS1_NOUT 67

PP12V_S0_CPU_FLTRD 67 68

PP5V_S0 1 C7530
67 64 62 61 48 42 41 24 23 7
91 80 71 70 69 68
0.1UF
1 C7582 1 C7531
10% 1UF 0.001UF
R7525 1 2 25V
X5R
10% 10%
402 2 35V
X5R 2 50V
CERM
2.2
C 5%
1/10W
MF-LF
2
CRITICAL
Q7523
603 402
C
603 2 VR_CPU_BOOT2_RC
VR_CPU_DRV2_VCC RJK0230DPA CRITICAL
L7521
PHASE 2 0.5 MM
0.2 mm 1 C7521
1UF
10%
R75241
0
DIDT=TRUE
0.2 mm 0.5 MM
1

7
WPAK
0.36UH-20%-40A-0.00075OHM
1 2
PPVCORE_S0_CPU
5

VCC
2 16V
X5R 5% C7523 1 PIMA104E-SM-1
7 10 13 15 50 67 68 91

402 1/16W 0.22UF 2

MF-LF 10%
U7521 2

www.teknisi-indonesia.com
402 2 16V
ISL6609 DIDT=TRUE
CERM 2
402
6 1
R7526 XW7521
SM XW7522
QFN1 0.5 MM 2.2 SM
VR_CPU_PWM2 VR_CPU_DRV2_BOOT 0.2 mm 5% 1
67 2 PWM BOOT 1 1/10W 1
IN MF-LF
CRITICAL
VR_CPU_DRV2_UGATE0.2 mm 0.5 MM DIDT=TRUE 3 4 5 2 603 0.2 mm 0.5 MM VR_CPU_ISNS2_N_R
UGATE 8 VR_CPU_ISNS2_P
OUT 67
6 EN DIDT=TRUE VR_CPU_PH2_SNUB 0.2 mm 0.2 MM 0.2 mm 0.2 MM
VR_CPU_PHASE2 SWITCH_NODE=TRUE 0.2 mm 0.5 MM SIGNAL_MODEL=EMPTY
PHASE 7
DIDT=TRUE DIDT=TRUE R75211 1 C7520
VR_CPU_DRV2_LGATE 0.2 mm 0.5 MM 1 C7528 5.76K 0.1UF
LGATE 4 1% 10%
0.001UF 1/16W
THRML 10% MF-LF 2 16V
X7R-CERM
GND PAD 2 50V
CERM
402 2 402
402 VR_CPU_ISNS2_N
3

67
9

OUT

B B

OUTPUT BULK OPTION: 6X 270UF/9MOHM/B2 CASE

PPVCORE_S0_CPU 7 10 13 15 50 67 68 91

CRITICAL CRITICAL CRITICAL CRITICAL

CRITICAL 1 CRITICAL 1 1 1
1
C7560 C7561 1
C7562 C7563 C7564 C7565
270UF 270UF 270UF 270UF 36A TDC, 1.9 MOHM LL
270UF 20% 270UF 20% 20% 20%
20% 2 2V 20% 2 2V 2 2V 2 2V
2V
2 TANT TANT 2V
2 TANT TANT TANT TANT
CASE-B4-SM CASE-B4-SM CASE-B4-SM CASE-B4-SM
CASE-B4-SM CASE-B4-SM

A SYNC_MASTER=J40I SYNC_DATE=11/23/2010 A
PAGE TITLE

VR - CPU VCORE OUTPUT PHASES

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
75 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 68 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

AXG PHASE (22A AVG/33A PEAK, 3.9MOHM LL)

D D

CRITICAL
L7602
0.47UH+/-20%-12MOHM-7A
PP12V_S0_AXG_FLTRD 1 2 PP12V_G3H_CPUDDR 6 51 64 66 68 70
MAKE_BASE=TRUE PIMB042T-COMBO
VOLTAGE=12V
MIN_LINE_WIDTH=0.6 mm CRITICAL CRITICAL
CRITICAL MIN_NECK_WIDTH=0.25 mm
1
1 C7615 1 C7607 1 C7610 C7633 1 C7634 1
67 64 62 61 48 42 41 24 23 7
PP5V_S0 C7651 CRITICAL CRITICAL MAX_NECK_LENGTH=3 MM 1UF 0.1UF 0.001UF 0.01UF 1UF
91 80 71 70 68 39UF 1
C7652 1
C7653 DIDT=TRUE 10% 10% 10% 10% 10%
20%
39UF 39UF 2 35V
X5R 2 25V
X5R 2 50V
CERM
50V 2
X7R
35V 2
X5R
R7601 16V
2 POLY
20% 20% 603 402 402 402 603
SM 2 16V 2 16V
1 2.2 POLY POLY
5% SM SM
1/10W
MF-LF
2 603 2
CRITICAL
VR_AXG_DRV1_PVCC CRITICAL
VR_AXG_BOOT1_RC 0.2MM 0.5MM
Q7603 R7620
MIN_NECK_WIDTH=0.2MM DIDT=TRUE RJK0230DPA CRITICAL 0.001
MIN_LINE_WIDTH=0.5MM
VOLTAGE=12V
1 C7601 1 WPAK L7601 1%
1W
1UF R76041 0.36UH-20%-40A-0.00075OHM MF-1 PPVAXG_S0_CPU 7 13 16 50 67
10% 0612
16V
2 X5R 0 7 1 2 PPVAXG_S0_CPU_RS 2 1 NOSTUFF
402 5% 1 C7603 VOLTAGE=1V CRITICAL CRITICAL CRITICAL CRITICAL
7

1/16W 0.22UF PIMA104E-SM-1 MIN_LINE_WIDTH=0.6MM 4 3

VCC MF-LF
402 2 10% MIN_NECK_WIDTH=0.3MM 1
C7620 1
C7621 1
C7622 1
C7635 1 C7623
2 16V 270UF 270UF 270UF 270UF 0.001UF
U7601 CERM 6 10%
C ISL6620A
QFN 0.5MM
402 1
R7606
2.2
20%
2 2V
TANT
CASE-B4-SM
20%
2 2V
TANT
CASE-B4-SM
20%
2 2V
TANT
CASE-B4-SM
20%
2 2V
TANT
CASE-B4-SM
2 50V
CERM
402
C
VR_AXG_PWM 0.2MM 5%
67 4 PWM BOOT 2 VR_AXG_DRV1_BOOT 1/10W
IN DIDT=TRUE MF-LF
3 4 5 VR_AXG_ISNS_N_R
2 603 0.2MM 0.5MM
9 EN UGATE 1 VR_AXG_DRV1_UGATE 0.2MM 0.5MM 0.2MM 0.2MM
DIDT=TRUE VR_AXG_PH1_SNUB
NC 3 NC
PHASE 10 VR_AXG_PHASE1 0.2MM 0.5MM
DIDT=TRUE DIDT=TRUE R76081
1K
NC
8 NC LGATE 6 VR_AXG_DRV1_LGATE 0.2MM 0.5MM 1 C7608 1%
DIDT=TRUE 1/16W

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SIGNAL_MODEL=EMPTY
THRML 0.001UF MF-LF
GND PAD
10%
2 50V
402 2 C7602
CERM 0.001UF
5

11

402 1 2

10% VR_AXG_ISNS_P 67
50V OUT
CERM
402
VR_AXG_ISNS_N 67
OUT

B B

A SYNC_MASTER=J40S SYNC_DATE=12/15/2010 A
PAGE TITLE

VR - GPU
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
76 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 69 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

CPU VCCIO (1.05V S0) REGULATOR @ 18A/22A

69 68 66 64 51 6 PP12V_G3H_CPUDDR

67 64 62 61 48 42 41 24 23 7 PP5V_S0
91 80 71 69 68

R77011 1
R7702
2.2 2.2
5% 5%
1/16W 1/10W
MF-LF MF-LF CPUVCCIOS0_VBST_RC CRITICAL CRITICAL
402 2 2 603 MIN_LINE_WIDTH=0.5 MM 1 1 1 C7722
1 C7724
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
C7720 C7721 0.001UF
0.1UF
39UF 39UF 10%
PP5V_U7700_PVCC 1
R7730 20% 20% 10%
50V 2 25V
X5R
VOLTAGE=5V 2 16V 2 16V 2 CERM 402
MIN_LINE_WIDTH=0.5 MM 0 POLY
SM
POLY
SM 402
MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 mm 5%
MIN_NECK_WIDTH=0.1 MM 1/16W
MAX_NECK_LENGTH=10MM MF-LF
CPU_VCCIOSENSE_P
PP5V_S0_CPUVCCIOS0_VCC
MIN_LINE_WIDTH=0.5 MM
C7701 1 2 402
1 C7730
81 13
2.2UF 0.22UF
C MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V 10% 10% C

13

14
81 13 CPU_VCCIOSENSE_N 16V 2 2 16V
X5R CERM
MIN_LINE_WIDTH=0.2 MM 603 CPUVCCIOS0_VBST 402
VCC PVCC
MIN_NECK_WIDTH=0.1 MM 1
MAX_NECK_LENGTH=10MM R7744 U7700 MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm 2
3.01K CRITICAL
1 1% ISL95870 DIDT=TRUE CRITICAL
R7704 1/16W Q7730
3.01K
MF-LF
CPUVCCIOS0_EN 3 UTQFN
BOOT 12 RJK0214DPA CRITICAL
R7740
1% 2 402 62 IN EN
CPUVCCIOS0_DRVH 0.001
1/16W
MF-LF
<Ra> 0.2 MM
0.2 mm CPUVCCIOS0_FB 6 FB
CRITICAL
UGATE 11
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm 1 WPAK2 L7730 1%
1W
0.68UH-22A-2.7MOHM

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402 2 GATE_NODE=TRUE MF-1
4 DIDT=TRUE 0612 PP1V05_S0
CPUVCCIOS0_SREF SREF PHASE 10 CPUVCCIOS0_LL 7 1 2 PPCPUVCCIO_S0_REG_R 1 2 7 24 46 50 62 76
MIN_LINE_WIDTH=0.5 MM PIMB104T-SM MIN_LINE_WIDTH=0.6 mm 3 4
8 MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
CPUVCCIOS0_VO VO LGATE 15 SWITCH_NODE=TRUE VOLTAGE=1.05V
DIDT=TRUE

CPUVCCIOS0_OCSET 7 CPUVCCIOS0_DRVL 6 CRITICAL CRITICAL CRITICAL

OCSET
MIN_LINE_WIDTH=0.5 MM R7731 C7723 1 1
C7725 1
C7726 1
C7727 1
R7760
9 PGOOD MIN_NECK_WIDTH=0.2 mm 2.2 CPUVCCSAS0_SNUB 0.001UF 270UF 270UF 270UF
62 OUT CPUVCCIOS0_PGOOD GATE_NODE=TRUE 2 1
10% 200
DIDT=TRUE
DIDT=TRUE MIN_LINE_WIDTH=0.5 MM 50V 20% 20% 20% 5%
0.2 MM 2 RTN 5% CERM 2 2 2V 2 2V 2 2V 1/10W
0.2 mm CPUVCCIOS0_RTN 3 4 5 1/10W MIN_NECK_WIDTH=0.2 MM 402 TANT TANT TANT MF-LF
MF-LF CASE-B4-SM CASE-B4-SM CASE-B4-SM
603 2 603
CPUVCCIOS0_FSEL 5 FSEL
R77051 1
R7745 GND PGND
2.74K 2.74K 1
R7703 1 C7731 MINIMUM LOAD REQUIRED.

16
1% 1%
1/16W
MF-LF
1/16W
MF-LF
C7702 1 0 0.001UF
402 2 1UF 10% Vout = 1.05V
2 402 10% 5%
1/16W 2 50V
<Rb> 16V 2 MF-LF CERM 18A MAX OUTPUT
X5R 402
402 2 402
NOSTUFF NOSTUFF f = 300 kHz
C7704 1 1 C7705 1 C7703
1000PF 1000PF 0.047UF
5% 5% 10%
25V
NP0-C0G 2 2 25V
NP0-C0G 2 16V
X7R XW7700
SM
402 402 402
B CPUVCCIOS0_AGND
MIN_LINE_WIDTH=0.6 mm
1 2
MIN_LINE_WIDTH=0.2
MIN_NECK_WIDTH=0.2
MM
mm CPUVCCIOS0_CS_P OUT 50 89 B
MIN_NECK_WIDTH=0.2 mm PLACE_NEAR=U7600.1:1mm MIN_LINE_WIDTH=0.2 MM
VOLTAGE=0V 1 MIN_NECK_WIDTH=0.2 mm CPUVCCIOS0_CS_N OUT 50 89
R7741
3.01K
1% SIGNAL_MODEL=EMPTY
1/16W
MF-LF
402 2 C7740
1000PF
2 1

5%
25V 1
NP0-C0G
402
R7742
3.01K
1%
1/16W
MIN_LINE_WIDTH=0.2 MM MF-LF
(CPUVCCIOS0_OCSET) MIN_NECK_WIDTH=0.2 mm 2 402
MIN_LINE_WIDTH=0.2 MM
(CPUVCCIOS0_VO) MIN_NECK_WIDTH=0.2 mm

OCP = R7641 x 8.5uA / R7640

OCP = 25.6A NOM/21.3A MIN
Vout = 0.5V * (1 + Ra / Rb)

A SYNC_MASTER=J40I SYNC_DATE=12/02/2010 A
PAGE TITLE

VR - 1.05V S0
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
77 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 70 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

1.8V S0 SWITCHER @ 1.7A/2A

D D
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27
PP3V3_S0
91 89 79 77 76 74 73 72 67

CRITICAL
C7860 1 C7867 1 C7861 1 L7860
10UF 10UF 0.1UF 1.0UH-2.1A-50MOHM
10% 10% 10%
16V 16V 16V

16
X5R-CERM 2 X5R-CERM 2 X7R-CERM 2

1
2
SW_1V8S0 1 2 PP1V8_S0
0805 0805 402 0.5 MM
7 15 18 21 23 26 71

0.2 mm 2520
VIN
DIDT=TRUE R7863 1 1 C7863 1 C7862 1 C7873
U7860
SWITCH_NODE=TRUE
10 0.001UF 22UF 22UF
1% 10% 20% 20%
TPS54218 1 C7866 1/16W
MF-LF
2 50V
CERM 2 6.3V
X5R-CERM1 2 6.3V
X5R-CERM1
62 IN P1V8S0_EN 15 EN QFN PH_0 10 0.1UF 402 2 402 0603 0603
10%
14 CRITICAL PH_1 11 16V
2 X7R-CERM
62 OUT P1V8S0_PGOOD PWRGD SNS_1V8S0
PH_2 12 402
6 0.5 MM 0.2 MM
FB_1V8S0 VSENSE 0.2 mm 0.2 mm
9 BOOT 13BOOT_1V8S0 DIDT=TRUE
1
R7862
R7865 SS_1V8S0 SS
24.9K
18.2K1 7 RT/CLK 8 RT_1V8S0 1%
COMP_RC_1V8S0 2 COMP_1V8S0 COMP 1/16W
0.2 MM 0.2 mm 0.2 MM MF-LF
0.2 mm 1% 2 402
1/16W
C7865 1 MF-LF
402
C7864 1 GND AGND THRM_PAD
1
R7860
NOSTUFF 0.0022UF 118K 0.2 MM
0.0068UF 10%

3
4

17
1% 0.2 mm
10%
25V C7868 1 50V
CERM 2 1/16W 1
CERM 2
402
100PF
5%
402 MF-LF
2 402
R7861
50V 20.0K
CERM 2 0.5 MM
1%
1/16W
402 XW7801 0.2 mm F=1.5MHZ MF-LF
C 1
SM
2
2 402 C
AGND_1V8S0 AGND_1V8S0 AGND_1V8S0

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1.5V S0 @ 0.3A/0.5A
B B
R7870
PP5V_S0 2
10 1 VDD_1V5S0
67 64 62 61 48 42 41 24 23 7
91 80 70 69 68
1% 0.5 MM
1/16W
MF-LF 0.2 mm
402
C7870 1 PP1V5_S0 7 17 21 23 39 53 72 91
0.1UF
10%
16V
U7870
TPS72015
1 C7872
X7R-CERM 2 0.5 MM 10uF
402 SON 20%
4 BIAS 0.2 mm 2 6.3V
X5R
603
71 26 23 21 18 15 7 PP1V8_S0 6 IN OUT 1
3 EN CRITICAL NC 2
NC
C7871 1 THRM
10uF GND PAD
20%
6.3V 2 5 7
X5R
603

62 IN P1V5S0_EN

A SYNC_MASTER=REFERENCE_MLBSYNC_DATE=11/23/2010 A
PAGE TITLE

VR - MISC DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
78 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 71 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

C C
SPRINKLE THESE CAPS SOMEWHAT EVENLY AROUND THE PLANES AND ROUTES FOR THESE RAILS.

91
78 65 60 51 41 6 PP12V_G3H
61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0
47 41 40 39 38 37 34 31 30 27
89 79 77 76 74 73 71 67 62 1 C7950 1 C7951 1 C7952 1 C7953

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1
R7920 0.01UF
10%
0.01UF
10%
0.01UF
10%
0.01UF
10%
1.5K
1% 2 50V
X7R 2 50V
X7R 2 50V
X7R
50V
2 X7R
1/16W 402 402 402 402
MF-LF
CRITICAL 2 402
PSU_TEMP OUT 46 91
J7900 91 66 61 32 31 30 28 6 PP1V5_S3
78048-0972
M-RT-SM 1 C7920 1 C7962 1 C7963
1 0.01UF 0.01UF 0.01UF
10% 10% 10%
2 2 50V
X7R 2 50V
X7R 2 50V
X7R
3 402 402 402
4
5
6 PP12V_G3H_PSU 6 51 91
7 91 71 53 39 23 21 17 7 PP1V5_S0
8 1 C7900 1 C7901 1 C7902 1 C7970 1 C7971 1 C7972 1 C7973
9 0.1UF 0.1UF 1UF
10% 10% 10% 0.01UF 0.01UF 0.01UF 0.01UF
2 25V
X5R 2 25V
X5R 2 35V
X5R
10% 10% 10% 10%
402 402 603 2 50V
X7R 2 50V
X7R 2 50V
X7R 2 50V
X7R
402 402 402 402
B B
518S0739
PLACE CAPS AS CLOSE TO J7900 AS POSSIBLE.
BEST IF VIAS ARE AFTER THE CAPS.

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

PSU CONNECTOR, MISC CAPS

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
79 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 72 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

C C

www.teknisi-indonesia.com
46 OUT
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27

SMC_GFX_OVERTEMP
91 89 79 77 76 74 72 71 67
PP3V3_S0

R8001
1
10K
5%
1/20W
MF
201
2

I1
46 IN =SMC_GFX_THROTTLE_L MAKE_BASE=TRUE TP_GFX_THROTTLE_L

B R8000 B
SMC_GPU_HI_ISENSE 1
10K 2
46 OUT
5%
1/20W
MF
201

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

NO GPU GLUE
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
80 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 73 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
CRITICAL

PCIE_T29_R2D_C_P<0> C9000 1 2 OMIT_TABLE C9040 1 2 PCIE_T29_D2R_P<0>

84 8 IN OUT 8 84
PCIE_T29_R2D_P<0> V19 V21 PCIE_T29_D2R_C_P<0>
0.1UF 10% 16V X7R-CERM
402 84
T19
PER_0_P U9000 PET_0_P
T21
84
0.1UF 10% 16V X7R-CERM
402
PCIE_T29_R2D_N<0> PER_0_N PET_0_N PCIE_T29_D2R_C_N<0>
84 8 IN PCIE_T29_R2D_C_N<0> C9001 1 2
84
T29 84
C9041 1 2 PCIE_T29_D2R_N<0> OUT 8 84
10% 16V X7R-CERM
402 FCBGA 10% 16V X7R-CERM
402
0.1UF 0.1UF
(SYM 1 OF 2)
84 8 PCIE_T29_R2D_C_P<1> C9002 1 2 C9042 1 2 PCIE_T29_D2R_P<1> 8 84

PCIE GEN2
IN PCIE_T29_R2D_P<1> P19 P21 PCIE_T29_D2R_C_P<1> OUT
10% 16V X7R-CERM
402 84 PER_1_P PET_1_P 84 10% 16V X7R-CERM
402
0.1UF M19 M21 0.1UF
PCIE_T29_R2D_N<1> PER_1_N PET_1_N PCIE_T29_D2R_C_N<1>
C9003 84 84
C9043

RECEIVE

TRANSMIT
84 8 PCIE_T29_R2D_C_N<1> 1 2 1 2 PCIE_T29_D2R_N<1> 8 84
IN OUT
10% 16V X7R-CERM
402 10% 16V X7R-CERM
402
0.1UF 0.1UF
84 8 IN PCIE_T29_R2D_C_P<2> C9004 1 2
10% 16V X7R-CERM
402 84 PCIE_T29_R2D_P<2> K19 PER_2_P PET_2_P K21 84 PCIE_T29_D2R_C_P<2>
C9044 1 2 PCIE_T29_D2R_P<2>
10% 16V X7R-CERM
402
OUT 8 84

D 84 8 IN PCIE_T29_R2D_C_N<2>
0.1UF
C9005 1 2
84 PCIE_T29_R2D_N<2> H19 PER_2_N PET_2_N H21 84 PCIE_T29_D2R_C_N<2>
C9045
0.1UF
1 2 PCIE_T29_D2R_N<2> OUT 8 84
D
10% 16V X7R-CERM
402 10% 16V X7R-CERM
402
0.1UF 0.1UF
84 8 IN PCIE_T29_R2D_C_P<3> C9006 1 2
10% 16V X7R-CERM
402 84 PCIE_T29_R2D_P<3> F19 PER_3_P PET_3_P F21 84 PCIE_T29_D2R_C_P<3>
C9046 1 2 PCIE_T29_D2R_P<3>
10% 16V X7R-CERM
402
OUT 8 84

0.1UF D19 D21 0.1UF

PCIE_T29_R2D_N<3> PER_3_N PET_3_N PCIE_T29_D2R_C_N<3>
84 8 IN PCIE_T29_R2D_C_N<3> C9007 1 2
10% 16V X7R-CERM
402
84 84
C9047 1 2 PCIE_T29_D2R_N<3>
10% 16V X7R-CERM
402 OUT 8 84

0.1UF 0.1UF
NO STUFF PP3V3_T29
TP_T29_MONDC0 R9010 1 2 T29_MONDC0 B21 MONDC0 F1 T29_PCIE_WAKE_L R9051 2 1
17 20 26 74 75 76

0 5% 1/16W MF-LF 402 WAKE*

DEBUG: For monitoring current/voltage
10K 5% 1/16W MF-LF 402
TP_T29_MONDC1 R9011 1 2 T29_MONDC1 A20 MONDC1 E6 T29_RESET_L
0 5% 1/16W MF-LF 402 PERST* IN 76

NO STUFF
RSENSE E14 T29_RSENSE
TP_T29_MONOBSP C9015 1 2 T29_MONOBSP
10% 16V X7R-CERM
402
K17 MONOBSP
CRITICAL
DEBUG: For monitoring clock 0.1UF
TP_T29_MONOBSN C9016 1 2 T29_MONOBSN M17 MONOBSN R90551
10% 16V X7R-CERM
402 1.0K
0.1UF 0.5%
76 75 74 26 20 17 PP3V3_T29 1/16W
MF-LF
603 2

RBIAS E16 T29_RBIAS

C9090 1 R90921 R90231 1
R9022 1
R9021
R90901 1
R9091 1UF
10% 3.3K 10K 10K 10K
3.3K 3.3K 10V 2 5% 5% 5% 5%

POWER ON RESET
5% 5% X5R 1/16W 1/16W 1/16W 1/16W Not used in host mode.
1/16W 1/16W 402-1 MF-LF MF-LF MF-LF MF-LF K1
MF-LF MF-LF 402 2 402 2 2 402 2 402 PCIE_RST_0* NC_T29_PCIE_RESET0_L 91
402 2 2 402

CLK REQUEST
8 J2 NC_T29_PCIE_RESET1_L
P3 PCIE_RST_1* 91
VCC 76 OUT T29_CLKREQ_ISOL_L PCIE_CLKREQ_0* K3
CRITICAL 1 N4 PCIE_RST_2* NC_T29_PCIE_RESET2_L 91
R9093 T29_GPIO<1> PCIE_CLKREQ_1* J4
(T29_SPI_MOSI) 5 D U9090 Q 2 (T29_SPI_MISO) M3 PCIE_RST_3* NC_T29_PCIE_RESET3_L 91
M95320-RMB6TG
3.3K T29_GPIO<2> PCIE_CLKREQ_2*
C (T29_SPI_CLK) 6 C MLP
5%
1/16W T29_RSVD L4 PCIE_CLKREQ_3* TDI T3 JTAG_ISP_TDI IN 20
PP3V3_T29 C

MISC
MF-LF R4 17 20 26 74 75 76
JTAG_T29_TMS

JTAG
1 OMIT_TABLE 2 402 T29_SPI_MOSI P1 TMS IN 17
(T29_SPI_CS_L) S_L 86 EE_DI R2 JTAG_ISP_TCK

EEPROM
M1 TCK IN 20
1
86 T29_SPI_MISO EE_DO T1 R9098
T29ROM_WP_L 3 W_L N2 TDO JTAG_ISP_TDO OUT 20
86 T29_SPI_CS_L EE_CS* 10K
L2 5%
T29ROM_HOLD_L 7 HOLD_L 86 T29_SPI_CLK EE_CLK REFCLK_100_IN_P H17 PCIE_CLK100M_T29_P IN 17 84 1/16W
G16 MF-LF
VSS THM A2 REFCLK_100_IN_N PCIE_CLK100M_T29_N IN 17 84
2 402 R9095
PAD TP_T29_THERMDP THERM_DP
806

CLOCKS
Use B1 GND ball for THERM_DN P17
4 9 XTAL_25_IN SYSCLK_CLK25M_T29_R 1 2 SYSCLK_CLK25M_T29

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E4 IN 26
T29_TEST_EN TEST_EN

TEST PORT
XTAL_25_OUT R16 TP_T29_XTAL25OUT 1%
TP_T29_TEST_POINT_0 P5 TEST_POINT_0 1/16W
1
R9025 TP_T29_TEST_POINT_1 N6 TEST_POINT_1 TMU_CLK_OUT U2 T29_TMU_CLK_OUT R90961 MF-LF
402
M5 E2 1K
0 TP_T29_TEST_POINT_2 TEST_POINT_2 TMU_CLK_IN T29_TMU_CLK_IN 5%
5% L6 1/16W
1/16W T29_TEST_POINT_3 TEST_POINT_3 NO STUFF MF-LF
MF-LF 402 2
2 402 R90991
10K
5%
AA4 1/16W
R90291 83 74 DP_T29SNK0_ML_P<3>
Y3
DPSNK0_ML_LANE_3P MF-LF
402 2
0 83 74 DP_T29SNK0_ML_N<3> DPSNK0_ML_LANE_3N
SNK0 AC Coupling 5%
1/16W AA6
MF-LF DP_T29SNK0_ML_P<2> DPSNK0_ML_LANE_2P
83 8 IN DP_T29SNK0_ML_C_P<0> C9020 1 2
10% 16V
DP_T29SNK0_ML_P<0> 74 83 402 2
83 74

83 74 DP_T29SNK0_ML_N<2> Y5 DPSNK0_ML_LANE_2N
0.1UF

SINK PORT 0
X7R-CERM
402
83 8 IN DP_T29SNK0_ML_C_N<0> C9021 1 2 DP_T29SNK0_ML_N<0> 74 83 83 74 DP_T29SNK0_ML_P<1> AA8 DPSNK0_ML_LANE_1P
10% 16V Y7 AA18
0.1UF 402
X7R-CERM 83 74 DP_T29SNK0_ML_N<1> DPSNK0_ML_LANE_1N DPSRC0_ML_LANE_3P NC_DP_T29SRC_ML_CP<3> 91

DPSRC0_ML_LANE_3N Y17 NC_DP_T29SRC_ML_CN<3>

83 8 IN DP_T29SNK0_ML_C_P<1> C9022 1 2
10% 16V
DP_T29SNK0_ML_P<1> 74 83 83 74 DP_T29SNK0_ML_P<0> AA10 DPSNK0_ML_LANE_0P
91

0.1UF 402
X7R-CERM 83 74 DP_T29SNK0_ML_N<0> Y9 DPSNK0_ML_LANE_0N DPSRC0_ML_LANE_2P AA16 NC_DP_T29SRC_ML_CP<2> 91

83 8 IN DP_T29SNK0_ML_C_N<1> C9023 1 2 DP_T29SNK0_ML_N<1> 74 83

DP_T29SNK0_AUXCH_P V1 DPSRC0_ML_LANE_2N Y15 NC_DP_T29SRC_ML_CN<2> 91

SOURCE PORT 0
10% 16V 83 74 DPSNK0_AUX_CHP
0.1UF X7R-CERM
402 W2 AA14
B 83 74 DP_T29SNK0_AUXCH_N DPSNK0_AUX_CHN DPSRC0_ML_LANE_1P NC_DP_T29SRC_ML_CP<1> 91
B

DISPLAY
83 8 IN DP_T29SNK0_ML_C_P<2> C9024 1 2
10% 16V
DP_T29SNK0_ML_P<2> 74 83
83 8 DP_T29SNK0_HPD V5 DPSNK0_HOT_PLUG_DET
DPSRC0_ML_LANE_1N Y13 NC_DP_T29SRC_ML_CN<1> 91

0.1UF OUT
X7R-CERM
402 AA12
DPSRC0_ML_LANE_0P NC_DP_T29SRC_ML_CP<0>
83 8 IN DP_T29SNK0_ML_C_N<2> C9025 1 2 DP_T29SNK0_ML_N<2> 74 83
Y11
91

0.1UF 10% 16V

X7R-CERM
402 R90301 V9
DPSRC0_ML_LANE_0N NC_DP_T29SRC_ML_CN<0> 91

100K 91 NC_DP_T29SNK1_MLP<3> DPSNK1_ML_LANE_3P W16

5% DPSRC0_AUX_CHP NC_DP_T29SRC_AUXCH_CP
83 8 IN DP_T29SNK0_ML_C_P<3> C9026 1 2
10% 16V
DP_T29SNK0_ML_P<3> 74 83 1/16W
MF-LF
91 NC_DP_T29SNK1_MLN<3>
U8 DPSNK1_ML_LANE_3N
DPSRC0_AUX_CHN U16 NC_DP_T29SRC_AUXCH_CN
91

91
0.1UF 402
X7R-CERM 402 2 V11 100pF SRF > 40MHz
NC_DP_T29SNK1_MLP<2> DPSNK1_ML_LANE_2P
83 8 IN DP_T29SNK0_ML_C_N<3> C9027 1 2
10% 16V
DP_T29SNK0_ML_N<3> 74 83
91

91 NC_DP_T29SNK1_MLN<2>
U10 DPSNK1_ML_LANE_2N
DPSRC0_HOT_PLUG_DET V3 PD_DP_T29SRC_HPD
BYPASS=U9000.Y19::2MM
0.1UF

SINK PORT 1
402
X7R-CERM
V13 Y19 BYPASS=U9000.Y19::5.08MM
91 NC_DP_T29SNK1_MLP<1> DPSNK1_ML_LANE_1P DP_ATEST T29_DP_ATEST
83 8 BI DP_T29SNK0_AUXCH_C_P C9028 1 2
10% 16V
DP_T29SNK0_AUXCH_P 74 83 91 NC_DP_T29SNK1_MLN<1>
U12 DPSNK1_ML_LANE_1N DP_RES_0 Y21
0.1UF 402
X7R-CERM
NC_DP_T29SNK1_MLP<0> V15 DPSNK1_ML_LANE_0P
DP_RES_1 AA20 T29_DP_RES C9085 1 1 C9086
83 8 BI DP_T29SNK0_AUXCH_C_N C9029 1 2
10% 16V
DP_T29SNK0_AUXCH_N 74 83
91

91 NC_DP_T29SNK1_MLN<0> U14 DPSNK1_ML_LANE_0N

100PF
5%
0.01UF
10%
0.1UF 1 1 50V 2 50V
X7R-CERM
402
V7
R9085 R9032 CERM 2
402
X7R
402
91 NC_DP_T29SNK1_AUXCHP DPSNK1_AUX_CHP 14.0K 100K
U6 1% 5%
91 NC_DP_T29SNK1_AUXCHN DPSNK1_AUX_CHN 1/16W 1/16W
MF-LF MF-LF
U4 402 2 2 402
PD_DP_T29SNK1_HPD DPSNK1_HOT_PLUG_DET

R90311
100K A6 A14
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 5% 91 NC_T29_R2D_CP0 PRT0_T29T_P PRT2_T29T_P T29_R2D_C_P<0> OUT 77 86
47 41 40 39 38 37 34 31 30 27 1/16W A4 A12
91 89 79 77 76 73 72 71 67
MF-LF 91 NC_T29_R2D_CN0 PRT0_T29T_N PRT2_T29T_N T29_R2D_C_N<0> OUT 77 86
R90411 R90401 402 2

PORT2
PORT0
2.2K 2.2K 91 NC_T29_D2RP0 C4 PRT0_T29R_P PRT2_T29R_P C12 T29_D2R_P<0> 77 86
IN

PORTS
5% 5% C2 C10
1/16W 1/16W 91 NC_T29_D2RN0 PRT0_T29R_N PRT2_T29R_N T29_D2R_N<0> IN 77 86
MF-LF MF-LF
402 2 402 2 J6 G4
T29_LSEO_LSOE0 T29_LSEO<0>
A 8 OUT DP_T29SNK0_CTRL_CLK K5
T29_0_LSEO
T29_0_LSOE
T29_2_LSEO
T29_2_LSOE H3 T29_LSOE<0>
OUT
IN
77

77 SYNC_MASTER=J40S SYNC_DATE=12/01/2010 A
8 OUT DP_T29SNK0_CTRL_DATA PAGE TITLE

91 NC_T29_R2D_CP1 A10 PRT1_T29T_P PRT3_T29T_P A18 T29_R2D_C_P<1> OUT 77 86 T29 Host (1 of 2)

91 NC_T29_R2D_CN1 A8 PRT1_T29T_N PRT3_T29T_N A16 T29_R2D_C_N<1> 77 86 DRAWING NUMBER SIZE
OUT
051-8768 D
PORT1

PORT3
91 NC_T29_D2RP1 C8 PRT1_T29R_P PRT3_T29R_P C16 T29_D2R_P<1> IN 77 86 Apple Inc. REVISION
91 NC_T29_D2RN1 C6 PRT1_T29R_N PRT3_T29R_N C14 T29_D2R_N<1> 77 86 R
IN
9.0.0
PULL-UPS ON THESE SIGNALS ENABLE PORT ON PCH. T29_LSEO_LSOE1 G6 T29_1_LSEO T29_3_LSEO G2 T29_LSEO<1> 77 NOTICE OF PROPRIETARY PROPERTY: BRANCH
OUT
H5 T29_1_LSOE T29_3_LSOE H1 T29_LSOE<1> 77 THE INFORMATION CONTAINED HEREIN IS THE
IN
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
86 49 BI I2C_T29_SDA F3 T29_SDA NOTE: All unused LSOE/EO pairs should be aliased I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
90 OF 512
86 49 I2C_T29_SCL F5 T29_SCL together. Other signals okay to float (TP/NC). SHEET
OUT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 74 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D CRITICAL
PP3V3_T29 17 20 26 74 76 D
135 mA (Single-Port)
76 PP1V05_T29 OMIT_TABLE 152 mA (Dual-Port)
2100 mA (Single Port) H9 VCC1P0 U9000 VCC3P3 H7 C9144 1 C9143 1 C9145 1 1 C9146 1 C9147 EDP: 200 mA
2250 mA (Dual Port) H11 VCC1P0 VCC3P3 M7 1UF 1UF 1UF 10UF 10UF
T29 10% 10% 10% 20% 20%
EDP: 3000 mA C9100 1 1 C9105 1 C9106 1 C9107 1 C9108 1 C9109 H13 VCC1P0 FCBGA VCC3P3 K7 10V 2
X5R
10V 2
X5R
10V 2
X5R 2 6.3V
X5R 2 6.3V
X5R
10UF 1UF 1UF 1UF 1UF 1UF K9 VCC1P0 (SYM 2 OF 2) 402-1 402-1 402-1 603 603
20% 10% 10% 10% 10% 10% VCC3P3_T29 G10
6.3V 2 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R K11 VCC1P0
X5R VCC3P3_T29 G12
603 402-1 402-1 402-1 402-1 402-1 K13 VCC1P0
M9
M11
VCC1P0 R9150
VCC1P0 P7 PP3V3_T29_DP 1
0 2
M13 VCC3P3_DP_RX1
VCC1P0 R6 MIN_LINE_WIDTH=0.4 mm
VCC3P3_DP_RX1 MIN_NECK_WIDTH=0.2 mm 5%
C9101 1 1 C9110 1 C9111 1 C9112 1 C9113 1 C9114 H15 VCC1P0_PE C9153 1 C9152 1 C9151 1 C9150 1 VOLTAGE=3.3V 1/16W
MF-LF
0-ohms are placeholders for now, replace
10UF 1UF 1UF 1UF 1UF 1UF VCC3P3_DP_TXRX P9 402 with proper values after characterization.

VCC
20% 10% 10% 10% 10% 10% K15 VCC1P0_PE 1UF 1UF 1UF 1UF
6.3V 2 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R VCC3P3_DP_TXRX P11 10% 10% 10% 10%
X5R M15 VCC1P0_PE 10V 2 10V 2 10V 2 10V 2
603 402-1 402-1 402-1 402-1 402-1 X5R X5R X5R X5R
E8 VCC1P0_PE 402-1 402-1 402-1 402-1
E10 VCC1P0_PE
E12 VCC1P0_PE
G14
R9120 VCC1P0_PE R9160
0 R8 P13 0
1 2 PP1V05_T29_VDD_DP VDD1P0_DP_RX1 VDD3P3DP_PLL PP3V3_T29_PLL 1 2
MIN_LINE_WIDTH=0.4 mm R10 MIN_LINE_WIDTH=0.4 mm
5% MIN_NECK_WIDTH=0.2 mm VDD1P0_DP_TXRX MIN_NECK_WIDTH=0.2 mm 5%
1/16W VOLTAGE=1.05V VOLTAGE=3.3V 1/16W
MF-LF
402
1 C9120 1 C9121 1 C9122 R12 VDD1P0_DP_TXRX C9160 1 MF-LF
402
1UF 1UF 1UF 2.2UF
10% 10% 10% 20%
2 10V 2 10V 2 10V 6.3V 2

teknisi-indonesia
X5R X5R X5R CERM
402-1 402-1 402-1 402-LF

C L9130 L9170
C
FERR-120-OHM-1.5A FERR-120-OHM-1.5A
1 2 PP1V05_T29_VDD_DPPLL R14 VDD1P0_DP_PLL VCC3P3_DP_TXRXBIAS P15 PP3V3_T29_DPBIAS 1 2
0402 MIN_LINE_WIDTH=0.4 mm MIN_LINE_WIDTH=0.4 mm 0402
MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V VOLTAGE=3.3V
1 C9130 C9170 1
2.2UF G8 VSS VSSDP T5 2.2UF
20% 20%
2 6.3V J8 VSS VSSDP T7 6.3V 2

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CERM CERM
402-LF J10 VSS VSSDP T9 402-LF
J12 VSS VSSDP T11
J14 VSS VSSDP T15
L8 VSS VSSDP T17
L10 VSS VSSDP V17
L12 VSS VSSDP W4
L14 VSS VSSDP W6
N8 VSS VSSDP W8
N10 VSS VSSDP W10
N12 VSS VSSDP W12
N14 VSS VSSDP W14
VSSDP Y1
VSSDP AA2
B1 VSSPE
VSSDP_PLL T13
B3 VSSPE

GND
B5 VSSPE VSSPE F9
B7 VSSPE VSSPE F11
B9 VSSPE VSSPE F13
B11 F15
B B13
VSSPE
VSSPE
VSSPE
VSSPE F17 B
B15 VSSPE VSSPE G18
B17 VSSPE VSSPE G20
B19 VSSPE VSSPE J16
C18 VSSPE VSSPE J18
C20 VSSPE VSSPE J20
D1 VSSPE VSSPE L16
D3 VSSPE VSSPE L18
D5 VSSPE VSSPE L20
D7 VSSPE VSSPE N16
D9 VSSPE VSSPE N18
D11 VSSPE VSSPE N20
D13 VSSPE VSSPE R18
D15 VSSPE VSSPE R20
D17 VSSPE VSSPE U18
E18 VSSPE VSSPE U20
E20 VSSPE VSSPE W18
F7 VSSPE VSSPE W20

A SYNC_MASTER=J40S SYNC_DATE=11/23/2010 A
PAGE TITLE

T29 Host (2 of 2)
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
91 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
Current numbers from Vendor slide (<REDACTED> power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.
IV ALL RIGHTS RESERVED 75 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Page Notes 1
OMIT
1
OMIT
1
OMIT

Power aliases required by this page: S9200 S9201 S9202

- =PPVIN_SW_T29BST (8-13V Boost Input) SM OMIT SM OMIT SM
- =PP18V_T29_REG (18V Boost Output) 1 1
- =PP3V3_T29_P3V3T29FET (3.3V FET Input) SHLD-K66-EMI-FRAME-CAN-MAIN-TOP S9203 SHLD-K66-EMI-FRAME-CAN-MAIN-TOP S9204 SHLD-K66-EMI-FRAME-CAN-MAIN-TOP
- =PP3V3_T29_FET (3.3V FET Output) SM SM
OMIT OMIT OMIT
- =PP3V3_S0_T29PWRCTL
- =PP1V05_T29_P1V05T29FET (1.05V FET Input) 1 1 1
SHLD-K66-EMI-FRAME-CAN-MAIN-TOP SHLD-K66-EMI-FRAME-CAN-MAIN-TOP
- =PP1V05_T29_FET (1.05V FET Output) S9205 S9206 S9207
SM OMIT SM OMIT SM
Signal aliases required by this page: 1 1
SL9202
D - =T29_CLKREQ_L
- =T29_RESET_L 1
TH-SP SHLD-K66-EMI-FRAME-CAN-MAIN-TOP S9208
SM
SHLD-K66-EMI-FRAME-CAN-MAIN-TOP S9209
SM
SHLD-K66-EMI-FRAME-CAN-MAIN-TOP D
OMIT OMIT OMIT
SL-1.0X0.63-1.4X1.0
BOM options provided by this page: 1 1 1
SL9203 SHLD-K66-EMI-FRAME-CAN-MAIN-TOP SHLD-K66-EMI-FRAME-CAN-MAIN-TOP
T29BST:Y - Stuffs 18V boost circuitry. TH-SP S9210 S9211 S9212
1 SM OMIT SM OMIT SM
SL-1.0X0.63-1.4X1.0 1 1
SHLD-K66-EMI-FRAME-CAN-MAIN-TOP S9213 SHLD-K66-EMI-FRAME-CAN-MAIN-TOP S9214 SHLD-K66-EMI-FRAME-CAN-MAIN-TOP
SM SM
OMIT OMIT OMIT
1 1 1
SHLD-K66-EMI-FRAME-CAN-MAIN-TOP SHLD-K66-EMI-FRAME-CAN-MAIN-TOP
S9215 S9216 S9217
SM OMIT SM OMIT SM
1 1
SHLD-K66-EMI-FRAME-CAN-MAIN-TOP S9218 SHLD-K66-EMI-FRAME-CAN-MAIN-TOP S9219 SHLD-K66-EMI-FRAME-CAN-MAIN-TOP
SM SM
OMIT OMIT OMIT
1 1 1
Supervisor & CLKREQ# Isolation SHLD-K66-EMI-FRAME-CAN-MAIN-TOP SHLD-K66-EMI-FRAME-CAN-MAIN-TOP
S9220 S9221 S9222
SM OMIT SM OMIT SM
1 1
SHLD-K66-EMI-FRAME-CAN-MAIN-TOP S9223 SHLD-K66-EMI-FRAME-CAN-MAIN-TOP S9224 SHLD-K66-EMI-FRAME-CAN-MAIN-TOP
SM SM
91
OMIT OMIT OMIT
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 1 1 1
47 41 40 39 38 37 34 31 30 27
89 79 77 76 74 73 72 71 67 SHLD-K66-EMI-FRAME-CAN-MAIN-TOP SHLD-K66-EMI-FRAME-CAN-MAIN-TOP
S9225 S9226 S9227
SM OMIT SM OMIT SM
1 C9200 1 1
0.1UF SHLD-K66-EMI-FRAME-CAN-MAIN-TOP S9228 SHLD-K66-EMI-FRAME-CAN-MAIN-TOP S9229 SHLD-K66-EMI-FRAME-CAN-MAIN-TOP
C 10%
2 25V
X5R
SM SM C
402 PP3V3_T29 17 20 26 74 75 76
R92151 SHLD-K66-EMI-FRAME-CAN-MAIN-TOP SHLD-K66-EMI-FRAME-CAN-MAIN-TOP
10K 1
CRITICAL R9207
1

5%
1/16W
MF-LF VDD 100K
Platform (PCIe) Reset 402 2 5%

=PLT_RST_T29_GPU
U9200 1/16W
MF-LF
27 IN SLG4AP016V 2 402

www.teknisi-indonesia.com
TDFN PP1V05_T29 75 76
R9203 2

+ SENSE
2
10K - 0.7V
5%
1/16W
MF-LF
402 1 DLY
Open-Drain GPIO
RESET* 4 T29_RESET_L OUT 74
20 IN T29_SW_RESET_L 3 MR*
DLY = 60 ms +/- 20% TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

6 EN TABLE_5_ITEM

806-2254 1 FRAME,EMI SHIELD,TB,J40 SH9200 CRITICAL ?

17 OUT T29_CLKREQ_L 8 OUT
(OD) IN 7 T29_CLKREQ_ISOL_L IN 74
MAKE_BASE=TRUE
Pull-up provided by SB page. THRM
GND PAD
5

78 77 IN T29_A_BIAS R9221 51 1 2 T29_A_BIAS0P OUT 77

5% 1/20W
MF 201
R9222 51 1 2 T29_A_BIAS0N
B 3.3V T29 Switch DP/T29 Bias Filters 5% 1/20W
MF 201
OUT 77

B
Max Current = 1.7A (85C)
91
U9210 Prevents high-frequency coupling between 1.5K bias resistors.
C9221 1 2
10% 16V
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 TPS22924 PP3V3_T29 17 20 26 74 75 76 0.01UF X5R-CERM 0201
47 41 40 39 38 37 34 31 30 27 CSP
89 79 77 76 74 73 72 71 67 A2 A1 VOLTAGE=3.3V
DP_A_BIAS R9231 51 1 2 DP_A_BIAS0P
C9222 1 2
VIN VOUT MIN_LINE_WIDTH=0.5 MM 77 IN OUT 77 10% 16V
B2 B1 MIN_NECK_WIDTH=0.25 mm 5% 1/20W 0.01UF X5R-CERM 0201
MF 201
CRITICAL MAX_NECK_LENGTH=3 MM
R9228 51 1 2 DP_A_BIAS0N R9223 51 1 2 T29_A_BIAS1P
C9210 1 C2 ON 5%
MF
1/20W
201
OUT 77
5%
MF
1/20W
201
OUT 78

1UF GND
10%
10V 2 C9231 1 2 R9224 51 1 2 T29_A_BIAS1N OUT 78
C1

X5R 10% 16V 5% 1/20W

402-1 0.01UF X5R-CERM 0201 MF 201
C9228 1 2
10% 16V
C9223 1 2
10% 16V
0.01UF X5R-CERM 0201 0.01UF X5R-CERM 0201
R9230 51 1 2 DP_A_BIAS2P 77
C9224 1 2
10% 16V
OUT 0.01UF
5% 1/20W X5R-CERM 0201
MF 201
1.05V T29 Switch R9225 51 1 2 DP_A_BIAS2N OUT 77 R9226 51 1 2 T29_A_BIAS2P OUT 77
5% 1/20W 5% 1/20W
MF 201 MF 201
U9215 C9230 1 2 R9227 51 1 2 T29_A_BIAS2N
70 62 50 46 24 7 PP1V05_S0 TPS22924 PP1V05_T29 75 76 10% 16V 5% 1/20W OUT 77

A2
CSP
A1
0.01UF X5R-CERM 0201 MF 201
VOLTAGE=1.05V
B2 VIN VOUT B1 MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 mm
C9225 1 2
10% 16V
C9226 1 2
10% 16V
0.01UF X5R-CERM 0201 0.01UF X5R-CERM 0201
C9215 1 CRITICAL MAX_NECK_LENGTH=3 MM
C9227 1 2
1UF C2 ON 10% 16V
10% 0.01UF X5R-CERM 0201
10V 2 GND
X5R Max Current = 3.4A (85C)
402-1
C1

U9210 & U9215/U9216

Part TPS22924C
T29_PWR_EN
A 20 IN
Type Load Switch SYNC_MASTER=J40S SYNC_DATE=11/23/2010 A
R92101 U9216 R(on) 18 mOhm Typ
PAGE TITLE

100
5%
TPS22924
CSP 50 mOhm Max
T29 Power Support
1/16W A2 A1 DRAWING NUMBER SIZE
MF-LF
402 2 B2 VIN VOUT B1 Max Output: 2A per IC
Apple Inc. 051-8768 D
CRITICAL REVISION
R
T29_PWR_EN_U2916 C2 ON U3816.A2: PLACE_NEAR=U3815.B2:3 mm 9.0.0
GND NOTICE OF PROPRIETARY PROPERTY: BRANCH
Pull-up provided by SB page.
C1

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
92 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 76 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
76 IN T29_A_BIAS0P
83 8 IN DP_EXTA_ML_C_P<0> C9300 1 2 DP_EXTA_ML_P<0> 77 83
GND_VOID=TRUE
C9370
VOLTAGE=3.3V
1 2
T29 A High-Speed Signals
10% 16V (C9370/C9371)
0.1UF X7R-CERM
402 86 74 OUT T29_D2R_N<0> 20% 4V T29_D2R_C_P<0> IN 78 86
0.47UF CERM-X5R-1
83 8 IN DP_EXTA_ML_C_N<0> C9301 1 2
10% 16V
DP_EXTA_ML_N<0> 77 83 86 74 OUT T29_D2R_P<0>
C9371 1 2 201
SIGNAL_MODEL=EMPTY
T29_D2R_C_N<0> IN 78 86

0.1UF X7R-CERM
402 OVERSIZE_PAD=0.875 mm^2 20% 4V GND_VOID=TRUE D9364 1 2
0.47UF CERM-X5R-1 5% 1/20W (D9364.2)
(Both L’s) 201 1.5K 1
R9372
2
MF 201 BAR90-02LRH TSLP-2-7
GND_VOID=TRUE

(C9372)
83 8 IN DP_EXTA_ML_C_P<1> C9302 1 2
10% 16V
DP_EXTA_ML_P<1> 77 83
L9372 1 2 C9372 2
GND_VOID=TRUE
1 BEAD_PROBE D9372 1 2 T29: TX_0
0.1UF X7R-CERM
402 86 74 IN T29_R2D_C_N<0> 1.0NH+/-0.1NH 0201-1 86 T29_R2D_C_F_N<0> 20% 4V 86 T29_R2D_P<0> BAR90-02LRH TSLP-2-7 T29DPA_ML_C_P<0> OUT 78 86
0.47UF
CERM-X5R-1
83 8 IN DP_EXTA_ML_C_N<1> C9303 1 2
10% 16V
DP_EXTA_ML_N<1> 77 83 86 74 IN T29_R2D_C_P<0>
L9373 1 2 86 T29_R2D_C_F_P<0>
C93731 2 201 86 T29_R2D_N<0>
GND_VOID=TRUE D9373 1 2 T29DPA_ML_C_N<0> OUT 78 86

0.1UF X7R-CERM
402 0201-1 BAR90-02LRH
1.0NH+/-0.1NH 0.47UF 20% 4V
CERM-X5R-1 1.5K 1 2 BEAD_PROBE TSLP-2-7
GND_VOID=TRUE (D9372/D9373)
(C9373) GND_VOID=TRUE 201 5% 1/20W
MF 201
R9373 D9365 1 2 (D9365.2)
83 8 DP_EXTA_ML_C_P<2> C9304 1 2 DP_EXTA_ML_P<2> 77 83 T29 signals are 76 T29_A_BIAS0N BAR90-02LRH TSLP-2-7
GND_VOID=TRUE

D
IN
0.1UF 10% 16V
X7R-CERM
402
P/N-swapped after AC
IN
VOLTAGE=3.3V
T29_A_BIAS2P
SIGNAL_MODEL=EMPTY
CRITICAL GND_VOID=TRUE D
83 8 IN DP_EXTA_ML_C_N<2> C9305 1 2 DP_EXTA_ML_N<2> 77 83
76 IN
VOLTAGE=3.3V T29 Path (All 4 D’s) R9374 1.5K 1 2
10% 16V 5% 1/20W
0.1UF X7R-CERM
402 caps to improve layout. Biasing MF 201
GND_VOID=TRUE D9372/D9373: SIGNAL_MODEL=T29PIN
R9375 1.5K 1 2
(C9380/C9381) D9364/D9365: SIGNAL_MODEL=EMPTY GND_VOID=TRUE 5% 1/20W
MF 201
83 8 IN DP_EXTA_ML_C_P<3> C9306 1 2 DP_EXTA_ML_P<3> 77 83
T29_D2R_N<1>
C9380 1 2
T29_D2R_C_P<1>
10% 16V
0.1UF X7R-CERM
402
86 74 OUT 0.47UF 20% 4V
CERM-X5R-1 IN 78 86
86
T29_D2R_P<1> 201 T29_D2R_C_N<1>
83 8 IN DP_EXTA_ML_C_N<3> C9307 1 2 DP_EXTA_ML_N<3> 77 83
PP3V3_S0
77 79 89 91
50 51 52 53 57
74 OUT C9381 1 2 SIGNAL_MODEL=EMPTY
IN 78 86

0.1UF 10% 16V

X7R-CERM
402 R9309 1 2
6 7 13 17 18 19 20 21 23 24 27
30 31 34 37 38 39 40 41 47 49
58 60 61 62 67 71 72 73 74 76
OVERSIZE_PAD=0.875 mm^2 20% 4V
0.47UF CERM-X5R-1 GND_VOID=TRUE
5% 1/20W
R9382 D9360 1 2 GND_VOID=TRUE (D9360.2)
(Both L’s) 201 1.5K 1 2
MF 201 BAR90-02LRH TSLP-2-7
1M 5% 1/16W (C9382) GND_VOID=TRUE
MF-LF 402
L9382 1 2 C9382 2 1 D9382 1 2 T29: TX_1
83 8 BI DP_EXTA_AUXCH_C_P C9308 1 2
10% 16V
DP_EXTA_AUXCH_P 77 83 86 74 IN T29_R2D_C_N<1> 1.0NH+/-0.1NH 0201-1 86 T29_R2D_C_F_N<1>
0.47UF 20% 4V
CERM-X5R-1
86 T29_R2D_P<1> BEAD_PROBE
BAR90-02LRH TSLP-2-7 T29DPA_ML_C_P<2> OUT 78 86

0.1UF X7R-CERM
402 T29_R2D_C_P<1> 86 T29_R2D_C_F_P<1> 201 86 T29_R2D_N<1> D9383 T29DPA_ML_C_N<2>
DP_EXTA_AUXCH_C_N C9309 1 2 DP_EXTA_AUXCH_N
86 74 IN L9383 1 2 C93831 2 GND_VOID=TRUE BEAD_PROBE 1 2 OUT 78 86

83 8 BI
10% 16V
77 83 1.0NH+/-0.1NH 0201-1
0.47UF 20% 4V
CERM-X5R-1 1.5K 1 2 BAR90-02LRH TSLP-2-7
GND_VOID=TRUE (D9382/D9383)
0.1UF X7R-CERM
402 R9308/R9309 maintain bias on C9308/C9309 (C9383) 201 5% 1/20W D9361
R9308 1 2 GND_VOID=TRUE
T29_A_BIAS2N MF 201
R9383 1 2 GND_VOID=TRUE (D9361.2)
If GPU uses common pins for AUX_CH 1M 5% 1/16W to prevent spikes when U9310 AUXDDC_OFF 76 IN BAR90-02LRH TSLP-2-7
MF-LF 402 VOLTAGE=3.3V SIGNAL_MODEL=EMPTY GND_VOID=TRUE
and DDC, alias nets together at GPU. transitions from high to low. CRITICAL R9384 1.5K 1 2
(All 4 D’s) 5% 1/20W
R9354 30 1 2
DP_SDRVA_ML_R_P<0>
C9364 1 2
DP_SDRVA_ML_P<0> R9385
GND_VOID=TRUE
1.5K 1 2 MF 201
5% 1/20W 86 20% 6.3V 86 SIGNAL_MODEL=T29PIN
MF 201 0.22UF X5R 0201 5% 1/20W
R9355 DP_SDRVA_ML_R_N<0> DP_SDRVA_ML_N<0> (D9382/D9383) MF 201
30 1 2
86
C9365 1 2
86

91
DP A Super-Driver 5%
MF
1/20W
201 0.22UF 20%
X5R
6.3V
0201
SIGNAL_MODEL=EMPTY

(D9360/D9361)
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 R9350 30 1 2
DP_SDRVA_ML_R_P<2>
C9360 1 2
DP_SDRVA_ML_P<2>
47 41 40 39 38 37 34 31 30 27 5% 1/20W 86 20% 6.3V 86
89 79 77 76 74 73 72 71 67
MF 201 0.22UF X5R 0201 DP Path Biasing
DP_SDRVA_ML_R_N<2> DP_SDRVA_ML_N<2>
C9310 1 1 C9311 1 C9312 R9351 30 1 2
86
C9361 1 2
86
SIGNAL_MODEL=EMPTY
2.2UF 0.1UF 0.1UF 5% 1/20W 20% 6.3V R9361 1.5K
0.22UF DP_A_BIAS2N

21
40
MF 201 X5R 0201 1 2 IN 76
20% 10% 10% SIGNAL_MODEL=EMPTY
5% 1/20W VOLTAGE=3.3V
6.3V 2 16V 2 16V 1 1
CERM 2
402-LF
X7R-CERM
402
X7R-CERM
402 VDD
R9352 R9353 R9360
1.5K 1 2 MF
201
DP_A_BIAS2P IN 76
PS8301 I2C Addresses: 270 270 5% 1/20W VOLTAGE=3.3V
C A1 A0 Addr (W/R)
U9310
PS8301TQFN40GTR-A2
5%
1/20W
MF
201 2
5%
1/20W
MF
91
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6
47 41 40 39 38 37 34 31 30 27
89 79 77 76 74 73 72 71 67
PP3V3_S0
R9365
1.5K 1 2
MF
SIGNAL_MODEL=EMPTY
201
DP_A_BIAS0N
C
0 0 0x96/0x97 2 201 SIGNAL_MODEL=EMPTY
5% 1/20W VOLTAGE=3.3V IN 76

0 1 0xB6/0xB7
QFN C9359 1 R9364
1.5K 1 2 MF 201
DP_A_BIAS0P
83 77 DP_EXTA_ML_P<0> 1 IN_D0P CRITICAL OUT_D0P 30 86 DP_SDRVA_ML_C_P<0> 0.1UF 5% 1/20W VOLTAGE=3.3V
IN 76

1 0 0x94/0x95 10% CRITICAL MF 201

DP_EXTA_ML_N<0> 2 IN_D0N OUT_D0N 29 DP_SDRVA_ML_C_N<0> 16V
83 77 86
X7R-CERM 2
1 1 0xB4/0xB5
C9363 1 2 402 5 U9359
74LVC1G04DBDCK
See Bill C. for layout-specific guidelines for DP_A_BIAS.
83 77 DP_EXTA_ML_P<1> 4 IN_D1P OUT_D1P 28 86 DP_SDRVA_ML_C_P<1> 10% 16V
Note: Other Parade 0.1UF X7R-CERM
402 77 DP_A_PWRDWN 2 4 DP_A_BIAS 76
DP_EXTA_ML_N<1> 5 IN_D1N 27 DP_SDRVA_ML_C_N<1> OUT
OUT_D1N
devices use 96/B6,
83 77 86
C9362 1 2 SC70

www.teknisi-indonesia.com
10% 16V 3
so only 94/B4 are 83 77 DP_EXTA_ML_P<2> 7 IN_D2P OUT_D2P 25 86 DP_SDRVA_ML_C_P<2> 0.1UF X7R-CERM
402 1 C9358
used for this part. 83 77 DP_EXTA_ML_N<2> 8 IN_D2N OUT_D2N 24 86 DP_SDRVA_ML_C_N<2>
C9367 IC supports input 10%
0.1UF DP/T29 A Low-Speed MUX
9 IN_D3P 23
1 2 2 16V
X7R-CERM
83 77 DP_EXTA_ML_P<3> OUT_D3P 86 DP_SDRVA_ML_C_P<3> 10% 16V high while Vcc = 0V. 402 47 38 35 34 33 28 25 20 19 6 PP3V3_S4
NOSTUFF 10 IN_D3N 22 0.1UF X7R-CERM
402 91 78 77 61 50 49
DP_EXTA_ML_N<3> OUT_D3N DP_SDRVA_ML_C_N<3> Must be 3.3V DP A port power
R9311 1 1
R9310
83 77 86
C9366 1 2
10% 16V
1K 1K DP_EXTA_DDC_CLK 14 IN_SCL AC_AUXP 20 86 DP_SDRVA_AUXCH_C_P 0.1UF X7R-CERM
402
5%
1/16W
5%
1/16W
83 77 8 IN
DP_EXTA_DDC_DATA 13 IN_SDA AC_AUXN 19 86 DP_SDRVA_AUXCH_C_N
1 C9390 1 C9391
MF-LF MF-LF
83 77 8 BI 0.1UF 0.1UF
10% 10%

29
20
16
12
402 2 2 402 AUXCH Snoop Port,
2 16V 2 16V

9
3
83 77 DP_EXTA_AUXCH_P 16 IN_AUXP OUT_AUXP_SCL 18 (DP_SDRVA_AUXCH_P) 1 X7R-CERM X7R-CERM
83 77 DP_EXTA_AUXCH_N 15 IN_AUXN OUT_AUXN_SDA 17 (DP_SDRVA_AUXCH_N)
used by PS8301
31
R9399 402 402
1 during training. 86 DP_SDRVA_ML_N<3> DIN1_0+ VDD 100K
R9312 DP_EXTA_HPD 3 IN_HPD OUT_HPD 31 (DP_SDRVA_HPD) DP_SDRVA_ML_P<3> 30 DIN1_0- U9390
5%
1/16W
1K
83 77 8 OUT (IPD)
C9369 1 2 86
MF-LF
5%
DPSDRVA_I2C_CTL_EN 26 I2C_CTL_EN 0.1UF 10% 16V
DP_SDRVA_ML_N<1> 27 CBTL04DP081A 2 402
1/16W (IPU) 32 X7R-CERM
402 86 DIN1_1+
MF-LF CA_DET DP_A_CA_DET HVQFN
2 402 DPSDRVA_I2C_ADDR0 36 I2C_ADDR0 (IPD)
IN 77
C9368 1 2
10% 16V
86 DP_SDRVA_ML_P<1> 26 DIN1_1- DOUT_0+ 1 T29DPA_ML_N<3> OUT 78 86

35 I2C_ADDR1 11 0.1UF X7R-CERM

402 19 DOUT_0- 2 T29DPA_ML_P<3> BI 78 86
DPSDRVA_I2C_ADDR1 (IPD) CEXT DPSDRVA_CEXT 86 DP_SDRVA_AUXCH_P AUX1+
18 T29: Unused
38 SCL_CTL PLACE_NEAR=U9310.11:2 mm 86 DP_SDRVA_AUXCH_N AUX1- CRITICAL
49 =I2C_DPSDRVA_SCL
IN
=I2C_DPSDRVA_SDA 37 SDA_CTL C9319 1 DP_SDRVA_HPD 17 HPD_1 DOUT_1+ 4 T29DPA_ML_N<1>
49 BI 2.2UF BI 78 86
20% CKPLUS_WAIVE=NdifPr_badTerm DOUT_1- 5 T29DPA_ML_P<1>
6.3V 2 78 86

B DP_EXTA_HPD OUT 8 77 83 DPSDRVA_REXT 12 REXT

39 AUXDDC_OFF
CERM
402-LF T29_A_RSVD_N 25
24
DIN2_0+ T29: LSX_A_R2P/P2R (P/N)
OUT
B
17 IN DP_AUXCH_ISOL (IPD) T29_A_RSVD_P DIN2_0-
1 OMIT_TABLEAUX+ 6 DP_A_EXT_AUXCH_P
R9302 DP_A_PWRDWN_R 34 PD (IPD) (T29_A_LSX_P2R) 23 DIN2_1+
BI 78 83 86

100K
5% SDRV_PD
91
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0 R93921 1
R9393 (T29_A_LSX_R2P) 22 DIN2_1-
AUX- 7 DP_A_EXT_AUXCH_N BI 78 83 86

1/16W 1 PS8301 has internal GND THMPAD 47 41 40 39 38 37 34 31 30 27 51 51 T29: RX_1 Bias Sink
MF-LF R9319 2
R9318 89 79 77 76 74 73 72 71 67

R9300 1
R9301 1 5% 5%
T29_D2R1_BIASP 15
6
33

41

2 402 4.02K 0 ~150K pull-down on PD 1/16W

MF-LF
1/16W
MF-LF
AUX2+
1% 5% pin. Okay to drive this 10K 10K 402 2 T29_D2R1_BIASN 14 HPD_IN 8 DP_A_EXT_HPD
1/16W 1/16W 5% 5% 2 402 AUX2- 77

MF-LF MF-LF pin even when VCC=0V per 1/16W 1/16W 13

402 2 402 MF-LF MF-LF NC HPD_2 1
1
Parade (pin is 5V-tolerant). 402 2 402 2 R9396 2 2
R9397 R9398
1K 1K 10 100K
Port A MCU DP_EXTA_DDC_CLK
DP_EXTA_DDC_DATA
BI
BI
8 77 83

8 77 83
5%
1/16W
MF-LF
5%
1/16W
MF-LF
77

78 77 76
DP_A_PWRDWN
T29_A_BIAS 32
GPU_SEL
AUX_SEL
LO=Port A
5%
1/16W
MF-LF
402 1 1
402 11 HI=Port B
2 402
NC
47 38 35 34 33 28 25 20 19 6 PP3V3_S4
91 78 77 61 50 49 Must be 3.3V DP A port power
CBTL04DP081A (353S3312) AND
PI3vEDP212 (353S3055) are THMPAD GND
22

1 C9330 1 C9331 1
5

R9338

33

28
21
footprint-compatible parts with SIGNAL_MODEL=T29DP_MUX
0.1UF 0.1UF 10K similar pinouts. NXP uses pin
CRITICAL VDD OMIT_TABLE 10% 10% 5%
16V
2 X7R-CERM 16V
2 X7R-CERM 1/16W 10 for ML and HPD, Pericom uses
DP_A_PWRDWN I2C Addr: MF-LF
77

0x26/0x27 (Wr/Rd)
U9330 402 402 402 2 pin 10 for ML and pin 11 for HPD.
See Bill C. for layout- LPC1112A
specific guidelines for DP_A_CA_DET 1 RESET#/PIO0_0 HVQFN25 16 T29DPA_CONFIG1_RC Note: U9390 ML/HPD defaults to T29 mode so that DP/T29
77 R/PIO1_0/AD1 IN 78

=T29_A_BIAS. 2 PIO0_1/CLKOUT R/PIO1_1/AD2 17 T29DPA_CONFIG2_RC IN 78

R9334 Display can detect host T29 support using I2C
10K
78 77 76 OUT T29_A_BIAS 74 IN T29_LSEO<0> 7 PIO0_2/SSEL/CT16B0_CAP0 R/PIO1_2/AD3 18 T29_A_HV_EN_R 1 2 T29_A_HV_EN OUT 78 pull-ups on ML<3>. U9390 AUX defaults to DP mode
(IPU) SWDIO/PIO1_3/AD4 19 T29_A_UC_ADDR 77 5% because 100-ohm pull-downs would defeat DP Sink’s
49 =I2C_T29AMCU_SCL 8 PIO0_4/SCL (OD) 1/16W
C9357 1 IN
=I2C_T29AMCU_SDA 9 PIO1_4/AD5/WAKEUP 20 DP_A_EXT_HPD 77 MF-LF
402
detection of DP Source.
0.1UF 49 BI PIO0_5/SDA (OD)
A =T29_WAKE_L: 10%
16V
X7R-CERM 2
78 IN T29DPA_HPD 10
11
PIO0_6/SCK PIO1_6/RXD 23 T29_A_LSX_P2R
T29_A_LSX_R2P
P2R = Plug to Receptacle
SYNC_MASTER=J40S SYNC_DATE=11/23/2010 A
Desktops use PCIe WAKE# 402 PIO0_7/CTS# PIO1_7/TXD 24 R2P = Receptacle to Plug PAGE TITLE
T29_LSOE<0> 12 PIO1_8/CT16B1_CAP0 6 T29_LSEO<1>
Mobiles use S4 WAKE#
74 OUT
T29_LSOE<1> 13
PIO0_8/MISO/CT16B0_MAT0 IN 74
DisplayPort/T29 A MUXing
74 OUT PIO0_9/MOSI/CT16B0_MAT1
DRAWING NUMBER SIZE
PCIE_WAKE_L 14 SWCLK/PIO0_10/SCK/CT16B0_MAT2 (OD) SMC_DP_HPD_L
91 38 35 18 OUT
T29_MCU_INT_L 15 Q9320
OUT 46 47
1
R9339 Apple Inc. 051-8768 D
OMIT 19 OUT R/PIO0_11/AD0 (OD) THRM XTALIN 4 1 1 1M
R93301 SWCLK VSS PAD R9335 R9336 SSM3K15FV D 3 5% R
REVISION
1K 10K SOD-VESM-HF 1/16W 9.0.0
21

25
3

0 5% 5% MF-LF
5% 1/16W 1/16W 2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
1/16W MF-LF MF-LF
MF-LF 2 402 2 402 THE INFORMATION CONTAINED HEREIN IS THE
402 2 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
SWDIO THE POSESSOR AGREES TO THE FOLLOWING: PAGE
1 G S 2
77 T29_A_UC_ADDR I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
93 OF 512
R9330 provides pads for programming/debug of MCU, please make accessible. III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
If project has space for 10-pin programming header it should be used. IV ALL RIGHTS RESERVED 77 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Nominal Min Max
IFLT 885mA 876mA 894mA (*)

3V3(DP)/2V9(T29) PORTA SUPPLY CRITICAL

12V T29 PORTA SUPPLY ILIM
TFLT
TSD
935mA 925mA 944mA (*)
18.3ms 13.4ms 26.7ms
470ms 235ms 724ms
66 65 61 45 44 43 28 6
PP5V_S4 D9401 12 VOLTS
91 78 POWERDI-123 CRITICAL (*) U9410 tolerance unknown
PP3V3R2V8_DPAPWR_D PP3V3R12V_SW_DPAPWR 12 WATTS MAX PER PORT
R94311 1
R9432 1 2 78
72 65 60 51 41 6
PP12V_G3H NOSTUFF
1.0
5%
1.0
5%
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
D9410
DSN2
1/4W 1/4W VOLTAGE=3.3V
DFLS260
MF-LF MF-LF P12V_T29 1 2 PP3V3R12V_SW_DPAPWR 78
1206 2 2 1206
1 C9422 1
R9421
10UF 20K NSR20F20NXXXG
10% 1/16W 5%
VRT29_VIN 2 16V MF-LF 402 1 1
R9450
VOLTAGE=5V X5R-CERM
C9423 1 C9424 1 C9425
D MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
CRITICAL 0805
2 330PF
1
R9424
11.5K
10UF
10%
10UF
10%
2.2K
5%
1/10W
1 CRITICAL 10
R9418
0
D
MAX_NECK_LENGTH=3 MM C9420 1 U9401 5% 50V 2
<RA> 1/16W 1%
MF-LF 402
2 25V
X5R 2 25V
X5R MF-LF 2
11
1 2
10UF 402 COG 805 805 2 603 1 3 VIN VOUT
10%
16V
ISL80101B
DFN 2
R9416 C9410 1 4
12 1 C9411 5%
1/10W
X5R-CERM 2 9 1 15.0K 0.1UF 0.1UF MF-LF
1% 603
0805
10 VIN VOUT 2 1/16W
MF-LF
10%
50V 2 U9410 10%
2 50V
402 2 X7R
603-1
SN1010017 X7R
603-1
7 ENABLE 3V3R2V8_DPAPWR_ADJ QFN
78 T29_DP_A_PWR_EN ADJ 3
6 SS DPAPWRSW_HVEN_L_R 16 EN* FLT* 15 TP_DPAPWRSW_FLT_L
3V3R2V8_SS_A NOSTUFF (IPU-Weak!)
PG 4 PP5V_S4 6 1 1
8 ISET 28 43 44 45 61 65 66 78 91 R9423 R9425 6 RTRY* ILIM 7 DPAPWRSW_ILIM
80101A_NC

THRM 2.05K 15.0K CRITICAL DPAPWRSW_CT

GND PAD
<RB2> <RB1> 1/16W1% NOSTUFF 9 CT IFLT 8 DPAPWRSW_IFLT
1 1/16W 1% MF-LF 402
R9422 GND THRM
5

11
MF-LF 402 D9403 3
R94171 PAD
1 C9421 100K 2 2
MMBZ5227BLT1H 1
R9412 R94101 1
R9411

5
13
14

17
0.022UF 1/16W 5% 13K
0 100K 174K

DP_A_PWRDWN_INV
10% MF-LF 402 SOT23 5%
1/16W 5% 1% 1%
2 16V
1
CERM-X5R 2 MF-LF 1/16W 1/16W 1/16W
402 402 2 MF-LF MF-LF MF-LF
1 PM_PGOOD_P3V3_2V8_A VO=0.5*(1+ RA/RB) 2 402 402 2 2 402
R9430 <CT> <RFLT> <RLIM>
25.5K
1/16W 1%
MF-LF 402
47 38 35 34 33 28 25 20 19 6
91 77 61 50 49
PP3V3_S4 VO=0.5*(1+ 1.18K/249)=2.87V
1 IFLT = 200k / RFLT = 885mA
2 R9426 Q9415
10K ILIM = 201k / RLIM = 935mA
5%
1/16W
SSM3K15FV D 3
MF-LF SOD-VESM-HF TFLT = CCT * 38900
3
2 402
DP_A_PWRDWN_FET_R D Q9420 TSD = CCT * 100000
6
2N7002DW-X-G
5 SOT-363
G S 1 G S 2
PP3V3_S5 6 17 18 19 20 21 23 24 25 27 28
D
Q9420
59 61 62 89 91 2N7002DW-X-G 4 77 IN T29_A_HV_EN
C 1 C9450 77 76
T29_A_BIAS
LO: 3V3 FOR DP
2 G S
SOT-363
C
0.1UF HI: 2V8 FOR T29 1
10%
2 50V
X7R
603-1
L9400
FERR-120-OHM-3A
5 78 PP3V3R12V_SW_DPAPWR 1 2 PP3V3R12V_SW_DPAPWR_F 91

T29_DP_PORTA_PWR_EN 1 MC74VHC1G08 MIN_LINE_WIDTH=0.38 MM 0603 MIN_LINE_WIDTH=0.38 MM

SC70-HF MIN_NECK_WIDTH=0.20 MM MIN_NECK_WIDTH=0.20 MM

www.teknisi-indonesia.com
24 19 IN
VOLTAGE=12V VOLTAGE=12V
U9420 4 T29_DP_A_PWR_EN 78 C9400 1
DisplayPort/T29 A Connector
65 62 IN PM_P5V_S4_PG 2 0.01UF
10%
50V 2
3 X7R
402
C9405
0.1UF
For J9400 T29 SMT pads GND_DPACONN_1 1 2 GND_VOID=TRUE
(3, 5, 17 & 19): MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V 10% (Both C’s) T29: TX_0
T29: RX_0 T29 Dir DP Dir DP Dir
GND_VOID=TRUE 6.3V

T29 Dir X5R

C9470 1 2
T29DPA_ML_C_P<0>
201 0.47UF 20% 4V
CERM-X5R-1
IN 77 86

T29_D2R_C_P<0> T29DPA_ML_P<0> 201 T29DPA_ML_C_N<0>

86 77 OUT
T29_D2R_C_N<0>
86

T29DPA_ML_N<0>
C9471 1 2 IN 77 86

0.47UF 20% 4V
86 77 86
OUT
GND_VOID=TRUE CERM-X5R-1
GND_VOID=TRUE GND_VOID=TRUE 201
R94941 1
R9495 BOT ROW TOP ROW C9406 1
GND_VOID=TRUE
1
GND_VOID=TRUE
1K 1K R9470 R9471
1% 1% R9403 TH PINS SM PINS 0.1UF
1/20W
MF
1/20W
MF 12 GND_VOID=TRUE
2 J9400 1 GND_DPACONN_7 1 2 470K
5%
470K
5%
201 2 1 2 GND_DPACONN_8 DP_HPD MINIDSPLYPRT-PL-J40 GND
2 201 MIN_LINE_WIDTH=0.38 MM 4 F-RT-TH 3 MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
1/20W
MF
1/20W
MF
5% MIN_NECK_WIDTH=0.20 MM CONFIG1 ML_LANE0P VOLTAGE=0V 10%
T29: Unused
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
1/20W VOLTAGE=0V 6 5 GND_VOID=TRUE 6.3V
2 201 2 201 T29: LSEO
MF CONFIG2 ML_LANE0N X5R
201 8 7 201
GND GND
86 77 BI T29DPA_ML_P<3> 10 ML_LANE3P ML_LANE1P
9 T29DPA_ML_P<1> IN 77 86
CRITICAL
B 86 77 BI T29DPA_ML_N<3> 12
14
ML_LANE3N
GND
ML_LANE1N
GND
11
13
T29DPA_ML_N<1> BI 77 86
B
R9404 GND_VOID=TRUE 16 AUX_CHP ML_LANE2P
15 T29: LSOE
76 IN T29_A_BIAS1P 12
1 2 GND_DPACONN_14 18 AUX_CHN ML_LANE2N
17
76 IN T29_A_BIAS1N 5%
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM 20 DP_PWR RETURN
19 GND_VOID=TRUE
R9407
1/20W
MF
VOLTAGE=0V
GND_DPACONN_13 1
12 2 GND_VOID=TRUE
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY CRITICAL 201 MIN_LINE_WIDTH=0.38 MM
1 1 L9498 SHIELD PINS MIN_NECK_WIDTH=0.20 MM 5% (Both C’s) T29: TX_1
R9498 R9499 650NH-5%-0.430MA-0.052OHM
VOLTAGE=0V 1/20W
MF C9472 1 2
2.2K 2.2K 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 201 T29DPA_ML_C_P<2>
5% 5% 2 1 GND_VOID=TRUE 0.47UF 20% 4V
CERM-X5R-1 IN 77 86

1/20W 1/20W T29DPA_ML_P<2> 201 T29DPA_ML_C_N<2>

MF
201 2
MF 0603
86

T29DPA_ML_N<2>
C9473 1 2 IN 77 86

2 201 86
0.47UF 20% 4V
GND_VOID=TRUE
D9498
GND_VOID=TRUE
1 2 SIGNAL_MODEL=EMPTY CERM-X5R-1
201
86 77 OUT T29_D2R_C_P<1> BAR90-02LRH TSLP-2-7 86 T29DPA_D2R1_AUXCH_P
GND_VOID=TRUE GND_VOID=TRUE
T29_D2R_C_N<1> D9499 86 T29DPA_D2R1_AUXCH_N
86 77 OUT
BAR90-02LRH
1 2
TSLP-2-7 (Both L’s) CRITICAL
L9408 1
R9472 1
R9473
FERR-120-OHM-3A 470K 470K
T29: RX_1 CRITICAL
GND_VOID=TRUE
L9499
650NH-5%-0.430MA-0.052OHM
514-0783 GND_DPACONN_19 1 2 5%
1/20W
5%
1/20W
SIGNAL_MODEL=T29PIN MIN_LINE_WIDTH=0.38 MM 0603 MF MF
2 1 MIN_NECK_WIDTH=0.20 MM 2 201 2 201
86 83 77 BI DP_A_EXT_AUXCH_P VOLTAGE=0V
GND_VOID=TRUE
86 83 77 BI DP_A_EXT_AUXCH_N 0603
R9408
SIGNAL_MODEL=EMPTY
1
12 2 470k R’s for ESD protection
1 C9498 1 C9499 5%
5%
30PF
5%
30PF R9402 1/20W
on AC-coupled signals.
12 MF
2 50V
CERM 2 50V
CERM 1 2 T29DPA_HPD_R 201
402 402 5%
1/20W
C9402 1 MF R9401
www.teknisi-indonesia.com
0.01UF 201
10% 12
16V DPACONN_20_RC 1 2
T29DPA_HPD X5R-CERM 2 MIN_LINE_WIDTH=0.38 MM
5% MM
A 77

77
OUT

T29DPA_CONFIG1_RC DP Source must pull

0201 MIN_NECK_WIDTH=0.20
VOLTAGE=12V 1/20W
MF
201
SYNC_MASTER=J40S SYNC_DATE=12/01/2010 A
OUT
down HPD input with
1
R9441 1 C9401 PAGE TITLE

77 OUT T29DPA_CONFIG2_RC 100K 0.01UF DisplayPort/T29 A Connector

greater than or equal 5% 10%
1/20W 2 16V
X5R-CERM DRAWING NUMBER SIZE
to 100K (DPv1.1a). MF
R94521 1
R9451 C9494 1 1 C9495 2 201
0201
Apple Inc. 051-8768 D
1M 1M 330PF 330PF REVISION
5% 5% Sink HPD range: R
1/20W
MF
1/20W
MF
10%
16V 2
10%
2 16V High: 2.0 - 5.0V
9.0.0
201 2 X7R X7R NOTICE OF PROPRIETARY PROPERTY:
2 201 201 201 Low: 0 - 0.8V
BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
94 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 78 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

ONE 0.1UF AND ONE 0.01UF CAP PER POWER PIN.

PP3V3_S0 50 51 52 53 57 58 60 61 62 67
6 7 13 17 18 19 20 21 23 24 27
30 31 34 37 38 39 40 41 47 49
71 72 73 74 76 77 79 89 91

C9740 1 C9741 1 C9742 1 C9743 1

0.1UF 0.01UF 0.1UF 0.01UF
10% 10% 10% 10%
16V 50V 2 16V 50V 2
X7R-CERM 2 X7R X7R-CERM 2 X7R
402 402 402 402

D D
C9744 1 C9745 1 C9746 1 C9747 1 C9748 1 C9749 1 C9750 1 C9751 1
0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF
10% 10% 10% 10% 10% 10% 10% 10%
PLACE DP CAPS NEXT TO U9740 16V 50V 2 16V 50V 2 16V 50V 2 16V 50V 2
X7R-CERM 2 X7R X7R-CERM 2 X7R X7R-CERM 2 X7R X7R-CERM 2 X7R
402 402 402 402 402 402 402 402
ALL CHANNELS ARE EQUIVALENT.
LANE SWAPPING AND POLARITY REVERSAL ARE ALLOWED.
83 8 IN HDMI_CLK_C_P C9711 1 2
10% 16V X7R-CERM 402
83 HDMI_CLK_LS_P HDMI_CLK_P OUT 80 83

0.1UF
83 8 IN HDMI_CLK_C_N C9710 1 2
10% 16V X7R-CERM 402
83 HDMI_CLK_LS_N HDMI_CLK_N OUT 80 83

15
21
26
40
46
0.1UF

2
83 8 IN HDMI_DATA_C_P<0> C9713 1 2
10% 16V X7R-CERM 402
83 HDMI_DATA_LS_P<0> VCC HDMI_DATA_P<0> OUT 80 83

0.1UF
83 8 HDMI_DATA_C_N<0> C9712 1 2 83 HDMI_DATA_LS_N<0> U9740 HDMI_DATA_N<0> 80 83
IN OUT
0.1UF 10% 16V X7R-CERM 402 PS8171
QFN
39 IN_D1+ CRITICAL OUT_D1+ 22
83 8 IN HDMI_DATA_C_P<1> C9715 1 2
10% 16V X7R-CERM 402
83 HDMI_DATA_LS_P<1> 38 IN_D1- OUT_D1- 23
HDMI_DATA_P<1> OUT 80 83

0.1UF 42 19
IN_D2+ OUT_D2+
83 8 IN HDMI_DATA_C_N<1> C9714 1 2
10% 16V X7R-CERM 402
83 HDMI_DATA_LS_N<1> 41 IN_D2- OUT_D2- 20
HDMI_DATA_N<1> OUT 80 83

0.1UF 45 16
IN_D3+ OUT_D3+
83 8 IN HDMI_DATA_C_P<2> C9717 1 2 83 HDMI_DATA_LS_P<2> 44 IN_D3- OUT_D3- 17 HDMI_DATA_P<2> OUT 80 83
10% 16V X7R-CERM 402
0.1UF 48 IN_D4+ OUT_D4+ 13
83 8 IN HDMI_DATA_C_N<2> C9716 1 2
10% 16V X7R-CERM 402
83 HDMI_DATA_LS_N<2> 47 IN_D4- OUT_D4- 14 HDMI_DATA_N<2> OUT 80 83

0.1UF
83 79 8 OUT HDMI_LS_HPD 7 HPDX HPD_SINK 30 HDMI_HPD IN 80

C 4 PIO C
83 79 8 BI HDMI_LS_SCL 9 SCL SCL_SINK 28 HDMI_DDC_CLK_5V BI 80

83 79 8 BI HDMI_LS_SDA 8 SDA SDA_SINK 29 HDMI_DDC_DATA_5V BI 80

91 32 DDC_EN
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0
47 41 40 39 38 37 34 31 30 27 34 DDCBUF PP3V3_S0 50 51 52 53 57 58 60 61 62 67
6 7 13 17 18 19 20 21 23 24 27
1NOSTUFF 1NOSTUFF
89 79 77 76 74 73 72 71 67 30 31 34 37 38 39 40 41 47 49
1 1 1
R9753 R9755 R9757 R9759 R9761 3 PEQ 35 1NOSTUFF 1 1
71 72 73 74 76 77 79 89 91

4.7K 4.7K 4.7K 4.7K 4.7K PRE R9763 R9765 R9769

www.teknisi-indonesia.com
5% 5% 5% 5% 5% 25
1/16W 1/16W 1/16W 1/16W 1/16W OE* 4.7K 4.7K 4.7K
MF-LF MF-LF MF-LF MF-LF MF-LF 11 APD 33 5% 5% 5%
2 402 2 402 2 402 2 402 2 402 EMI1 1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
HDMI_LS_PIO EMI0 27
2 402 2 402 2 402
HDMI_LS_DDC_EN 12 RSV_1
HDMI_LS_PRE
HDMI_LS_DDCBUF PD_HDMI_LS_RSV0 1 RSV_0
HDMI_LS_OE_L
HDMI_LS_PEQ HDMI_LS_REXT 6 REXT
HDMI_LS_EMI1
HDMI_LS_APD HDMI_LS_CEXT 10 CEXT GND THRM HDMI_LS_EMI0
PU_HDMI_LS_RSV1 PAD

5
18
24
31
36
37
43

49
1 1 1 1NOSTUFF 1 1 1 1NOSTUFF 1 1
R9750 R9754 R9756 R9758 R9740 R9741 1 C9760 R9762 R9764 R9766 R9768
4.7K 4.7K 4.7K 4.7K 4.7K 470 2.2UF 4.7K 4.7K 4.7K 4.7K
5% 5% 5% 5% 5% 1% 20% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 6.3V 1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF 2 CERM MF-LF MF-LF MF-LF MF-LF
2 402 2 402 2 402 2 402 2 402 2 402 402-LF 2 402 2 402 2 402 2 402

EMI0 - EMI FILTER ENABLE 0

HIGH MIDDLE RISE/FALL TIME
MID LARGE RISE/FALL TIME
APD - AUTOMATIC POWER DOWN LOW SMALL RISE/FALL TIME PRE - PRE-EMPHASIS
B PIO - HPD INPUT
HIGH INVERT HPD_SINK
PEQ
MID
- INPUT EQ
HIGH HIGH EQ
LOW EQ
AUTO-POWER-DOWN WHEN HPD_SINK IS LOW.
HIGH
MID
ENABLE
(RESERVED) EMI1 - EMI FILTER ENABLE 1
HIGH LOW PRE-EMPHASIS
MID
LOW
HIGH PRE-EMPHASIS
NO PRE-EMPHASIS
B
LOW NO INVERSION LOW MID EQ LOW DISABLE HIGH NO EFFECT
MID (RESERVED)
LOW EMI FILTER ENABLE

DDCBUF - DDC LEVEL SHIFTER TYPE

HIGH ACTIVE
LOW PASSIVE
OE* - OUTPUT ENABLE.
HIGH DISABLE TMDS DRIVERS
LOW ENABLE TMDS DRIVERS

91
HDMI_LS_HPD OUT 8 79 83
62 61 60 58 57 53 52 51 50 49
24 23 21 20 19 18 17 13 7 6 PP3V3_S0
47 41 40 39 38 37 34 31 30 27
1
89 79 77 76 74 73 72 71 67

R97251 R97241 R9726

100K
10K 10K 5%
5% 5% 1/16W
1/16W 1/16W MF-LF
MF-LF MF-LF 2 402
402 2 402 2

HDMI_LS_SCL BI 8 79 83

HDMI_LS_SDA BI 8 79 83

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

HDMI SHIFTER
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
97 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 79 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

PLACE NEAR J9430 CONNECTOR

CRITICAL

L9890
90-OHM-300MA
ACM2012H
83 79 IN HDMI_DATA_P<0> 1 SYM_VER-2 4 HDMI_DATA_CONN_P<0> 80 83

83 79 IN HDMI_DATA_N<0> 2 3 HDMI_DATA_CONN_N<0> 80 83

CRITICAL CRITICAL
D D9811
RCLAMP0524P
D9810
RCLAMP0524P
HDMI CONNECTOR D
SLP2510P8 SLP2510P8

(0.055A TO 0.5A LIMITS PER HDMI SPEC.)

2 IO IO 1 2 IO IO 1
9 NC NC 10 9 NC NC 10 PP5V_HDMI_DDC_FUSE 80
VOLTAGE=5V
CRITICAL MIN_LINE_WIDTH=0.5 MM

GND

GND
MIN_NECK_WIDTH=0.2 MM
CRITICAL
CRITICAL
3 3 U9800 L9830
TPS2051B 400-OHM-EMIVOLTAGE=5V
MIN_LINE_WIDTH=0.5 MM
L9891
90-OHM-300MA 67 64 62 61 48 42 41 24 23 7 PP5V_S0 5 IN
SOT23
OUT 1 1 2 MIN_NECK_WIDTH=0.2 MM
91 71 70 69 68
ACM2012H SM-1
83 79 HDMI_DATA_P<1> 1 SYM_VER-2 4 HDMI_DATA_CONN_P<1> 80 83
4 EN OC* 3 NC_HD_OC 91
IN
C9800 1 1 C9802 GND
NO_TEST=TRUE 1 C9803 1 C9830
22UF 0.1UF 10UF 0.01UF
20% 10% 2 20% 20%
HDMI_DATA_N<1> 2 3 HDMI_DATA_CONN_N<1> 6.3V 16V 6.3V 2 50V
83 79 IN 80 83 X5R-CERM1 2 2 X7R-CERM 2 X5R CERM
0603 402 603 603
CRITICAL

L9892
90-OHM-300MA

HDMI_DATA_P<2> 1
ACM2012H
SYM_VER-2 4 HDMI_DATA_CONN_P<2> J9830
83 79 IN 80 83
HDMI-PLASTIC-J40
F-RT-SM
83 79 IN HDMI_DATA_N<2> 2 3 HDMI_DATA_CONN_N<2> 80 83 83 80 HDMI_DATA_CONN_P<2> 1
TMDS_DATA2_P 2
TMDS_DATA2_SHLD1
80 HDMI_DATA_CONN_N<2>
83
3
5
TMDS_DATA2_M
TMDS_DATA1_P 4 HDMI_DATA_CONN_P<1> 80 83
CRITICAL CRITICAL TMDS_DATA1_SHLD1 6 HDMI_DATA_CONN_N<1>
TMDS_DATA1_M 80 83
D9810 D9811 HDMI_DATA_CONN_P<0> 7
C RCLAMP0524P RCLAMP0524P
83 80

83 80 HDMI_DATA_CONN_N<0>
9
TMDS_DATA0_P
TMDS_DATA0_M
TMDS_DATA0_SHLD1
TMDS_CLK_P
8
10 HDMI_CLK_CONN_P 80 83
C
SLP2510P8 SLP2510P8 11
TMDS_CLK_SHLD
TMDS_CLK_M 12 HDMI_CLK_CONN_N 80 83
TP_HDMI_CEC_CONN 13
CEC 14
RSRVD
80 HDMI_DDC_CLK_CONN 15
SCL
5 IO IO 4 5 IO IO 4
17 SDA 16 HDMI_DDC_DATA_CONN 80
6 NC NC 7 6 NC NC 7 DDC_CED_GND 18 PP5V_HDMI_DDC_CONN 80
P_5V_PWR 91
80 HDMI_HPD_CONN 19
HOT_PLUG_DETECT
GND

www.teknisi-indonesia.com GND
20 IO20 IO21 21
3 3 22 IO22 23
CRITICAL IO23
CRITICAL 24 25
IO24 IO25

L9893 26 27

SHLD
PINS
IO26 IO27
360-OHM-0.100MA 28 29
IO28 IO29
ACM2012-SM
83 79 HDMI_CLK_P 1 SYM_VER-2 4 HDMI_CLK_CONN_P 80 83
30 IO30 IO31 31
IN
32 IO32 IO33 33
34 IO34
83 79 IN HDMI_CLK_N 2 3 HDMI_CLK_CONN_N 80 83

CRITICAL PLACE CAPS CLOSE

D9800 TO HDMI CONNECTOR
RCLAMP0504F
SC70-6-1
80 PP5V_HDMI_DDC_FUSE
6
B 1 1 C9810 B
R98101 1
R9812 0.01UF
10%
2 5 PP5V_HDMI_DDC_CONN 80 91 4.7K 4.7K 2 50V
X7R
5% 5% 402
1/16W 1/16W
4 CRITICAL MF-LF MF-LF
402 2 2 402
NC 3 L9810
FERR-220-OHM R9811
HDMI_DDC_CLK_CONN 1 2 HDMI_DDC_CLK_F 1
33 2 HDMI_DDC_CLK_5V
80 BI 79
0402 5%
1/16W
MF-LF
C9811 1 402
22PF CRITICAL
5%
50V
CERM 2 L9811
402 FERR-220-OHM R9813
1 2 33 HDMI_DDC_DATA_5V BI 79
80 HDMI_DDC_DATA_CONN HDMI_DDC_DATA_F 1 2
0402 5%
1/16W
MF-LF
1 C9813 CRITICAL
402
22PF
5%
2 50V
L9841
CERM
402
FERR-220-OHM R9814
2 1 10K
80 HDMI_HPD_CONN HDMI_HPD_Q 1 2 HDMI_HPD OUT 79
0402 5%
1/16W
1 C9814 MF-LF
402
220PF 100K PULL-DOWN IS BUILT INTO LEVEL SHIFTER.
10%
2 50V
X7R-CERM
402

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

HDMI CONNECTOR
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
98 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 80 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
CPU Signal Constraints CPU Net Properties XDP Properties
NET_TYPE
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

NET_TYPE
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
CPU_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD XDP_BPM_L<3..0>
XDP_BPM CPU_50S CPU_ITP 11 24
TABLE_PHYSICAL_RULE_ITEM

DMI_S2N PCIE_85D PCIE DMI_S2N_P<3:0> 10 18

CPU_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD XDP_BPM_L CPU_50S CPU_ITP XDP_BPM_L<7..4> 11 24
DMI_S2N PCIE_85D PCIE DMI_S2N_N<3:0> 10 18
TABLE_PHYSICAL_RULE_ITEM

CPU_50S CPU_ITP XDP_CPURST_L 24

CPU_27P4S * =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE 7 MIL 7 MIL DMI_N2S PCIE_85D PCIE DMI_N2S_P<3:0> 10 18
I127 CPU_CFG CPU_50S CPU_ITP XDP_CPU_CFG<0> 24
DMI_N2S PCIE_85D PCIE DMI_N2S_N<3:0> 10 18
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance. XDP_PRDY_L CPU_50S CPU_ITP XDP_CPU_PRDY_L 11 24

TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD
I125 DMI_CLK100M CLK_PCIE_90D CLK_PCIE DMI_CLK100M_CPU_P 11 17 XDP_PREQ_l CPU_50S CPU_ITP XDP_CPU_PREQ_L 11 24

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT CLK_PCIE_90D CLK_PCIE DMI_CLK100M_CPU_N 11 17
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
I126
XDP_TDI CPU_50S CPU_ITP XDP_CPU_TDI 11 24

D CPU_AGTL * =STANDARD ?
TABLE_SPACING_RULE_ITEM
CPU_AGTL TOP,BOTTOM =2x_DIELECTRIC ?
TABLE_SPACING_RULE_ITEM
FDI_DATA PCIE_85D PCIE FDI_DATA_P<7:0> 8 18
XDP_TDO
XDP_TMS
CPU_50S
CPU_50S
CPU_ITP
CPU_ITP
XDP_CPU_TDO
XDP_CPU_TMS
11 24

11 24
D
CPU_8MIL * 8 MIL ? CPU_VID * 0.457 MM ? FDI_DATA PCIE_85D PCIE FDI_DATA_N<7:0> 8 18
XDP_TCK CPU_50S CPU_ITP XDP_CPU_TCK 11 24
TABLE_SPACING_RULE_ITEM

CPU_50S CPU_AGTL FDI_FSYNC<1..0> 8 18

CPU_COMP * 20 MIL ? XDP_TRST_L CPU_50S CPU_ITP XDP_CPU_TRST_L 11 24
TABLE_SPACING_RULE_ITEM
CPU_50S CPU_AGTL FDI_LSYNC<1..0> 8 18

CPU_ITP * =2:1_SPACING ? CPU_50S CPU_AGTL FDI_INT 8 18 I128 CPU_50S CPU_ITP XDP_PCH_TCK 17 24

TABLE_SPACING_RULE_ITEM

I129 CPU_50S CPU_ITP XDP_PCH_TDI 17 24

CPU_VCCSENSE * 25 MIL ? XDP_PCH_TDO
I131 CPU_50S CPU_ITP 17 24

Most CPU signals with impedance requirements are 50-ohm single-ended. I130 CPU_50S CPU_ITP XDP_PCH_TMS 17 24

Some signals require 27.4-ohm single-ended impedance.

SOURCE: HR PDG section 4.1.9, PDDG section 2.5.1 I137 CPU_50S CPU_ITP XDP_TDI 24

I139 CPU_50S CPU_ITP XDP_TDO 24

PCI-Express TABLE_PHYSICAL_RULE_HEAD
I138 CPU_50S CPU_ITP XDP_TMS 24

PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP XDP_CPU_PWRGOOD CPU_50S CPU_ITP XDP_CPU_PWRGD 24
TABLE_PHYSICAL_RULE_ITEM

XDP_BDRESET_L CPU_50S CPU_ITP XDP_DBRESET_L 11 24 27

PCIE_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF XDP_PRESENT_L
TABLE_PHYSICAL_RULE_ITEM
I132 CPU_50S CPU_ITP 24

CLK_PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF I133 CPU_50S CPU_ITP XDP_RES_RL 24

I134 CPU_50S CPU_ITP XDP_CPU_PWRBTN_L 24

TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD

I135 CPU_50S CPU_ITP XDP_VR_READY 24

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

XDP_CLK_CPU CLK_PCIE_90D CLK_PCIE ITPCPU_CLK100M_P 11 17

PCIE * =3X_DIELECTRIC ? PCIE TOP,BOTTOM =4X_DIELECTRIC ? ITPCPU_CLK100M_N
TABLE_SPACING_RULE_ITEM
XDP_CLK_CPU CLK_PCIE_90D CLK_PCIE 11 17

CLK_PCIE * 20 MIL ? XDP_CLK_PCH CLK_PCIE_90D CLK_PCIE ITPXDP_CLK100M_P 17 24

XDP_CLK_PCH CLK_PCIE_90D CLK_PCIE ITPXDP_CLK100M_N 17 24

XDP_CLK_ITP CLK_PCIE_90D CLK_PCIE XDP_CPU_CLK100M_P 24

XDP_CLK_ITP CLK_PCIE_90D CLK_PCIE XDP_CPU_CLK100M_N 24

C CPU_50S
CPU_50S
CPU_VID
CPU_VID
CPU_VCCSA_VID<1>
CPU_VIDALERT_L
13 64

13 67
C
I145

I144 CPU_50S CPU_VID CPU_VIDALERT_L_R 13

I143 CPU_50S CPU_VID CPU_VIDSCLK 13 67

I142 CPU_50S CPU_VID CPU_VIDSCLK_R 13

I141 CPU_50S CPU_VID CPU_VIDSOUT 13 67

I140 CPU_50S CPU_VID CPU_VIDSOUT_R 13

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I146 CPU_PECI CPU_50S PCIE CPU_PECI 11 20 46

CPU_50S PCIE CPU_PECI_R 46

PM_SYNC CPU_50S CPU_AGTL PM_SYNC 11 18

PM_MEM_PWRGD CPU_50S CPU_AGTL PM_MEM_PWRGD 11 18 28

CPU_SM_RCOMP CPU_27P4S CPU_COMP CPU_SM_RCOMP<2..0> 11

CPU_CFG CPU_50S CPU_ITP CPU_CFG<11..0> 10 24

I124 CPU_CFG CPU_50S CPU_ITP CPU_CFG<17..16> 10

CPU_CATERR_L CPU_50S CPU_AGTL CPU_CATERR_L 6 11

I115 CPU_50S CPU_AGTL CPU_PROC_SEL_L 11 18

CPU_50S CPU_AGTL CPU_VTTSELECT

CPU_PROCHOT_L CPU_50S CPU_AGTL CPU_PROCHOT_L 11 47 67

CPU_PWRGD CPU_50S CPU_AGTL CPU_PWRGD 11 20 24

PM_THRMTRIP_L CPU_50S CPU_8MIL PM_THRMTRIP_L 11 20

CPU_55S CPU_8MIL CPU_PSI_L

PM_DPRSLPVR CPU_50S CPU_AGTL PM_DPRSLPVR
CPU_27P4S CPU_COMP CPU_PEG_COMP 10

B CPU_27P4S CPU_COMP CPU_PEG_RBIAS B

CPU_COMP CPU_27P4S CPU_COMP CPU_COMP3
CPU_COMP CPU_27P4S CPU_COMP CPU_COMP2
CPU_COMP CPU_27P4S CPU_COMP CPU_COMP1
CPU_COMP CPU_27P4S CPU_COMP CPU_COMP0

CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_P 13 67

CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_N 13 67

CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCIOSENSE_P 13 70

CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCIOSENSE_N 13 70

CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_AXG_SENSE_P 13 67

CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_AXG_SENSE_N 13 67

I120 CPU_27P4S CPU_VCCSENSE CPU_VCC_VALSENSE_P 10

I121 CPU_27P4S CPU_VCCSENSE CPU_VCC_VALSENSE_N 10

I122 CPU_27P4S CPU_VCCSENSE CPU_AXG_VALSENSE_P 10

I123 CPU_27P4S CPU_VCCSENSE CPU_AXG_VALSENSE_N 10

CPU_55S CPU_8MIL GFX_VID<6..0>

PM_DPRSLPVR CPU_50S CPU_AGTL GFX_DPRSLPVR
CPU_50S CPU_AGTL GFX_VR_EN
CPU_50S CPU_AGTL GFXIMVP_IMON
A PCIE_85D PCIE PEG_R2D_P<7..0> SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE
PEG_R2D_N<7..0>
PEG_R2D
PCIE_85D
PCIE_85D
PCIE
PCIE PEG_R2D_C_P<7..0> CPU Constraints
DRAWING NUMBER SIZE
PCIE_85D PCIE PEG_R2D_C_N<7..0> PEG CLOCK ON PP103 WITH PCIE CONSTRAINTS.
PEG_D2R PCIE_85D PCIE PEG_D2R_P<7..0> Apple Inc. 051-8768 D
REVISION
PCIE_85D PCIE PEG_D2R_N<7..0> R

PCIE_85D PCIE PEG_D2R_C_P<7..0> 9.0.0

PEG_D2R_C_N<7..0> NOTICE OF PROPRIETARY PROPERTY: BRANCH
PCIE_85D PCIE
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
100 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 81 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Memory Bus Constraints Memory Net Properties
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

NET_TYPE
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
MEM_40S * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD MEM_A_CLK_P<5..0>
TABLE_PHYSICAL_RULE_ITEM
MEM_A_CLK MEM_85D MEM_CLK 12 30

MEM_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD MEM_A_CLK MEM_85D MEM_CLK MEM_A_CLK_N<5..0> 12 30
TABLE_PHYSICAL_RULE_ITEM

MEM_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF MEM_A_CNTL MEM_40S MEM_CTRL MEM_A_CKE<3..0> 12 30

MEM_A_CNTL MEM_40S MEM_CTRL MEM_A_CS_L<3..0> 12 30

MEM_A_CNTL MEM_40S MEM_CTRL MEM_A_ODT<3..0> 12 30

MEM_A_CMD MEM_40S MEM_CMD MEM_A_A<15..0> 12 30

MEM_A_CMD MEM_40S MEM_CMD MEM_A_BA<2..0> 12 30

D SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_SPACING_RULE_HEAD

MEM_A_CMD MEM_40S MEM_CMD MEM_A_RAS_L 12 30 D

TABLE_SPACING_RULE_ITEM

MEM_A_CMD MEM_40S MEM_CMD MEM_A_CAS_L 12 30

MEM_CLK2MEM * =4:1_SPACING ? MEM_A_WE_L
TABLE_SPACING_RULE_ITEM
MEM_A_CMD MEM_40S MEM_CMD 12 30

MEM_CTRL2CTRL * =3:1_SPACING ? MEM_A_DQ<7..0>

TABLE_SPACING_RULE_ITEM
MEM_A_DQ_BYTE0 MEM_50S MEM_DATA 12 29

MEM_CTRL2MEM * =2.5:1_SPACING ? MEM_A_DQ_BYTE1 MEM_50S MEM_DATA MEM_A_DQ<15..8> 12 29

TABLE_SPACING_RULE_ITEM

MEM_A_DQ_BYTE2 MEM_50S MEM_DATA MEM_A_DQ<23..16> 12 29

MEM_CMD2CMD * =1.5:1_SPACING ? MEM_A_DQ<31..24>
TABLE_SPACING_RULE_ITEM
MEM_A_DQ_BYTE3 MEM_50S MEM_DATA 12 29

MEM_CMD2MEM * =3:1_SPACING ? MEM_A_DQ_BYTE4 MEM_50S MEM_DATA MEM_A_DQ<39..32> 12 29

TABLE_SPACING_RULE_ITEM

MEM_A_DQ_BYTE5 MEM_50S MEM_DATA MEM_A_DQ<47..40> 12 29

MEM_DATA2DATA * =1.5:1_SPACING ? MEM_A_DQ<55..48>
TABLE_SPACING_RULE_ITEM
MEM_A_DQ_BYTE6 MEM_50S MEM_DATA 12 29

MEM_DATA2MEM * =3:1_SPACING ? MEM_A_DQ_BYTE7 MEM_50S MEM_DATA MEM_A_DQ<63..56> 12 29

TABLE_SPACING_RULE_ITEM

MEM_DQS2MEM * =3:1_SPACING ? MEM_A_DQS0 MEM_85D MEM_DQS MEM_A_DQS_P<0> 12 29

TABLE_SPACING_RULE_ITEM

MEM_A_DQS0 MEM_85D MEM_DQS MEM_A_DQS_N<0> 12 29

MEM_2OTHER * 25 MILS ?
MEM_A_DQS1 MEM_85D MEM_DQS MEM_A_DQS_P<1> 12 29

MEM_A_DQS1 MEM_85D MEM_DQS MEM_A_DQS_N<1> 12 29

Memory Bus Spacing Group Assignments MEM_A_DQS2 MEM_85D MEM_DQS MEM_A_DQS_P<2> 12 29

TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD

MEM_A_DQS2 MEM_85D MEM_DQS MEM_A_DQS_N<2> 12 29

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS3 MEM_85D MEM_DQS MEM_A_DQS_P<3> 12 29

MEM_CLK MEM_CLK * MEM_CLK2MEM MEM_CMD MEM_CLK * MEM_CMD2MEM MEM_A_DQS3 MEM_85D MEM_DQS MEM_A_DQS_N<3> 12 29
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS4 MEM_85D MEM_DQS MEM_A_DQS_P<4> 12 29

MEM_CLK MEM_CTRL * MEM_CLK2MEM MEM_CMD MEM_CTRL * MEM_CMD2MEM MEM_A_DQS_N<4>
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS4 MEM_85D MEM_DQS 12 29

MEM_CLK MEM_CMD * MEM_CLK2MEM MEM_CMD MEM_CMD * MEM_CMD2CMD MEM_A_DQS5 MEM_85D MEM_DQS MEM_A_DQS_P<5> 12 29
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS5 MEM_85D MEM_DQS MEM_A_DQS_N<5> 12 29

MEM_CLK MEM_DATA * MEM_CLK2MEM MEM_CMD MEM_DATA * MEM_CMD2MEM MEM_A_DQS_P<6>
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS6 MEM_85D MEM_DQS 12 29

MEM_CLK MEM_DQS * MEM_CLK2MEM MEM_CMD MEM_DQS * MEM_CMD2MEM MEM_A_DQS6 MEM_85D MEM_DQS MEM_A_DQS_N<6> 12 29

MEM_A_DQS_P<7>
C NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE

TABLE_SPACING_ASSIGNMENT_HEAD

SPACING_RULE_SET
MEM_A_DQS7
MEM_A_DQS7
MEM_85D
MEM_85D
MEM_DQS
MEM_DQS MEM_A_DQS_N<7>
12 29

12 29
C
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL MEM_CLK * MEM_CTRL2MEM MEM_DATA MEM_CLK * MEM_DATA2MEM

TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_DATA MEM_CTRL * MEM_DATA2MEM

TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL MEM_CMD * MEM_CTRL2MEM MEM_DATA MEM_CMD * MEM_DATA2MEM

TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL MEM_DATA * MEM_CTRL2MEM MEM_DATA MEM_DATA * MEM_DATA2DATA

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TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL MEM_DQS * MEM_CTRL2MEM MEM_DATA MEM_DQS * MEM_DATA2MEM

TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD

MEM_B_CLK MEM_85D MEM_CLK MEM_B_CLK_P<5..0> 12 31

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_CLK MEM_85D MEM_CLK MEM_B_CLK_N<5..0> 12 31

MEM_DQS MEM_CLK * MEM_DQS2MEM MEM_CLK * * MEM_2OTHER MEM_B_CKE<3..0>

TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_CNTL MEM_40S MEM_CTRL 12 31

MEM_DQS MEM_CTRL * MEM_DQS2MEM MEM_CTRL * * MEM_2OTHER MEM_B_CNTL MEM_40S MEM_CTRL MEM_B_CS_L<3..0> 12 31

TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_CNTL MEM_40S MEM_CTRL MEM_B_ODT<3..0> 12 31

MEM_DQS MEM_CMD * MEM_DQS2MEM MEM_CMD * * MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_CMD MEM_40S MEM_CMD MEM_B_A<15..0> 12 31

MEM_DQS MEM_DATA * MEM_DQS2MEM MEM_DATA * * MEM_2OTHER MEM_B_BA<2..0>
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_CMD MEM_40S MEM_CMD 12 31

MEM_DQS MEM_DQS * MEM_DQS2MEM MEM_DQS * * MEM_2OTHER MEM_B_CMD MEM_40S MEM_CMD MEM_B_RAS_L 12 31

MEM_B_CMD MEM_40S MEM_CMD MEM_B_CAS_L 12 31

Need to support MEM_*-style wildcards! MEM_B_WE_L
MEM_B_CMD MEM_40S MEM_CMD 12 31
DDR3:
DQ/DM signals should be matched within 0.508mm of associated DQS pair. MEM_B_DQ_BYTE0 MEM_50S MEM_DATA MEM_B_DQ<7..0> 12 29

DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement. MEM_B_DQ_BYTE1 MEM_50S MEM_DATA MEM_B_DQ<15..8> 12 29

DQS to clock matching should be within [CLK-12.7mm] and [CLK+25.4mm]. MEM_B_DQ_BYTE2 MEM_50S MEM_DATA MEM_B_DQ<23..16> 12 29

CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm. MEM_B_DQ_BYTE3 MEM_50S MEM_DATA MEM_B_DQ<31..24> 12 29

B CONTROL signals should be matched within [CLK-12.7mm] to [CLK+0.0mm] of CLK pairs.

A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs.
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_50S
MEM_50S
MEM_DATA
MEM_DATA
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
12 29

12 29
B
DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric. MEM_B_DQ_BYTE6 MEM_50S MEM_DATA MEM_B_DQ<55..48> 12 29

Maximum length of any signal from die pad to SODIMM pad is 139.7mm, from procesor ball to SODIMM pad is 114.3mm. MEM_B_DQ_BYTE7 MEM_50S MEM_DATA MEM_B_DQ<63..56> 12 29

SOURCE: Calpella SFF Platform DG, Rev 1.5 (#407364), Section 2.2 MEM_B_DQS0 MEM_85D MEM_DQS MEM_B_DQS_P<0> 12 29

SOURCE: HR PDG, Section 4.1.9 MEM_B_DQS0 MEM_85D MEM_DQS MEM_B_DQS_N<0> 12 29

MEM_B_DQS1 MEM_85D MEM_DQS MEM_B_DQS_P<1> 12 29

MEM_B_DQS1 MEM_85D MEM_DQS MEM_B_DQS_N<1> 12 29

MEM_B_DQS2 MEM_85D MEM_DQS MEM_B_DQS_P<2> 12 29

MEM_B_DQS2 MEM_85D MEM_DQS MEM_B_DQS_N<2> 12 29

MEM_B_DQS3 MEM_85D MEM_DQS MEM_B_DQS_P<3> 12 29

MEM_B_DQS3 MEM_85D MEM_DQS MEM_B_DQS_N<3> 12 29

MEM_B_DQS4 MEM_85D MEM_DQS MEM_B_DQS_P<4> 12 29

MEM_B_DQS4 MEM_85D MEM_DQS MEM_B_DQS_N<4> 12 29

MEM_B_DQS5 MEM_85D MEM_DQS MEM_B_DQS_P<5> 12 29

MEM_B_DQS5 MEM_85D MEM_DQS MEM_B_DQS_N<5> 12 29

MEM_B_DQS6 MEM_85D MEM_DQS MEM_B_DQS_P<6> 12 29

MEM_B_DQS6 MEM_85D MEM_DQS MEM_B_DQS_N<6> 12 29

MEM_B_DQS7 MEM_85D MEM_DQS MEM_B_DQS_P<7> 12 29

MEM_B_DQS7 MEM_85D MEM_DQS MEM_B_DQS_N<7> 12 29

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

Memory Constraints
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
101 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 82 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Digital Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD
PCH Net Properties DP Properties
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP NET_TYPE NET_TYPE
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING

DP_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM

DP_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SATA_HDD_D2R SATA_90D SATA SATA_HDD1_D2R_CONN_N 42 91 DP_90D DISPLAYPORT DP_AUX_CH_CK_N
TABLE_PHYSICAL_RULE_ITEM

SATA_90D SATA SATA_HDD1_D2R_CONN_P 42 91 DP_90D DISPLAYPORT DP_AUX_CH_CK_P

TMDS_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF SATA_HDD1_D2R_N DP_AUX_CH_C_N
TABLE_PHYSICAL_RULE_ITEM
SATA_HDD_D2R SATA_90D SATA 17 42 DP_90D DISPLAYPORT
TMDS_100D * =100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF SATA_90D SATA SATA_HDD1_D2R_P 17 42 DP_90D DISPLAYPORT DP_AUX_CH_C_P
TABLE_PHYSICAL_RULE_ITEM

SATA_HDD_R2D SATA_90D SATA SATA_HDD1_R2D_CONN_N 42 91 T29DP_90D T29DP DP_A_EXT_AUXCH_N 77 78 86

TMDS_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SATA_HDD1_R2D_CONN_P DP_A_EXT_AUXCH_P
SATA_90D SATA 42 91 T29DP_90D T29DP 77 78 86

SATA_HDD_R2D SATA_90D SATA SATA_HDD1_R2D_C_N 17 42 DP_90D DISPLAYPORT DP_EXTA_AUXCH_C_N 8 77

D SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM
SATA_HDD_D2R
SATA_90D
SATA_90D
SATA
SATA
SATA_HDD1_R2D_C_P
SATA_HDD2_D2R_CONN_N
17 42

42 91
DP_90D
DP_90D
DISPLAYPORT
DISPLAYPORT
DP_EXTA_AUXCH_C_P
DP_EXTA_AUXCH_N
8 77

77
D
DISPLAYPORT * =4:1_SPACING ? DISPLAYPORT TOP,BOTTOM =4:1_SPACING ? SATA_90D SATA SATA_HDD2_D2R_CONN_P 42 91 DP_90D DISPLAYPORT DP_EXTA_AUXCH_P 77
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

SATA_HDD_D2R SATA_90D SATA SATA_HDD2_D2R_N 17 42 DP_90D DISPLAYPORT DP_EXTA_DDC_CLK_AUX_P Manual

TMDS * =4:1_SPACING ? TMDS TOP,BOTTOM =4:1_SPACING ?
SATA_HDD2_D2R_P DP_EXTA_DDC_DATA_AUX_N
SATA_90D SATA 17 42 DP_90D DISPLAYPORT Diff Pair
SATA_HDD_R2D SATA_90D SATA SATA_HDD2_R2D_CONN_N 42 91 DP_55S DISPLAYPORT DP_EXTA_DDC_CLK 8 77
SOURCE: HR PDG, TABLES 191,193, Radeon TRM section 7.7.1 SATA_HDD2_R2D_CONN_P DP_EXTA_DDC_DATA
SATA_90D SATA 42 91 DP_55S DISPLAYPORT 8 77
PER ANIL: MODIFIED DP CONNECTOR NEEDS 90 OHMS. MEASURE PROTO BOARD AND ADJUST IF NEEDED. SATA_HDD2_R2D_C_N DP_EXTA_HPD
SATA_HDD_R2D SATA_90D SATA 17 42 DP_55S DISPLAYPORT 8 77

SATA_90D SATA SATA_HDD2_R2D_C_P 17 42

I312 SATA_HDD_D2R SATA_90D SATA SATA_HDD1_D2R_DF_N 42 DP_90D DISPLAYPORT DP_T29SNK0_AUXCH_C_N 8 74

I311 SATA_90D SATA SATA_HDD1_D2R_DF_P 42 DP_90D DISPLAYPORT DP_T29SNK0_AUXCH_C_P 8 74

SATA_HDD1_R2D_DF_N DP_T29SNK0_AUXCH_N
SATA Interface Constraints TABLE_PHYSICAL_RULE_HEAD
I309

I310
SATA_HDD_R2D SATA_90D
SATA_90D
SATA
SATA SATA_HDD1_R2D_DF_P
42

42
DP_90D
DP_90D
DISPLAYPORT
DISPLAYPORT DP_T29SNK0_AUXCH_P
74

74

PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP I307 SATA_HDD_D2R SATA_90D SATA SATA_HDD2_D2R_DF_N 42 DP_90D DISPLAYPORT DP_EXTA_ML_C_N<3..0> 8 77
TABLE_PHYSICAL_RULE_ITEM

I308 SATA_90D SATA SATA_HDD2_D2R_DF_P 42 DP_90D DISPLAYPORT DP_EXTA_ML_C_P<3..0> 8 77

SATA_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF SATA_HDD2_R2D_DF_N DP_EXTA_ML_N<3..0>
TABLE_PHYSICAL_RULE_ITEM
I305 SATA_HDD_R2D SATA_90D SATA 42 DP_90D DISPLAYPORT 77

SATA_37SE * =37_OHM_SE =37_OHM_SE =37_OHM_SE =37_OHM_SE =37_OHM_SE =37_OHM_SE I306 SATA_90D SATA SATA_HDD2_R2D_DF_P 42 DP_90D DISPLAYPORT DP_EXTA_ML_P<3..0> 77
TABLE_PHYSICAL_RULE_ITEM

DP_90D DISPLAYPORT DP_ML_CK_N<3..0>

SATA_50SE * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE
DP_90D DISPLAYPORT DP_ML_CK_P<3..0>
PCH_SATA3_ICOMP SATA_50SE SATA_ICOMP PCH_SATA3COMP 17
DP_90D DISPLAYPORT DP_ML_C_N<3..0>
PCH_SATA_ICOMP SATA_37SE SATA_ICOMP PCH_SATAICOMP 17
TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD
DP_90D DISPLAYPORT DP_ML_C_P<3..0>
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
I313 DP_90D DISPLAYPORT DP_T29SNK1_AUXCH_C_N
SATA * =5:1_SPACING ? SATA TOP,BOTTOM =5:1_SPACING ? I314 DP_90D DISPLAYPORT DP_T29SNK1_AUXCH_C_P
TABLE_SPACING_RULE_ITEM

I315 DP_90D DISPLAYPORT DP_T29SNK1_AUXCH_N

SATA_ICOMP * 15 MIL ? PCH_USB_RBIAS DP_T29SNK1_AUXCH_P
PCH_USB_RBIAS PCH_USB_RBIAS USB_RBIAS 19 I316 DP_90D DISPLAYPORT

DP_T29SNK0_ML_C_N<3..0> 8 74
C SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193
DP_90D
DP_90D
DISPLAYPORT
DISPLAYPORT DP_T29SNK0_ML_C_P<3..0> 8 74 C
DP_90D DISPLAYPORT DP_T29SNK0_ML_N<3..0> 74
DP_90D DISPLAYPORT DP_T29SNK0_ML_P<3..0> 74
DP_55S DISPLAYPORT DP_T29SNK0_DDC_CLK
DP_55S DISPLAYPORT DP_T29SNK0_DDC_DATA
DP_55S DISPLAYPORT DP_T29SNK0_HPD 8 74

USB_HUB1_UP USB_85D USB USB_HUB1_UP_N

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19 25

USB 2.0 Interface Constraints USB_85D USB USB_HUB1_UP_P 19 25 I318 DP_90D DISPLAYPORT DP_T29SNK1_ML_C_N<3..0>
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

USB_HUB2_UP USB_85D USB USB_HUB2_UP_N 19 25 I319 DP_90D DISPLAYPORT DP_T29SNK1_ML_C_P<3..0>

PHYSICAL_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM
USB_85D USB USB_HUB2_UP_P 19 25 I320 DP_90D DISPLAYPORT DP_T29SNK1_ML_N<3..0>
PCH_USB_RBIAS * =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD USB_EXTA USB_85D USB USB_EXTA_N 25 43 I321 DP_90D DISPLAYPORT DP_T29SNK1_ML_P<3..0>
TABLE_PHYSICAL_RULE_ITEM

USB_85D USB USB_EXTA_P 25 43 I317 DP_55S DISPLAYPORT DP_T29SNK1_HPD

USB_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF USB_EXTB_N
USB_EXTB USB_85D USB 25 43

TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD
USB_85D USB USB_EXTB_P 25 43

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT USB_EXTC USB_85D USB USB_EXTC_N 25 43
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

USB_85D USB USB_EXTC_P 25 43

USB * =4:1_SPACING ? USB TOP,BOTTOM =4:1_SPACING ? USB_EXTD_N
TABLE_SPACING_RULE_ITEM
USB_EXTD USB_85D USB 25 43

USB_RBIAS * 15 MIL ? USB_85D USB USB_EXTD_P 25 43

USB_85D USB USB_PORT0_N 43

USB_85D USB USB_PORT0_P 43

USB_85D USB USB_PORT1_N 43

USB_85D USB USB_PORT1_P 43

USB_PORT2_N
SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193
USB_85D
USB_85D
USB
USB USB_PORT2_P
43

43
HDMI Properties
NET_TYPE
USB_85D USB USB_PORT3_N 43
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
B USB_IR
USB_85D
USB_85D
USB
USB
USB_PORT3_P
USB_IR_N
43

25 44
B
USB_85D USB USB_IR_P 25 44 TMDS_100D TMDS HDMI_CLK_CONN_N 80

USB_85D USB USB_IR_R_N 44 TMDS_100D TMDS HDMI_CLK_CONN_P 80

USB_85D USB USB_IR_R_P 44 TMDS_85D TMDS HDMI_CLK_C_N 8 79

USB_BT USB_85D USB USB_BT_N 25 35 TMDS_85D TMDS HDMI_CLK_C_P 8 79

USB_85D USB USB_BT_P 25 35 TMDS_85D TMDS HDMI_CLK_LS_N 79

USB_85D USB USB_BT_CONN_N 35 91 TMDS_85D TMDS HDMI_CLK_LS_P 79

USB_85D USB USB_BT_CONN_P 35 91 TMDS_100D TMDS HDMI_CLK_N 79 80

USB_85D USB USB_B_MUXED_N 43 TMDS_100D TMDS HDMI_CLK_P 79 80

USB_85D USB USB_B_MUXED_P 43 TMDS_100D TMDS HDMI_DATA_CONN_N<2..0> 80

TMDS_100D TMDS HDMI_DATA_CONN_P<2..0> 80

TMDS_85D TMDS HDMI_DATA_C_N<2..0> 8 79

TMDS_85D TMDS HDMI_DATA_C_P<2..0> 8 79

TMDS_85D TMDS HDMI_DATA_LS_N<2..0> 79

TMDS_85D TMDS HDMI_DATA_LS_P<2..0> 79

TMDS_100D TMDS HDMI_DATA_N<2..0> 79 80

TMDS_100D TMDS HDMI_DATA_P<2..0> 79 80

TMDS_55S TMDS HDMI_LS_SCL 8 79

TMDS_55S TMDS HDMI_LS_SDA 8 79

TMDS_55S TMDS HDMI_LS_HPD 8 79

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
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PAGE TITLE

PCH Constraints 1
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
102 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 83 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
LPC Bus Constraints TABLE_PHYSICAL_RULE_HEAD
PCH Net Properties
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP NET_TYPE
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING

LPC_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD
TABLE_PHYSICAL_RULE_ITEM

PCIE_85D PCIE PCIE_ENET_R2D_P 37

CLK_LPC_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD LPC_AD LPC_50S LPC LPC_AD<3..0> 17 46 48
PCIE_85D PCIE PCIE_ENET_R2D_N 37
LPC_50S LPC LPC_R_AD<3..0> 17
TABLE_SPACING_RULE_HEAD
I273
PCIE_ENET_R2D PCIE_85D PCIE PCIE_ENET_R2D_C_P 17 37

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT LPC_FRAME_L LPC_50S LPC LPC_FRAME_L 17 46 48 PCIE_85D PCIE PCIE_ENET_R2D_C_N 17 37
TABLE_SPACING_RULE_ITEM

LPC_50S LPC LPC_FRAME_R_L 17 PCIE_ENET_D2R PCIE_85D PCIE PCIE_ENET_D2R_P 17 37

LPC * 6 MIL ? LPCPLUS_RESET_L PCIE_ENET_D2R_N
TABLE_SPACING_RULE_ITEM
I272 LPC_RESET_L LPC_50S LPC 27 48 PCIE_85D PCIE 17 37

CLK_LPC * 8 MIL ? PCIE_85D PCIE PCIE_ENET_D2R_C_P 37

PCH_LPC_CLK0 CLK_LPC_50S CLK_LPC LPC_CLK33M_SMC_R 19 27
PCIE_85D PCIE PCIE_ENET_D2R_C_N 37

D CLK_LPC_50S
CLK_LPC_50S
CLK_LPC
CLK_LPC
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
27 46

27 48 PCIE_85D PCIE PCIE_AP_R2D_P 35 91

D
SMBus Interface Constraints I271 CLK_LPC_50S CLK_LPC LPC_CLK33M_LPCPLUS_R 19 27 PCIE_85D PCIE PCIE_AP_R2D_N 35 91

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

PCIE_AP_R2D PCIE_85D PCIE PCIE_AP_R2D_C_P 17 35

PHYSICAL_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER? PCIE_85D PCIE PCIE_AP_R2D_C_N 17 35
TABLE_PHYSICAL_RULE_ITEM

SMB_50S SMB SMB_PCH_STR_SCL 49

SMB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD I282
PCIE_AP_D2R PCIE_85D PCIE PCIE_AP_D2R_P 17 35 91
SMB_50S SMB SMB_PCH_STR_SDA 49
I283
PCIE_85D PCIE PCIE_AP_D2R_N 17 35 91
TABLE_SPACING_RULE_HEAD
I280 SMB_50S SMB SMB_PCH_DIMM_SCL 49

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT I281 SMB_50S SMB SMB_PCH_DIMM_SDA 49 PCIE_85D PCIE PCIE_FW_R2D_P 39
TABLE_SPACING_RULE_ITEM

I278 SMB_50S SMB SMB_PCH_MKY_SCL 49 PCIE_85D PCIE PCIE_FW_R2D_N 39

SMB * =2x_DIELECTRIC ? SMB_PCH_MKY_SDA PCIE_FW_R2D_C_P
I279 SMB_50S SMB 49 PCIE_FW_R2D PCIE_85D PCIE 17 39

I276 SMB_50S SMB SMB_PCH_VRF_SCL 49 PCIE_85D PCIE PCIE_FW_R2D_C_N 17 39

I277 SMB_50S SMB SMB_PCH_VRF_SDA 49 PCIE_FW_D2R PCIE_85D PCIE PCIE_FW_D2R_P 17 39

HD Audio Interface Constraints SMBUS_PCH_CLK SMB_50S SMB SMBUS_PCH_CLK 17 49 PCIE_85D PCIE PCIE_FW_D2R_N 17 39

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

SMB_50S SMB SMBUS_PCH_DATA 17 49 PCIE_85D PCIE PCIE_FW_D2R_C_P 39

PHYSICAL_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM
SMBUS_PCH_0_CLK SMB_50S SMB SMB_PCH_XDP_SCL 49 PCIE_85D PCIE PCIE_FW_D2R_C_N 39

HDA_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD SMB_50S SMB SMB_PCH_XDP_SDA 49

SMB_50S SMB SML_PCH_1_CLK 17 49 I253 CLK_PCIE_90D CLK_PCIE PCIE_CLK100M_PCH_P 17

TABLE_SPACING_RULE_HEAD

SMB_50S SMB SML_PCH_1_DATA 17 49 I254 CLK_PCIE_90D CLK_PCIE PCIE_CLK100M_PCH_N 17

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
PCIE_CLK100M_T29_ CLK_PCIE_90D CLK_PCIE PCIE_CLK100M_T29_P 17 74
TABLE_SPACING_RULE_ITEM

SPI_CLK SPI_55S SPI SPI_CLK_R 17 48

I262

HDA * =2x_DIELECTRIC ? CLK_PCIE_90D CLK_PCIE PCIE_CLK100M_T29_N 17 74

SPI_55S SPI SPI_CLK 48 91
I261

SPI_MOSI SPI_55S SPI SPI_MOSI_R 17 48

PCIE_CLK100M CLK_PCIE_90D CLK_PCIE PEG_CLK100M_P 8 17
SPI_55S SPI SPI_MOSI 48 91
PEG_CLK100M_N
SIO Signal Constraints SPI_MISO SPI_55S SPI SPI_MISO 17 48 91
PCIE_CLK100M_ENET
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE PCIE_CLK100M_ENET_P
8 17

17 37
TABLE_PHYSICAL_RULE_HEAD

SPI_CS0 SPI_55S SPI SPI_CS0_R_L 17 48

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CLK_PCIE_90D CLK_PCIE PCIE_CLK100M_ENET_N 17 37
ON LAYER? SPI_55S SPI SPI_CS0_L 48 91
TABLE_PHYSICAL_RULE_ITEM

I275 PCIE_CLK100M_AP CLK_PCIE_90D CLK_PCIE PCIE_CLK100M_AP_CONN_P 35 91

CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD PCIE_CLK100M_AP_CONN_N
C TABLE_SPACING_RULE_HEAD

HDA_BIT_CLK HDA_50S HDA HDA_BIT_CLK 17 53

I274
PCIE_CLK100M_AP
CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE PCIE_CLK100M_AP_P 17 35
35 91
C
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT CLK_PCIE_90D CLK_PCIE PCIE_CLK100M_AP_N 17 35
HDA_50S HDA HDA_BIT_CLK_R 17
TABLE_SPACING_RULE_ITEM

PCIE_CLK100M_FW CLK_PCIE_90D CLK_PCIE PCIE_CLK100M_FW_P 17 39

CLK_SLOW * 8 MIL ? HDA_SYNC HDA_50S HDA HDA_SYNC 17 53
CLK_PCIE_90D CLK_PCIE PCIE_CLK100M_FW_N 17 39
HDA_50S HDA HDA_SYNC_R 17

HDA_RST_L HDA_50S HDA HDA_RST_R_L 17

PCIE_T29_R2D PCIE_85D PCIE PCIE_T29_R2D_C_P<3..0> 8 74
HDA_RST_L I263

SPI Interface Constraints HDA_SDIN0

HDA_50S
HDA_50S
HDA
HDA HDA_SDIN0
17 53
I264 PCIE_T29_R2D PCIE_85D PCIE PCIE_T29_R2D_C_N<3..0> 8 74

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17 53
TABLE_PHYSICAL_RULE_HEAD

PCIE_T29_R2D PCIE_85D PCIE PCIE_T29_R2D_P<3..0> 74

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP HDA_50S HDA AUD_SDI_R 53
I265
ON LAYER? PCIE_T29_R2D PCIE_85D PCIE PCIE_T29_R2D_N<3..0> 74
TABLE_PHYSICAL_RULE_ITEM

HDA_SDOUT HDA_50S HDA HDA_SDOUT 17 53

I267

SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD PCIE_T29_D2R PCIE_85D PCIE PCIE_T29_D2R_P<3..0> 8 74
HDA_50S HDA HDA_SDOUT_R 17
I266

I268 PCIE_T29_D2R PCIE_85D PCIE PCIE_T29_D2R_N<3..0> 8 74

TABLE_SPACING_RULE_HEAD

I270 PCIE_T29_D2R PCIE_85D PCIE PCIE_T29_D2R_C_P<3..0> 74

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM
I269 PCIE_T29_D2R PCIE_85D PCIE PCIE_T29_D2R_C_N<3..0> 74

SPI * 8 MIL ?

B B
I255 CLK_PCIE_90D CLK_PCIE PCH_CLK96M_DOT_P 17

I257 CLK_PCIE_90D CLK_PCIE PCH_CLK96M_DOT_N 17

I256 CLK_PCIE_90D CLK_PCIE PCH_CLK100M_SATA_P 17

I259 CLK_PCIE_90D CLK_PCIE PCH_CLK100M_SATA_N 17

I258 CPU_50S CLK_PCIE PCH_CLK14P3M_REFCLK 17

I260 CPU_50S CLK_PCIE PCH_CLK33M_PCIIN 17 27

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

PCH Constraints 2
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
103 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 84 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
ETHERNET CONSTRAINTS Ethernet Net Properties
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

NET_TYPE
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
ENET_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD BCM5764_CLK25M_XTALI
ENET_50S ENET_3X 26 37

TABLE_SPACING_RULE_HEAD
ENET_50S ENET_3X BCM5764_CLK25M_XTALO 26 37

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT ENET_50S ENET_3X ENET_RESET_L 27 34

TABLE_SPACING_RULE_ITEM

ENET_3X * =3:1_SPACING ? ENET_MDI ENET_100D ENET_MDI ENET_MDI_P<3..0> 36 37

ENET_100D ENET_MDI ENET_MDI_N<3..0> 36 37

SOURCE: Broadcom 5764-DS04-RDS Page 38

D PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_HEAD
D
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM
I174 ENET_100D ENET_HV ENET_MDI_TRAN_N<3..0> 36

ENET_100D * =100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF I175 ENET_100D ENET_HV ENET_MDI_TRAN_P<3..0> 36 High-voltage isolated
I176 ENET_50S ENET_HV ENET_CENTER_TAP<3..0> 36 ethernet signals.
TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD

I177 ENET_HV ENET_CMODE_REF 36

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

ENET_MDI * 0.6 MM ? ENET_HV * * 2KV_SPACING

TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

2KV_SPACING * 0.50 MM 100 ENET_HV ENET_HV * ENET_MDI

TABLE_SPACING_RULE_ITEM

2KV_SPACING TOP,BOTTOM 1.27 MM 100

NOTE: 2.2kV isolation needed on all primary-side ethernet signals. Min 1.27mm separation from all other copper on the board!

SD Interface Properties
SD CARD INTERFACE CONSTRAINTS NET_TYPE
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING

PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM

SD_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

I178
SD_55S SD_INTERFACE SDCONN_CLK 34 37 91

TABLE_SPACING_RULE_HEAD
I187
SD_55S SD_INTERFACE SDCONN_CLK_FF 34

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT I180

SD_55S SD_INTERFACE SDCONN_CMD 34 37 91
TABLE_SPACING_RULE_ITEM

I181
SD_55S SD_INTERFACE SDCONN_DATA<7..0> 34 37 91
SD_INTERFACE * =3X_DIELECTRIC ?
I188
SD_55S SD_INTERFACE SDCONN_CLK_R 34

I189
SD_55S SD_INTERFACE SDCONN_CMD_R 34

I190
SD_55S SD_INTERFACE SDCONN_DATA_R<7..0> 34

I182
SD_55S SD_INTERFACE ENET_CR_CLK 37

ENET_CR_CMD
C FireWire Interface Constraints I183

I184
SD_55S
SD_55S
SD_INTERFACE
SD_INTERFACE ENET_CR_DATA<7..0>
37

37
C
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

I191
SD_55S SD_INTERFACE SDCONNF_CLK 34
PHYSICAL_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM
I192
SD_55S SD_INTERFACE SDCONNF_CLK_FF 34

FW_110D * =110_OHM_DIFF=110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

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TABLE_SPACING_RULE_ITEM

FW_TP * =3:1_SPACING ?

FireWire Net Properties

NET_TYPE
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING

I162 FW_P1_TPA FW_110D FW_TP FW_P0_TPA_L_N 40

I163 FW_110D FW_TP FW_P0_TPA_L_P 40

I164 FW_P1_TPB FW_110D FW_TP FW_P0_TPB_L_N 40

I165 FW_110D FW_TP FW_P0_TPB_L_P 40

I166 FW_110D FW_TP FW_PORT0_TPAL_N 41

I167 FW_110D FW_TP FW_PORT0_TPAL_P 41

I168 FW_110D FW_TP FW_PORT0_TPA_N 40 41

I169 FW_110D FW_TP FW_PORT0_TPA_P 40 41

I170 FW_110D FW_TP FW_PORT0_TPBL_N 41

I171 FW_110D FW_TP FW_PORT0_TPBL_P 41

I172 FW_110D FW_TP FW_PORT0_TPB_N 40 41

FW_110D FW_TP FW_PORT0_TPB_P 40 41

B I173
B
I185
50_OHM_SE CLK_PCIE CLK98M_FW_XI 39

I186
50_OHM_SE CLK_PCIE CLK98M_FW_XI_R 39

Port 0 and 2 Not Used

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

Ethernet/FW Constraints
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
104 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 85 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
DisplayPort Signal Constraints T29 IC Net Properties
NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page. NET_TYPE
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
T29 I2C Signal Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

T29_I2C_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_SPACING_RULE_ITEM

T29_I2C * =2x_DIELECTRIC ?

D T29 SPI Signal Constraints D

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

T29_SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_SPACING_RULE_ITEM

T29_SPI * =2x_DIELECTRIC ?

T29/DP Connector Signal Constraints TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

T29DP_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

T29_I2C_55S T29_I2C I2C_T29_SCL 49 74

TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD
T29_I2C_55S T29_I2C I2C_T29_SDA 49 74

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

T29_SPI_CLK T29_SPI_55S T29_SPI T29_SPI_CLK 74

T29DP * =5x_DIELECTRIC ? T29DP TOP,BOTTOM =7x_DIELECTRIC ? T29_SPI_MOSI
T29_SPI_MOSI T29_SPI_55S T29_SPI 74

T29_SPI_MISO T29_SPI_55S T29_SPI T29_SPI_MISO 74

T29_SPI_CS_L T29_SPI_55S T29_SPI T29_SPI_CS_L 74

T29DP_90D T29DP T29_R2D_C_P<3..0> 74 77

T29DP_90D T29DP T29_R2D_C_N<3..0> 74 77

SOURCE: Bill Cornelius’s T29 Routing Notes T29_D2R_P<3..0>
T29DP_90D T29DP 74 77

T29DP_90D T29DP T29_D2R_N<3..0> 74 77

C C
T29/DP Net Properties
NET_TYPE
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING

T29_R2D0 T29DP_90D T29DP T29_R2D_P<0> 77

T29_R2D0 T29DP_90D T29DP T29_R2D_N<0> 77

T29_R2D1 T29DP_90D T29DP T29_R2D_P<1>

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77

T29_R2D1 T29DP_90D T29DP T29_R2D_N<1> 77

T29_D2R0 T29DP_90D T29DP T29_D2R_C_P<0> 77 78

T29_D2R0 T29DP_90D T29DP T29_D2R_C_N<0> 77 78

T29_D2R1 T29DP_90D T29DP T29_D2R_C_P<1> 77 78

T29_D2R1 T29DP_90D T29DP T29_D2R_C_N<1> 77 78

T29DP_90D T29DP T29_R2D_C_F_P<1..0> 77

T29DP_90D T29DP T29_R2D_C_F_N<1..0> 77

T29DP_90D T29DP T29DPA_D2R1_AUXCH_P 78

T29DP_90D T29DP T29DPA_D2R1_AUXCH_N 78

T29DP_90D T29DP DP_SDRVA_ML_C_P<3..0> 77

T29DP_90D T29DP DP_SDRVA_ML_C_N<3..0> 77

T29DP_90D T29DP DP_SDRVA_ML_R_P<3..0> 77

T29DP_90D T29DP DP_SDRVA_ML_R_N<3..0> 77

T29DP_90D T29DP DP_SDRVA_ML_P<2> 77

T29DP_90D T29DP DP_SDRVA_ML_N<2> 77

DP_SDRVA_ML T29DP_90D T29DP DP_SDRVA_ML_P<3> 77

DP_SDRVA_ML T29DP_90D T29DP DP_SDRVA_ML_N<3> 77

T29DP_90D T29DP DP_SDRVA_ML_P<0> 77

B T29DP_90D T29DP DP_SDRVA_ML_N<0> 77 B

DP_SDRVA_ML T29DP_90D T29DP DP_SDRVA_ML_P<1> 77

DP_SDRVA_ML T29DP_90D T29DP DP_SDRVA_ML_N<1> 77

DP_SDRVA_AUXCH T29DP_90D T29DP DP_SDRVA_AUXCH_P 77

DP_SDRVA_AUXCH T29DP_90D T29DP DP_SDRVA_AUXCH_N 77

T29DP_90D T29DP DP_SDRVA_AUXCH_C_P 77

T29DP_90D T29DP DP_SDRVA_AUXCH_C_N 77

T29DP_90D T29DP T29DPA_ML_P<3..0> 77 78

T29DP_90D T29DP T29DPA_ML_N<3..0> 77 78

T29DP_90D T29DP T29DPA_ML_C_P<3..0> 77 78

T29DP_90D T29DP T29DPA_ML_C_N<3..0> 77 78

T29DP_90D T29DP DP_A_EXT_AUXCH_P 77 78 83

T29DP_90D T29DP DP_A_EXT_AUXCH_N 77 78 83

T29DP_90D T29DP T29DPA_D2R1_AUXCH_CC_P

T29DP_90D T29DP T29DPA_D2R1_AUXCH_CC_N
T29DP_90D T29DP T29_D2R_CC_P<0>
T29DP_90D T29DP T29_D2R_CC_N<0>

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

T29 Constraints
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
105 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 86 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
SMC SMBus Net Properties
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

NET_TYPE
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
1TO1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SCL SMB_50S SMB 46 49

SMB_50S SMB SMBUS_SMC_A_S3_SDA 46 49

SMBUS_SMC_B_S0_SCL SMB_50S SMB SMBUS_SMC_B_S0_SCL 46 49

SMB_50S SMB SMBUS_SMC_B_S0_SDA 46 49

SMBUS_SMC_0_S0_SCL SMB_50S SMB SMBUS_SMC_0_S0_SCL 46 49

SMB_50S SMB SMBUS_SMC_0_S0_SDA 46 49

SMBUS_SMC_BSA_SCL SMB_50S SMB ENET_ASF_SMB_CLK 37 49

SMB_50S SMB ENET_ASF_SMB_DATA 37 49

D SMBUS_SMC_MGMT_SCL SMB_50S SMB SMBUS_SMC_MGMT_SCL 46 49 D

SMB_50S SMB SMBUS_SMC_MGMT_SDA 46 49

I83 SMB_50S SMB SMB_SMC_B_STR_SCL 49

I84 SMB_50S SMB SMB_SMC_B_STR_SDA 49

I85 SMB_50S SMB SMB_SMC_B_TSN_SCL 49

I86 SMB_50S SMB SMB_SMC_B_TSN_SDA 49

C C

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B B

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

SMC Constraints
DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
106 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 87 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
GDDR5 Frame Buffer Signal Constraints GDDR5 FB B Net Properties
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP NET_TYPE
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING

GDDR5_45R50SE * =50_OHM_SE =50_OHM_SE =50_OHM_SE 12.7 MM =STANDARD =STANDARD
TABLE_PHYSICAL_RULE_ITEM

FB_B0_CLK GDDR5_80D GDDR5_CLK FB_B0_CLK_P

GDDR5_45SE * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD FB_B0_CLK_N
TABLE_PHYSICAL_RULE_ITEM
FB_B0_CLK GDDR5_80D GDDR5_CLK
GDDR5_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF FB_B1_CLK GDDR5_80D GDDR5_CLK FB_B1_CLK_P
FB_B1_CLK GDDR5_80D GDDR5_CLK FB_B1_CLK_N
TABLE_SPACING_RULE_HEAD

FB_B0_CMD GDDR5_45R50SE GDDR5_CMD FB_B0_A<8..0>

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM
FB_B1_CMD GDDR5_45R50SE GDDR5_CMD FB_B1_A<8..0>
GDDR5_CLK * =5x_DIELECTRIC ? FB_B0_CMD GDDR5_45R50SE GDDR5_CMD FB_B0_ABI_L
TABLE_SPACING_RULE_ITEM

FB_B1_CMD GDDR5_45R50SE GDDR5_CMD FB_B1_ABI_L

D GDDR5_CMD * =2x_DIELECTRIC ?
TABLE_SPACING_RULE_ITEM
FB_B0_CMD GDDR5_45R50SE GDDR5_CMD FB_B0_RAS_L D
GDDR5_DATA * =3x_DIELECTRIC ? FB_B1_CMD GDDR5_45R50SE GDDR5_CMD FB_B1_RAS_L
TABLE_SPACING_RULE_ITEM

FB_B0_CMD GDDR5_45R50SE GDDR5_CMD FB_B0_CAS_L

GDDR5_EDC * =7x_DIELECTRIC ? FB_B1_CAS_L
FB_B1_CMD GDDR5_45R50SE GDDR5_CMD
FB_B0_CMD GDDR5_45R50SE GDDR5_CMD FB_B0_WE_L
FB_B1_CMD GDDR5_45R50SE GDDR5_CMD FB_B1_WE_L
FB_B0_CMD GDDR5_45R50SE GDDR5_CMD FB_B0_CKE_L
FB_B1_CMD GDDR5_45R50SE GDDR5_CMD FB_B1_CKE_L
FB_B0_CMD GDDR5_45R50SE GDDR5_CMD FB_B0_CS_L
FB_B1_CMD GDDR5_45R50SE GDDR5_CMD FB_B1_CS_L
FB_B0_EDC0 GDDR5_45SE GDDR5_EDC FB_B0_EDC<0>
I305 FB_B0_EDC1 GDDR5_45SE GDDR5_EDC FB_B0_EDC<1>
I306 FB_B0_EDC2 GDDR5_45SE GDDR5_EDC FB_B0_EDC<2>
I307 FB_B0_EDC3 GDDR5_45SE GDDR5_EDC FB_B0_EDC<3>
I310 FB_B1_EDC0 GDDR5_45SE GDDR5_EDC FB_B1_EDC<0>
I309 FB_B1_EDC1 GDDR5_45SE GDDR5_EDC FB_B1_EDC<1>
I308 FB_B1_EDC2 GDDR5_45SE GDDR5_EDC FB_B1_EDC<2>
FB_B1_EDC3 GDDR5_45SE GDDR5_EDC FB_B1_EDC<3>
FB_B0_DBI_L0 GDDR5_45SE GDDR5_DATA FB_B0_DBI_L<0>
I311 FB_B0_DBI_L1 GDDR5_45SE GDDR5_DATA FB_B0_DBI_L<1>
I312 FB_B0_DBI_L2 GDDR5_45SE GDDR5_DATA FB_B0_DBI_L<2>
I313 FB_B0_DBI_L3 GDDR5_45SE GDDR5_DATA FB_B0_DBI_L<3>
I316 FB_B1_DBI_L0 GDDR5_45SE GDDR5_DATA FB_B1_DBI_L<0>
I315 FB_B1_DBI_L1 GDDR5_45SE GDDR5_DATA FB_B1_DBI_L<1>
I314 FB_B1_DBI_L2 GDDR5_45SE GDDR5_DATA FB_B1_DBI_L<2>
FB_B1_DBI_L3 GDDR5_45SE GDDR5_DATA FB_B1_DBI_L<3>
FB_B0_WCLK_P<0>
C FB_B0_WCLK0
FB_B0_WCLK0
GDDR5_80D
GDDR5_80D
GDDR5_CMD
GDDR5_CMD FB_B0_WCLK_N<0> C
FB_B0_WCLK1 GDDR5_80D GDDR5_CMD FB_B0_WCLK_P<1>
FB_B0_WCLK1 GDDR5_80D GDDR5_CMD FB_B0_WCLK_N<1>
FB_B1_WCLK0 GDDR5_80D GDDR5_CMD FB_B1_WCLK_P<0>
FB_B1_WCLK0 GDDR5_80D GDDR5_CMD FB_B1_WCLK_N<0>
FB_B1_WCLK1 GDDR5_80D GDDR5_CMD FB_B1_WCLK_P<1>
FB_B1_WCLK1 GDDR5_80D GDDR5_CMD FB_B1_WCLK_N<1>

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FB_B0_DQ_BYTE0 GDDR5_45SE GDDR5_DATA FB_B0_DQ<7..0>
FB_B0_DQ_BYTE1 GDDR5_45SE GDDR5_DATA FB_B0_DQ<15..8>
FB_B0_DQ_BYTE2 GDDR5_45SE GDDR5_DATA FB_B0_DQ<23..16>
FB_B0_DQ_BYTE3 GDDR5_45SE GDDR5_DATA FB_B0_DQ<31..24>
FB_B1_DQ_BYTE0 GDDR5_45SE GDDR5_DATA FB_B1_DQ<7..0>
FB_B1_DQ_BYTE1 GDDR5_45SE GDDR5_DATA FB_B1_DQ<15..8>
FB_B1_DQ_BYTE2 GDDR5_45SE GDDR5_DATA FB_B1_DQ<23..16>
FB_B1_DQ_BYTE3 GDDR5_45SE GDDR5_DATA FB_B1_DQ<31..24>
FB_AB_RESET GDDR5_45R50SE GDDR5_CMD FB_RESET_L

Whistler Net Properties

NET_TYPE
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
B GPU_CLK27M CLK_SLOW_55S CLK_SLOW GPU_CLK27M
B
GPU_CLK100M CLK_SLOW_55S CLK_SLOW GPU_CLK100M
I317 100_OHM_DIFF 3X_DIELECTRIC GPU_CLK_TEST_N
I318 100_OHM_DIFF 3X_DIELECTRIC GPU_CLK_TEST_P

DP_AUX_CH DP_90D DISPLAYPORT DP_EG_AUX_CH_P

DP_90D DISPLAYPORT DP_EG_AUX_CH_N

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

GPU (Whistler) CONSTRAINTS

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
107 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 88 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
J40* SPECIFIC NET PROPERTIES
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_HEAD

ELECTRICAL_CONSTRAINT_SET
NET_TYPE
PHYSICAL SPACING
J40* SPECIFIC NET PROPERTIES
ON LAYER? NET_TYPE
TABLE_PHYSICAL_RULE_ITEM

SENSE_1TO1_55S * =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
TABLE_PHYSICAL_RULE_ITEM

THERM_1TO1_55S * =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR

TABLE_PHYSICAL_RULE_ITEM

SENSE_DIFFPAIR SENSE_1TO1_55S SENSE VCCSAS0_CS_P 50 64

DIFFPAIR * =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR VCCSAS0_CS_N
TABLE_PHYSICAL_RULE_ITEM
SENSE_1TO1_55S SENSE 50 64

AUDIODIFF * =1:1_DIFFPAIR 0.1 MM 0.1 MM 10 MM 0.1 MM 0.1 MM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

CPU_COMP GND * GND_P2MM

D SENSE * =2:1_SPACING ?
TABLE_SPACING_RULE_ITEM

CPU_VCCSENSE GND * GND_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM
SENSE_DIFFPAIR SENSE_1TO1_55S SENSE
SENSE_1TO1_55S SENSE
CPUVCCIOS0_CS_P
CPUVCCIOS0_CS_N
50 70

50 70
D
THERM * =2:1_SPACING ?
TABLE_SPACING_RULE_ITEM

AUDIO * =2:1_SPACING ?

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

ENETCONN * 25 MILS ? TABLE_SPACING_ASSIGNMENT_ITEM

ENET_MDI GND * GND_P2MM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_HEAD

GND * =STANDARD ? NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_ITEM

CLK_PCIE GND * GND_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD
PCIE GND * GND_P2MM
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM
SATA GND * GND_P2MM
GND_P2MM * 0.20 MM 1000 TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM
USB GND * GND_P2MM
PWR_P2MM * 0.20 MM 1000 TABLE_SPACING_ASSIGNMENT_ITEM

CLK_PCIE SB_POWER * PWR_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

SATA SB_POWER * PWR_P2MM

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

USB SB_POWER * PWR_P2MM

MEM_CLK GND * GND_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM

I372 SENSE_DIFFPAIR SENSE_1TO1_55S SENSE ISNS_HS_GPU_P

MEM_CMD GND * GND_P2MM
SENSE_1TO1_55S SENSE ISNS_HS_GPU_N
TABLE_SPACING_ASSIGNMENT_ITEM
I371
SB_POWER PP3V3_S5 6 17 18 19 20 21 23 24 25 27 28

C MEM_CTRL
MEM_DATA
GND
GND
*
*
GND_P2MM
GND_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM
59 61 62 78 91
C
TABLE_SPACING_ASSIGNMENT_ITEM
SB_POWER PP3V3_S0 50 51 52 53 57 58 60 61 62 67
6 7 13 17 18 19 20 21 23 24 27
30 31 34 37 38 39 40 41 47 49
71 72 73 74 76 77 79 91
MEM_DQS GND * GND_P2MM

TABLE_PHYSICAL_RULE_HEAD
GND GND
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?

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TABLE_PHYSICAL_RULE_ITEM

MEM_40S * 0.09 MM 2.54 MM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM

MEM_72D * 0.09 MM 2.54 MM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM

PCIE_85D * 0.09 MM 10 MM NET_TYPE

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
TABLE_PHYSICAL_RULE_ITEM

USB_85D TOP 0.1 MM 12.7 MM CPUTHMSNS_D2_P

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE SENSE_DIFFPAIR THERM_1TO1_55S THERM
TABLE_PHYSICAL_RULE_ITEM

THERM_1TO1_55S THERM CPUTHMSNS_D2_N

CPU_27P4S BOTTOM 0.23 MM 2.54 MM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE I287 SENSE_DIFFPAIR THERM_1TO1_55S THERM CPU_THERMD_P 10 52

I288 THERM_1TO1_55S THERM CPU_THERMD_N 10 52

SENSE_DIFFPAIR THERM_1TO1_55S THERM GPUTHMSNS_D_P

THERM_1TO1_55S THERM GPUTHMSNS_D_N
SENSE_DIFFPAIR THERM_1TO1_55S THERM GPU_TDIODE_P
THERM_1TO1_55S THERM GPU_TDIODE_N
I367 SENSE_DIFFPAIR THERM_1TO1_55S THERM T29_THERMD_P
I368 THERM_1TO1_55S THERM T29_THERMD_N

B B
Breakout Constraint Overrides
Alternate diffpair width/gap through BGA fanout areas
TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM

CLK_PCIE_90D BGA 100_DIFF_BGA MEM_40S BGA BGA_P075

TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM

DP_90D BGA 100_DIFF_BGA MEM_50S BGA BGA_P075

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TMDS_85D BGA TMDS_85D

TABLE_PHYSICAL_ASSIGNMENT_ITEM

ENET_100D BGA 100_DIFF_BGA

TABLE_PHYSICAL_ASSIGNMENT_ITEM

FW_110D BGA 100_DIFF_BGA

TABLE_PHYSICAL_ASSIGNMENT_ITEM

SATA_90D BGA 100_DIFF_BGA

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PCIE_85D BGA PCIE_85D

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MEM_85D BGA MEM_85D

TABLE_PHYSICAL_ASSIGNMENT_ITEM

USB_85D BGA USB_85D

TABLE_PHYSICAL_ASSIGNMENT_ITEM

GDDR5_80D BGA GDDR5_80D

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

Project Specific Constraints

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
108 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 89 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
J40* 12 LAYER BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS
TABLE_BOARD_INFO TABLE_PHYSICAL_RULE_HEAD

BOARD LAYERS BOARD AREAS BOARD UNITS ALLEGRO PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
(MIL or MM) VERSION ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA MM 15.5.1 1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

DEFAULT * Y =50_OHM_SE =50_OHM_SE 10 MM 0 MM 0 MM ALLOW ROUTE

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
STANDARD * Y =DEFAULT =DEFAULT 10 MM =DEFAULT =DEFAULT TABLE_PHYSICAL_RULE_ITEM

100_DIFF_BGA * =100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

100_DIFF_BGA ISL3,ISL4 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM

D PHYSICAL_RULE_SET LAYER ALLOW ROUTE
ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM

100_DIFF_BGA ISL9,ISL10 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM

TABLE_PHYSICAL_RULE_ITEM
D
27P4_OHM_SE TOP,BOTTOM Y 0.310 MM 0.095 MM
TABLE_PHYSICAL_RULE_ITEM

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.
27P4_OHM_SE * Y 0.250 MM 0.1 MM =STANDARD =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER? TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
37_OHM_SE TOP,BOTTOM Y 0.185 MM 0.095 MM ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

BGA_P075 TOP Y 0.110 MM 0.080 MM 10 MM

37_OHM_SE * Y 0.155 MM 0.090 MM =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM

BGA_P075 BOTTOM Y 0.110 MM 0.073 MM 10 MM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

40_OHM_SE TOP,BOTTOM Y 0.165 MM 0.095 MM

TABLE_PHYSICAL_RULE_ITEM

40_OHM_SE * Y 0.135 MM 0.090 MM =STANDARD =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

45_OHM_SE TOP,BOTTOM Y 0.13 MM 0.13 MM

TABLE_PHYSICAL_RULE_ITEM

45_OHM_SE * Y 0.099 MM 0.099 MM =STANDARD =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

50_OHM_SE TOP,BOTTOM Y 0.110 MM 0.095 MM

TABLE_PHYSICAL_RULE_ITEM

50_OHM_SE * Y 0.090 MM 0.090 MM =STANDARD =STANDARD =STANDARD

TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD

C PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP
TABLE_PHYSICAL_RULE_HEAD

DIFFPAIR NECK GAP

SPACING_RULE_SET

DEFAULT
LAYER

*
LINE-TO-LINE SPACING

0.1 MM
WEIGHT

?
TABLE_SPACING_RULE_ITEM
NET_SPACING_TYPE1

*
NET_SPACING_TYPE2

*
AREA_TYPE

BGA
SPACING_RULE_SET

BGA_P075MM
TABLE_SPACING_ASSIGNMENT_ITEM
C
TABLE_PHYSICAL_RULE_ITEM

55_OHM_SE TOP,BOTTOM Y 0.090 MM 0.090 MM TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM
STANDARD * =DEFAULT ?
55_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM

BGA_P1MM * =DEFAULT ?
TABLE_SPACING_RULE_ITEM

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

BGA_P2MM * =DEFAULT ?
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM

BGA_P075MM * 0.075 MM ?

www.teknisi-indonesia.com
TABLE_PHYSICAL_RULE_ITEM

72_OHM_DIFF * Y 0.154 MM 0.154 MM =STANDARD 0.200 MM 0.200 MM

TABLE_PHYSICAL_RULE_ITEM

72_OHM_DIFF TOP,BOTTOM Y 0.175 MM 0.175 MM 0.200 MM 0.200 MM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_HEAD
1.5:1_SPACING * 0.15 MM ? SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

ON LAYER? 2:1_SPACING * 0.2 MM ? 2X_DIELECTRIC * 0.140 MM ?

TABLE_PHYSICAL_RULE_ITEM

80_OHM_DIFF * Y 0.105 MM 0.105 MM =STANDARD 0.120 MM 0.120 MM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM
2.5:1_SPACING * 0.25 MM ? 3X_DIELECTRIC * 0.210 MM ?
80_OHM_DIFF TOP,BOTTOM Y 0.135 MM 0.135 MM 0.160 MM 0.160 MM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

3:1_SPACING * 0.3 MM ? 4X_DIELECTRIC * 0.280 MM ?

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

4:1_SPACING * 0.4 MM ? 5X_DIELECTRIC * 0.350 MM ?

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

5:1_SPACING * 0.5 MM ? 7X_DIELECTRIC * 0.490 MM ?

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP NOTE: Based on K92 mlb stackup.
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

B 85_OHM_DIFF * Y 0.110 MM 0.090 MM =STANDARD 0.180 MM 0.180 MM

TABLE_PHYSICAL_RULE_ITEM
B
85_OHM_DIFF TOP,BOTTOM Y 0.125 MM 0.090 MM 0.190 MM 0.190 MM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

90_OHM_DIFF * Y 0.102 MM 0.090 MM =STANDARD 0.220 MM 0.220 MM

TABLE_PHYSICAL_RULE_ITEM

90_OHM_DIFF TOP,BOTTOM Y 0.115 MM 0.090 MM 0.230 MM 0.230 MM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

100_OHM_DIFF * Y 0.080 MM 0.080 MM =STANDARD 0.200 MM 0.200 MM

TABLE_PHYSICAL_RULE_ITEM

100_OHM_DIFF TOP,BOTTOM Y 0.089 MM 0.089 MM 0.220 MM 0.220 MM

A SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
PAGE TITLE

PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP
TABLE_PHYSICAL_RULE_HEAD

DIFFPAIR NECK GAP PCB Rule Definitions

TABLE_PHYSICAL_RULE_ITEM

DRAWING NUMBER SIZE

110_OHM_DIFF * Y 0.065 MM 0.065 MM =STANDARD 0.200 MM 0.200 MM
TABLE_PHYSICAL_RULE_ITEM

Apple Inc. 051-8768 D

110_OHM_DIFF TOP,BOTTOM Y 0.075 MM 0.075 MM 0.330 MM 0.330 MM REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
109 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 90 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
NO_TEST NO_TEST NO_TEST
TRUE NC_AUD_GPIO_0 53 TRUE NC_AUD_GPIO_2 53 TRUE NC_AUD_HP_PORT_L 53

TRUE NC_AUD_HP_PORT_R TRUE NC_AUD_LO3_N_R TRUE NC_AUD_LO3_P_R

Airport/BT/Camera Conn. Speaker Connectors TRUE NC_AUD_MIC_INN_R
53

53 TRUE NC_AUD_MIC_INP_R
53

53 TRUE NC_BCM57765_CE_L_MS_INS_L
53

37

TRUE NC_CLINK_CLK 17 TRUE NC_CLINK_DATA 17 TRUE NC_CLINK_RESET_L 17

FUNC_TEST FUNC_TEST
TRUE NC_CRT_IG_BLUE 18 TRUE NC_CRT_IG_DDC_CLK 18 TRUE NC_CRT_IG_DDC_DATA 18
TRUE PCIE_AP_D2R_P 17 35 84 TRUE SPKRAMP_M_P_OUT 56 57
TRUE NC_CRT_IG_GREEN 18 TRUE NC_CRT_IG_HSYNC 18 TRUE NC_CRT_IG_RED 18
TRUE PCIE_AP_D2R_N 17 35 84 TRUE SPKRAMP_M_N_OUT 56 57
TRUE NC_CRT_IG_VSYNC 18 TRUE NC_CS4206_FP 53 TRUE NC_CS4206_MICBIAS 53
TRUE PCIE_AP_R2D_P 35 84
TRUE NC_DP_OC TRUE NC_EDP_AUXN 10 TRUE NC_EDP_AUXP 10
TRUE PCIE_AP_R2D_N 35 84
TRUE NC_EDP_TXN<3..0> 10 TRUE NC_EDP_TXP<3..0> 10 TRUE NC_FW_P1_TPAN 39
TRUE PCIE_CLK100M_AP_CONN_P
TRUE PCIE_CLK100M_AP_CONN_N
35 84

35 84
Fan Connectors TRUE NC_FW_P1_TPAP 39 TRUE NC_FW_P1_TPBIAS 39 TRUE NC_FW_P2_TPAN 39

TRUE NC_FW_P2_TPAP 39 TRUE NC_FW_P2_TPBIAS 39 TRUE NC_GPIO35 20

D TRUE

TRUE
AP_CLKREQ_Q_L
PCIE_WAKE_L
35

18 35 38 77
FUNC_TEST TRUE NC_HD_OC 80 TRUE NC_HDA_SDIN1 17 TRUE NC_HDA_SDIN2 17 D
TRUE NC_HDA_SDIN3 17 TRUE NC_IG_D_AUXN 18 TRUE NC_IG_D_AUXP 18
TRUE AP_RESET_CONN_L 35 TRUE PP12V_S0_FAN0_F 60
TRUE NC_IG_DP_T29SNK0_AUXCH_CN TRUE NC_IG_DP_T29SNK0_AUXCH_CP TRUE NC_IG_DP_T29SNK0_CTRL_CLK
TRUE WLAN_THROTTLE_L 35
TRUE FAN0_CTL_F 60 TRUE NC_IG_DP_T29SNK0_CTRL_DATA TRUE NC_IG_DP_T29SNK0_HPD TRUE NC_IG_DP_T29SNK0_ML_CN<3..0>
TRUE PP3V3_S4_BT_F 35
TRUE FAN0_TACH_F 60 TRUE NC_IG_DP_T29SNK0_ML_CP<3..0> TRUE NC_IRUC_P02 44 TRUE NC_IRUC_P03 44

TRUE PP3V3_WLAN 35 47 3 TPS TRUE NC_IRUC_P04 44 TRUE NC_IRUC_P06 44 TRUE NC_IRUC_P13 44

TRUE GND
1 TPS TRUE NC_IRUC_P14 44 TRUE NC_IRUC_P15 44 TRUE NC_IRUC_P16 44

TRUE USB_BT_CONN_P 35 83 TRUE NC_LPC_DREQ0_L 17 TRUE NC_LVDS_IG_A_CLKN 19 TRUE NC_LVDS_IG_A_CLKP 19

TRUE USB_BT_CONN_N 35 83 TRUE NC_LVDS_IG_A_DATAN<3..0> 19 TRUE NC_LVDS_IG_A_DATAP<3..0> 19 TRUE NC_LVDS_IG_B_CLKN 19

TRUE GND PSU CONNECTOR TRUE NC_LVDS_IG_B_CLKP 19 TRUE NC_LVDS_IG_B_DATAN<3..0> 19 TRUE NC_LVDS_IG_B_DATAP<3..0> 19

3 TPS TRUE NC_LVDS_IG_BKL_ON 19 TRUE NC_LVDS_IG_BKL_PWM 19 TRUE NC_LVDS_IG_CTRL_CLK 19

FUNC_TEST TRUE NC_LVDS_IG_CTRL_DATA 19 TRUE NC_LVDS_IG_DDC_CLK 19 TRUE NC_LVDS_IG_DDC_DATA 19

TRUE PP12V_G3H_PSU 6 51 72 4 TPS TRUE NC_LVDS_IG_PANEL_PWR 19 TRUE NC_LVDS_IG_VREFH 19 TRUE NC_LVDS_IG_VREFL 19

TRUE NC_OBSFN_B0 24 TRUE NC_OBSFN_B1 24 TRUE NC_OBSFN_C0 24

TRUE PSU_TEMP
SD Card Connector 46 72
TRUE NC_OBSFN_D01 24 TRUE NC_OBSFN_D11 24 TRUE NC_PCH_CLKOUT_DPN 17

NOT USED - REMOVE

FUNC_TEST
TRUE GND 4 TPS
TRUE
TRUE
NC_PCH_CLKOUT_DPP
NC_PCH_GPIO66_CLKOUTFLEX2
17

17
TRUE
TRUE
NC_PCH_GPIO64_CLKOUTFLEX0
NC_PCH_GPIO67_CLKOUTFLEX3
17

17
TRUE
TRUE
NC_PCH_GPIO65_CLKOUTFLEX1
NC_PCH_LVDS_IBG
17

19

FALSE SDCONN_DATA<7..0> 34 37 85 TRUE NC_PCH_LVDS_VBG 19 TRUE NC_PCI_PME_L 19 TRUE NC_PCIE_4_D2RN 17

FALSE SDCONN_CMD 34 37 85 TRUE NC_PCIE_4_D2RP 17 TRUE NC_PCIE_4_R2D_CN 17 TRUE NC_PCIE_4_R2D_CP 17

FALSE SDCONN_CLK 34 37 85 TRUE NC_PCIE_5_D2RN 17 TRUE NC_PCIE_5_D2RP 17 TRUE NC_PCIE_5_R2D_CN 17

FALSE SDCONN_DETECT 34 TRUE NC_PCIE_5_R2D_CP 17 TRUE NC_PCIE_6_D2RN 17 TRUE NC_PCIE_6_D2RP 17

FALSE SDCONN_WP 34 37 TRUE NC_PCIE_6_R2D_CN 17 TRUE NC_PCIE_6_R2D_CP 17 TRUE NC_PCIE_7_D2RN 17

FALSE PP3V3_SW_SD_PWR TRUE NC_PCIE_7_D2RP TRUE NC_PCIE_7_R2D_CN TRUE NC_PCIE_7_R2D_CP

34
Power Nets TRUE NC_PCIE_8_D2RN
17

17 TRUE NC_PCIE_8_D2RP
17

17 TRUE NC_PCIE_8_R2D_CN
17

17
TRUE GND
2 TPs TRUE NC_PCIE_8_R2D_CP 17 TRUE NC_PCIE_CLK100M_EXCARDN 17 TRUE NC_PCIE_CLK100M_EXCARDP 17
FUNC_TEST
TRUE NC_PCIE_CLK100M_PE5N 17 TRUE NC_PCIE_CLK100M_PE5P 17 TRUE NC_PCIE_CLK100M_PE6N 20
TRUE PP3V3_G3_RTC 6 17 18 21 27
NC_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7P
C TRUE

TRUE
PP5V_G3H
PP3V3_G3H
6 45 47 61 65

6 27 43 45 46 47 48 61 65 91
TRUE
TRUE NC_PCIE_CLK100M_PEBN
20

17
TRUE
TRUE NC_PCIE_CLK100M_PEBP
20

17
TRUE
TRUE NC_PCIE_CLK100M_T29N
20
C
TRUE NC_PCIE_CLK100M_T29P TRUE NC_PCIE_T29_D2RN<3..0> TRUE NC_PCIE_T29_D2RP<3..0>
SATA HDD Connector TRUE PP3V3_S5 6 17 18 19 20 21 23 24 25 27 28
59 61 62 78 89 TRUE NC_PCIE_T29_R2D_CN<3..0> TRUE NC_PCIE_T29_R2D_CP<3..0> TRUE NC_PEG_CLK100MN 8

TRUE NC_PEG_CLK100MP 8 TRUE NC_PEG_D2RN<7..0> 8 TRUE NC_PEG_D2RN<15..12> 10

FUNC_TEST TRUE PP3V3_ENET 6 26 37 38 62
80 91
TRUE NC_PEG_D2RP<7..0> 8 TRUE NC_PEG_D2RP<15..12> 10 TRUE NC_PEG_R2D_CN<7..0> 8
TRUE PP5V_S0 67 68 69 70
7 23 24 41 42 2 TPS TRUE PP1V2_ENET 6 37 38
48 61 62 64 TRUE NC_PEG_R2D_CN<15..12> 10 TRUE NC_PEG_R2D_CP<7..0> 8 TRUE NC_PEG_R2D_CP<15..12> 10
TRUE SATA_HDD1_D2R_CONN_P 42 83
71
TRUE NC_SATA_C_D2RN 17 TRUE NC_SATA_C_D2RP 17 TRUE NC_SATA_C_R2D_CN 17
SATA_HDD1_D2R_CONN_N PP5V_S4

www.teknisi-indonesia.com
TRUE 42 83 TRUE 6 28 43 44 45 61 65 66 78
TRUE NC_SATA_C_R2D_CP 17 TRUE NC_SATA_D_D2RN 17 TRUE NC_SATA_D_D2RP 17
TRUE SATA_HDD1_R2D_CONN_N 42 83 TRUE PP3V3_S4 6 19 20 25 28 33 34 35 38 47 49
50 61 77 78 TRUE NC_SATA_D_R2D_CN 17 TRUE NC_SATA_D_R2D_CP 17 TRUE NC_SATA_E_D2RN 17
TRUE SATA_HDD1_R2D_CONN_P 42 83 TRUE PP1V5_S3 6 28 30 31 32 61 66 72
TRUE NC_SATA_E_D2RP 17 TRUE NC_SATA_E_R2D_CN 17 TRUE NC_SATA_E_R2D_CP 17
TRUE PPDDRVREF_S3 6 33 66
TRUE GND 2 TPS TRUE NC_SATA_F_D2RN 17 TRUE NC_SATA_F_D2RP 17 TRUE NC_SATA_F_R2D_CN 17
TRUE PP5V_S0 7 23 24 41 42 48 61 62 64 67 68
69 70 71 80 91 TRUE NC_SATA_F_R2D_CP 17 TRUE NC_SDVO_INTN 18 TRUE NC_SDVO_INTP 18
TRUE PP3V3_S0 50 51 52 53 57
6 7 13 17 18 19 20 21 23 24 27
30 31 34 37 38 39 40 41 47 49 TRUE NC_SDVO_STALLN 18 TRUE NC_SDVO_STALLP 18 TRUE NC_SDVO_TVCLKINN 18
TRUE PP1V5_S0 58 60
7 17 21 23 39 53 71 72 61 71
62 73 TRUE NC_SDVO_TVCLKINP 18 TRUE NC_SMC_BMON_MUX_SEL 46 TRUE NC_SMC_FAN_1_CTL 46
TRUE PP1V05_S0_VCCIO 67 76
SATA HDD2 CONNECTOR TRUE PP0V75_S0_DDRVTT
7 10 11 13 15 67

7 28 30 31 66
72 79
74
77
TRUE NC_SMC_FAN_1_TACH 46 TRUE NC_SMC_FAN_2_CTL 46 TRUE NC_SMC_FAN_2_TACH 46
89
TRUE NC_SMC_FAN_3_CTL 46 TRUE NC_SMC_FAN_3_TACH 46 TRUE NC_SMC_P10 46
TRUE PPVCORE_S0_CPU 7 10 13 15 50 67 68
FUNC_TEST TRUE NC_SMC_P20 46 TRUE NC_SMC_P24 46 TRUE NC_SMC_P41 46

TRUE PP5V_S0 67 68 69 70
7 23 24 41 42 2 TPS TRUE NC_SMC_P43 46 TRUE NC_SMC_PF5 46 TRUE NC_SMC_RSTGATE_L 46
48 61 62 64
71 80 91
TRUE NC_SMC_SYS_KBDLED 46 TRUE NC_SPI_DESCRIPTOR_OVERRIDE_L 46 TRUE NC_T29_PWR_EN
TRUE SATA_HDD2_D2R_CONN_N 42 83
FW_PORT0_VP TRUE NC_USB_1N 19 TRUE NC_USB_1P 19 TRUE NC_USB_2N 19
TRUE SATA_HDD2_D2R_CONN_P 42 83 TRUE 41
TRUE NC_USB_2P 19 TRUE NC_USB_3N 19 TRUE NC_USB_3P 19
TRUE SATA_HDD2_R2D_CONN_N 42 83 TRUE PP3V3_S5_AVREF_SMC 46 47
TRUE NC_USB_4N 19 TRUE NC_USB_4P 19 TRUE NC_USB_5N 19
TRUE SATA_HDD2_R2D_CONN_P 42 83 TRUE PP4V5_AUDIO_ANALOG 53
TRUE NC_USB_5P 19 TRUE NC_USB_6N 19 TRUE NC_USB_6P 19
TRUE PP3V3R12V_SW_DPAPWR_F 78
NC_USB_7N NC_USB_7P NC_USB_9N
TRUE 19 TRUE 19 TRUE 19
TRUE PP5V_HDMI_DDC_CONN 80
TRUE GND 2 TPS TRUE NC_USB_9P 19 TRUE NC_USB_10N 19 TRUE NC_USB_10P 19

TRUE NC_USB_11N 19 TRUE NC_USB_11P 19 TRUE NC_USB_12N 19

B TRUE GND 1 TPS

TRUE NC_USB_12P 19 TRUE NC_USB_13N 19 TRUE NC_USB_13P 19 B
IR/LED,POWER BUTTON CONNECTORS
FUNC_TEST
PPIRRCVR_F TRUE NC_CPU_AXG_SENSEN TRUE NC_CPU_AXG_SENSEP TRUE NC_T29_R2D_CP1 74
TRUE 45 1 TPS
TRUE NC_CPU_AXG_VALSENSEP TRUE NC_CPU_AXG_VALSENSEN TRUE NC_T29_R2D_CP0 74
SMC_SYS_LED_DR NC_EG_DP_T29SNK0_AUXCH_CP NC_EG_DP_T29SNK0_AUXCH_CN NC_T29_R2D_CN1
TRUE 45 TRUE TRUE TRUE 74

TRUE IRRCVR_OUT 44 45 TRUE NC_EG_DP_T29SNK0_ML_CP<3..0> TRUE NC_EG_DP_T29SNK0_ML_CN<3..0> TRUE NC_T29_R2D_CN0 74

TRUE SMC_PM_G2_EN 46 47 62
TRUE POWER_BTN_N 45 TRUE NC_FB_A0_ABI_L TRUE NC_FB_A0_A<8..0> TRUE NC_T29_PCIE_RESET3_L 74
TRUE PM_SLP_S5_L 18 46 62
TRUE POWER_BTN_P 45 TRUE NC_FB_A0_CKE_L TRUE NC_FB_A0_CAS_L TRUE NC_T29_PCIE_RESET2_L 74
TRUE PM_SLP_S4_L 18 28 46 62
TRUE NC_FB_A0_CLKP TRUE NC_FB_A0_CLKN TRUE NC_T29_PCIE_RESET1_L 74
TRUE PM_SLP_S3_L 18 28 46 51 62
TRUE NC_FB_A0_DBI_L<3..0> TRUE NC_FB_A0_CS_L TRUE NC_T29_PCIE_RESET0_L 74
TRUE GND 1 TPS
TRUE NC_FB_A0_EDC<3..0> TRUE NC_FB_A0_DQ<31..0> TRUE NC_T29_D2RP1 74

TRUE NC_FB_A0_WCLKN<1..0> TRUE NC_FB_A0_RAS_L TRUE NC_T29_D2RP0 74

TRUE NC_FB_A0_WE_L TRUE NC_FB_A0_WCLKP<1..0> TRUE NC_T29_D2RN1

SPI BOOTROM SIGNALS TRUE NC_FB_A1_ABI_L TRUE NC_FB_A1_A<8..0> TRUE NC_T29_D2RN0
74

74

TRUE NC_FB_A1_CKE_L TRUE NC_FB_A1_CAS_L TRUE NC_DP_T29SRC_ML_CP<3..0> 74

FUNC_TEST
TEMPERATURE SENSOR CONNECTORS TRUE PP3V3_G3H
91
48 61
6 27 43 45 1 TPS
TRUE NC_FB_A1_CLKP TRUE NC_FB_A1_CLKN TRUE NC_DP_T29SRC_ML_CN<3..0> 74

46 47
65
TRUE NC_FB_A1_DBI_L<3..0> TRUE NC_FB_A1_CS_L TRUE NC_DP_T29SRC_AUXCH_CP 74

SPI_CS0_L NC_FB_A1_EDC<3..0> NC_FB_A1_DQ<31..0> NC_DP_T29SRC_AUXCH_CN

teknisi-indonesia
TRUE 48 84 TRUE TRUE TRUE 74

TRUE SPI_CLK 48 84 TRUE NC_FB_A1_WCLKN<1..0> TRUE NC_FB_A1_RAS_L TRUE NC_DP_T29SNK1_MLP<3..0> 74

TRUE SPI_MOSI 48 84 TRUE NC_FB_A1_WE_L TRUE NC_FB_A1_WCLKP<1..0> TRUE NC_DP_T29SNK1_MLN<3..0> 74

TRUE SPI_MISO 17 48 84 TRUE NC_GPU_GENERICB TRUE NC_DP_T29SNK1_AUXCHP 74

TRUE SPIROM_USE_MLB 20 48 59 TRUE NC_GPU_GENERICC TRUE NC_EDP_HPD 10 TRUE NC_DP_T29SNK1_AUXCHN 74

TRUE HDD_THRMD_P
NC_GPU_GENERICE
A TRUE HDD_THRMD_N TRUE GND 1 TPS
TRUE
TRUE NC_GPU_GENERICF SYNC_MASTER=REFERENCE_MLB SYNC_DATE=11/23/2010 A
TRUE NC_GPU_GENERICG PAGE TITLE

TRUE NC_LVDS_EG_A_CLKN FUNCTIONAL / ICT TEST PROPERTIES

TRUE NC_LVDS_EG_A_CLKP DRAWING NUMBER SIZE
TRUE NC_LVDS_EG_A_DATAN<3..0>
Apple Inc. 051-8768 D
TRUE NC_LVDS_EG_A_DATAP<3..0> REVISION
R
TRUE NC_LVDS_EG_B_CLKN 9.0.0
TRUE NC_LVDS_EG_B_CLKP NOTICE OF PROPRIETARY PROPERTY: BRANCH
TRUE NC_LVDS_EG_B_DATAN<3..0> THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
TRUE NC_LVDS_EG_B_DATAP<3..0> THE POSESSOR AGREES TO THE FOLLOWING: PAGE
TRUE NC_LVDS_EG_DDC_CLK I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
120 OF 512
TRUE NC_LVDS_EG_DDC_DATA III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 91 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

LAST SCHEMATIC PAGE.

FORCES CROSS REFERENCE PAGES TO COME AFTER THIS.
SKIPS ANY TEMPORARY PAGES I MIGHT MAKE.

C C

www.teknisi-indonesia.com
B B

A A
PAGE TITLE

LAST SCHEMATIC PAGE

DRAWING NUMBER SIZE

Apple Inc. 051-8768 D

REVISION
R
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
500 OF 512
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 92 OF 104
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Title: Basenet Report COMP_RC_1V8S0 COMP_RC_1V8S0 - @mlb_lib.MLB 71C8 DMI_N2S_N<3..0> DMI_N2S_N<3..0> - @mlb_lib.MLB 81D3 DP_SDRVA_ML_C_P<0> DP_SDRVA_ML_C_P<0> - @mlb_lib.MLB 77C6
Design: mlb CPUIMVP_ISUMG_IOUT CPUIMVP_ISUMG_IOUT - @mlb_lib.MLB 50B3 DMI_N2S_N<1> DMI_N2S_N<1> - @mlb_lib.MLB 10D8 18D8 DP_SDRVA_ML_C_P<3..0 DP_SDRVA_ML_C_P<3..0> - 86B3
Date: Apr 7 18:57:22 2011 CPUIMVP_ISUMG_RN CPUIMVP_ISUMG_RN - @mlb_lib.MLB 50B3 DMI_N2S_N<2> DMI_N2S_N<2> - @mlb_lib.MLB 10D8 18D8 > @mlb_lib.MLB
CPUIMVP_ISUM_IOUT CPUIMVP_ISUM_IOUT - @mlb_lib.MLB 50D2 DMI_N2S_N<3> DMI_N2S_N<3> - @mlb_lib.MLB 10D8 18D8 DP_SDRVA_ML_C_P<1> DP_SDRVA_ML_C_P<1> - @mlb_lib.MLB 77C6
Base nets and synonyms for mlb_lib.MLB(@mlb_lib.mlb(sch_1)) CPUIMVP_ISUM_RN CPUIMVP_ISUM_RN - @mlb_lib.MLB 50D3 DMI_N2S_P<0> DMI_N2S_P<0> - @mlb_lib.MLB 10D8 18D8 DP_SDRVA_ML_C_P<2> DP_SDRVA_ML_C_P<2> - @mlb_lib.MLB 77C6
Base Signal Synonyms Location([Zone][dir]) CPUTHMSNS_D2_N CPUTHMSNS_D2_N - @mlb_lib.MLB 89B1 DMI_N2S_P<3..0> DMI_N2S_P<3..0> - @mlb_lib.MLB 81D3 DP_SDRVA_ML_C_P<3> DP_SDRVA_ML_C_P<3> - @mlb_lib.MLB 77C6
CPUTHMSNS_D2_P CPUTHMSNS_D2_P - @mlb_lib.MLB 89B1 DMI_N2S_P<1> DMI_N2S_P<1> - @mlb_lib.MLB 10D8 18D8 DP_SDRVA_ML_N<0> DP_SDRVA_ML_N<0> - @mlb_lib.MLB 77C3 86B3
1V05_S0_LDO_EN 1V05_S0_LDO_EN - @mlb_lib.MLB 62C1 CPUVCCIOS0_AGND CPUVCCIOS0_AGND - @mlb_lib.MLB 70B6 DMI_N2S_P<2> DMI_N2S_P<2> - @mlb_lib.MLB 10D8 18D8 DP_SDRVA_ML_N<1> DP_SDRVA_ML_N<1> - @mlb_lib.MLB 77B3 86B3
CPUVCCIOS0_EN - @mlb_lib.MLB 62C1 70C7 CPUVCCIOS0_CS_N CPUVCCIOS0_CS_N - @mlb_lib.MLB 50B8 70B2 89D3 DMI_N2S_P<3> DMI_N2S_P<3> - @mlb_lib.MLB 10D8 18D8 DP_SDRVA_ML_N<2> DP_SDRVA_ML_N<2> - @mlb_lib.MLB 77C3 86B3
3V3R2V8_DPAPWR_ADJ 3V3R2V8_DPAPWR_ADJ - @mlb_lib.MLB 78D7 CPUVCCIOS0_CS_P CPUVCCIOS0_CS_P - @mlb_lib.MLB 50B8 70B2 89D3 DMI_S2N_N<0> DMI_S2N_N<0> - @mlb_lib.MLB 10D8 18D8 DP_SDRVA_ML_N<3> DP_SDRVA_ML_N<3> - @mlb_lib.MLB 77B3 86B3
3V3R2V8_SS_A 3V3R2V8_SS_A - @mlb_lib.MLB 78D8 CPUVCCIOS0_DRVH CPUVCCIOS0_DRVH - @mlb_lib.MLB 70C5 DMI_S2N_N<3..0> DMI_S2N_N<3..0> - @mlb_lib.MLB 81D3 DP_SDRVA_ML_P<0> DP_SDRVA_ML_P<0> - @mlb_lib.MLB 77C3 86B3
80101A_NC 80101A_NC - @mlb_lib.MLB 78C8 CPUVCCIOS0_DRVL CPUVCCIOS0_DRVL - @mlb_lib.MLB 70C5 DMI_S2N_N<1> DMI_S2N_N<1> - @mlb_lib.MLB 10D8 18D8 DP_SDRVA_ML_P<1> DP_SDRVA_ML_P<1> - @mlb_lib.MLB 77B3 86B3
=I2C_DPSDRVA_SCL =I2C_DPSDRVA_SCL - @mlb_lib.MLB 49B1 49B6 77B7 CPUVCCIOS0_FB CPUVCCIOS0_FB - @mlb_lib.MLB 70C6 DMI_S2N_N<2> DMI_S2N_N<2> - @mlb_lib.MLB 10D8 18D8 DP_SDRVA_ML_P<2> DP_SDRVA_ML_P<2> - @mlb_lib.MLB 77C3 86B3
I2C_DPSDRVA_SCL - @mlb_lib.MLB 49B2 49B7 CPUVCCIOS0_FSEL CPUVCCIOS0_FSEL - @mlb_lib.MLB 70B6 DMI_S2N_N<3> DMI_S2N_N<3> - @mlb_lib.MLB 10D8 18D8 DP_SDRVA_ML_P<3> DP_SDRVA_ML_P<3> - @mlb_lib.MLB 77B3 86B3

D =I2C_DPSDRVA_SDA =I2C_DPSDRVA_SDA - @mlb_lib.MLB

I2C_DPSDRVA_SDA - @mlb_lib.MLB
49B1 49B6 77B7
49B2 49B7
CPUVCCIOS0_LL
CPUVCCIOS0_OCSET
CPUVCCIOS0_LL - @mlb_lib.MLB
CPUVCCIOS0_OCSET - @mlb_lib.MLB
70C5
70C6
DMI_S2N_P<0>
DMI_S2N_P<3..0>
DMI_S2N_P<0> - @mlb_lib.MLB
DMI_S2N_P<3..0> - @mlb_lib.MLB
10D8 18D8
81D3
DP_SDRVA_ML_R_N<0>
DP_SDRVA_ML_R_N<3..0
DP_SDRVA_ML_R_N<0> - @mlb_lib.MLB
DP_SDRVA_ML_R_N<3..0> -
77C4
86B3
D
=IG_DP_T29SNK0_CTRL_ =IG_DP_T29SNK0_CTRL_CLK - 8B8 18C1 CPUVCCIOS0_PGOOD CPUVCCIOS0_PGOOD - @mlb_lib.MLB 62A6 62B5 70B7 DMI_S2N_P<1> DMI_S2N_P<1> - @mlb_lib.MLB 10D8 18D8 > @mlb_lib.MLB
CLK @mlb_lib.MLB CPUVCCIOS0_RTN CPUVCCIOS0_RTN - @mlb_lib.MLB 70B6 DMI_S2N_P<2> DMI_S2N_P<2> - @mlb_lib.MLB 10D8 18C8 DP_SDRVA_ML_R_N<2> DP_SDRVA_ML_R_N<2> - @mlb_lib.MLB 77C4
DP_T29SNK0_CTRL_CLK - @mlb_lib.MLB 8B5 74A8 CPUVCCIOS0_SREF CPUVCCIOS0_SREF - @mlb_lib.MLB 70C6 DMI_S2N_P<3> DMI_S2N_P<3> - @mlb_lib.MLB 10D8 18C8 DP_SDRVA_ML_R_P<0> DP_SDRVA_ML_R_P<0> - @mlb_lib.MLB 77C4
=IG_DP_T29SNK0_CTRL_ =IG_DP_T29SNK0_CTRL_DATA - 8B8 18C1 CPUVCCIOS0_VBST CPUVCCIOS0_VBST - @mlb_lib.MLB 70C5 DPACONN_20_RC DPACONN_20_RC - @mlb_lib.MLB 78A5 DP_SDRVA_ML_R_P<3..0 DP_SDRVA_ML_R_P<3..0> - 86B3
DATA @mlb_lib.MLB CPUVCCIOS0_VBST_RC CPUVCCIOS0_VBST_RC - @mlb_lib.MLB 70C5 DPAPWRSW_CT DPAPWRSW_CT - @mlb_lib.MLB 78D3 > @mlb_lib.MLB
DP_T29SNK0_CTRL_DATA - @mlb_lib.MLB 8B5 74A8 CPUVCCIOS0_VO CPUVCCIOS0_VO - @mlb_lib.MLB 70C6 DPAPWRSW_HVEN_L_R DPAPWRSW_HVEN_L_R - @mlb_lib.MLB 78D3 DP_SDRVA_ML_R_P<2> DP_SDRVA_ML_R_P<2> - @mlb_lib.MLB 77C4
=PLT_RST_T29_GPU =PLT_RST_T29_GPU - @mlb_lib.MLB 27C1 76C8 CPUVCCIO_IOUT CPUVCCIO_IOUT - @mlb_lib.MLB 50B7 DPAPWRSW_IFLT DPAPWRSW_IFLT - @mlb_lib.MLB 78D2 DP_T29SNK0_AUXCH_C_N DP_T29SNK0_AUXCH_C_N - @mlb_lib.MLB 8B5 74B8 83D1
PLT_RST_BUF_L - @mlb_lib.MLB 27C3 CPUVCCSAS0_SNUB CPUVCCSAS0_SNUB - @mlb_lib.MLB 70B3 DPAPWRSW_ILIM DPAPWRSW_ILIM - @mlb_lib.MLB 78D2 =IG_DP_T29SNK0_AUXCH_C_N - 8B8 18C1
=SMC_GFX_THROTTLE_L =SMC_GFX_THROTTLE_L - @mlb_lib.MLB 46C8 73B6 CPUVSENSE_IN CPUVSENSE_IN - @mlb_lib.MLB 50C3 DPLL_REF_CLKN DPLL_REF_CLKN - @mlb_lib.MLB 11C3 @mlb_lib.MLB
TP_GFX_THROTTLE_L - @mlb_lib.MLB 73B4 CPU_AXG_SENSE_N CPU_AXG_SENSE_N - @mlb_lib.MLB 13B4 67D8 81A3 DPLL_REF_CLKP DPLL_REF_CLKP - @mlb_lib.MLB 11C3 DP_T29SNK0_AUXCH_C_P DP_T29SNK0_AUXCH_C_P - @mlb_lib.MLB 8B5 74B8 83D1
ALL_SYS_PWRGD ALL_SYS_PWRGD - @mlb_lib.MLB 27A8 46D8 62A5 62C5 62C6 CPU_AXG_SENSE_P CPU_AXG_SENSE_P - @mlb_lib.MLB 13B4 67D8 81A3 DPSDRVA_CEXT DPSDRVA_CEXT - @mlb_lib.MLB 77B6 =IG_DP_T29SNK0_AUXCH_C_P - 8B8 18C1
ALL_SYS_PWRGD_R ALL_SYS_PWRGD_R - @mlb_lib.MLB 62A6 CPU_AXG_VALSENSE_N CPU_AXG_VALSENSE_N - @mlb_lib.MLB 10C4 81A3 DPSDRVA_I2C_ADDR0 DPSDRVA_I2C_ADDR0 - @mlb_lib.MLB 77B7 @mlb_lib.MLB
AMBIENT_THRMD_N AMBIENT_THRMD_N - @mlb_lib.MLB 52B3 52C8 CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_P - @mlb_lib.MLB 10C4 81A3 DPSDRVA_I2C_ADDR1 DPSDRVA_I2C_ADDR1 - @mlb_lib.MLB 77B7 DP_T29SNK0_AUXCH_N DP_T29SNK0_AUXCH_N - @mlb_lib.MLB 74B5 74B6 83D1
AMBIENT_THRMD_P AMBIENT_THRMD_P - @mlb_lib.MLB 52B3 52C8 CPU_CATERR_L CPU_CATERR_L - @mlb_lib.MLB 6B3 11C6 81B3 DPSDRVA_I2C_CTL_EN DPSDRVA_I2C_CTL_EN - @mlb_lib.MLB 77B7 DP_T29SNK0_AUXCH_P DP_T29SNK0_AUXCH_P - @mlb_lib.MLB 74B5 74B6 83D1
AP_CLKREQ_L AP_CLKREQ_L - @mlb_lib.MLB 17B4 17B5 35A3 CPU_CATERR_RL CPU_CATERR_RL - @mlb_lib.MLB 6B3 DPSDRVA_REXT DPSDRVA_REXT - @mlb_lib.MLB 77B7 DP_T29SNK0_DDC_CLK DP_T29SNK0_DDC_CLK - @mlb_lib.MLB 83C1
AP_CLKREQ_Q_L AP_CLKREQ_Q_L - @mlb_lib.MLB 35A4 91D7 CPU_CFG<0> CPU_CFG<0> - @mlb_lib.MLB 10A7 10D3 24C8 DP_AUXCH_ISOL DP_AUXCH_ISOL - @mlb_lib.MLB 17C5 77B7 DP_T29SNK0_DDC_DATA DP_T29SNK0_DDC_DATA - @mlb_lib.MLB 83C1
AP_PWR_EN AP_PWR_EN - @mlb_lib.MLB 19C1 24D4 35A3 62A4 CPU_CFG<11..0> CPU_CFG<11..0> - @mlb_lib.MLB 81B3 DP_AUX_CH_CK_N DP_AUX_CH_CK_N - @mlb_lib.MLB 83D1 DP_T29SNK0_HPD DP_T29SNK0_HPD - @mlb_lib.MLB 8B5 74B6 83C1
AP_RESET_CONN_L AP_RESET_CONN_L - @mlb_lib.MLB 35B4 91D7 CPU_CFG<1> CPU_CFG<1> - @mlb_lib.MLB 10A7 10D3 DP_AUX_CH_CK_P DP_AUX_CH_CK_P - @mlb_lib.MLB 83D1 =IG_DP_T29SNK0_HPD - @mlb_lib.MLB 8B8 18C1
AP_RESET_L AP_RESET_L - @mlb_lib.MLB 27D1 35B3 CPU_CFG<2> CPU_CFG<2> - @mlb_lib.MLB 10A8 10D3 DP_AUX_CH_C_N DP_AUX_CH_C_N - @mlb_lib.MLB 83D1 DP_T29SNK0_ML_C_N<0> DP_T29SNK0_ML_C_N<0> - @mlb_lib.MLB 74B8
AUD_4V5_REG_IN AUD_4V5_REG_IN - @mlb_lib.MLB 53A6 CPU_CFG<3> CPU_CFG<3> - @mlb_lib.MLB 10A7 10D3 DP_AUX_CH_C_P DP_AUX_CH_C_P - @mlb_lib.MLB 83D1 =IG_DP_T29SNK0_ML_C_N<3..0> - 8B8
AUD_CONNJ1_MIC_HI AUD_CONNJ1_MIC_HI - @mlb_lib.MLB 57D7 CPU_CFG<4> CPU_CFG<4> - @mlb_lib.MLB 10A8 10D3 DP_A_BIAS DP_A_BIAS - @mlb_lib.MLB 76B5 77C3 @mlb_lib.MLB
AUD_CONNJ1_PERIPHDET AUD_CONNJ1_PERIPHDET - @mlb_lib.MLB 57C7 CPU_CFG<5> CPU_CFG<5> - @mlb_lib.MLB 10A8 10D3 DP_A_BIAS0N DP_A_BIAS0N - @mlb_lib.MLB 76B3 77C1 DP_T29SNK0_ML_C_N<3. DP_T29SNK0_ML_C_N<3..0> - 8B5 83C1
AUD_CONNJ1_RING AUD_CONNJ1_RING - @mlb_lib.MLB 57D7 CPU_CFG<6> CPU_CFG<6> - @mlb_lib.MLB 10A8 10D3 DP_A_BIAS0P DP_A_BIAS0P - @mlb_lib.MLB 76B3 77C1 .0> @mlb_lib.MLB
AUD_CONNJ1_SLEEVE AUD_CONNJ1_SLEEVE - @mlb_lib.MLB 57C7 CPU_CFG<7> CPU_CFG<7> - @mlb_lib.MLB 10A8 10D3 DP_A_BIAS2N DP_A_BIAS2N - @mlb_lib.MLB 76A3 77C1 =IG_DP_T29SNK0_ML_C_N<3..0> - 8B8
AUD_CONNJ1_SLEEVEDET AUD_CONNJ1_SLEEVEDET - @mlb_lib.MLB 57D7 CPU_CFG<16> CPU_CFG<16> - @mlb_lib.MLB 10A7 10D3 DP_A_BIAS2P DP_A_BIAS2P - @mlb_lib.MLB 76B3 77C1 @mlb_lib.MLB
AUD_CONNJ1_TIP AUD_CONNJ1_TIP - @mlb_lib.MLB 57D7 CPU_CFG<17..16> CPU_CFG<17..16> - @mlb_lib.MLB 81B3 DP_A_CA_DET DP_A_CA_DET - @mlb_lib.MLB 77A7 77B5 DP_T29SNK0_ML_C_N<1> DP_T29SNK0_ML_C_N<1> - @mlb_lib.MLB 74B8
AUD_CONNJ1_TIPDET AUD_CONNJ1_TIPDET - @mlb_lib.MLB 57C7 CPU_COMP0 CPU_COMP0 - @mlb_lib.MLB 81B3 DP_A_EXT_AUXCH_N DP_A_EXT_AUXCH_N - @mlb_lib.MLB 77B1 78A7 83D1 86B3 =IG_DP_T29SNK0_ML_C_N<3..0> - 8B8
AUD_CONNJ2_RING AUD_CONNJ2_RING - @mlb_lib.MLB 57B6 CPU_COMP1 CPU_COMP1 - @mlb_lib.MLB 81B3 DP_A_EXT_AUXCH_P DP_A_EXT_AUXCH_P - @mlb_lib.MLB 77B1 78A7 83D1 86B3 @mlb_lib.MLB
AUD_CONNJ2_SLEEVE AUD_CONNJ2_SLEEVE - @mlb_lib.MLB 57B6 CPU_COMP2 CPU_COMP2 - @mlb_lib.MLB 81B3 DP_A_EXT_HPD DP_A_EXT_HPD - @mlb_lib.MLB 77A4 77B1 DP_T29SNK0_ML_C_N<2> DP_T29SNK0_ML_C_N<2> - @mlb_lib.MLB 74B8
AUD_CONNJ2_TIP AUD_CONNJ2_TIP - @mlb_lib.MLB 57B6 CPU_COMP3 CPU_COMP3 - @mlb_lib.MLB 81B3 DP_A_PWRDWN DP_A_PWRDWN - @mlb_lib.MLB 77A8 77B3 77C4 =IG_DP_T29SNK0_ML_C_N<3..0> - 8B8

C AUD_CONNJ2_TIPDET
AUD_GPIO_1
AUD_CONNJ2_TIPDET - @mlb_lib.MLB
AUD_GPIO_1 - @mlb_lib.MLB
57B6
53D7 55B6
CPU_DC_TEST_BE59_BE6
1
CPU_DC_TEST_BE59_BE61 -
@mlb_lib.MLB
10C2 DP_A_PWRDWN_FET_R
DP_A_PWRDWN_INV
DP_A_PWRDWN_FET_R - @mlb_lib.MLB
DP_A_PWRDWN_INV - @mlb_lib.MLB
78C6
78D5 DP_T29SNK0_ML_C_N<3>
@mlb_lib.MLB
DP_T29SNK0_ML_C_N<3> - @mlb_lib.MLB 74B8
C
AUD_GPIO_3 AUD_GPIO_3 - @mlb_lib.MLB 53C7 56B7 CPU_DC_TEST_BG59_BG6 CPU_DC_TEST_BG59_BG61 - 10C2 DP_A_PWRDWN_R DP_A_PWRDWN_R - @mlb_lib.MLB 77B7 =IG_DP_T29SNK0_ML_C_N<3..0> - 8B8
AUD_HPAMP_INL_N AUD_HPAMP_INL_N - @mlb_lib.MLB 55C5 1 @mlb_lib.MLB DP_EG_AUX_CH_N DP_EG_AUX_CH_N - @mlb_lib.MLB 88A1 @mlb_lib.MLB
AUD_HPAMP_INL_P AUD_HPAMP_INL_P - @mlb_lib.MLB 55C5 CPU_DC_TEST_C4_BE1_B CPU_DC_TEST_C4_BE1_BG1 - 10B2 DP_EG_AUX_CH_P DP_EG_AUX_CH_P - @mlb_lib.MLB 88A1 DP_T29SNK0_ML_C_P<0> DP_T29SNK0_ML_C_P<0> - @mlb_lib.MLB 74B8
AUD_HPAMP_INR_N AUD_HPAMP_INR_N - @mlb_lib.MLB 55B5 G1 @mlb_lib.MLB DP_EXTA_AUXCH_C_N DP_EXTA_AUXCH_C_N - @mlb_lib.MLB 8C5 77D8 83D1 =IG_DP_T29SNK0_ML_C_P<3..0> - 8B8
AUD_HPAMP_INR_P AUD_HPAMP_INR_P - @mlb_lib.MLB 55C5 CPU_DC_TEST_C4_BE3_B CPU_DC_TEST_C4_BE3_BG3 - 10C2 =IG_DP_EXTA_AUXCH_C_N - 8C8 18D1 @mlb_lib.MLB
AUD_HPAMP_MUTE_L AUD_HPAMP_MUTE_L - @mlb_lib.MLB 55B5 G3 @mlb_lib.MLB @mlb_lib.MLB DP_T29SNK0_ML_C_P<3. DP_T29SNK0_ML_C_P<3..0> - 8B5 83C1
AUD_HPAMP_OUTL AUD_HPAMP_OUTL - @mlb_lib.MLB 55C1 55C5 57D3 CPU_DC_TEST_C4_D3 CPU_DC_TEST_C4_D3 - @mlb_lib.MLB 10C2 DP_EXTA_AUXCH_C_P DP_EXTA_AUXCH_C_P - @mlb_lib.MLB 8C5 77D8 83D1 .0> @mlb_lib.MLB

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AUD_HPAMP_OUTR AUD_HPAMP_OUTR - @mlb_lib.MLB 55B1 55B5 57D3 CPU_DC_TEST_C59_A59 CPU_DC_TEST_C59_A59 - @mlb_lib.MLB 10C2 =IG_DP_EXTA_AUXCH_C_P - 8C8 18D1 =IG_DP_T29SNK0_ML_C_P<3..0> - 8B8
AUD_HPAMP_RETURN AUD_HPAMP_RETURN - @mlb_lib.MLB 55B1 57C3 CPU_DC_TEST_C61_A61 CPU_DC_TEST_C61_A61 - @mlb_lib.MLB 10C2 @mlb_lib.MLB @mlb_lib.MLB
AUD_HPREF AUD_HPREF - @mlb_lib.MLB 53D3 CPU_DDR_VREF CPU_DDR_VREF - @mlb_lib.MLB 13B1 13C1 DP_EXTA_AUXCH_N DP_EXTA_AUXCH_N - @mlb_lib.MLB 77B7 77D6 83D1 DP_T29SNK0_ML_C_P<1> DP_T29SNK0_ML_C_P<1> - @mlb_lib.MLB 74B8
AUD_I2C_INT_L AUD_I2C_INT_L - @mlb_lib.MLB 19D6 58D5 CPU_MEM_RESET_L CPU_MEM_RESET_L - @mlb_lib.MLB 11B6 28A8 DP_EXTA_AUXCH_P DP_EXTA_AUXCH_P - @mlb_lib.MLB 77B7 77D6 83D1 =IG_DP_T29SNK0_ML_C_P<3..0> - 8B8
AUD_INJACK_INSERT_L AUD_INJACK_INSERT_L - @mlb_lib.MLB 58A5 CPU_MEM_VREFDQ_A CPU_MEM_VREFDQ_A - @mlb_lib.MLB 10B2 10D1 DP_EXTA_DDC_CLK DP_EXTA_DDC_CLK - @mlb_lib.MLB 8C5 77B4 77B7 83D1 @mlb_lib.MLB
AUD_IPHS_SWITCH_EN AUD_IPHS_SWITCH_EN - @mlb_lib.MLB 20B1 58D5 CPU_MEM_VREFDQ_B CPU_MEM_VREFDQ_B - @mlb_lib.MLB 10B2 10D1 =IG_DP_EXTA_DDC_CLK - @mlb_lib.MLB 8C8 18D1 DP_T29SNK0_ML_C_P<2> DP_T29SNK0_ML_C_P<2> - @mlb_lib.MLB 74B8
AUD_IPHS_SWITCH_EN_P AUD_IPHS_SWITCH_EN_PCH - 20A1 20B3 20D6 CPU_PECI CPU_PECI - @mlb_lib.MLB 11C6 20D3 46A4 81C3 DP_EXTA_DDC_CLK_AUX_ DP_EXTA_DDC_CLK_AUX_P - 83D1 =IG_DP_T29SNK0_ML_C_P<3..0> - 8B8
CH @mlb_lib.MLB CPU_PECI_R CPU_PECI_R - @mlb_lib.MLB 46A5 81C3 P @mlb_lib.MLB @mlb_lib.MLB
AUD_IP_PERIPHERAL_DE AUD_IP_PERIPHERAL_DET - 19D6 58B1 CPU_PEG_COMP CPU_PEG_COMP - @mlb_lib.MLB 10D5 81B3 DP_EXTA_DDC_DATA DP_EXTA_DDC_DATA - @mlb_lib.MLB 8C5 77B4 77B7 83D1 DP_T29SNK0_ML_C_P<3> DP_T29SNK0_ML_C_P<3> - @mlb_lib.MLB 74B8
T @mlb_lib.MLB CPU_PEG_RBIAS CPU_PEG_RBIAS - @mlb_lib.MLB 81B3 =IG_DP_EXTA_DDC_DATA - @mlb_lib.MLB 8C8 18D1 =IG_DP_T29SNK0_ML_C_P<3..0> - 8B8
AUD_J1_DET_RC AUD_J1_DET_RC - @mlb_lib.MLB 58B7 CPU_PROCHOT_BUF CPU_PROCHOT_BUF - @mlb_lib.MLB 47D2 DP_EXTA_DDC_DATA_AUX DP_EXTA_DDC_DATA_AUX_N - 83D1 @mlb_lib.MLB
AUD_J1_PERIPHDET AUD_J1_PERIPHDET - @mlb_lib.MLB 57C3 58A4 CPU_PROCHOT_L CPU_PROCHOT_L - @mlb_lib.MLB 11C7 47D4 67B6 81B3 _N @mlb_lib.MLB DP_T29SNK0_ML_N<0> DP_T29SNK0_ML_N<0> - @mlb_lib.MLB 74B5 74B6
AUD_J1_PERIPHDET_INV AUD_J1_PERIPHDET_INV - @mlb_lib.MLB 58A2 CPU_PROCHOT_L_R CPU_PROCHOT_L_R - @mlb_lib.MLB 47D3 DP_EXTA_HPD DP_EXTA_HPD - @mlb_lib.MLB 8C5 77B7 77B8 83D1 DP_T29SNK0_ML_N<3..0 DP_T29SNK0_ML_N<3..0> - 83C1
AUD_J1_SLEEVEDET AUD_J1_SLEEVEDET - @mlb_lib.MLB 57D3 58C6 58C8 CPU_PROCHOT_R_L CPU_PROCHOT_R_L - @mlb_lib.MLB 11C6 =IG_DP_EXTA_HPD - @mlb_lib.MLB 8C8 18D1 > @mlb_lib.MLB
AUD_J1_SLEEVEDET_INV AUD_J1_SLEEVEDET_INV - @mlb_lib.MLB 58C7 CPU_PROC_SEL_L CPU_PROC_SEL_L - @mlb_lib.MLB 11C6 18B4 81B3 DP_EXTA_ML_C_N<0> DP_EXTA_ML_C_N<0> - @mlb_lib.MLB 77D8 DP_T29SNK0_ML_N<1> DP_T29SNK0_ML_N<1> - @mlb_lib.MLB 74B5 74B6
AUD_J1_TIPDET AUD_J1_TIPDET - @mlb_lib.MLB 57C3 58B8 CPU_PROX_THRM_N CPU_PROX_THRM_N - @mlb_lib.MLB 52D3 52D8 =IG_DP_EXTA_ML_C_N<3..0> - 8C8 DP_T29SNK0_ML_N<2> DP_T29SNK0_ML_N<2> - @mlb_lib.MLB 74B5 74B6
AUD_J2_DET_RC AUD_J2_DET_RC - @mlb_lib.MLB 58A6 CPU_PROX_THRM_P CPU_PROX_THRM_P - @mlb_lib.MLB 52D3 52D8 @mlb_lib.MLB DP_T29SNK0_ML_N<3> DP_T29SNK0_ML_N<3> - @mlb_lib.MLB 74B5 74B6
AUD_J2_OPT_OUT AUD_J2_OPT_OUT - @mlb_lib.MLB 57B6 CPU_PSI_L CPU_PSI_L - @mlb_lib.MLB 81B3 DP_EXTA_ML_C_N<3..0> DP_EXTA_ML_C_N<3..0> - @mlb_lib.MLB 8C5 83D1 DP_T29SNK0_ML_P<0> DP_T29SNK0_ML_P<0> - @mlb_lib.MLB 74B5 74B6
AUD_J2_TIPDET_R AUD_J2_TIPDET_R - @mlb_lib.MLB 57B3 58A7 CPU_PWRGD CPU_PWRGD - @mlb_lib.MLB 11C6 20D3 24C8 81B3 =IG_DP_EXTA_ML_C_N<3..0> - 8C8 DP_T29SNK0_ML_P<3..0 DP_T29SNK0_ML_P<3..0> - 83C1
AUD_LI_GND AUD_LI_GND - @mlb_lib.MLB 54C6 57B3 CPU_RESET_L CPU_RESET_L - @mlb_lib.MLB 11B7 24C3 27C1 @mlb_lib.MLB > @mlb_lib.MLB
AUD_LI_INL AUD_LI_INL - @mlb_lib.MLB 54D6 57B3 PLT_RST_CPU_BUF_L - @mlb_lib.MLB 27C3 DP_EXTA_ML_C_N<1> DP_EXTA_ML_C_N<1> - @mlb_lib.MLB 77D8 DP_T29SNK0_ML_P<1> DP_T29SNK0_ML_P<1> - @mlb_lib.MLB 74B5 74B6
AUD_LI_INR AUD_LI_INR - @mlb_lib.MLB 54C6 57B3 CPU_SM_RCOMP<0> CPU_SM_RCOMP<0> - @mlb_lib.MLB 11B5 =IG_DP_EXTA_ML_C_N<3..0> - 8C8 DP_T29SNK0_ML_P<2> DP_T29SNK0_ML_P<2> - @mlb_lib.MLB 74B5 74B6
AUD_LI_LF AUD_LI_LF - @mlb_lib.MLB 54D5 CPU_SM_RCOMP<2..0> CPU_SM_RCOMP<2..0> - @mlb_lib.MLB 81C3 @mlb_lib.MLB DP_T29SNK0_ML_P<3> DP_T29SNK0_ML_P<3> - @mlb_lib.MLB 74B5 74B6

B AUD_LI_N_LR
AUD_LI_P_L
AUD_LI_N_LR - @mlb_lib.MLB
AUD_LI_P_L - @mlb_lib.MLB
53C2
53C2
54C3
54D3
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>
CPU_SM_RCOMP<1> - @mlb_lib.MLB
CPU_SM_RCOMP<2> - @mlb_lib.MLB
11B5
11B5
DP_EXTA_ML_C_N<2> DP_EXTA_ML_C_N<2> - @mlb_lib.MLB
=IG_DP_EXTA_ML_C_N<3..0> -
77D8
8C8
DP_T29SNK1_AUXCH_C_N
DP_T29SNK1_AUXCH_C_P
DP_T29SNK1_AUXCH_C_N - @mlb_lib.MLB
DP_T29SNK1_AUXCH_C_P - @mlb_lib.MLB
83C1
83C1 B
AUD_LI_P_R AUD_LI_P_R - @mlb_lib.MLB 53C2 54C3 CPU_THERMD_N CPU_THERMD_N - @mlb_lib.MLB 10C4 52D2 52D8 89B1 @mlb_lib.MLB DP_T29SNK1_AUXCH_N DP_T29SNK1_AUXCH_N - @mlb_lib.MLB 83C1
AUD_LI_RF AUD_LI_RF - @mlb_lib.MLB 54C5 CPU_THERMD_P CPU_THERMD_P - @mlb_lib.MLB 10C4 52D2 52D8 89B1 DP_EXTA_ML_C_N<3> DP_EXTA_ML_C_N<3> - @mlb_lib.MLB 77D8 DP_T29SNK1_AUXCH_P DP_T29SNK1_AUXCH_P - @mlb_lib.MLB 83C1
AUD_LO2_N_L AUD_LO2_N_L - @mlb_lib.MLB 53D2 55C8 CPU_VCCIOSENSE_N CPU_VCCIOSENSE_N - @mlb_lib.MLB 13A5 70C8 81A3 =IG_DP_EXTA_ML_C_N<3..0> - 8C8 DP_T29SNK1_HPD DP_T29SNK1_HPD - @mlb_lib.MLB 83C1
AUD_LO2_N_R AUD_LO2_N_R - @mlb_lib.MLB 53C2 55B8 CPU_VCCIOSENSE_P CPU_VCCIOSENSE_P - @mlb_lib.MLB 13A5 70C8 81B3 @mlb_lib.MLB DP_T29SNK1_ML_C_N<3. DP_T29SNK1_ML_C_N<3..0> - 83C1
AUD_LO2_P_L AUD_LO2_P_L - @mlb_lib.MLB 53D2 55C8 CPU_VCCIO_SEL CPU_VCCIO_SEL - @mlb_lib.MLB 13B7 DP_EXTA_ML_C_P<0> DP_EXTA_ML_C_P<0> - @mlb_lib.MLB 77D8 .0> @mlb_lib.MLB
AUD_LO2_P_R AUD_LO2_P_R - @mlb_lib.MLB 53D2 55B8 CPU_VCCSA_SENSE CPU_VCCSA_SENSE - @mlb_lib.MLB 13C1 64C8 =IG_DP_EXTA_ML_C_P<3..0> - 8C8 DP_T29SNK1_ML_C_P<3. DP_T29SNK1_ML_C_P<3..0> - 83C1
AUD_LO3_N_L AUD_LO3_N_L - @mlb_lib.MLB 53C2 56C7 CPU_VCCSA_VID<0> CPU_VCCSA_VID<0> - @mlb_lib.MLB 13C1 64A6 @mlb_lib.MLB .0> @mlb_lib.MLB
AUD_LO3_P_L AUD_LO3_P_L - @mlb_lib.MLB 53C2 56B7 PD_CPU_VCCSA_VID0 - @mlb_lib.MLB 64A5 DP_EXTA_ML_C_P<3..0> DP_EXTA_ML_C_P<3..0> - @mlb_lib.MLB 8C5 83C1 DP_T29SNK1_ML_N<3..0 DP_T29SNK1_ML_N<3..0> - 83C1
AUD_MIC_INN_L AUD_MIC_INN_L - @mlb_lib.MLB 53C2 58C4 CPU_VCCSA_VID<1> CPU_VCCSA_VID<1> - @mlb_lib.MLB 13C1 64B6 81C3 =IG_DP_EXTA_ML_C_P<3..0> - 8C8 > @mlb_lib.MLB
AUD_MIC_INP_L AUD_MIC_INP_L - @mlb_lib.MLB 53C2 58C4 CPU_VCCSENSE_N CPU_VCCSENSE_N - @mlb_lib.MLB 13A5 67A8 81B3 @mlb_lib.MLB DP_T29SNK1_ML_P<3..0 DP_T29SNK1_ML_P<3..0> - 83C1
AUD_OUTJACK_INSERT_L AUD_OUTJACK_INSERT_L - @mlb_lib.MLB 58B6 CPU_VCCSENSE_P CPU_VCCSENSE_P - @mlb_lib.MLB 13A5 67A8 81B3 DP_EXTA_ML_C_P<1> DP_EXTA_ML_C_P<1> - @mlb_lib.MLB 77D8 > @mlb_lib.MLB
AUD_PERIPH_DET_R AUD_PERIPH_DET_R - @mlb_lib.MLB 58B2 CPU_VCC_VALSENSE_N CPU_VCC_VALSENSE_N - @mlb_lib.MLB 10C4 81A3 =IG_DP_EXTA_ML_C_P<3..0> - 8C8 EDP_COMP EDP_COMP - @mlb_lib.MLB 10C7
AUD_PORT_D_DET_L AUD_PORT_D_DET_L - @mlb_lib.MLB 58C5 CPU_VCC_VALSENSE_P CPU_VCC_VALSENSE_P - @mlb_lib.MLB 10C4 81A3 @mlb_lib.MLB ENET_ASF_GPIO ENET_ASF_GPIO - @mlb_lib.MLB 37B1 46B5
AUD_PORT_G_DET_L AUD_PORT_G_DET_L - @mlb_lib.MLB 58C5 CPU_VIDALERT_L CPU_VIDALERT_L - @mlb_lib.MLB 13B5 67B6 81C3 DP_EXTA_ML_C_P<2> DP_EXTA_ML_C_P<2> - @mlb_lib.MLB 77D8 ENET_ASF_GPIO_R ENET_ASF_GPIO_R - @mlb_lib.MLB 37B3
AUD_REG_SHDN_L AUD_REG_SHDN_L - @mlb_lib.MLB 53A7 CPU_VIDALERT_L_R CPU_VIDALERT_L_R - @mlb_lib.MLB 13B6 81C3 =IG_DP_EXTA_ML_C_P<3..0> - 8C8 ENET_ASF_SMB_CLK ENET_ASF_SMB_CLK - @mlb_lib.MLB 37B6 49D3 87D3
AUD_SDI_R AUD_SDI_R - @mlb_lib.MLB 53C6 84C3 CPU_VIDSCLK CPU_VIDSCLK - @mlb_lib.MLB 13B5 67C6 81C3 @mlb_lib.MLB =SMBUS_SMC_2_SCL - @mlb_lib.MLB 46B5 49D1
AUD_SENSE_A AUD_SENSE_A - @mlb_lib.MLB 53C7 58A7 58C8 CPU_VIDSCLK_R CPU_VIDSCLK_R - @mlb_lib.MLB 13B6 81C3 DP_EXTA_ML_C_P<3> DP_EXTA_ML_C_P<3> - @mlb_lib.MLB 77D8 ENET_ASF_SMB_DATA ENET_ASF_SMB_DATA - @mlb_lib.MLB 37B6 49D3 87D3
AUD_SPDIF_IN AUD_SPDIF_IN - @mlb_lib.MLB 53C7 57B3 CPU_VIDSOUT CPU_VIDSOUT - @mlb_lib.MLB 13B5 67B6 81C3 =IG_DP_EXTA_ML_C_P<3..0> - 8C8 =SMBUS_SMC_2_SDA - @mlb_lib.MLB 46B5 49D1
AUD_SPDIF_OUT AUD_SPDIF_OUT - @mlb_lib.MLB 53C7 57C3 CPU_VIDSOUT_R CPU_VIDSOUT_R - @mlb_lib.MLB 13B6 81C3 @mlb_lib.MLB ENET_CENTER_TAP<0> ENET_CENTER_TAP<0> - @mlb_lib.MLB 36B5
AUD_SPKRAMP_INL AUD_SPKRAMP_INL - @mlb_lib.MLB 56B6 CPU_VTTSELECT CPU_VTTSELECT - @mlb_lib.MLB 81B3 DP_EXTA_ML_N<0> DP_EXTA_ML_N<0> - @mlb_lib.MLB 77C7 77D6 ENET_CENTER_TAP<3..0 ENET_CENTER_TAP<3..0> - 85D3
AUD_SPKRAMP_INL_L AUD_SPKRAMP_INL_L - @mlb_lib.MLB 56B7 CS4206_SPDIF_OUT CS4206_SPDIF_OUT - @mlb_lib.MLB 53C6 DP_EXTA_ML_N<3..0> DP_EXTA_ML_N<3..0> - @mlb_lib.MLB 83C1 > @mlb_lib.MLB
AUD_SPKRAMP_INR AUD_SPKRAMP_INR - @mlb_lib.MLB 56C6 CS4206_VCOM CS4206_VCOM - @mlb_lib.MLB 53C3 DP_EXTA_ML_N<1> DP_EXTA_ML_N<1> - @mlb_lib.MLB 77C7 77D6 ENET_CENTER_TAP<1> ENET_CENTER_TAP<1> - @mlb_lib.MLB 36C4
AUD_SPKRAMP_INR_L AUD_SPKRAMP_INR_L - @mlb_lib.MLB 56C7 CS4206_VREF_ADC CS4206_VREF_ADC - @mlb_lib.MLB 53C3 DP_EXTA_ML_N<2> DP_EXTA_ML_N<2> - @mlb_lib.MLB 77C7 77D6 ENET_CENTER_TAP<2> ENET_CENTER_TAP<2> - @mlb_lib.MLB 36B5
AUD_SPKRAMP_SD_H AUD_SPKRAMP_SD_H - @mlb_lib.MLB 56B7 DCINVSENS_EN_L DCINVSENS_EN_L - @mlb_lib.MLB 51C3 DP_EXTA_ML_N<3> DP_EXTA_ML_N<3> - @mlb_lib.MLB 77C7 77D6 ENET_CENTER_TAP<3> ENET_CENTER_TAP<3> - @mlb_lib.MLB 36C4
BCM5764_CLK25M_XTALI BCM5764_CLK25M_XTALI - @mlb_lib.MLB 26C1 37B6 85D3 DCIN_IOUT DCIN_IOUT - @mlb_lib.MLB 51D6 DP_EXTA_ML_P<0> DP_EXTA_ML_P<0> - @mlb_lib.MLB 77C7 77D6 ENET_CLKREQ_L ENET_CLKREQ_L - @mlb_lib.MLB 17B4 17B5 37B6
SYSCLK_CLK25M_ENET - @mlb_lib.MLB 26C3 DCIN_S5_VSENSE DCIN_S5_VSENSE - @mlb_lib.MLB 51D3 DP_EXTA_ML_P<3..0> DP_EXTA_ML_P<3..0> - @mlb_lib.MLB 83C1 ENET_CMODE_REF ENET_CMODE_REF - @mlb_lib.MLB 36B4 85D3
BCM5764_CLK25M_XTALO BCM5764_CLK25M_XTALO - @mlb_lib.MLB 26C1 37B6 85D3 DDRREG_1V8_VREF DDRREG_1V8_VREF - @mlb_lib.MLB 66C7 DP_EXTA_ML_P<1> DP_EXTA_ML_P<1> - @mlb_lib.MLB 77C7 77D6 ENET_CONN_CTAP ENET_CONN_CTAP - @mlb_lib.MLB 36D5
TP_ENET_CLK25M_XTALO - @mlb_lib.MLB 26C3 DDRREG_DRVH DDRREG_DRVH - @mlb_lib.MLB 66C6 DP_EXTA_ML_P<2> DP_EXTA_ML_P<2> - @mlb_lib.MLB 77C7 77D6 ENET_CR_CLK ENET_CR_CLK - @mlb_lib.MLB 37B3 85C3
BCM57765_CS_L BCM57765_CS_L - @mlb_lib.MLB 37A8 37B6 DDRREG_DRVL DDRREG_DRVL - @mlb_lib.MLB 66C6 DP_EXTA_ML_P<3> DP_EXTA_ML_P<3> - @mlb_lib.MLB 77C7 77D6 ENET_CR_CMD ENET_CR_CMD - @mlb_lib.MLB 37B3 85C3
BCM57765_MISO BCM57765_MISO - @mlb_lib.MLB 37A6 37B6 DDRREG_MODE DDRREG_MODE - @mlb_lib.MLB 66C7 DP_ML_CK_N<3..0> DP_ML_CK_N<3..0> - @mlb_lib.MLB 83C1 ENET_CR_DATA<0> ENET_CR_DATA<0> - @mlb_lib.MLB 37B3
A BCM57765_MOSI
BCM57765_RDAC
BCM57765_MOSI - @mlb_lib.MLB
BCM57765_RDAC - @mlb_lib.MLB
37A6
37B6
37B6 DDRREG_PGOOD
DDRREG_REFIN
DDRREG_PGOOD - @mlb_lib.MLB
DDRREG_REFIN - @mlb_lib.MLB
62B6
33B1
66C5
66C7
DP_ML_CK_P<3..0>
DP_ML_C_N<3..0>
DP_ML_CK_P<3..0> - @mlb_lib.MLB
DP_ML_C_N<3..0> - @mlb_lib.MLB
83C1
83C1
ENET_CR_DATA<7..0>
ENET_CR_DATA<1>
ENET_CR_DATA<7..0> - @mlb_lib.MLB
ENET_CR_DATA<1> - @mlb_lib.MLB
85C3
37B3
A
BCM57765_SCLK BCM57765_SCLK - @mlb_lib.MLB 37A8 37B6 DDRREG_SNUB DDRREG_SNUB - @mlb_lib.MLB 66C3 DP_ML_C_P<3..0> DP_ML_C_P<3..0> - @mlb_lib.MLB 83C1 ENET_CR_DATA<2> ENET_CR_DATA<2> - @mlb_lib.MLB 37B3
BCM57765_VMAIN_PRSNT BCM57765_VMAIN_PRSNT - @mlb_lib.MLB 37C6 DDRREG_SW DDRREG_SW - @mlb_lib.MLB 66C6 DP_SDRVA_AUXCH_C_N DP_SDRVA_AUXCH_C_N - @mlb_lib.MLB 77B6 86B3 ENET_CR_DATA<3> ENET_CR_DATA<3> - @mlb_lib.MLB 37B3
BCM57765_WAKE_R_L BCM57765_WAKE_R_L - @mlb_lib.MLB 37B6 DDRREG_TRIP DDRREG_TRIP - @mlb_lib.MLB 66C7 DP_SDRVA_AUXCH_C_P DP_SDRVA_AUXCH_C_P - @mlb_lib.MLB 77B6 86B3 ENET_CR_DATA<4> ENET_CR_DATA<4> - @mlb_lib.MLB 37B3
BDM57765_SR_DISABLE BDM57765_SR_DISABLE - @mlb_lib.MLB 37B4 DDRREG_VBST DDRREG_VBST - @mlb_lib.MLB 66C6 DP_SDRVA_AUXCH_N DP_SDRVA_AUXCH_N - @mlb_lib.MLB 77B3 86B3 ENET_CR_DATA<5> ENET_CR_DATA<5> - @mlb_lib.MLB 37B3
BOOT_1V8S0 BOOT_1V8S0 - @mlb_lib.MLB 71C6 DDRREG_VBST_R DDRREG_VBST_R - @mlb_lib.MLB 66C5 DP_SDRVA_AUXCH_P DP_SDRVA_AUXCH_P - @mlb_lib.MLB 77B3 86B3 ENET_CR_DATA<6> ENET_CR_DATA<6> - @mlb_lib.MLB 37B3
CATERR_LED CATERR_LED - @mlb_lib.MLB 6B1 DDRREG_VDDQSNS DDRREG_VDDQSNS - @mlb_lib.MLB 66C6 DP_SDRVA_HPD DP_SDRVA_HPD - @mlb_lib.MLB 77B3 ENET_CR_DATA<7> ENET_CR_DATA<7> - @mlb_lib.MLB 37B3
CATERR_LED_R CATERR_LED_R - @mlb_lib.MLB 6B1 DDRREG_VTTSNS DDRREG_VTTSNS - @mlb_lib.MLB 66C6 DP_SDRVA_ML_C_N<0> DP_SDRVA_ML_C_N<0> - @mlb_lib.MLB 77C6 ENET_CR_DETECT_L ENET_CR_DETECT_L - @mlb_lib.MLB 34B2 37B1
CATERR_R CATERR_R - @mlb_lib.MLB 6B2 DIMM_PROX_THRM_N DIMM_PROX_THRM_N - @mlb_lib.MLB 52C3 52D8 DP_SDRVA_ML_C_N<3..0 DP_SDRVA_ML_C_N<3..0> - 86B3 ENET_CR_PWREN ENET_CR_PWREN - @mlb_lib.MLB 34D4 37B3
CIV_ENET_RESET_L CIV_ENET_RESET_L - @mlb_lib.MLB 34B2 37B6 DIMM_PROX_THRM_P DIMM_PROX_THRM_P - @mlb_lib.MLB 52C3 52D8 > @mlb_lib.MLB ENET_LOW_PWR ENET_LOW_PWR - @mlb_lib.MLB 20C1 34B5 37B6
CLK98M_FW_XI CLK98M_FW_XI - @mlb_lib.MLB 39C3 85B3 DMI_CLK100M_CPU_N DMI_CLK100M_CPU_N - @mlb_lib.MLB 11C2 17C1 81D3 DP_SDRVA_ML_C_N<1> DP_SDRVA_ML_C_N<1> - @mlb_lib.MLB 77C6 ENET_LOW_PWR_PCH ENET_LOW_PWR_PCH - @mlb_lib.MLB 20A1 20C3 20C6
CLK98M_FW_XI_R CLK98M_FW_XI_R - @mlb_lib.MLB 39C2 85B3 DMI_CLK100M_CPU_P DMI_CLK100M_CPU_P - @mlb_lib.MLB 11C2 17C1 81D3 DP_SDRVA_ML_C_N<2> DP_SDRVA_ML_C_N<2> - @mlb_lib.MLB 77C6 ENET_MDI_N<0> ENET_MDI_N<0> - @mlb_lib.MLB 36B8 37C3
COMP_1V8S0 COMP_1V8S0 - @mlb_lib.MLB 71C7 DMI_N2S_N<0> DMI_N2S_N<0> - @mlb_lib.MLB 10D8 18D8 DP_SDRVA_ML_C_N<3> DP_SDRVA_ML_C_N<3> - @mlb_lib.MLB 77C6 ENET_MDI_N<3..0> ENET_MDI_N<3..0> - @mlb_lib.MLB 85D3

501

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
ENET_MDI_N<1> ENET_MDI_N<1> - @mlb_lib.MLB 36C8 37C3 FDI_FSYNC<0> FDI_FSYNC<0> - @mlb_lib.MLB 18C5 HDA_BIT_CLK_R HDA_BIT_CLK_R - @mlb_lib.MLB 17A5 17D8 84C3 ISNS_P1V05PCH_P ISNS_P1V05PCH_P - @mlb_lib.MLB 50C7
ENET_MDI_N<2> ENET_MDI_N<2> - @mlb_lib.MLB 36C8 37C3 =FDI_FSYNC<1..0> - @mlb_lib.MLB 8D8 HDA_RST_L HDA_RST_L - @mlb_lib.MLB 17A4 53C7 84C3 ISNS_P12VG3H_N ISNS_P12VG3H_N - @mlb_lib.MLB 51D7
ENET_MDI_N<3> ENET_MDI_N<3> - @mlb_lib.MLB 36B8 37B3 FDI_FSYNC<1..0> FDI_FSYNC<1..0> - @mlb_lib.MLB 8D5 81D3 HDA_RST_R_L HDA_RST_R_L - @mlb_lib.MLB 17A5 17D8 84C3 ISNS_P12VG3H_P ISNS_P12VG3H_P - @mlb_lib.MLB 51D7
ENET_MDI_P<0> ENET_MDI_P<0> - @mlb_lib.MLB 36C8 37C3 =FDI_FSYNC<1..0> - @mlb_lib.MLB 8D8 HDA_SDIN0 HDA_SDIN0 - @mlb_lib.MLB 17D8 53C7 84C3 ISNS_VDDQ_N ISNS_VDDQ_N - @mlb_lib.MLB 50D7
ENET_MDI_P<3..0> ENET_MDI_P<3..0> - @mlb_lib.MLB 85D3 FDI_FSYNC<1> FDI_FSYNC<1> - @mlb_lib.MLB 18C5 HDA_SDOUT HDA_SDOUT - @mlb_lib.MLB 17A4 53C7 84C3 ISNS_VDDQ_P ISNS_VDDQ_P - @mlb_lib.MLB 50D7
ENET_MDI_P<1> ENET_MDI_P<1> - @mlb_lib.MLB 36C8 37C3 =FDI_FSYNC<1..0> - @mlb_lib.MLB 8D8 HDA_SDOUT_R HDA_SDOUT_R - @mlb_lib.MLB 17A3 17A5 17C8 84C3 ISOLATE_CPU_MEM_L ISOLATE_CPU_MEM_L - @mlb_lib.MLB 20C6 28C8
ENET_MDI_P<2> ENET_MDI_P<2> - @mlb_lib.MLB 36C8 37C3 FDI_INT FDI_INT - @mlb_lib.MLB 8D5 18C5 81D3 HDA_SYNC HDA_SYNC - @mlb_lib.MLB 17A4 53C7 84C3 ITPCPU_CLK100M_N ITPCPU_CLK100M_N - @mlb_lib.MLB 11C2 17A4 81C1
ENET_MDI_P<3> ENET_MDI_P<3> - @mlb_lib.MLB 36B8 37C3 =FDI_INT - @mlb_lib.MLB 8D8 10C8 HDA_SYNC_R HDA_SYNC_R - @mlb_lib.MLB 17A3 17A5 17D8 84C3 ITPCPU_CLK100M_P ITPCPU_CLK100M_P - @mlb_lib.MLB 11C2 17A4 81C1
ENET_MDI_TRAN_N<0> ENET_MDI_TRAN_N<0> - @mlb_lib.MLB 36B3 FDI_LSYNC<0> FDI_LSYNC<0> - @mlb_lib.MLB 18C5 HDD_THRMD_N HDD_THRMD_N - @mlb_lib.MLB 91A7 ITPXDP_CLK100M_N ITPXDP_CLK100M_N - @mlb_lib.MLB 17A5 17B1 24C3 81C1
ENET_MDI_TRAN_N<3..0 ENET_MDI_TRAN_N<3..0> - 85D3 =FDI_LSYNC<1..0> - @mlb_lib.MLB 8D8 HDD_THRMD_P HDD_THRMD_P - @mlb_lib.MLB 91A7 ITPXDP_CLK100M_P ITPXDP_CLK100M_P - @mlb_lib.MLB 17A5 17B1 24C3 81C1
> @mlb_lib.MLB FDI_LSYNC<1..0> FDI_LSYNC<1..0> - @mlb_lib.MLB 8D5 81D3 HDMI_CLK_CONN_N HDMI_CLK_CONN_N - @mlb_lib.MLB 80B5 80C1 83B1 ITS_ALIVE ITS_ALIVE - @mlb_lib.MLB 6C2
ENET_MDI_TRAN_N<1> ENET_MDI_TRAN_N<1> - @mlb_lib.MLB 36C4 =FDI_LSYNC<1..0> - @mlb_lib.MLB 8D8 HDMI_CLK_CONN_P HDMI_CLK_CONN_P - @mlb_lib.MLB 80C1 80C5 83B1 ITS_BREATHING ITS_BREATHING - @mlb_lib.MLB 6C1
ENET_MDI_TRAN_N<2> ENET_MDI_TRAN_N<2> - @mlb_lib.MLB 36C4 FDI_LSYNC<1> FDI_LSYNC<1> - @mlb_lib.MLB 18C5 HDMI_CLK_C_N HDMI_CLK_C_N - @mlb_lib.MLB 8C5 79D8 83B1 ITS_BREATHING_Q ITS_BREATHING_Q - @mlb_lib.MLB 6C1
ENET_MDI_TRAN_N<3> ENET_MDI_TRAN_N<3> - @mlb_lib.MLB 36B3 =FDI_LSYNC<1..0> - @mlb_lib.MLB 8D8 =IG_HDMI_CLK_C_N - @mlb_lib.MLB 8C8 18B1 ITS_PLUGGED_IN ITS_PLUGGED_IN - @mlb_lib.MLB 6C2

D ENET_MDI_TRAN_P<0>
ENET_MDI_TRAN_P<3..0
ENET_MDI_TRAN_P<0> - @mlb_lib.MLB
ENET_MDI_TRAN_P<3..0> -
36C3
85D3
FWOHCI_CLK98M_LCLK
FWOHCI_LINKON_L
FWOHCI_CLK98M_LCLK - @mlb_lib.MLB
FWOHCI_LINKON_L - @mlb_lib.MLB
39C3
39C3
HDMI_CLK_C_P HDMI_CLK_C_P - @mlb_lib.MLB
=IG_HDMI_CLK_C_P - @mlb_lib.MLB
8C5 79D8 83B1
8C8 18B1
JTAG_GMUX_TMS
JTAG_ISP_TCK
JTAG_GMUX_TMS - @mlb_lib.MLB
JTAG_ISP_TCK - @mlb_lib.MLB
19D6
20C6 20D8 74C2
D
> @mlb_lib.MLB FWOHCI_LPS FWOHCI_LPS - @mlb_lib.MLB 39B3 HDMI_CLK_LS_N HDMI_CLK_LS_N - @mlb_lib.MLB 79D6 83B1 JTAG_ISP_TDI JTAG_ISP_TDI - @mlb_lib.MLB 20A2 20C6 74C2
ENET_MDI_TRAN_P<1> ENET_MDI_TRAN_P<1> - @mlb_lib.MLB 36C4 FWOHCI_LREQ FWOHCI_LREQ - @mlb_lib.MLB 39B3 HDMI_CLK_LS_P HDMI_CLK_LS_P - @mlb_lib.MLB 79D6 83B1 JTAG_ISP_TDO JTAG_ISP_TDO - @mlb_lib.MLB 20B6 20C6 74C2
ENET_MDI_TRAN_P<2> ENET_MDI_TRAN_P<2> - @mlb_lib.MLB 36C4 FWPHY_BMODE FWPHY_BMODE - @mlb_lib.MLB 39A6 HDMI_CLK_N HDMI_CLK_N - @mlb_lib.MLB 79D2 80B8 83B1 JTAG_T29_TMS JTAG_T29_TMS - @mlb_lib.MLB 17B5 17C8 74C2
ENET_MDI_TRAN_P<3> ENET_MDI_TRAN_P<3> - @mlb_lib.MLB 36B3 FWPHY_CLK98M_PCLK FWPHY_CLK98M_PCLK - @mlb_lib.MLB 39B3 HDMI_CLK_P HDMI_CLK_P - @mlb_lib.MLB 79D2 80C8 83B1 LPCPLUS_GPIO LPCPLUS_GPIO - @mlb_lib.MLB 20D7 48C3
ENET_MEDIA_SENSE ENET_MEDIA_SENSE - @mlb_lib.MLB 37B1 38B5 FWPHY_CPS FWPHY_CPS - @mlb_lib.MLB 39B3 HDMI_DATA_CONN_N<0> HDMI_DATA_CONN_N<0> - @mlb_lib.MLB 80C4 80D5 LPCPLUS_RESET_L LPCPLUS_RESET_L - @mlb_lib.MLB 27C1 48C5 84D3
ENET_MEDIA_SENSE_RDI ENET_MEDIA_SENSE_RDIV - 17C8 38B3 FWPHY_LKON_DS2 FWPHY_LKON_DS2 - @mlb_lib.MLB 39C3 HDMI_DATA_CONN_N<2.. HDMI_DATA_CONN_N<2..0> - 83B1 LPC_AD<0> LPC_AD<0> - @mlb_lib.MLB 17D5 46C8 48C5
V @mlb_lib.MLB FWPHY_PINT FWPHY_PINT - @mlb_lib.MLB 39B3 0> @mlb_lib.MLB LPC_AD<3..0> LPC_AD<3..0> - @mlb_lib.MLB 84D3
ENET_MSNS_EN ENET_MSNS_EN - @mlb_lib.MLB 38A4 FWPHY_R0 FWPHY_R0 - @mlb_lib.MLB 39B3 HDMI_DATA_CONN_N<1> HDMI_DATA_CONN_N<1> - @mlb_lib.MLB 80C1 80C5 LPC_AD<1> LPC_AD<1> - @mlb_lib.MLB 17D5 46C8 48C5
ENET_MSNS_EN_L ENET_MSNS_EN_L - @mlb_lib.MLB 38A4 FWPHY_R1 FWPHY_R1 - @mlb_lib.MLB 39B3 HDMI_DATA_CONN_N<2> HDMI_DATA_CONN_N<2> - @mlb_lib.MLB 80C4 80C5 LPC_AD<2> LPC_AD<2> - @mlb_lib.MLB 17D5 46C8 48C3
ENET_PWR_EN ENET_PWR_EN - @mlb_lib.MLB 19C1 24D4 FWPHY_RESET_L FWPHY_RESET_L - @mlb_lib.MLB 39A3 HDMI_DATA_CONN_P<0> HDMI_DATA_CONN_P<0> - @mlb_lib.MLB 80C4 80D5 LPC_AD<3> LPC_AD<3> - @mlb_lib.MLB 17D5 46C8 48C3
ENET_RESET_L ENET_RESET_L - @mlb_lib.MLB 27D1 34B8 85D3 FWPHY_TESTM FWPHY_TESTM - @mlb_lib.MLB 39A6 HDMI_DATA_CONN_P<2.. HDMI_DATA_CONN_P<2..0> - 83B1 LPC_CLK33M_LPCPLUS LPC_CLK33M_LPCPLUS - @mlb_lib.MLB 27B1 48C3 84D3
ENET_SR_LX ENET_SR_LX - @mlb_lib.MLB 37D4 38D5 FWPHY_TESTW FWPHY_TESTW - @mlb_lib.MLB 39A6 0> @mlb_lib.MLB LPC_CLK33M_LPCPLUS_R LPC_CLK33M_LPCPLUS_R - @mlb_lib.MLB 19C6 27B4 84D3
ENET_SR_VFB ENET_SR_VFB - @mlb_lib.MLB 37D4 38C5 FWXIO_CYCLEOUT FWXIO_CYCLEOUT - @mlb_lib.MLB 39B6 HDMI_DATA_CONN_P<1> HDMI_DATA_CONN_P<1> - @mlb_lib.MLB 80C1 80D5 LPC_CLK33M_SMC LPC_CLK33M_SMC - @mlb_lib.MLB 27B1 46C8 84D3
ENET_WAKE_L ENET_WAKE_L - @mlb_lib.MLB 37B8 38C1 FWXIO_JTAG_TCK FWXIO_JTAG_TCK - @mlb_lib.MLB 39B6 HDMI_DATA_CONN_P<2> HDMI_DATA_CONN_P<2> - @mlb_lib.MLB 80C4 80C5 LPC_CLK33M_SMC_R LPC_CLK33M_SMC_R - @mlb_lib.MLB 19C6 27B4 84D3
EXCARD_CLKREQ_L EXCARD_CLKREQ_L - @mlb_lib.MLB 17B4 17B5 FWXIO_JTAG_TRST FWXIO_JTAG_TRST - @mlb_lib.MLB 39A6 HDMI_DATA_C_N<0> HDMI_DATA_C_N<0> - @mlb_lib.MLB 79C8 LPC_FRAME_L LPC_FRAME_L - @mlb_lib.MLB 17D5 46C8 48C5 84D3
FAN0_CTL_F FAN0_CTL_F - @mlb_lib.MLB 60C3 91D5 FWXIO_REF0_PCIE FWXIO_REF0_PCIE - @mlb_lib.MLB 39C6 =IG_HDMI_DATA_C_N<2..0> - 8C8 LPC_FRAME_R_L LPC_FRAME_R_L - @mlb_lib.MLB 17D6 84D3
FAN0_TACH_F FAN0_TACH_F - @mlb_lib.MLB 60C3 91D5 FWXIO_REF1_PCIE FWXIO_REF1_PCIE - @mlb_lib.MLB 39C6 @mlb_lib.MLB LPC_PWRDWN_L LPC_PWRDWN_L - @mlb_lib.MLB 18C5 46C5 48C3
FAN_S0_EN_L FAN_S0_EN_L - @mlb_lib.MLB 60C6 FWXIO_REFCLK_SEL FWXIO_REFCLK_SEL - @mlb_lib.MLB 39B6 HDMI_DATA_C_N<2..0> HDMI_DATA_C_N<2..0> - @mlb_lib.MLB 8C5 83B1 LPC_R_AD<0> LPC_R_AD<0> - @mlb_lib.MLB 17D6
FAN_S0_EN_L_G FAN_S0_EN_L_G - @mlb_lib.MLB 60C5 FWXIO_REF_PCIE FWXIO_REF_PCIE - @mlb_lib.MLB 39C7 =IG_HDMI_DATA_C_N<2..0> - 8C8 LPC_R_AD<3..0> LPC_R_AD<3..0> - @mlb_lib.MLB 84D3
FAN_TACH0 FAN_TACH0 - @mlb_lib.MLB 60C7 FWXIO_SCL FWXIO_SCL - @mlb_lib.MLB 39B6 @mlb_lib.MLB LPC_R_AD<1> LPC_R_AD<1> - @mlb_lib.MLB 17D6
FB_1V8S0 FB_1V8S0 - @mlb_lib.MLB 71C7 FWXIO_SDA FWXIO_SDA - @mlb_lib.MLB 39B6 HDMI_DATA_C_N<1> HDMI_DATA_C_N<1> - @mlb_lib.MLB 79C8 LPC_R_AD<2> LPC_R_AD<2> - @mlb_lib.MLB 17D6
FB_B0_A<8..0> FB_B0_A<8..0> - @mlb_lib.MLB 88D1 FWXIO_SNOOP_EN FWXIO_SNOOP_EN - @mlb_lib.MLB 39A6 =IG_HDMI_DATA_C_N<2..0> - 8C8 LPC_R_AD<3> LPC_R_AD<3> - @mlb_lib.MLB 17D6
FB_B0_ABI_L FB_B0_ABI_L - @mlb_lib.MLB 88D1 FWXIO_VDD15COMB FWXIO_VDD15COMB - @mlb_lib.MLB 39C3 @mlb_lib.MLB LPC_SERIRQ LPC_SERIRQ - @mlb_lib.MLB 17D5 46C8 48C3
FB_B0_CAS_L FB_B0_CAS_L - @mlb_lib.MLB 88D1 FWXIO_VDD33COMB FWXIO_VDD33COMB - @mlb_lib.MLB 39C3 HDMI_DATA_C_N<2> HDMI_DATA_C_N<2> - @mlb_lib.MLB 79C8 MAX8840_BP MAX8840_BP - @mlb_lib.MLB 53A5
FB_B0_CKE_L FB_B0_CKE_L - @mlb_lib.MLB 88D1 FWXIO_VDD33COMIO FWXIO_VDD33COMIO - @mlb_lib.MLB 39C3 =IG_HDMI_DATA_C_N<2..0> - 8C8 MEMRESET_ISOL_LS5V_L MEMRESET_ISOL_LS5V_L - @mlb_lib.MLB 28B7
FB_B0_CLK_N FB_B0_CLK_N - @mlb_lib.MLB 88D1 FWXIO_VREG_PD33 FWXIO_VREG_PD33 - @mlb_lib.MLB 39A6 @mlb_lib.MLB MEMVTT_EN MEMVTT_EN - @mlb_lib.MLB 28A4 28C5 66C8
FB_B0_CLK_P FB_B0_CLK_P - @mlb_lib.MLB 88D1 FW_CLKREQ_L FW_CLKREQ_L - @mlb_lib.MLB 17B5 17C4 39C6 HDMI_DATA_C_P<0> HDMI_DATA_C_P<0> - @mlb_lib.MLB 79D8 MEMVTT_EN_L MEMVTT_EN_L - @mlb_lib.MLB 28B6
FB_B0_CS_L FB_B0_CS_L - @mlb_lib.MLB 88D1 FW_CUTOFF FW_CUTOFF - @mlb_lib.MLB 41A6 41C8 =IG_HDMI_DATA_C_P<2..0> - 8C8 MEM_A_A<0> MEM_A_A<0> - @mlb_lib.MLB 12C5 30C5
FB_B0_DBI_L<0> FB_B0_DBI_L<0> - @mlb_lib.MLB 88C1 FW_EN_A FW_EN_A - @mlb_lib.MLB 41C7 @mlb_lib.MLB MEM_A_A<15..0> MEM_A_A<15..0> - @mlb_lib.MLB 82D3
FB_B0_DBI_L<1> FB_B0_DBI_L<1> - @mlb_lib.MLB 88C1 FW_EN_B FW_EN_B - @mlb_lib.MLB 41C7 HDMI_DATA_C_P<2..0> HDMI_DATA_C_P<2..0> - @mlb_lib.MLB 8C5 83A1 MEM_A_A<1> MEM_A_A<1> - @mlb_lib.MLB 12C5 30C7

C FB_B0_DBI_L<2>
FB_B0_DBI_L<3>
FB_B0_DBI_L<2> - @mlb_lib.MLB
FB_B0_DBI_L<3> - @mlb_lib.MLB
88C1
88C1
FW_FETGATE
FW_FETV
FW_FETGATE - @mlb_lib.MLB
FW_FETV - @mlb_lib.MLB
41D7
41C6
=IG_HDMI_DATA_C_P<2..0> -
@mlb_lib.MLB
8C8 MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<2> - @mlb_lib.MLB
MEM_A_A<3> - @mlb_lib.MLB
12C5
12C5
30C5
30C7
C
FB_B0_DQ<7..0> FB_B0_DQ<7..0> - @mlb_lib.MLB 88C1 FW_FET_TEMP FW_FET_TEMP - @mlb_lib.MLB 41A8 41B7 HDMI_DATA_C_P<1> HDMI_DATA_C_P<1> - @mlb_lib.MLB 79C8 MEM_A_A<4> MEM_A_A<4> - @mlb_lib.MLB 12C5 30C5
FB_B0_DQ<15..8> FB_B0_DQ<15..8> - @mlb_lib.MLB 88C1 FW_FET_TREF FW_FET_TREF - @mlb_lib.MLB 41A8 =IG_HDMI_DATA_C_P<2..0> - 8C8 MEM_A_A<5> MEM_A_A<5> - @mlb_lib.MLB 12C5 30C7
FB_B0_DQ<23..16> FB_B0_DQ<23..16> - @mlb_lib.MLB 88C1 FW_IREF FW_IREF - @mlb_lib.MLB 41C5 @mlb_lib.MLB MEM_A_A<6> MEM_A_A<6> - @mlb_lib.MLB 12C5 30C5
FB_B0_DQ<31..24> FB_B0_DQ<31..24> - @mlb_lib.MLB 88C1 FW_LATEVG_L FW_LATEVG_L - @mlb_lib.MLB 41A4 HDMI_DATA_C_P<2> HDMI_DATA_C_P<2> - @mlb_lib.MLB 79C8 MEM_A_A<7> MEM_A_A<7> - @mlb_lib.MLB 12C5 30C5
FB_B0_EDC<0> FB_B0_EDC<0> - @mlb_lib.MLB 88D1 FW_LATEVG_PP2V4_RC FW_LATEVG_PP2V4_RC - @mlb_lib.MLB 41A5 =IG_HDMI_DATA_C_P<2..0> - 8C8 MEM_A_A<8> MEM_A_A<8> - @mlb_lib.MLB 12C5 30C7
FB_B0_EDC<1> FB_B0_EDC<1> - @mlb_lib.MLB 88D1 FW_LATEVG_REF FW_LATEVG_REF - @mlb_lib.MLB 41A5 @mlb_lib.MLB MEM_A_A<9> MEM_A_A<9> - @mlb_lib.MLB 12C5 30C7
FB_B0_EDC<2> FB_B0_EDC<2> - @mlb_lib.MLB 88D1 FW_OC_DR FW_OC_DR - @mlb_lib.MLB 41C7 HDMI_DATA_LS_N<0> HDMI_DATA_LS_N<0> - @mlb_lib.MLB 79C6 MEM_A_A<10> MEM_A_A<10> - @mlb_lib.MLB 12C5 30B7

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FB_B0_EDC<3> FB_B0_EDC<3> - @mlb_lib.MLB 88C1 FW_P0_TPA_C FW_P0_TPA_C - @mlb_lib.MLB 40C3 HDMI_DATA_LS_N<2..0> HDMI_DATA_LS_N<2..0> - @mlb_lib.MLB 83A1 MEM_A_A<11> MEM_A_A<11> - @mlb_lib.MLB 12B5 30C5
FB_B0_RAS_L FB_B0_RAS_L - @mlb_lib.MLB 88D1 FW_P0_TPA_L_N FW_P0_TPA_L_N - @mlb_lib.MLB 40D2 85B3 HDMI_DATA_LS_N<1> HDMI_DATA_LS_N<1> - @mlb_lib.MLB 79C6 MEM_A_A<12> MEM_A_A<12> - @mlb_lib.MLB 12B5 30C7
FB_B0_WCLK_N<0> FB_B0_WCLK_N<0> - @mlb_lib.MLB 88C1 FW_P0_TPA_L_P FW_P0_TPA_L_P - @mlb_lib.MLB 40D3 85B3 HDMI_DATA_LS_N<2> HDMI_DATA_LS_N<2> - @mlb_lib.MLB 79C6 MEM_A_A<13> MEM_A_A<13> - @mlb_lib.MLB 12B5 30B7
FB_B0_WCLK_N<1> FB_B0_WCLK_N<1> - @mlb_lib.MLB 88C1 FW_P0_TPBIAS FW_P0_TPBIAS - @mlb_lib.MLB 39A2 40D4 HDMI_DATA_LS_P<0> HDMI_DATA_LS_P<0> - @mlb_lib.MLB 79D6 MEM_A_A<14> MEM_A_A<14> - @mlb_lib.MLB 12B5 30C5
FB_B0_WCLK_P<0> FB_B0_WCLK_P<0> - @mlb_lib.MLB 88C1 FW_P0_TPB_L_N FW_P0_TPB_L_N - @mlb_lib.MLB 40C3 85B3 HDMI_DATA_LS_P<2..0> HDMI_DATA_LS_P<2..0> - @mlb_lib.MLB 83A1 MEM_A_A<15> MEM_A_A<15> - @mlb_lib.MLB 12B5 30C5
FB_B0_WCLK_P<1> FB_B0_WCLK_P<1> - @mlb_lib.MLB 88C1 FW_P0_TPB_L_P FW_P0_TPB_L_P - @mlb_lib.MLB 40C2 85B3 HDMI_DATA_LS_P<1> HDMI_DATA_LS_P<1> - @mlb_lib.MLB 79C6 MEM_A_BA<0> MEM_A_BA<0> - @mlb_lib.MLB 12B7 30B7
FB_B0_WE_L FB_B0_WE_L - @mlb_lib.MLB 88D1 FW_P12V_FETPWR FW_P12V_FETPWR - @mlb_lib.MLB 41C6 HDMI_DATA_LS_P<2> HDMI_DATA_LS_P<2> - @mlb_lib.MLB 79C6 MEM_A_BA<2..0> MEM_A_BA<2..0> - @mlb_lib.MLB 82D3
FB_B1_A<8..0> FB_B1_A<8..0> - @mlb_lib.MLB 88D1 FW_PHY_DS0 FW_PHY_DS0 - @mlb_lib.MLB 39C2 40B7 HDMI_DATA_N<0> HDMI_DATA_N<0> - @mlb_lib.MLB 79C2 80D8 MEM_A_BA<1> MEM_A_BA<1> - @mlb_lib.MLB 12B7 30B5
FB_B1_ABI_L FB_B1_ABI_L - @mlb_lib.MLB 88D1 FW_PHY_DS1 FW_PHY_DS1 - @mlb_lib.MLB 39C2 40B7 HDMI_DATA_N<2..0> HDMI_DATA_N<2..0> - @mlb_lib.MLB 83A1 MEM_A_BA<2> MEM_A_BA<2> - @mlb_lib.MLB 12B7 30C7
FB_B1_CAS_L FB_B1_CAS_L - @mlb_lib.MLB 88D1 FW_PHY_PC0 FW_PHY_PC0 - @mlb_lib.MLB 39C2 40A7 HDMI_DATA_N<1> HDMI_DATA_N<1> - @mlb_lib.MLB 79C2 80C8 MEM_A_CAS_L MEM_A_CAS_L - @mlb_lib.MLB 12B7 30B7 82D3
FB_B1_CKE_L FB_B1_CKE_L - @mlb_lib.MLB 88D1 FW_PME_L FW_PME_L - @mlb_lib.MLB 20B6 20D6 39B6 HDMI_DATA_N<2> HDMI_DATA_N<2> - @mlb_lib.MLB 79C2 80C8 MEM_A_CKE<0> MEM_A_CKE<0> - @mlb_lib.MLB 12D5 30C7
FB_B1_CLK_N FB_B1_CLK_N - @mlb_lib.MLB 88D1 FW_PORT0_TPAL_N FW_PORT0_TPAL_N - @mlb_lib.MLB 41C2 85B3 HDMI_DATA_P<0> HDMI_DATA_P<0> - @mlb_lib.MLB 79D2 80D8 MEM_A_CKE<3..0> MEM_A_CKE<3..0> - @mlb_lib.MLB 82D3
FB_B1_CLK_P FB_B1_CLK_P - @mlb_lib.MLB 88D1 FW_PORT0_TPAL_P FW_PORT0_TPAL_P - @mlb_lib.MLB 41C2 85B3 HDMI_DATA_P<2..0> HDMI_DATA_P<2..0> - @mlb_lib.MLB 83A1 MEM_A_CKE<1> MEM_A_CKE<1> - @mlb_lib.MLB 12D5 30C5
FB_B1_CS_L FB_B1_CS_L - @mlb_lib.MLB 88D1 FW_PORT0_TPA_N FW_PORT0_TPA_N - @mlb_lib.MLB 40C1 41C4 85B3 HDMI_DATA_P<1> HDMI_DATA_P<1> - @mlb_lib.MLB 79C2 80D8 MEM_A_CLK_N<0> MEM_A_CLK_N<0> - @mlb_lib.MLB 12D5 30C7
FB_B1_DBI_L<0> FB_B1_DBI_L<0> - @mlb_lib.MLB 88C1 FW_P0_TPA_N - @mlb_lib.MLB 39A2 40C3 HDMI_DATA_P<2> HDMI_DATA_P<2> - @mlb_lib.MLB 79C2 80C8 MEM_A_CLK_N<5..0> MEM_A_CLK_N<5..0> - @mlb_lib.MLB 82D3
FB_B1_DBI_L<1> FB_B1_DBI_L<1> - @mlb_lib.MLB 88C1 FW_PORT0_TPA_P FW_PORT0_TPA_P - @mlb_lib.MLB 40C1 41C4 85B3 HDMI_DDC_CLK_5V HDMI_DDC_CLK_5V - @mlb_lib.MLB 79C2 80B4 MEM_A_CLK_N<1> MEM_A_CLK_N<1> - @mlb_lib.MLB 12D5 30C5
FB_B1_DBI_L<2> FB_B1_DBI_L<2> - @mlb_lib.MLB 88C1 FW_P0_TPA_P - @mlb_lib.MLB 39A2 40C3 HDMI_DDC_CLK_CONN HDMI_DDC_CLK_CONN - @mlb_lib.MLB 80B8 80C4 MEM_A_CLK_P<0> MEM_A_CLK_P<0> - @mlb_lib.MLB 12D5 30C7
FB_B1_DBI_L<3> FB_B1_DBI_L<3> - @mlb_lib.MLB 88C1 FW_PORT0_TPA_R FW_PORT0_TPA_R - @mlb_lib.MLB 41C2 HDMI_DDC_CLK_F HDMI_DDC_CLK_F - @mlb_lib.MLB 80B6 MEM_A_CLK_P<5..0> MEM_A_CLK_P<5..0> - @mlb_lib.MLB 82D3
FB_B1_DQ<7..0> FB_B1_DQ<7..0> - @mlb_lib.MLB 88C1 FW_PORT0_TPBL_N FW_PORT0_TPBL_N - @mlb_lib.MLB 41C2 85B3 HDMI_DDC_DATA_5V HDMI_DDC_DATA_5V - @mlb_lib.MLB 79C2 80B4 MEM_A_CLK_P<1> MEM_A_CLK_P<1> - @mlb_lib.MLB 12D5 30C5
FB_B1_DQ<15..8> FB_B1_DQ<15..8> - @mlb_lib.MLB 88C1 FW_PORT0_TPBL_P FW_PORT0_TPBL_P - @mlb_lib.MLB 41C2 85B3 HDMI_DDC_DATA_CONN HDMI_DDC_DATA_CONN - @mlb_lib.MLB 80A8 80C1 MEM_A_CS_L<0> MEM_A_CS_L<0> - @mlb_lib.MLB 12D5 30B5
FB_B1_DQ<23..16> FB_B1_DQ<23..16> - @mlb_lib.MLB 88B1 FW_PORT0_TPB_N FW_PORT0_TPB_N - @mlb_lib.MLB 40C1 41C4 85B3 HDMI_DDC_DATA_F HDMI_DDC_DATA_F - @mlb_lib.MLB 80B6 MEM_A_CS_L<3..0> MEM_A_CS_L<3..0> - @mlb_lib.MLB 82D3
FB_B1_DQ<31..24> FB_B1_DQ<31..24> - @mlb_lib.MLB 88B1 FW_P0_TPB_N - @mlb_lib.MLB 39A2 40C3 HDMI_HPD HDMI_HPD - @mlb_lib.MLB 79C2 80A4 MEM_A_CS_L<1> MEM_A_CS_L<1> - @mlb_lib.MLB 12D5 30B7
FB_B1_EDC<0> FB_B1_EDC<0> - @mlb_lib.MLB 88C1 FW_PORT0_TPB_P FW_PORT0_TPB_P - @mlb_lib.MLB 40C1 41C4 85B3 HDMI_HPD_CONN HDMI_HPD_CONN - @mlb_lib.MLB 80A8 80C4 MEM_A_DQ<0> MEM_A_DQ<0> - @mlb_lib.MLB 12D7 29D8

B FB_B1_EDC<1>
FB_B1_EDC<2>
FB_B1_EDC<1> - @mlb_lib.MLB
FB_B1_EDC<2> - @mlb_lib.MLB
88C1
88C1 FW_PORT0_VP
FW_P0_TPB_P - @mlb_lib.MLB
FW_PORT0_VP - @mlb_lib.MLB
39A2 40C3
41D2 91B5
HDMI_HPD_Q
HDMI_LS_APD
HDMI_HPD_Q - @mlb_lib.MLB
HDMI_LS_APD - @mlb_lib.MLB
80A6
79B6
MEM_A_DQ<7..0>
MEM_A_DQ<1>
MEM_A_DQ<7..0> - @mlb_lib.MLB
MEM_A_DQ<1> - @mlb_lib.MLB
82D3
12D7 29D8 B
FB_B1_EDC<3> FB_B1_EDC<3> - @mlb_lib.MLB 88C1 FW_PORT0_VP_F FW_PORT0_VP_F - @mlb_lib.MLB 41D2 HDMI_LS_CEXT HDMI_LS_CEXT - @mlb_lib.MLB 79B5 MEM_A_DQ<2> MEM_A_DQ<2> - @mlb_lib.MLB 12D7 29D8
FB_B1_RAS_L FB_B1_RAS_L - @mlb_lib.MLB 88D1 FW_PORTPWR_DISABLE_L FW_PORTPWR_DISABLE_L - @mlb_lib.MLB 41A3 41C8 HDMI_LS_DDCBUF HDMI_LS_DDCBUF - @mlb_lib.MLB 79C6 MEM_A_DQ<3> MEM_A_DQ<3> - @mlb_lib.MLB 12D7 29D8
FB_B1_WCLK_N<0> FB_B1_WCLK_N<0> - @mlb_lib.MLB 88C1 FW_PWR_EN FW_PWR_EN - @mlb_lib.MLB 20B6 20C6 HDMI_LS_DDC_EN HDMI_LS_DDC_EN - @mlb_lib.MLB 79C6 MEM_A_DQ<4> MEM_A_DQ<4> - @mlb_lib.MLB 12D7 29D8
FB_B1_WCLK_N<1> FB_B1_WCLK_N<1> - @mlb_lib.MLB 88C1 FW_REF_A FW_REF_A - @mlb_lib.MLB 41B5 HDMI_LS_EMI0 HDMI_LS_EMI0 - @mlb_lib.MLB 79B4 MEM_A_DQ<5> MEM_A_DQ<5> - @mlb_lib.MLB 12D7 29D8
FB_B1_WCLK_P<0> FB_B1_WCLK_P<0> - @mlb_lib.MLB 88C1 FW_REF_B FW_REF_B - @mlb_lib.MLB 41B5 HDMI_LS_EMI1 HDMI_LS_EMI1 - @mlb_lib.MLB 79B4 MEM_A_DQ<6> MEM_A_DQ<6> - @mlb_lib.MLB 12D7 29D8
FB_B1_WCLK_P<1> FB_B1_WCLK_P<1> - @mlb_lib.MLB 88C1 FW_RESET_L FW_RESET_L - @mlb_lib.MLB 27D1 39C6 HDMI_LS_HPD HDMI_LS_HPD - @mlb_lib.MLB 8C5 79B5 79C8 83A1 MEM_A_DQ<7> MEM_A_DQ<7> - @mlb_lib.MLB 12D7 29D8
FB_B1_WE_L FB_B1_WE_L - @mlb_lib.MLB 88D1 FW_SNSN FW_SNSN - @mlb_lib.MLB 41D7 =IG_HDMI_LS_HPD - @mlb_lib.MLB 8C8 18B1 MEM_A_DQ<8> MEM_A_DQ<8> - @mlb_lib.MLB 12D7 29D8
FB_RESET_L FB_RESET_L - @mlb_lib.MLB 88B1 FW_SNSP FW_SNSP - @mlb_lib.MLB 41D8 HDMI_LS_OE_L HDMI_LS_OE_L - @mlb_lib.MLB 79C4 MEM_A_DQ<15..8> MEM_A_DQ<15..8> - @mlb_lib.MLB 82D3
FDI_DATA_N<0> FDI_DATA_N<0> - @mlb_lib.MLB 18D5 FW_V_PD FW_V_PD - @mlb_lib.MLB 41C5 HDMI_LS_PEQ HDMI_LS_PEQ - @mlb_lib.MLB 79B6 MEM_A_DQ<9> MEM_A_DQ<9> - @mlb_lib.MLB 12D7 29D8
=FDI_DATA_N<7..0> - @mlb_lib.MLB 8D8 G3_POWERON_L G3_POWERON_L - @mlb_lib.MLB 44C7 46B5 47C2 HDMI_LS_PIO HDMI_LS_PIO - @mlb_lib.MLB 79C6 MEM_A_DQ<10> MEM_A_DQ<10> - @mlb_lib.MLB 12D7 29D8
FDI_DATA_N<7..0> FDI_DATA_N<7..0> - @mlb_lib.MLB 8D5 81D3 G3_POWERON_R_L G3_POWERON_R_L - @mlb_lib.MLB 44C6 HDMI_LS_PRE HDMI_LS_PRE - @mlb_lib.MLB 79C4 MEM_A_DQ<11> MEM_A_DQ<11> - @mlb_lib.MLB 12D7 29D8
=FDI_DATA_N<7..0> - @mlb_lib.MLB 8D8 GFXIMVP_IMON GFXIMVP_IMON - @mlb_lib.MLB 81A3 HDMI_LS_REXT HDMI_LS_REXT - @mlb_lib.MLB 79B5 MEM_A_DQ<12> MEM_A_DQ<12> - @mlb_lib.MLB 12D7 29D8
FDI_DATA_N<1> FDI_DATA_N<1> - @mlb_lib.MLB 18D5 GFXVSENSE_IN GFXVSENSE_IN - @mlb_lib.MLB 50B3 HDMI_LS_SCL HDMI_LS_SCL - @mlb_lib.MLB 8C5 79A6 79C8 83A1 MEM_A_DQ<13> MEM_A_DQ<13> - @mlb_lib.MLB 12D7 29D8
=FDI_DATA_N<7..0> - @mlb_lib.MLB 8D8 GFX_DPRSLPVR GFX_DPRSLPVR - @mlb_lib.MLB 81A3 =IG_HDMI_LS_SCL - @mlb_lib.MLB 8C8 18C1 MEM_A_DQ<14> MEM_A_DQ<14> - @mlb_lib.MLB 12D7 29D8
FDI_DATA_N<2> FDI_DATA_N<2> - @mlb_lib.MLB 18D5 GFX_VID<6..0> GFX_VID<6..0> - @mlb_lib.MLB 81A3 HDMI_LS_SDA HDMI_LS_SDA - @mlb_lib.MLB 8C5 79A6 79C8 83A1 MEM_A_DQ<15> MEM_A_DQ<15> - @mlb_lib.MLB 12D7 29D8
=FDI_DATA_N<7..0> - @mlb_lib.MLB 8D8 GFX_VR_EN GFX_VR_EN - @mlb_lib.MLB 81A3 =IG_HDMI_LS_SDA - @mlb_lib.MLB 8C8 18C1 MEM_A_DQ<16> MEM_A_DQ<16> - @mlb_lib.MLB 12D7 29C8
FDI_DATA_N<3> FDI_DATA_N<3> - @mlb_lib.MLB 18D5 GMUX_INT GMUX_INT - @mlb_lib.MLB 20D6 20D8 HPAMP_B4GAIN_INL_N HPAMP_B4GAIN_INL_N - @mlb_lib.MLB 55C7 MEM_A_DQ<23..16> MEM_A_DQ<23..16> - @mlb_lib.MLB 82D3
=FDI_DATA_N<7..0> - @mlb_lib.MLB 8D8 GND_AUDIO_CODEC GND_AUDIO_CODEC - @mlb_lib.MLB 53A3 53B7 53D1 53D2 54C6 HPAMP_B4GAIN_INL_P HPAMP_B4GAIN_INL_P - @mlb_lib.MLB 55C7 MEM_A_DQ<17> MEM_A_DQ<17> - @mlb_lib.MLB 12D7 29C8
FDI_DATA_N<4> FDI_DATA_N<4> - @mlb_lib.MLB 18D5 57C1 58A4 58A4 58A7 58B3 HPAMP_B4GAIN_INR_N HPAMP_B4GAIN_INR_N - @mlb_lib.MLB 55B7 MEM_A_DQ<18> MEM_A_DQ<18> - @mlb_lib.MLB 12C7 29C8
=FDI_DATA_N<7..0> - @mlb_lib.MLB 8D8 58B8 58B8 58C4 HPAMP_B4GAIN_INR_P HPAMP_B4GAIN_INR_P - @mlb_lib.MLB 55B7 MEM_A_DQ<19> MEM_A_DQ<19> - @mlb_lib.MLB 12C7 29C8
FDI_DATA_N<5> FDI_DATA_N<5> - @mlb_lib.MLB 18D5 GND_AUDIO_HPAMP GND_AUDIO_HPAMP - @mlb_lib.MLB 53A3 55A6 55C7 HPAMP_BIAS HPAMP_BIAS - @mlb_lib.MLB 55C4 MEM_A_DQ<20> MEM_A_DQ<20> - @mlb_lib.MLB 12C7 29C8
=FDI_DATA_N<7..0> - @mlb_lib.MLB 8D8 GND_CHASSIS_AUDIO_JA GND_CHASSIS_AUDIO_JACK - 57A3 57B3 57C3 HPAMP_CN HPAMP_CN - @mlb_lib.MLB 55B4 MEM_A_DQ<21> MEM_A_DQ<21> - @mlb_lib.MLB 12C7 29C8
FDI_DATA_N<6> FDI_DATA_N<6> - @mlb_lib.MLB 18D5 CK @mlb_lib.MLB HPAMP_CP HPAMP_CP - @mlb_lib.MLB 55B4 MEM_A_DQ<22> MEM_A_DQ<22> - @mlb_lib.MLB 12C7 29C8
=FDI_DATA_N<7..0> - @mlb_lib.MLB 8D8 GND_DDRREG_SGND GND_DDRREG_SGND - @mlb_lib.MLB 66B7 HPAMP_PVSS HPAMP_PVSS - @mlb_lib.MLB 55B4 MEM_A_DQ<23> MEM_A_DQ<23> - @mlb_lib.MLB 12C7 29C8
FDI_DATA_N<7> FDI_DATA_N<7> - @mlb_lib.MLB 18D5 GND_DPACONN_1 GND_DPACONN_1 - @mlb_lib.MLB 78C3 HS_CPUDDR_IOUT HS_CPUDDR_IOUT - @mlb_lib.MLB 51C6 MEM_A_DQ<24> MEM_A_DQ<24> - @mlb_lib.MLB 12C7 29C8
=FDI_DATA_N<7..0> - @mlb_lib.MLB 8D8 GND_DPACONN_7 GND_DPACONN_7 - @mlb_lib.MLB 78B3 HS_MIC_BIAS HS_MIC_BIAS - @mlb_lib.MLB 58D2 MEM_A_DQ<31..24> MEM_A_DQ<31..24> - @mlb_lib.MLB 82D3
FDI_DATA_P<0> FDI_DATA_P<0> - @mlb_lib.MLB 18D5 GND_DPACONN_8 GND_DPACONN_8 - @mlb_lib.MLB 78B6 HS_MIC_HI HS_MIC_HI - @mlb_lib.MLB 57D3 58C1 MEM_A_DQ<25> MEM_A_DQ<25> - @mlb_lib.MLB 12C7 29C8
=FDI_DATA_P<7..0> - @mlb_lib.MLB 8D8 GND_DPACONN_13 GND_DPACONN_13 - @mlb_lib.MLB 78B3 HS_MIC_HI_R HS_MIC_HI_R - @mlb_lib.MLB 58C3 MEM_A_DQ<26> MEM_A_DQ<26> - @mlb_lib.MLB 12C7 29C8
FDI_DATA_P<7..0> FDI_DATA_P<7..0> - @mlb_lib.MLB 8D5 81D3 GND_DPACONN_14 GND_DPACONN_14 - @mlb_lib.MLB 78B6 HS_MIC_LO HS_MIC_LO - @mlb_lib.MLB 57D3 58C1 MEM_A_DQ<27> MEM_A_DQ<27> - @mlb_lib.MLB 12C7 29C8
=FDI_DATA_P<7..0> - @mlb_lib.MLB 8D8 GND_DPACONN_19 GND_DPACONN_19 - @mlb_lib.MLB 78A3 HS_RX_BP HS_RX_BP - @mlb_lib.MLB 58D2 MEM_A_DQ<28> MEM_A_DQ<28> - @mlb_lib.MLB 12C7 29C8
A FDI_DATA_P<1> FDI_DATA_P<1> - @mlb_lib.MLB
=FDI_DATA_P<7..0> - @mlb_lib.MLB
18D5
8D8
GND_IR_F
GND_SMC_AVSS
GND_IR_F - @mlb_lib.MLB
GND_SMC_AVSS - @mlb_lib.MLB
45C2
46C2 47D6 50A2 50A5 50A6
HS_SW_DET
I2C_T29_SCL
HS_SW_DET - @mlb_lib.MLB
I2C_T29_SCL - @mlb_lib.MLB
58D2
49B3 74A5 86C3
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<29> - @mlb_lib.MLB
MEM_A_DQ<30> - @mlb_lib.MLB
12C7
12C7
29C8
29C8
A
FDI_DATA_P<2> FDI_DATA_P<2> - @mlb_lib.MLB 18D5 50B1 50B5 50B5 50C2 50C5 =I2C_T29AMCU_SCL - @mlb_lib.MLB 49B1 77A7 MEM_A_DQ<31> MEM_A_DQ<31> - @mlb_lib.MLB 12C7 29C8
=FDI_DATA_P<7..0> - @mlb_lib.MLB 8D8 50D1 50D5 51C2 51C5 51D5 I2C_T29_SDA I2C_T29_SDA - @mlb_lib.MLB 49B3 74A5 86C3 MEM_A_DQ<32> MEM_A_DQ<32> - @mlb_lib.MLB 12C7 29B8
FDI_DATA_P<3> FDI_DATA_P<3> - @mlb_lib.MLB 18D5 GPIO29_SLP_LAN_L GPIO29_SLP_LAN_L - @mlb_lib.MLB 18A6 18C5 =I2C_T29AMCU_SDA - @mlb_lib.MLB 49B1 77A7 MEM_A_DQ<39..32> MEM_A_DQ<39..32> - @mlb_lib.MLB 82D3
=FDI_DATA_P<7..0> - @mlb_lib.MLB 8D8 GPUTHMSNS_D_N GPUTHMSNS_D_N - @mlb_lib.MLB 89B1 ICT_SEL ICT_SEL - @mlb_lib.MLB 24A5 24A8 24B8 MEM_A_DQ<33> MEM_A_DQ<33> - @mlb_lib.MLB 12C7 29B8
FDI_DATA_P<4> FDI_DATA_P<4> - @mlb_lib.MLB 18D5 GPUTHMSNS_D_P GPUTHMSNS_D_P - @mlb_lib.MLB 89B1 IRRCVR_OUT IRRCVR_OUT - @mlb_lib.MLB 44B7 45D4 91B7 MEM_A_DQ<34> MEM_A_DQ<34> - @mlb_lib.MLB 12C7 29B8
=FDI_DATA_P<7..0> - @mlb_lib.MLB 8D8 GPU_CLK27M GPU_CLK27M - @mlb_lib.MLB 88B1 IRRCVR_OUT_RC IRRCVR_OUT_RC - @mlb_lib.MLB 44B6 MEM_A_DQ<35> MEM_A_DQ<35> - @mlb_lib.MLB 12C7 29B8
FDI_DATA_P<5> FDI_DATA_P<5> - @mlb_lib.MLB 18D5 GPU_CLK100M GPU_CLK100M - @mlb_lib.MLB 88B1 IRUC_VREG IRUC_VREG - @mlb_lib.MLB 44C4 MEM_A_DQ<36> MEM_A_DQ<36> - @mlb_lib.MLB 12C7 29B8
=FDI_DATA_P<7..0> - @mlb_lib.MLB 8D8 GPU_CLK_TEST_N GPU_CLK_TEST_N - @mlb_lib.MLB 88B1 ISNS_HS_CPUDDR_N ISNS_HS_CPUDDR_N - @mlb_lib.MLB 51C7 MEM_A_DQ<37> MEM_A_DQ<37> - @mlb_lib.MLB 12C7 29B8
FDI_DATA_P<6> FDI_DATA_P<6> - @mlb_lib.MLB 18D5 GPU_CLK_TEST_P GPU_CLK_TEST_P - @mlb_lib.MLB 88B1 ISNS_HS_CPUDDR_P ISNS_HS_CPUDDR_P - @mlb_lib.MLB 51C7 MEM_A_DQ<38> MEM_A_DQ<38> - @mlb_lib.MLB 12C7 29B8
=FDI_DATA_P<7..0> - @mlb_lib.MLB 8D8 GPU_TDIODE_N GPU_TDIODE_N - @mlb_lib.MLB 89B1 ISNS_HS_GPU_N ISNS_HS_GPU_N - @mlb_lib.MLB 89C3 MEM_A_DQ<39> MEM_A_DQ<39> - @mlb_lib.MLB 12C7 29B8
FDI_DATA_P<7> FDI_DATA_P<7> - @mlb_lib.MLB 18C5 GPU_TDIODE_P GPU_TDIODE_P - @mlb_lib.MLB 89B1 ISNS_HS_GPU_P ISNS_HS_GPU_P - @mlb_lib.MLB 89C3 MEM_A_DQ<40> MEM_A_DQ<40> - @mlb_lib.MLB 12C7 29B8
=FDI_DATA_P<7..0> - @mlb_lib.MLB 8D8 HDA_BIT_CLK HDA_BIT_CLK - @mlb_lib.MLB 17A4 53C7 84C3 ISNS_P1V05PCH_N ISNS_P1V05PCH_N - @mlb_lib.MLB 50C7 MEM_A_DQ<47..40> MEM_A_DQ<47..40> - @mlb_lib.MLB 82D3

502

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
MEM_A_DQ<41> MEM_A_DQ<41> - @mlb_lib.MLB 12C7 29B8 MEM_B_DQ<37> MEM_B_DQ<37> - @mlb_lib.MLB 12C4 29B5 NC_EDP_TXN<3..0> NC_EDP_TXN<3..0> - @mlb_lib.MLB 91D3 NC_LVDS_IG_B_CLKP NC_LVDS_IG_B_CLKP - @mlb_lib.MLB 19B6 91D3
MEM_A_DQ<42> MEM_A_DQ<42> - @mlb_lib.MLB 12C7 29B8 MEM_B_DQ<38> MEM_B_DQ<38> - @mlb_lib.MLB 12C4 29B5 NC_EDP_TXN<1> NC_EDP_TXN<1> - @mlb_lib.MLB 10B7 NC_LVDS_IG_B_DATAN<0 NC_LVDS_IG_B_DATAN<0> - 19C6
MEM_A_DQ<43> MEM_A_DQ<43> - @mlb_lib.MLB 12C7 29B8 MEM_B_DQ<39> MEM_B_DQ<39> - @mlb_lib.MLB 12C4 29B5 NC_EDP_TXN<2> NC_EDP_TXN<2> - @mlb_lib.MLB 10B7 > @mlb_lib.MLB
MEM_A_DQ<44> MEM_A_DQ<44> - @mlb_lib.MLB 12B7 29B8 MEM_B_DQ<40> MEM_B_DQ<40> - @mlb_lib.MLB 12C4 29B5 NC_EDP_TXN<3> NC_EDP_TXN<3> - @mlb_lib.MLB 10B7 NC_LVDS_IG_B_DATAN<3 NC_LVDS_IG_B_DATAN<3..0> - 91D2
MEM_A_DQ<45> MEM_A_DQ<45> - @mlb_lib.MLB 12B7 29B8 MEM_B_DQ<47..40> MEM_B_DQ<47..40> - @mlb_lib.MLB 82B3 NC_EDP_TXP<0> NC_EDP_TXP<0> - @mlb_lib.MLB 10B7 ..0> @mlb_lib.MLB
MEM_A_DQ<46> MEM_A_DQ<46> - @mlb_lib.MLB 12B7 29B8 MEM_B_DQ<41> MEM_B_DQ<41> - @mlb_lib.MLB 12C4 29B5 NC_EDP_TXP<3..0> NC_EDP_TXP<3..0> - @mlb_lib.MLB 91D2 NC_LVDS_IG_B_DATAN<1 NC_LVDS_IG_B_DATAN<1> - 19C6
MEM_A_DQ<47> MEM_A_DQ<47> - @mlb_lib.MLB 12B7 29B8 MEM_B_DQ<42> MEM_B_DQ<42> - @mlb_lib.MLB 12C4 29B5 NC_EDP_TXP<1> NC_EDP_TXP<1> - @mlb_lib.MLB 10B7 > @mlb_lib.MLB
MEM_A_DQ<48> MEM_A_DQ<48> - @mlb_lib.MLB 12B7 29A8 MEM_B_DQ<43> MEM_B_DQ<43> - @mlb_lib.MLB 12C4 29B5 NC_EDP_TXP<2> NC_EDP_TXP<2> - @mlb_lib.MLB 10B7 NC_LVDS_IG_B_DATAN<2 NC_LVDS_IG_B_DATAN<2> - 19C6
MEM_A_DQ<55..48> MEM_A_DQ<55..48> - @mlb_lib.MLB 82D3 MEM_B_DQ<44> MEM_B_DQ<44> - @mlb_lib.MLB 12B4 29B5 NC_EDP_TXP<3> NC_EDP_TXP<3> - @mlb_lib.MLB 10B7 > @mlb_lib.MLB
MEM_A_DQ<49> MEM_A_DQ<49> - @mlb_lib.MLB 12B7 29A8 MEM_B_DQ<45> MEM_B_DQ<45> - @mlb_lib.MLB 12B4 29B5 NC_EG_DP_T29SNK0_AUX NC_EG_DP_T29SNK0_AUXCH_CN - 91B2 NC_LVDS_IG_B_DATAN<3 NC_LVDS_IG_B_DATAN<3> - 19C6
MEM_A_DQ<50> MEM_A_DQ<50> - @mlb_lib.MLB 12B7 29A8 MEM_B_DQ<46> MEM_B_DQ<46> - @mlb_lib.MLB 12B4 29B5 CH_CN @mlb_lib.MLB > @mlb_lib.MLB
MEM_A_DQ<51> MEM_A_DQ<51> - @mlb_lib.MLB 12B7 29A8 MEM_B_DQ<47> MEM_B_DQ<47> - @mlb_lib.MLB 12B4 29B5 NC_EG_DP_T29SNK0_AUX NC_EG_DP_T29SNK0_AUXCH_CP - 91B3 NC_LVDS_IG_B_DATAP<0 NC_LVDS_IG_B_DATAP<0> - 19C6
MEM_A_DQ<52> MEM_A_DQ<52> - @mlb_lib.MLB 12B7 29A8 MEM_B_DQ<48> MEM_B_DQ<48> - @mlb_lib.MLB 12B4 29A5 CH_CP @mlb_lib.MLB > @mlb_lib.MLB
MEM_A_DQ<53> MEM_A_DQ<53> - @mlb_lib.MLB 12B7 29A8 MEM_B_DQ<55..48> MEM_B_DQ<55..48> - @mlb_lib.MLB 82B3 NC_EG_DP_T29SNK0_ML_ NC_EG_DP_T29SNK0_ML_CN<3..0> - 91B2 NC_LVDS_IG_B_DATAP<3 NC_LVDS_IG_B_DATAP<3..0> - 91D1

D MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<54> - @mlb_lib.MLB
MEM_A_DQ<55> - @mlb_lib.MLB
12B7
12B7
29A8
29A8
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<49> - @mlb_lib.MLB
MEM_B_DQ<50> - @mlb_lib.MLB
12B4
12B4
29A5
29A5
CN<3..0>
NC_EG_DP_T29SNK0_ML_
@mlb_lib.MLB
NC_EG_DP_T29SNK0_ML_CP<3..0> - 91B3
..0>
NC_LVDS_IG_B_DATAP<1
@mlb_lib.MLB
NC_LVDS_IG_B_DATAP<1> - 19C6
D
MEM_A_DQ<56> MEM_A_DQ<56> - @mlb_lib.MLB 12B7 29A8 MEM_B_DQ<51> MEM_B_DQ<51> - @mlb_lib.MLB 12B4 29A5 CP<3..0> @mlb_lib.MLB > @mlb_lib.MLB
MEM_A_DQ<63..56> MEM_A_DQ<63..56> - @mlb_lib.MLB 82D3 MEM_B_DQ<52> MEM_B_DQ<52> - @mlb_lib.MLB 12B4 29A5 NC_FB_A0_A<8..0> NC_FB_A0_A<8..0> - @mlb_lib.MLB 91B2 NC_LVDS_IG_B_DATAP<2 NC_LVDS_IG_B_DATAP<2> - 19C6
MEM_A_DQ<57> MEM_A_DQ<57> - @mlb_lib.MLB 12B7 29A8 MEM_B_DQ<53> MEM_B_DQ<53> - @mlb_lib.MLB 12B4 29A5 NC_FB_A0_ABI_L NC_FB_A0_ABI_L - @mlb_lib.MLB 91B3 > @mlb_lib.MLB
MEM_A_DQ<58> MEM_A_DQ<58> - @mlb_lib.MLB 12B7 29A8 MEM_B_DQ<54> MEM_B_DQ<54> - @mlb_lib.MLB 12B4 29A5 NC_FB_A0_CAS_L NC_FB_A0_CAS_L - @mlb_lib.MLB 91B2 NC_LVDS_IG_B_DATAP<3 NC_LVDS_IG_B_DATAP<3> - 19C6
MEM_A_DQ<59> MEM_A_DQ<59> - @mlb_lib.MLB 12B7 29A8 MEM_B_DQ<55> MEM_B_DQ<55> - @mlb_lib.MLB 12B4 29A5 NC_FB_A0_CKE_L NC_FB_A0_CKE_L - @mlb_lib.MLB 91B3 > @mlb_lib.MLB
MEM_A_DQ<60> MEM_A_DQ<60> - @mlb_lib.MLB 12B7 29A8 MEM_B_DQ<56> MEM_B_DQ<56> - @mlb_lib.MLB 12B4 29A5 NC_FB_A0_CLKN NC_FB_A0_CLKN - @mlb_lib.MLB 91B2 NC_LVDS_IG_CTRL_CLK NC_LVDS_IG_CTRL_CLK - @mlb_lib.MLB 19B6 91D1
MEM_A_DQ<61> MEM_A_DQ<61> - @mlb_lib.MLB 12B7 29A8 MEM_B_DQ<63..56> MEM_B_DQ<63..56> - @mlb_lib.MLB 82B3 NC_FB_A0_CLKP NC_FB_A0_CLKP - @mlb_lib.MLB 91B3 NC_LVDS_IG_CTRL_DATA NC_LVDS_IG_CTRL_DATA - @mlb_lib.MLB 19B6 91D3
MEM_A_DQ<62> MEM_A_DQ<62> - @mlb_lib.MLB 12B7 29A8 MEM_B_DQ<57> MEM_B_DQ<57> - @mlb_lib.MLB 12B4 29A5 NC_FB_A0_CS_L NC_FB_A0_CS_L - @mlb_lib.MLB 91B2 NC_LVDS_IG_DDC_CLK NC_LVDS_IG_DDC_CLK - @mlb_lib.MLB 19B6 91D2
MEM_A_DQ<63> MEM_A_DQ<63> - @mlb_lib.MLB 12B7 29A8 MEM_B_DQ<58> MEM_B_DQ<58> - @mlb_lib.MLB 12B4 29A5 NC_FB_A0_DBI_L<3..0> NC_FB_A0_DBI_L<3..0> - @mlb_lib.MLB 91B3 NC_LVDS_IG_DDC_DATA NC_LVDS_IG_DDC_DATA - @mlb_lib.MLB 19B6 91D1
MEM_A_DQS_N<0> MEM_A_DQS_N<0> - @mlb_lib.MLB 12D5 29D8 82C3 MEM_B_DQ<59> MEM_B_DQ<59> - @mlb_lib.MLB 12B4 29A5 NC_FB_A0_DQ<31..0> NC_FB_A0_DQ<31..0> - @mlb_lib.MLB 91A2 NC_LVDS_IG_PANEL_PWR NC_LVDS_IG_PANEL_PWR - @mlb_lib.MLB 19B6 91D3
MEM_A_DQS_N<1> MEM_A_DQS_N<1> - @mlb_lib.MLB 12D5 29D8 82C3 MEM_B_DQ<60> MEM_B_DQ<60> - @mlb_lib.MLB 12B4 29A5 NC_FB_A0_EDC<3..0> NC_FB_A0_EDC<3..0> - @mlb_lib.MLB 91A3 NC_LVDS_IG_VREFH NC_LVDS_IG_VREFH - @mlb_lib.MLB 19B6 91D2
MEM_A_DQS_N<2> MEM_A_DQS_N<2> - @mlb_lib.MLB 12D5 29C8 82C3 MEM_B_DQ<61> MEM_B_DQ<61> - @mlb_lib.MLB 12B4 29A5 NC_FB_A0_RAS_L NC_FB_A0_RAS_L - @mlb_lib.MLB 91A2 NC_LVDS_IG_VREFL NC_LVDS_IG_VREFL - @mlb_lib.MLB 19B6 91D1
MEM_A_DQS_N<3> MEM_A_DQS_N<3> - @mlb_lib.MLB 12C5 29C8 82C3 MEM_B_DQ<62> MEM_B_DQ<62> - @mlb_lib.MLB 12B4 29A5 NC_FB_A0_WCLKN<1..0> NC_FB_A0_WCLKN<1..0> - @mlb_lib.MLB 91A3 NC_OBSFN_B0 NC_OBSFN_B0 - @mlb_lib.MLB 24D7 91C3
MEM_A_DQS_N<4> MEM_A_DQS_N<4> - @mlb_lib.MLB 12C5 29B8 82C3 MEM_B_DQ<63> MEM_B_DQ<63> - @mlb_lib.MLB 12B4 29A5 NC_FB_A0_WCLKP<1..0> NC_FB_A0_WCLKP<1..0> - @mlb_lib.MLB 91A2 NC_OBSFN_B1 NC_OBSFN_B1 - @mlb_lib.MLB 24D7 91C2
MEM_A_DQS_N<5> MEM_A_DQS_N<5> - @mlb_lib.MLB 12C5 29B8 82C3 MEM_B_DQS_N<0> MEM_B_DQS_N<0> - @mlb_lib.MLB 12D2 29D5 82B3 NC_FB_A0_WE_L NC_FB_A0_WE_L - @mlb_lib.MLB 91A3 NC_OBSFN_C0 NC_OBSFN_C0 - @mlb_lib.MLB 24D4 91C1
MEM_A_DQS_N<6> MEM_A_DQS_N<6> - @mlb_lib.MLB 12C5 29A8 82C3 MEM_B_DQS_N<1> MEM_B_DQS_N<1> - @mlb_lib.MLB 12D2 29D5 82B3 NC_FB_A1_A<8..0> NC_FB_A1_A<8..0> - @mlb_lib.MLB 91A2 NC_OBSFN_D01 NC_OBSFN_D01 - @mlb_lib.MLB 24D4 91C3
MEM_A_DQS_N<7> MEM_A_DQS_N<7> - @mlb_lib.MLB 12C5 29A8 82C3 MEM_B_DQS_N<2> MEM_B_DQS_N<2> - @mlb_lib.MLB 12D2 29C5 82B3 NC_FB_A1_ABI_L NC_FB_A1_ABI_L - @mlb_lib.MLB 91A3 NC_OBSFN_D11 NC_OBSFN_D11 - @mlb_lib.MLB 24D4 91C2
MEM_A_DQS_P<0> MEM_A_DQS_P<0> - @mlb_lib.MLB 12C5 29D8 82D3 MEM_B_DQS_N<3> MEM_B_DQS_N<3> - @mlb_lib.MLB 12C2 29C5 82B3 NC_FB_A1_CAS_L NC_FB_A1_CAS_L - @mlb_lib.MLB 91A2 NC_PCH_CLKOUT_DPN NC_PCH_CLKOUT_DPN - @mlb_lib.MLB 17C1 91C1
MEM_A_DQS_P<1> MEM_A_DQS_P<1> - @mlb_lib.MLB 12C5 29D8 82C3 MEM_B_DQS_N<4> MEM_B_DQS_N<4> - @mlb_lib.MLB 12C2 29B5 82A3 NC_FB_A1_CKE_L NC_FB_A1_CKE_L - @mlb_lib.MLB 91A3 NC_PCH_CLKOUT_DPP NC_PCH_CLKOUT_DPP - @mlb_lib.MLB 17C1 91C3
MEM_A_DQS_P<2> MEM_A_DQS_P<2> - @mlb_lib.MLB 12C5 29C8 82C3 MEM_B_DQS_N<5> MEM_B_DQS_N<5> - @mlb_lib.MLB 12C2 29B5 82A3 NC_FB_A1_CLKN NC_FB_A1_CLKN - @mlb_lib.MLB 91A2 NC_PCH_GPIO64_CLKOUT NC_PCH_GPIO64_CLKOUTFLEX0 - 17B1 91C2
MEM_A_DQS_P<3> MEM_A_DQS_P<3> - @mlb_lib.MLB 12C5 29C8 82C3 MEM_B_DQS_N<6> MEM_B_DQS_N<6> - @mlb_lib.MLB 12C2 29A5 82A3 NC_FB_A1_CLKP NC_FB_A1_CLKP - @mlb_lib.MLB 91A3 FLEX0 @mlb_lib.MLB
MEM_A_DQS_P<4> MEM_A_DQS_P<4> - @mlb_lib.MLB 12C5 29B8 82C3 MEM_B_DQS_N<7> MEM_B_DQS_N<7> - @mlb_lib.MLB 12C2 29A5 82A3 NC_FB_A1_CS_L NC_FB_A1_CS_L - @mlb_lib.MLB 91A2 NC_PCH_GPIO65_CLKOUT NC_PCH_GPIO65_CLKOUTFLEX1 - 17B1 91C1
MEM_A_DQS_P<5> MEM_A_DQS_P<5> - @mlb_lib.MLB 12C5 29B8 82C3 MEM_B_DQS_P<0> MEM_B_DQS_P<0> - @mlb_lib.MLB 12C2 29D5 82B3 NC_FB_A1_DBI_L<3..0> NC_FB_A1_DBI_L<3..0> - @mlb_lib.MLB 91A3 FLEX1 @mlb_lib.MLB
MEM_A_DQS_P<6> MEM_A_DQS_P<6> - @mlb_lib.MLB 12C5 29A8 82C3 MEM_B_DQS_P<1> MEM_B_DQS_P<1> - @mlb_lib.MLB 12C2 29D5 82B3 NC_FB_A1_DQ<31..0> NC_FB_A1_DQ<31..0> - @mlb_lib.MLB 91A2 NC_PCH_GPIO66_CLKOUT NC_PCH_GPIO66_CLKOUTFLEX2 - 17B1 91C3
MEM_A_DQS_P<7> MEM_A_DQS_P<7> - @mlb_lib.MLB 12C5 29A8 82C3 MEM_B_DQS_P<2> MEM_B_DQS_P<2> - @mlb_lib.MLB 12C2 29C5 82B3 NC_FB_A1_EDC<3..0> NC_FB_A1_EDC<3..0> - @mlb_lib.MLB 91A3 FLEX2 @mlb_lib.MLB
MEM_A_ODT<0> MEM_A_ODT<0> - @mlb_lib.MLB 12D5 30B5 MEM_B_DQS_P<3> MEM_B_DQS_P<3> - @mlb_lib.MLB 12C2 29C5 82B3 NC_FB_A1_RAS_L NC_FB_A1_RAS_L - @mlb_lib.MLB 91A2 NC_PCH_GPIO67_CLKOUT NC_PCH_GPIO67_CLKOUTFLEX3 - 17B1 91C2
MEM_A_ODT<3..0> MEM_A_ODT<3..0> - @mlb_lib.MLB 82D3 MEM_B_DQS_P<4> MEM_B_DQS_P<4> - @mlb_lib.MLB 12C2 29B5 82B3 NC_FB_A1_WCLKN<1..0> NC_FB_A1_WCLKN<1..0> - @mlb_lib.MLB 91A3 FLEX3 @mlb_lib.MLB
MEM_A_ODT<1> MEM_A_ODT<1> - @mlb_lib.MLB 12D5 30B5 MEM_B_DQS_P<5> MEM_B_DQS_P<5> - @mlb_lib.MLB 12C2 29B5 82A3 NC_FB_A1_WCLKP<1..0> NC_FB_A1_WCLKP<1..0> - @mlb_lib.MLB 91A2 NC_PCH_LVDS_IBG NC_PCH_LVDS_IBG - @mlb_lib.MLB 19B6 91C1
MEM_A_RAS_L MEM_A_RAS_L - @mlb_lib.MLB 12B7 30B5 82D3 MEM_B_DQS_P<6> MEM_B_DQS_P<6> - @mlb_lib.MLB 12C2 29A5 82A3 NC_FB_A1_WE_L NC_FB_A1_WE_L - @mlb_lib.MLB 91A3 NC_PCH_LVDS_VBG NC_PCH_LVDS_VBG - @mlb_lib.MLB 19B6 91C3
MEM_A_SA<0> MEM_A_SA<0> - @mlb_lib.MLB 30A7 30B3 MEM_B_DQS_P<7> MEM_B_DQS_P<7> - @mlb_lib.MLB 12C2 29A5 82A3 NC_FW_P1_TPAN NC_FW_P1_TPAN - @mlb_lib.MLB 39A3 91D1 NC_PCIE_4_D2RN NC_PCIE_4_D2RN - @mlb_lib.MLB 17D4 91C1

C MEM_A_SA<1>
MEM_A_WE_L
MEM_A_SA<1> - @mlb_lib.MLB
MEM_A_WE_L - @mlb_lib.MLB
30A7
12A7
30B3
30B7 82D3
MEM_B_ODT<0>
MEM_B_ODT<3..0>
MEM_B_ODT<0> - @mlb_lib.MLB
MEM_B_ODT<3..0> - @mlb_lib.MLB
12D2
82B3
31B5 NC_FW_P1_TPAP
NC_FW_P1_TPBIAS
NC_FW_P1_TPAP - @mlb_lib.MLB
NC_FW_P1_TPBIAS - @mlb_lib.MLB
39A3
39A3
91D3
91D2
NC_PCIE_4_D2RP
NC_PCIE_4_R2D_CN
NC_PCIE_4_D2RP - @mlb_lib.MLB
NC_PCIE_4_R2D_CN - @mlb_lib.MLB
17D4
17D4
91C3
91C2
C
MEM_B_A<0> MEM_B_A<0> - @mlb_lib.MLB 12C2 31C5 MEM_B_ODT<1> MEM_B_ODT<1> - @mlb_lib.MLB 12D2 31B5 NC_FW_P2_TPAN NC_FW_P2_TPAN - @mlb_lib.MLB 39A3 91D1 NC_PCIE_4_R2D_CP NC_PCIE_4_R2D_CP - @mlb_lib.MLB 17D4 91C1
MEM_B_A<15..0> MEM_B_A<15..0> - @mlb_lib.MLB 82B3 MEM_B_RAS_L MEM_B_RAS_L - @mlb_lib.MLB 12B4 31B5 82B3 NC_FW_P2_TPAP NC_FW_P2_TPAP - @mlb_lib.MLB 39A3 91D3 NC_PCIE_5_D2RN NC_PCIE_5_D2RN - @mlb_lib.MLB 17C4 91C3
MEM_B_A<1> MEM_B_A<1> - @mlb_lib.MLB 12C2 31C7 MEM_B_SA<0> MEM_B_SA<0> - @mlb_lib.MLB 31A7 31B3 NC_FW_P2_TPBIAS NC_FW_P2_TPBIAS - @mlb_lib.MLB 39A3 91D2 NC_PCIE_5_D2RP NC_PCIE_5_D2RP - @mlb_lib.MLB 17C4 91C2
MEM_B_A<2> MEM_B_A<2> - @mlb_lib.MLB 12C2 31C5 MEM_B_SA<1> MEM_B_SA<1> - @mlb_lib.MLB 31A7 31B3 NC_GPIO35 NC_GPIO35 - @mlb_lib.MLB 20C6 91D1 NC_PCIE_5_R2D_CN NC_PCIE_5_R2D_CN - @mlb_lib.MLB 17C4 91C1
MEM_B_A<3> MEM_B_A<3> - @mlb_lib.MLB 12C2 31C7 MEM_B_WE_L MEM_B_WE_L - @mlb_lib.MLB 12A4 31B7 82B3 NC_GPU_GENERICB NC_GPU_GENERICB - @mlb_lib.MLB 91A3 NC_PCIE_5_R2D_CP NC_PCIE_5_R2D_CP - @mlb_lib.MLB 17C4 91C3
MEM_B_A<4> MEM_B_A<4> - @mlb_lib.MLB 12C2 31C5 MEM_EVENT_L MEM_EVENT_L - @mlb_lib.MLB 30A5 31A5 46B8 NC_GPU_GENERICC NC_GPU_GENERICC - @mlb_lib.MLB 91A3 NC_PCIE_6_D2RN NC_PCIE_6_D2RN - @mlb_lib.MLB 17C4 91C2
MEM_B_A<5> MEM_B_A<5> - @mlb_lib.MLB 12C2 31C7 MEM_RESET_L MEM_RESET_L - @mlb_lib.MLB 28A5 30D5 31D5 NC_GPU_GENERICE NC_GPU_GENERICE - @mlb_lib.MLB 91A3 NC_PCIE_6_D2RP NC_PCIE_6_D2RP - @mlb_lib.MLB 17C4 91C1

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MEM_B_A<6> MEM_B_A<6> - @mlb_lib.MLB 12C2 31C5 NC_AUD_GPIO_0 NC_AUD_GPIO_0 - @mlb_lib.MLB 53D7 91D3 NC_GPU_GENERICF NC_GPU_GENERICF - @mlb_lib.MLB 91A3 NC_PCIE_6_R2D_CN NC_PCIE_6_R2D_CN - @mlb_lib.MLB 17C4 91C3
MEM_B_A<7> MEM_B_A<7> - @mlb_lib.MLB 12C2 31C5 NC_AUD_GPIO_2 NC_AUD_GPIO_2 - @mlb_lib.MLB 53D7 91D2 NC_GPU_GENERICG NC_GPU_GENERICG - @mlb_lib.MLB 91A3 NC_PCIE_6_R2D_CP NC_PCIE_6_R2D_CP - @mlb_lib.MLB 17C4 91C2
MEM_B_A<8> MEM_B_A<8> - @mlb_lib.MLB 12C2 31C7 NC_AUD_HP_PORT_L NC_AUD_HP_PORT_L - @mlb_lib.MLB 53D2 91D1 NC_HDA_SDIN1 NC_HDA_SDIN1 - @mlb_lib.MLB 17C8 91D2 NC_PCIE_7_D2RN NC_PCIE_7_D2RN - @mlb_lib.MLB 17C4 91C1
MEM_B_A<9> MEM_B_A<9> - @mlb_lib.MLB 12C2 31C7 NC_AUD_HP_PORT_R NC_AUD_HP_PORT_R - @mlb_lib.MLB 53D2 91D3 NC_HDA_SDIN2 NC_HDA_SDIN2 - @mlb_lib.MLB 17C8 91D1 NC_PCIE_7_D2RP NC_PCIE_7_D2RP - @mlb_lib.MLB 17C4 91C3
MEM_B_A<10> MEM_B_A<10> - @mlb_lib.MLB 12C2 31B7 NC_AUD_LO3_N_R NC_AUD_LO3_N_R - @mlb_lib.MLB 53C2 91D2 NC_HDA_SDIN3 NC_HDA_SDIN3 - @mlb_lib.MLB 17C8 91D3 NC_PCIE_7_R2D_CN NC_PCIE_7_R2D_CN - @mlb_lib.MLB 17C4 91C2
MEM_B_A<11> MEM_B_A<11> - @mlb_lib.MLB 12B2 31C5 NC_AUD_LO3_P_R NC_AUD_LO3_P_R - @mlb_lib.MLB 53C2 91D1 NC_HD_OC NC_HD_OC - @mlb_lib.MLB 80D3 91D3 NC_PCIE_7_R2D_CP NC_PCIE_7_R2D_CP - @mlb_lib.MLB 17C4 91C1
MEM_B_A<12> MEM_B_A<12> - @mlb_lib.MLB 12B2 31C7 NC_AUD_MIC_INN_R NC_AUD_MIC_INN_R - @mlb_lib.MLB 53C2 91D3 NC_IG_DP_T29SNK0_AUX NC_IG_DP_T29SNK0_AUXCH_CN - 91D3 NC_PCIE_8_D2RN NC_PCIE_8_D2RN - @mlb_lib.MLB 17C4 91C3
MEM_B_A<13> MEM_B_A<13> - @mlb_lib.MLB 12B2 31B7 NC_AUD_MIC_INP_R NC_AUD_MIC_INP_R - @mlb_lib.MLB 53C2 91D2 CH_CN @mlb_lib.MLB NC_PCIE_8_D2RP NC_PCIE_8_D2RP - @mlb_lib.MLB 17C4 91C2
MEM_B_A<14> MEM_B_A<14> - @mlb_lib.MLB 12B2 31C5 NC_BCM57765_CE_L_MS_ NC_BCM57765_CE_L_MS_INS_L - 37B3 91D1 NC_IG_DP_T29SNK0_AUX NC_IG_DP_T29SNK0_AUXCH_CP - 91D2 NC_PCIE_8_R2D_CN NC_PCIE_8_R2D_CN - @mlb_lib.MLB 17C4 91C1
MEM_B_A<15> MEM_B_A<15> - @mlb_lib.MLB 12B2 31C5 INS_L @mlb_lib.MLB CH_CP @mlb_lib.MLB NC_PCIE_8_R2D_CP NC_PCIE_8_R2D_CP - @mlb_lib.MLB 17C4 91C3
MEM_B_BA<0> MEM_B_BA<0> - @mlb_lib.MLB 12B4 31B7 NC_CLINK_CLK NC_CLINK_CLK - @mlb_lib.MLB 17B1 91D3 NC_IG_DP_T29SNK0_CTR NC_IG_DP_T29SNK0_CTRL_CLK - 91D1 NC_PCIE_CLK100M_EXCA NC_PCIE_CLK100M_EXCARDN - 17B4 91C2
MEM_B_BA<2..0> MEM_B_BA<2..0> - @mlb_lib.MLB 82B3 NC_CLINK_DATA NC_CLINK_DATA - @mlb_lib.MLB 17B1 91D2 L_CLK @mlb_lib.MLB RDN @mlb_lib.MLB
MEM_B_BA<1> MEM_B_BA<1> - @mlb_lib.MLB 12B4 31B5 NC_CLINK_RESET_L NC_CLINK_RESET_L - @mlb_lib.MLB 17B1 91D1 NC_IG_DP_T29SNK0_CTR NC_IG_DP_T29SNK0_CTRL_DATA - 91D3 NC_PCIE_CLK100M_EXCA NC_PCIE_CLK100M_EXCARDP - 17B4 91C1
MEM_B_BA<2> MEM_B_BA<2> - @mlb_lib.MLB 12B4 31C7 NC_CPU_AXG_SENSEN NC_CPU_AXG_SENSEN - @mlb_lib.MLB 91B3 L_DATA @mlb_lib.MLB RDP @mlb_lib.MLB
MEM_B_CAS_L MEM_B_CAS_L - @mlb_lib.MLB 12B4 31B7 82B3 NC_CPU_AXG_SENSEP NC_CPU_AXG_SENSEP - @mlb_lib.MLB 91B2 NC_IG_DP_T29SNK0_HPD NC_IG_DP_T29SNK0_HPD - @mlb_lib.MLB 91D2 NC_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5N - @mlb_lib.MLB 17B4 91C3
MEM_B_CKE<0> MEM_B_CKE<0> - @mlb_lib.MLB 12D2 31C7 NC_CPU_AXG_VALSENSEN NC_CPU_AXG_VALSENSEN - @mlb_lib.MLB 91B2 NC_IG_DP_T29SNK0_ML_ NC_IG_DP_T29SNK0_ML_CN<3..0> - 91D1 NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE5P - @mlb_lib.MLB 17B4 91C2
MEM_B_CKE<3..0> MEM_B_CKE<3..0> - @mlb_lib.MLB 82B3 NC_CPU_AXG_VALSENSEP NC_CPU_AXG_VALSENSEP - @mlb_lib.MLB 91B3 CN<3..0> @mlb_lib.MLB NC_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6N - @mlb_lib.MLB 20D3 91C1
MEM_B_CKE<1> MEM_B_CKE<1> - @mlb_lib.MLB 12D2 31C5 NC_CRT_IG_BLUE NC_CRT_IG_BLUE - @mlb_lib.MLB 18C4 91D3 NC_IG_DP_T29SNK0_ML_ NC_IG_DP_T29SNK0_ML_CP<3..0> - 91D3 NC_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE6P - @mlb_lib.MLB 20D3 91C3
MEM_B_CLK_N<0> MEM_B_CLK_N<0> - @mlb_lib.MLB 12D2 31C7 NC_CRT_IG_DDC_CLK NC_CRT_IG_DDC_CLK - @mlb_lib.MLB 18B4 91D2 CP<3..0> @mlb_lib.MLB NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7N - @mlb_lib.MLB 20D3 91C2
MEM_B_CLK_N<5..0> MEM_B_CLK_N<5..0> - @mlb_lib.MLB 82C3 NC_CRT_IG_DDC_DATA NC_CRT_IG_DDC_DATA - @mlb_lib.MLB 18B4 91D1 NC_IG_D_AUXN NC_IG_D_AUXN - @mlb_lib.MLB 18C1 91D2 NC_PCIE_CLK100M_PE7P NC_PCIE_CLK100M_PE7P - @mlb_lib.MLB 20D3 91C1
MEM_B_CLK_N<1> MEM_B_CLK_N<1> - @mlb_lib.MLB 12D2 31C5 NC_CRT_IG_GREEN NC_CRT_IG_GREEN - @mlb_lib.MLB 18C4 91D3 NC_IG_D_AUXP NC_IG_D_AUXP - @mlb_lib.MLB 18C1 91D1 NC_PCIE_CLK100M_PEBN NC_PCIE_CLK100M_PEBN - @mlb_lib.MLB 17B4 91C3
MEM_B_CLK_P<0> MEM_B_CLK_P<0> - @mlb_lib.MLB 12D2 31C7 NC_CRT_IG_HSYNC NC_CRT_IG_HSYNC - @mlb_lib.MLB 18B4 91D2 NC_IRUC_P02 NC_IRUC_P02 - @mlb_lib.MLB 44C6 91D2 NC_PCIE_CLK100M_PEBP NC_PCIE_CLK100M_PEBP - @mlb_lib.MLB 17B4 91C2
MEM_B_CLK_P<5..0> MEM_B_CLK_P<5..0> - @mlb_lib.MLB 82C3 NC_CRT_IG_RED NC_CRT_IG_RED - @mlb_lib.MLB 18B4 91D1 NC_IRUC_P03 NC_IRUC_P03 - @mlb_lib.MLB 44C6 91D1 NC_PCIE_CLK100M_T29N NC_PCIE_CLK100M_T29N - @mlb_lib.MLB 91C1

B MEM_B_CLK_P<1>
MEM_B_CS_L<0>
MEM_B_CLK_P<1> - @mlb_lib.MLB
MEM_B_CS_L<0> - @mlb_lib.MLB
12D2
12D2
31C5
31B5
NC_CRT_IG_VSYNC
NC_CS4206_FP
NC_CRT_IG_VSYNC - @mlb_lib.MLB
NC_CS4206_FP - @mlb_lib.MLB
18B4
53D5
91D3
91D2
NC_IRUC_P04
NC_IRUC_P06
NC_IRUC_P04 - @mlb_lib.MLB
NC_IRUC_P06 - @mlb_lib.MLB
44C6
44B6
91D3
91D2
NC_PCIE_CLK100M_T29P
NC_PCIE_T29_D2RN<3..
NC_PCIE_CLK100M_T29P - @mlb_lib.MLB
NC_PCIE_T29_D2RN<3..0> -
91C3
91C2 B
MEM_B_CS_L<3..0> MEM_B_CS_L<3..0> - @mlb_lib.MLB 82B3 NC_CS4206_MICBIAS NC_CS4206_MICBIAS - @mlb_lib.MLB 53C2 91D1 NC_IRUC_P13 NC_IRUC_P13 - @mlb_lib.MLB 44C4 91D1 0> @mlb_lib.MLB
MEM_B_CS_L<1> MEM_B_CS_L<1> - @mlb_lib.MLB 12D2 31B7 NC_DP_OC NC_DP_OC - @mlb_lib.MLB 91D3 NC_IRUC_P14 NC_IRUC_P14 - @mlb_lib.MLB 44C4 91D3 NC_PCIE_T29_D2RP<3.. NC_PCIE_T29_D2RP<3..0> - 91C1
MEM_B_DQ<0> MEM_B_DQ<0> - @mlb_lib.MLB 12D4 29D5 NC_DP_T29SNK1_AUXCHN NC_DP_T29SNK1_AUXCHN - @mlb_lib.MLB 74A5 91A1 NC_IRUC_P15 NC_IRUC_P15 - @mlb_lib.MLB 44B4 91D2 0> @mlb_lib.MLB
MEM_B_DQ<7..0> MEM_B_DQ<7..0> - @mlb_lib.MLB 82B3 NC_DP_T29SNK1_AUXCHP NC_DP_T29SNK1_AUXCHP - @mlb_lib.MLB 74A5 91A1 NC_IRUC_P16 NC_IRUC_P16 - @mlb_lib.MLB 44B4 91D1 NC_PCIE_T29_R2D_CN<3 NC_PCIE_T29_R2D_CN<3..0> - 91C3
MEM_B_DQ<1> MEM_B_DQ<1> - @mlb_lib.MLB 12D4 29D5 NC_DP_T29SNK1_MLN<0> NC_DP_T29SNK1_MLN<0> - @mlb_lib.MLB 74A5 NC_LPC_DREQ0_L NC_LPC_DREQ0_L - @mlb_lib.MLB 17D5 91D3 ..0> @mlb_lib.MLB
MEM_B_DQ<2> MEM_B_DQ<2> - @mlb_lib.MLB 12D4 29D5 NC_DP_T29SNK1_MLN<3. NC_DP_T29SNK1_MLN<3..0> - 91A1 NC_LVDS_EG_A_CLKN NC_LVDS_EG_A_CLKN - @mlb_lib.MLB 91A3 NC_PCIE_T29_R2D_CP<3 NC_PCIE_T29_R2D_CP<3..0> - 91C2
MEM_B_DQ<3> MEM_B_DQ<3> - @mlb_lib.MLB 12D4 29D5 .0> @mlb_lib.MLB NC_LVDS_EG_A_CLKP NC_LVDS_EG_A_CLKP - @mlb_lib.MLB 91A3 ..0> @mlb_lib.MLB
MEM_B_DQ<4> MEM_B_DQ<4> - @mlb_lib.MLB 12D4 29D5 NC_DP_T29SNK1_MLN<1> NC_DP_T29SNK1_MLN<1> - @mlb_lib.MLB 74B5 NC_LVDS_EG_A_DATAN<3 NC_LVDS_EG_A_DATAN<3..0> - 91A3 NC_PCI_PME_L NC_PCI_PME_L - @mlb_lib.MLB 19D6 91C2
MEM_B_DQ<5> MEM_B_DQ<5> - @mlb_lib.MLB 12D4 29D5 NC_DP_T29SNK1_MLN<2> NC_DP_T29SNK1_MLN<2> - @mlb_lib.MLB 74B5 ..0> @mlb_lib.MLB NC_PEG_CLK100MN NC_PEG_CLK100MN - @mlb_lib.MLB 8D5 91C1
MEM_B_DQ<6> MEM_B_DQ<6> - @mlb_lib.MLB 12D4 29D5 NC_DP_T29SNK1_MLN<3> NC_DP_T29SNK1_MLN<3> - @mlb_lib.MLB 74B5 NC_LVDS_EG_A_DATAP<3 NC_LVDS_EG_A_DATAP<3..0> - 91A3 PEG_CLK100M_N - @mlb_lib.MLB 8D8 17C1 84C1
MEM_B_DQ<7> MEM_B_DQ<7> - @mlb_lib.MLB 12D4 29D5 NC_DP_T29SNK1_MLP<0> NC_DP_T29SNK1_MLP<0> - @mlb_lib.MLB 74B5 ..0> @mlb_lib.MLB NC_PEG_CLK100MP NC_PEG_CLK100MP - @mlb_lib.MLB 8D5 91C3
MEM_B_DQ<8> MEM_B_DQ<8> - @mlb_lib.MLB 12D4 29D5 NC_DP_T29SNK1_MLP<3. NC_DP_T29SNK1_MLP<3..0> - 91A1 NC_LVDS_EG_B_CLKN NC_LVDS_EG_B_CLKN - @mlb_lib.MLB 91A3 PEG_CLK100M_P - @mlb_lib.MLB 8D8 17C1 84C1
MEM_B_DQ<15..8> MEM_B_DQ<15..8> - @mlb_lib.MLB 82B3 .0> @mlb_lib.MLB NC_LVDS_EG_B_CLKP NC_LVDS_EG_B_CLKP - @mlb_lib.MLB 91A3 NC_PEG_D2RN<7..0> NC_PEG_D2RN<7..0> - @mlb_lib.MLB 8D5 91C2
MEM_B_DQ<9> MEM_B_DQ<9> - @mlb_lib.MLB 12D4 29D5 NC_DP_T29SNK1_MLP<1> NC_DP_T29SNK1_MLP<1> - @mlb_lib.MLB 74B5 NC_LVDS_EG_B_DATAN<3 NC_LVDS_EG_B_DATAN<3..0> - 91A3 =PEG_D2R_N<7..0> - @mlb_lib.MLB 8D8
MEM_B_DQ<10> MEM_B_DQ<10> - @mlb_lib.MLB 12D4 29D5 NC_DP_T29SNK1_MLP<2> NC_DP_T29SNK1_MLP<2> - @mlb_lib.MLB 74B5 ..0> @mlb_lib.MLB NC_PEG_D2RN<12> NC_PEG_D2RN<12> - @mlb_lib.MLB 10D5
MEM_B_DQ<11> MEM_B_DQ<11> - @mlb_lib.MLB 12D4 29D5 NC_DP_T29SNK1_MLP<3> NC_DP_T29SNK1_MLP<3> - @mlb_lib.MLB 74B5 NC_LVDS_EG_B_DATAP<3 NC_LVDS_EG_B_DATAP<3..0> - 91A3 NC_PEG_D2RN<15..12> NC_PEG_D2RN<15..12> - @mlb_lib.MLB 91C1
MEM_B_DQ<12> MEM_B_DQ<12> - @mlb_lib.MLB 12D4 29D5 NC_DP_T29SRC_AUXCH_C NC_DP_T29SRC_AUXCH_CN - 74B3 91A1 ..0> @mlb_lib.MLB NC_PEG_D2RN<13> NC_PEG_D2RN<13> - @mlb_lib.MLB 10D5
MEM_B_DQ<13> MEM_B_DQ<13> - @mlb_lib.MLB 12D4 29D5 N @mlb_lib.MLB NC_LVDS_EG_DDC_CLK NC_LVDS_EG_DDC_CLK - @mlb_lib.MLB 91A3 NC_PEG_D2RN<14> NC_PEG_D2RN<14> - @mlb_lib.MLB 10C5
MEM_B_DQ<14> MEM_B_DQ<14> - @mlb_lib.MLB 12D4 29D5 NC_DP_T29SRC_AUXCH_C NC_DP_T29SRC_AUXCH_CP - 74B3 91A1 NC_LVDS_EG_DDC_DATA NC_LVDS_EG_DDC_DATA - @mlb_lib.MLB 91A3 NC_PEG_D2RN<15> NC_PEG_D2RN<15> - @mlb_lib.MLB 10C5
MEM_B_DQ<15> MEM_B_DQ<15> - @mlb_lib.MLB 12D4 29D5 P @mlb_lib.MLB NC_LVDS_IG_A_CLKN NC_LVDS_IG_A_CLKN - @mlb_lib.MLB 19C6 91D2 NC_PEG_D2RP<7..0> NC_PEG_D2RP<7..0> - @mlb_lib.MLB 8D5 91C3
MEM_B_DQ<16> MEM_B_DQ<16> - @mlb_lib.MLB 12D4 29C5 NC_DP_T29SRC_ML_CN<0 NC_DP_T29SRC_ML_CN<0> - 74B3 NC_LVDS_IG_A_CLKP NC_LVDS_IG_A_CLKP - @mlb_lib.MLB 19C6 91D1 =PEG_D2R_P<7..0> - @mlb_lib.MLB 8D8
MEM_B_DQ<23..16> MEM_B_DQ<23..16> - @mlb_lib.MLB 82B3 > @mlb_lib.MLB NC_LVDS_IG_A_DATAN<0 NC_LVDS_IG_A_DATAN<0> - 19C6 NC_PEG_D2RP<12> NC_PEG_D2RP<12> - @mlb_lib.MLB 10C5
MEM_B_DQ<17> MEM_B_DQ<17> - @mlb_lib.MLB 12D4 29C5 NC_DP_T29SRC_ML_CN<3 NC_DP_T29SRC_ML_CN<3..0> - 91A1 > @mlb_lib.MLB NC_PEG_D2RP<15..12> NC_PEG_D2RP<15..12> - @mlb_lib.MLB 91C2
MEM_B_DQ<18> MEM_B_DQ<18> - @mlb_lib.MLB 12C4 29C5 ..0> @mlb_lib.MLB NC_LVDS_IG_A_DATAN<3 NC_LVDS_IG_A_DATAN<3..0> - 91D3 NC_PEG_D2RP<13> NC_PEG_D2RP<13> - @mlb_lib.MLB 10C5
MEM_B_DQ<19> MEM_B_DQ<19> - @mlb_lib.MLB 12C4 29C5 NC_DP_T29SRC_ML_CN<1 NC_DP_T29SRC_ML_CN<1> - 74B3 ..0> @mlb_lib.MLB NC_PEG_D2RP<14> NC_PEG_D2RP<14> - @mlb_lib.MLB 10C5
MEM_B_DQ<20> MEM_B_DQ<20> - @mlb_lib.MLB 12C4 29C5 > @mlb_lib.MLB NC_LVDS_IG_A_DATAN<1 NC_LVDS_IG_A_DATAN<1> - 19C6 NC_PEG_D2RP<15> NC_PEG_D2RP<15> - @mlb_lib.MLB 10C5
MEM_B_DQ<21> MEM_B_DQ<21> - @mlb_lib.MLB 12C4 29C5 NC_DP_T29SRC_ML_CN<2 NC_DP_T29SRC_ML_CN<2> - 74B3 > @mlb_lib.MLB NC_PEG_R2D_CN<7..0> NC_PEG_R2D_CN<7..0> - @mlb_lib.MLB 8D5 91C1
MEM_B_DQ<22> MEM_B_DQ<22> - @mlb_lib.MLB 12C4 29C5 > @mlb_lib.MLB NC_LVDS_IG_A_DATAN<2 NC_LVDS_IG_A_DATAN<2> - 19C6 =PEG_R2D_C_N<7..0> - @mlb_lib.MLB 8D8
MEM_B_DQ<23> MEM_B_DQ<23> - @mlb_lib.MLB 12C4 29C5 NC_DP_T29SRC_ML_CN<3 NC_DP_T29SRC_ML_CN<3> - 74B3 > @mlb_lib.MLB NC_PEG_R2D_CN<12> NC_PEG_R2D_CN<12> - @mlb_lib.MLB 10B5
MEM_B_DQ<24> MEM_B_DQ<24> - @mlb_lib.MLB 12C4 29C5 > @mlb_lib.MLB NC_LVDS_IG_A_DATAN<3 NC_LVDS_IG_A_DATAN<3> - 19C6 NC_PEG_R2D_CN<15..12 NC_PEG_R2D_CN<15..12> - 91C3
A MEM_B_DQ<31..24>
MEM_B_DQ<25>
MEM_B_DQ<31..24> - @mlb_lib.MLB
MEM_B_DQ<25> - @mlb_lib.MLB
82B3
12C4 29C5
NC_DP_T29SRC_ML_CP<0
>
NC_DP_T29SRC_ML_CP<0> -
@mlb_lib.MLB
74B3 >
NC_LVDS_IG_A_DATAP<0
@mlb_lib.MLB
NC_LVDS_IG_A_DATAP<0> - 19C6
>
NC_PEG_R2D_CN<13>
@mlb_lib.MLB
NC_PEG_R2D_CN<13> - @mlb_lib.MLB 10B5
A
MEM_B_DQ<26> MEM_B_DQ<26> - @mlb_lib.MLB 12C4 29C5 NC_DP_T29SRC_ML_CP<3 NC_DP_T29SRC_ML_CP<3..0> - 91A1 > @mlb_lib.MLB NC_PEG_R2D_CN<14> NC_PEG_R2D_CN<14> - @mlb_lib.MLB 10B5
MEM_B_DQ<27> MEM_B_DQ<27> - @mlb_lib.MLB 12C4 29C5 ..0> @mlb_lib.MLB NC_LVDS_IG_A_DATAP<3 NC_LVDS_IG_A_DATAP<3..0> - 91D2 NC_PEG_R2D_CN<15> NC_PEG_R2D_CN<15> - @mlb_lib.MLB 10B5
MEM_B_DQ<28> MEM_B_DQ<28> - @mlb_lib.MLB 12C4 29C5 NC_DP_T29SRC_ML_CP<1 NC_DP_T29SRC_ML_CP<1> - 74B3 ..0> @mlb_lib.MLB NC_PEG_R2D_CP<7..0> NC_PEG_R2D_CP<7..0> - @mlb_lib.MLB 8D5 91C2
MEM_B_DQ<29> MEM_B_DQ<29> - @mlb_lib.MLB 12C4 29C5 > @mlb_lib.MLB NC_LVDS_IG_A_DATAP<1 NC_LVDS_IG_A_DATAP<1> - 19C6 =PEG_R2D_C_P<7..0> - @mlb_lib.MLB 8D8
MEM_B_DQ<30> MEM_B_DQ<30> - @mlb_lib.MLB 12C4 29C5 NC_DP_T29SRC_ML_CP<2 NC_DP_T29SRC_ML_CP<2> - 74B3 > @mlb_lib.MLB NC_PEG_R2D_CP<12> NC_PEG_R2D_CP<12> - @mlb_lib.MLB 10B5
MEM_B_DQ<31> MEM_B_DQ<31> - @mlb_lib.MLB 12C4 29C5 > @mlb_lib.MLB NC_LVDS_IG_A_DATAP<2 NC_LVDS_IG_A_DATAP<2> - 19C6 NC_PEG_R2D_CP<15..12 NC_PEG_R2D_CP<15..12> - 91C1
MEM_B_DQ<32> MEM_B_DQ<32> - @mlb_lib.MLB 12C4 29B5 NC_DP_T29SRC_ML_CP<3 NC_DP_T29SRC_ML_CP<3> - 74B3 > @mlb_lib.MLB > @mlb_lib.MLB
MEM_B_DQ<39..32> MEM_B_DQ<39..32> - @mlb_lib.MLB 82B3 > @mlb_lib.MLB NC_LVDS_IG_A_DATAP<3 NC_LVDS_IG_A_DATAP<3> - 19C6 NC_PEG_R2D_CP<13> NC_PEG_R2D_CP<13> - @mlb_lib.MLB 10B5
MEM_B_DQ<33> MEM_B_DQ<33> - @mlb_lib.MLB 12C4 29B5 NC_EDP_AUXN NC_EDP_AUXN - @mlb_lib.MLB 10B7 91D2 > @mlb_lib.MLB NC_PEG_R2D_CP<14> NC_PEG_R2D_CP<14> - @mlb_lib.MLB 10B5
MEM_B_DQ<34> MEM_B_DQ<34> - @mlb_lib.MLB 12C4 29B5 NC_EDP_AUXP NC_EDP_AUXP - @mlb_lib.MLB 10B7 91D1 NC_LVDS_IG_BKL_ON NC_LVDS_IG_BKL_ON - @mlb_lib.MLB 19B6 91D3 NC_PEG_R2D_CP<15> NC_PEG_R2D_CP<15> - @mlb_lib.MLB 10B5
MEM_B_DQ<35> MEM_B_DQ<35> - @mlb_lib.MLB 12C4 29B5 NC_EDP_HPD NC_EDP_HPD - @mlb_lib.MLB 10B7 91A2 NC_LVDS_IG_BKL_PWM NC_LVDS_IG_BKL_PWM - @mlb_lib.MLB 19B6 91D2 NC_SATA_C_D2RN NC_SATA_C_D2RN - @mlb_lib.MLB 17C5 91C3
MEM_B_DQ<36> MEM_B_DQ<36> - @mlb_lib.MLB 12C4 29B5 NC_EDP_TXN<0> NC_EDP_TXN<0> - @mlb_lib.MLB 10B7 NC_LVDS_IG_B_CLKN NC_LVDS_IG_B_CLKN - @mlb_lib.MLB 19B6 91D1 NC_SATA_C_D2RP NC_SATA_C_D2RP - @mlb_lib.MLB 17C5 91C2

503

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
NC_SATA_C_R2D_CN NC_SATA_C_R2D_CN - @mlb_lib.MLB 17C5 91C1 PCH_CLK32K_RTCX1 PCH_CLK32K_RTCX1 - @mlb_lib.MLB 17D8 27C8 PCIE_T29_D2R_P<2> PCIE_T29_D2R_P<2> - @mlb_lib.MLB 74D1 PP1V2_ENET_PHY_GPHYP PP1V2_ENET_PHY_GPHYPLL - 37C3
NC_SATA_C_R2D_CP NC_SATA_C_R2D_CP - @mlb_lib.MLB 17C5 91C3 PCH_CLK32K_RTCX2 PCH_CLK32K_RTCX2 - @mlb_lib.MLB 17D8 27C8 =PCIE_T29_D2R_P<3..0> - 8C8 LL @mlb_lib.MLB
NC_SATA_D_D2RN NC_SATA_D_D2RN - @mlb_lib.MLB 17C5 91C2 PCH_CLK32K_RTCX2_R PCH_CLK32K_RTCX2_R - @mlb_lib.MLB 27C7 @mlb_lib.MLB PP1V2_ENET_PHY_PCIEP PP1V2_ENET_PHY_PCIEPLL - 37D3
NC_SATA_D_D2RP NC_SATA_D_D2RP - @mlb_lib.MLB 17C5 91C1 PCH_CLK33M_PCIIN PCH_CLK33M_PCIIN - @mlb_lib.MLB 17C1 27B1 84B3 PCIE_T29_D2R_P<3> PCIE_T29_D2R_P<3> - @mlb_lib.MLB 74D1 LL @mlb_lib.MLB
NC_SATA_D_R2D_CN NC_SATA_D_R2D_CN - @mlb_lib.MLB 17C5 91C3 PCH_CLK33M_PCIOUT PCH_CLK33M_PCIOUT - @mlb_lib.MLB 19C6 27B4 =PCIE_T29_D2R_P<3..0> - 8C8 PP1V05_S0_PCH PP1V05_S0_PCH - @mlb_lib.MLB 7D4 17C5 17C5 17D2 18D8
NC_SATA_D_R2D_CP NC_SATA_D_R2D_CP - @mlb_lib.MLB 17C5 91C2 PCH_CLK96M_DOT_N PCH_CLK96M_DOT_N - @mlb_lib.MLB 17A8 17C1 84B3 @mlb_lib.MLB 21B1 21B1 21B5 21B7 21B7
NC_SATA_E_D2RN NC_SATA_E_D2RN - @mlb_lib.MLB 17C5 91C1 PCH_CLK96M_DOT_P PCH_CLK96M_DOT_P - @mlb_lib.MLB 17A8 17C1 84B3 PCIE_T29_R2D_C_N<0> PCIE_T29_R2D_C_N<0> - @mlb_lib.MLB 74D7 21B7 21B7 21C1 21C4 21C4
NC_SATA_E_D2RP NC_SATA_E_D2RP - @mlb_lib.MLB 17C5 91C3 PCH_CLK100M_SATA_N PCH_CLK100M_SATA_N - @mlb_lib.MLB 17A8 17C1 84B3 =PCIE_T29_R2D_C_N<3..0> - 8B8 21C4 21C5 21C5 21C5 21C5
NC_SATA_E_R2D_CN NC_SATA_E_R2D_CN - @mlb_lib.MLB 17C5 91C2 PCH_CLK100M_SATA_P PCH_CLK100M_SATA_P - @mlb_lib.MLB 17A8 17C1 84B3 @mlb_lib.MLB 21C7 21C7 23B2 23B2 23B6
NC_SATA_E_R2D_CP NC_SATA_E_R2D_CP - @mlb_lib.MLB 17C5 91C1 PCH_CLKIN_GNDN1 PCH_CLKIN_GNDN1 - @mlb_lib.MLB 17B1 PCIE_T29_R2D_C_N<3.. PCIE_T29_R2D_C_N<3..0> - 8B5 84C1 23C1 23C2 23C2 23C5 23D1
NC_SATA_F_D2RN NC_SATA_F_D2RN - @mlb_lib.MLB 17C5 91C3 PCH_CLKIN_GNDP1 PCH_CLKIN_GNDP1 - @mlb_lib.MLB 17B1 0> @mlb_lib.MLB 23D2 23D2 23D5 23D8 50C8
NC_SATA_F_D2RP NC_SATA_F_D2RP - @mlb_lib.MLB 17C5 91C2 PCH_DAC_IREF PCH_DAC_IREF - @mlb_lib.MLB 18B4 =PCIE_T29_R2D_C_N<3..0> - 8B8 PP1V05_S0_PCH_VCCADP PP1V05_S0_PCH_VCCADPLLA_F - 21B8 23B3
NC_SATA_F_R2D_CN NC_SATA_F_R2D_CN - @mlb_lib.MLB 17C5 91C1 PCH_DF_TVS PCH_DF_TVS - @mlb_lib.MLB 18B6 @mlb_lib.MLB LLA_F @mlb_lib.MLB
NC_SATA_F_R2D_CP NC_SATA_F_R2D_CP - @mlb_lib.MLB 17C5 91C3 PCH_DMI2RBIAS PCH_DMI2RBIAS - @mlb_lib.MLB 18C8 PCIE_T29_R2D_C_N<1> PCIE_T29_R2D_C_N<1> - @mlb_lib.MLB 74D7 PP1V05_S0_PCH_VCCADP PP1V05_S0_PCH_VCCADPLLA_R - 23B5

D NC_SDVO_INTN
NC_SDVO_INTP
NC_SDVO_INTN - @mlb_lib.MLB
NC_SDVO_INTP - @mlb_lib.MLB
18D1
18D1
91C2
91C1
PCH_DMI_COMP
PCH_DSWVRMEN
PCH_DMI_COMP - @mlb_lib.MLB
PCH_DSWVRMEN - @mlb_lib.MLB
18C8
18B6
=PCIE_T29_R2D_C_N<3..0> -
@mlb_lib.MLB
8B8 LLA_R
PP1V05_S0_PCH_VCCADP
@mlb_lib.MLB
PP1V05_S0_PCH_VCCADPLLB_F - 21B8 23B3
D
NC_SDVO_STALLN NC_SDVO_STALLN - @mlb_lib.MLB 18D1 91C3 PCH_GPIO0 PCH_GPIO0 - @mlb_lib.MLB 20B6 20D6 PCIE_T29_R2D_C_N<2> PCIE_T29_R2D_C_N<2> - @mlb_lib.MLB 74D7 LLB_F @mlb_lib.MLB
NC_SDVO_STALLP NC_SDVO_STALLP - @mlb_lib.MLB 18D1 91C2 PCH_GPIO10_OC6_L PCH_GPIO10_OC6_L - @mlb_lib.MLB 19C1 24C4 =PCIE_T29_R2D_C_N<3..0> - 8B8 PP1V05_S0_PCH_VCCADP PP1V05_S0_PCH_VCCADPLLB_R - 23B5
NC_SDVO_TVCLKINN NC_SDVO_TVCLKINN - @mlb_lib.MLB 18D1 91C1 PCH_GPIO11 PCH_GPIO11 - @mlb_lib.MLB 17A3 17D1 @mlb_lib.MLB LLB_R @mlb_lib.MLB
NC_SDVO_TVCLKINP NC_SDVO_TVCLKINP - @mlb_lib.MLB 18D1 91B3 PCH_GPIO12 PCH_GPIO12 - @mlb_lib.MLB 20C7 20D6 PCIE_T29_R2D_C_N<3> PCIE_T29_R2D_C_N<3> - @mlb_lib.MLB 74D7 PP1V05_S0_PCH_VCCCLK PP1V05_S0_PCH_VCCCLKDMI_F - 21C1 23D6
NC_SMC_BMON_MUX_SEL NC_SMC_BMON_MUX_SEL - @mlb_lib.MLB 46C8 91B2 PCH_GPIO14_OC7_L PCH_GPIO14_OC7_L - @mlb_lib.MLB 19C1 24C4 =PCIE_T29_R2D_C_N<3..0> - 8B8 DMI_F @mlb_lib.MLB
NC_SMC_FAN_1_CTL NC_SMC_FAN_1_CTL - @mlb_lib.MLB 46A8 91B1 PCH_GPIO15 PCH_GPIO15 - @mlb_lib.MLB 20A6 20D6 24D4 @mlb_lib.MLB PP1V05_S0_PCH_VCCCLK PP1V05_S0_PCH_VCCCLKDMI_R - 23D7
NC_SMC_FAN_1_TACH NC_SMC_FAN_1_TACH - @mlb_lib.MLB 46A8 91B3 PCH_GPIO24 PCH_GPIO24 - @mlb_lib.MLB 20C6 20C7 PCIE_T29_R2D_C_P<0> PCIE_T29_R2D_C_P<0> - @mlb_lib.MLB 74D7 DMI_R @mlb_lib.MLB
NC_SMC_FAN_2_CTL NC_SMC_FAN_2_CTL - @mlb_lib.MLB 46A8 91B2 PCH_GPIO36_SATA2GP PCH_GPIO36_SATA2GP - @mlb_lib.MLB 20A1 20C6 =PCIE_T29_R2D_C_P<3..0> - 8B8 PP1V05_S0_VCCIO PP1V05_S0_VCCIO - @mlb_lib.MLB 7D4 10C8 10D4 11B7 11C7
NC_SMC_FAN_2_TACH NC_SMC_FAN_2_TACH - @mlb_lib.MLB 46A8 91B1 PCH_GPIO43_OC4_L PCH_GPIO43_OC4_L - @mlb_lib.MLB 19C1 24C4 @mlb_lib.MLB 13B5 13B5 13D6 15B8 67B6
NC_SMC_FAN_3_CTL NC_SMC_FAN_3_CTL - @mlb_lib.MLB 46A8 91B3 PCH_GPIO46 PCH_GPIO46 - @mlb_lib.MLB 20A6 20C6 PCIE_T29_R2D_C_P<3.. PCIE_T29_R2D_C_P<3..0> - 8B5 84C1 91B5
NC_SMC_FAN_3_TACH NC_SMC_FAN_3_TACH - @mlb_lib.MLB 46A8 91B2 PCH_GPIO52 PCH_GPIO52 - @mlb_lib.MLB 19D6 0> @mlb_lib.MLB PP1V05_S0 - @mlb_lib.MLB 7D4 24B3 24B4 24D1 24D6
NC_SMC_P10 NC_SMC_P10 - @mlb_lib.MLB 46D8 91B1 PCH_GPIO68_TACH4 PCH_GPIO68_TACH4 - @mlb_lib.MLB 20A6 20C6 =PCIE_T29_R2D_C_P<3..0> - 8B8 46A4 50C8 62A7 62B8 70C1
NC_SMC_P20 NC_SMC_P20 - @mlb_lib.MLB 46C8 91B3 PCH_GPIO69_TACH5 PCH_GPIO69_TACH5 - @mlb_lib.MLB 20A6 20C6 @mlb_lib.MLB 76A8
NC_SMC_P24 NC_SMC_P24 - @mlb_lib.MLB 46C8 91B2 PCH_GPIO70_TACH6 PCH_GPIO70_TACH6 - @mlb_lib.MLB 20A6 20C6 PCIE_T29_R2D_C_P<1> PCIE_T29_R2D_C_P<1> - @mlb_lib.MLB 74D7 PP1V05_S0_VCCQ PP1V05_S0_VCCQ - @mlb_lib.MLB 11D3 13B6 15A6
NC_SMC_P41 NC_SMC_P41 - @mlb_lib.MLB 46C8 91B1 PCH_GPIO71_TACH7 PCH_GPIO71_TACH7 - @mlb_lib.MLB 20A6 20C6 =PCIE_T29_R2D_C_P<3..0> - 8B8 PP1V05_S5_PCH PP1V05_S5_PCH - @mlb_lib.MLB 24B3
NC_SMC_P43 NC_SMC_P43 - @mlb_lib.MLB 46C8 91B3 PCH_INTRUDER_L PCH_INTRUDER_L - @mlb_lib.MLB 17A7 17D8 @mlb_lib.MLB PP1V05_T29 PP1V05_T29 - @mlb_lib.MLB 75D8 76A6 76C6
NC_SMC_PF5 NC_SMC_PF5 - @mlb_lib.MLB 46B5 91B2 PCH_INTVRMEN_L PCH_INTVRMEN_L - @mlb_lib.MLB 17A7 17D8 PCIE_T29_R2D_C_P<2> PCIE_T29_R2D_C_P<2> - @mlb_lib.MLB 74D7 PP1V05_T29_VDD_DP PP1V05_T29_VDD_DP - @mlb_lib.MLB 75C7
NC_SMC_RSTGATE_L NC_SMC_RSTGATE_L - @mlb_lib.MLB 46D8 91B1 PCH_PCI_GNT1_L PCH_PCI_GNT1_L - @mlb_lib.MLB 19B8 19D6 =PCIE_T29_R2D_C_P<3..0> - 8B8 PP1V05_T29_VDD_DPPLL PP1V05_T29_VDD_DPPLL - @mlb_lib.MLB 75C7
NC_SMC_SYS_KBDLED NC_SMC_SYS_KBDLED - @mlb_lib.MLB 46C8 91B3 PCH_PCI_GNT2_L PCH_PCI_GNT2_L - @mlb_lib.MLB 19B8 19D6 @mlb_lib.MLB PP1V5_FW_VDDA PP1V5_FW_VDDA - @mlb_lib.MLB 39D2
NC_SPI_DESCRIPTOR_OV NC_SPI_DESCRIPTOR_OVERRIDE_L - 46B8 91B2 PCH_PCI_GNT3_L PCH_PCI_GNT3_L - @mlb_lib.MLB 19B8 19D6 PCIE_T29_R2D_C_P<3> PCIE_T29_R2D_C_P<3> - @mlb_lib.MLB 74D7 PP1V5_S0 PP1V5_S0 - @mlb_lib.MLB 7C7 17B4 21B5 23D4 39D1
ERRIDE_L @mlb_lib.MLB PCH_PECI PCH_PECI - @mlb_lib.MLB 20D4 =PCIE_T29_R2D_C_P<3..0> - 8B8 53D7 71B5 72B3 91B5
NC_T29_D2RN0 NC_T29_D2RN0 - @mlb_lib.MLB 74A5 91A1 PCH_PROCPWRGD PCH_PROCPWRGD - @mlb_lib.MLB 20D4 @mlb_lib.MLB PP1V5_S3 PP1V5_S3 - @mlb_lib.MLB 6B3 28B5 30C5 30C7 30D4
NC_T29_D2RN1 NC_T29_D2RN1 - @mlb_lib.MLB 74A5 91A1 PCH_RCIN_L PCH_RCIN_L - @mlb_lib.MLB 20D4 PCIE_T29_R2D_N<0> PCIE_T29_R2D_N<0> - @mlb_lib.MLB 74D5 31C5 31C7 31D4 32B6 61B7
NC_T29_D2RP0 NC_T29_D2RP0 - @mlb_lib.MLB 74A5 91A1 PCH_RI_L PCH_RI_L - @mlb_lib.MLB 18C8 PCIE_T29_R2D_N<3..0> PCIE_T29_R2D_N<3..0> - @mlb_lib.MLB
84C1 66C1 66C6 72B3 91C5
NC_T29_D2RP1 NC_T29_D2RP1 - @mlb_lib.MLB 74A5 91A1 PCH_SATA3COMP PCH_SATA3COMP - @mlb_lib.MLB 17B6 83C3 PCIE_T29_R2D_N<1> PCIE_T29_R2D_N<1> - @mlb_lib.MLB 74D5 PP1V5_S3_CPU_VCCDQ PP1V5_S3_CPU_VCCDQ - @mlb_lib.MLB 13C1 16A6
NC_T29_PCIE_RESET0_L NC_T29_PCIE_RESET0_L - @mlb_lib.MLB 74C3 91B1 PCH_SATA3RBIAS PCH_SATA3RBIAS - @mlb_lib.MLB 17B6 PCIE_T29_R2D_N<2> PCIE_T29_R2D_N<2> - @mlb_lib.MLB 74D5 PP1V5_S3_REG PP1V5_S3_REG - @mlb_lib.MLB 66C3
NC_T29_PCIE_RESET1_L NC_T29_PCIE_RESET1_L - @mlb_lib.MLB 74C3 91B1 PCH_SATAICOMP PCH_SATAICOMP - @mlb_lib.MLB 17C6 83C3 PCIE_T29_R2D_N<3> PCIE_T29_R2D_N<3> - @mlb_lib.MLB 74D5 PP1V5_VDDQ_CPU PP1V5_VDDQ_CPU - @mlb_lib.MLB 7A4 11C7 13B2 13D2 16B8
NC_T29_PCIE_RESET2_L NC_T29_PCIE_RESET2_L - @mlb_lib.MLB 74C3 91B1 PCH_SATALED_L PCH_SATALED_L - @mlb_lib.MLB 17B5 17C5 PCIE_T29_R2D_P<0> PCIE_T29_R2D_P<0> - @mlb_lib.MLB 74D5 28D4 31A5 32B6 50D8 62A8
NC_T29_PCIE_RESET3_L NC_T29_PCIE_RESET3_L - @mlb_lib.MLB 74C3 91B1 PCH_SPKR PCH_SPKR - @mlb_lib.MLB 17B5 17D8 PCIE_T29_R2D_P<3..0> PCIE_T29_R2D_P<3..0> - @mlb_lib.MLB
84C1 62C8
NC_T29_PWR_EN NC_T29_PWR_EN - @mlb_lib.MLB 91B1 PCH_SRTCRST_L PCH_SRTCRST_L - @mlb_lib.MLB 17A7 17D8 PCIE_T29_R2D_P<1> PCIE_T29_R2D_P<1> - @mlb_lib.MLB 74D5 PP1V5_VDDQ_CPU_R PP1V5_VDDQ_CPU_R - @mlb_lib.MLB 7B4 50D8 61B5

C NC_T29_R2D_CN0
NC_T29_R2D_CN1
NC_T29_R2D_CN0 - @mlb_lib.MLB
NC_T29_R2D_CN1 - @mlb_lib.MLB
74A5
74A5
91B1
91B1
PCH_SUSACK_L
PCH_THRMD_N
PCH_SUSACK_L - @mlb_lib.MLB
PCH_THRMD_N - @mlb_lib.MLB
18B5
52B3
18B5
52C8
PCIE_T29_R2D_P<2>
PCIE_T29_R2D_P<3>
PCIE_T29_R2D_P<2> - @mlb_lib.MLB
PCIE_T29_R2D_P<3> - @mlb_lib.MLB
74D5
74D5
PP1V8_S0 PP1V8_S0 - @mlb_lib.MLB 7D4 15B3 18C5 21B1 21B7
21C1 21C1 21C5 23D3 26D7
C
NC_T29_R2D_CP0 NC_T29_R2D_CP0 - @mlb_lib.MLB 74A5 91B1 PCH_THRMD_P PCH_THRMD_P - @mlb_lib.MLB 52C3 52C8 PCIE_WAKE_L PCIE_WAKE_L - @mlb_lib.MLB 18A6 18C5 35D8 38C3 77A8 71B7 71D4
NC_T29_R2D_CP1 NC_T29_R2D_CP1 - @mlb_lib.MLB 74A5 91B1 PCH_USB_RBIAS PCH_USB_RBIAS - @mlb_lib.MLB 19C4 83C3 91D7 PP1V8_S0_CPU_VCCPLL_ PP1V8_S0_CPU_VCCPLL_R - 7C4 13B4 15B1
NC_USB_1N NC_USB_1N - @mlb_lib.MLB 19D4 91B3 PCH_XCLK_RCOMP PCH_XCLK_RCOMP - @mlb_lib.MLB 17B2 PCI_INTA_L PCI_INTA_L - @mlb_lib.MLB 19D6 R @mlb_lib.MLB
NC_USB_1P NC_USB_1P - @mlb_lib.MLB 19D4 91B2 PCIECLKRQ5_L_GPIO44 PCIECLKRQ5_L_GPIO44 - @mlb_lib.MLB 17A5 17B4 PCI_INTB_L PCI_INTB_L - @mlb_lib.MLB 19D6 PP1V96_FW_PLLVDD PP1V96_FW_PLLVDD - @mlb_lib.MLB 39D2
NC_USB_2N NC_USB_2N - @mlb_lib.MLB 19D4 91B1 PCIE_AP_D2R_N PCIE_AP_D2R_N - @mlb_lib.MLB 17D4 35D4 84D1 91D7 PCI_INTC_L PCI_INTC_L - @mlb_lib.MLB 19D6 PP1V96_FW_XTAL PP1V96_FW_XTAL - @mlb_lib.MLB 39C1
NC_USB_2P NC_USB_2P - @mlb_lib.MLB 19D4 91B3 PCIE_AP_D2R_P PCIE_AP_D2R_P - @mlb_lib.MLB 17D4 35D4 84D1 91D7 PCI_INTD_L PCI_INTD_L - @mlb_lib.MLB 19D6 PP1V96_S0_FW PP1V96_S0_FW - @mlb_lib.MLB 39D1 40D5
NC_USB_3N NC_USB_3N - @mlb_lib.MLB 19D4 91B2 PCIE_AP_R2D_C_N PCIE_AP_R2D_C_N - @mlb_lib.MLB 17D4 35C4 84D1 PCI_INTE_L PCI_INTE_L - @mlb_lib.MLB 19D6 PP2V2_FW_ESD PP2V2_FW_ESD - @mlb_lib.MLB 41A6 41B2 41C4 41C4

www.teknisi-indonesia.com
NC_USB_3P NC_USB_3P - @mlb_lib.MLB 19D4 91B1 PCIE_AP_R2D_C_P PCIE_AP_R2D_C_P - @mlb_lib.MLB 17D4 35C4 84D1 PCI_REQ3_L PCI_REQ3_L - @mlb_lib.MLB 19D6 PP3V3R1V8_ENET_LR_OU PP3V3R1V8_ENET_LR_OUT - 37C1 37D5
NC_USB_4N NC_USB_4N - @mlb_lib.MLB 19D4 91B3 PCIE_AP_R2D_N PCIE_AP_R2D_N - @mlb_lib.MLB 35C6 84D1 91D7 PDCINVSENS_EN_L_DIV PDCINVSENS_EN_L_DIV - @mlb_lib.MLB 51C3 T @mlb_lib.MLB
NC_USB_4P NC_USB_4P - @mlb_lib.MLB 19D4 91B2 PCIE_AP_R2D_P PCIE_AP_R2D_P - @mlb_lib.MLB 35C6 84D1 91D7 PD_DP_T29SNK1_HPD PD_DP_T29SNK1_HPD - @mlb_lib.MLB 74A5 PP3V3R2V8_DPAPWR_D PP3V3R2V8_DPAPWR_D - @mlb_lib.MLB 78D7
NC_USB_5N NC_USB_5N - @mlb_lib.MLB 19D4 91B1 PCIE_CLK100M_AP_CONN PCIE_CLK100M_AP_CONN_N - 35C6 84C1 91D7 PD_DP_T29SRC_HPD PD_DP_T29SRC_HPD - @mlb_lib.MLB 74B3 PP3V3R12V_SW_DPAPWR PP3V3R12V_SW_DPAPWR - @mlb_lib.MLB 78C6 78D1 78D4
NC_USB_5P NC_USB_5P - @mlb_lib.MLB 19D4 91B3 _N @mlb_lib.MLB PD_HDMI_LS_RSV0 PD_HDMI_LS_RSV0 - @mlb_lib.MLB 79C5 PP3V3R12V_SW_DPAPWR_ PP3V3R12V_SW_DPAPWR_F - 78C4 91B5
NC_USB_6N NC_USB_6N - @mlb_lib.MLB 19D4 91B2 PCIE_CLK100M_AP_CONN PCIE_CLK100M_AP_CONN_P - 35C6 84C1 91D7 PD_PCH_INIT3V3_L PD_PCH_INIT3V3_L - @mlb_lib.MLB 20A4 F @mlb_lib.MLB
NC_USB_6P NC_USB_6P - @mlb_lib.MLB 19D4 91B1 _P @mlb_lib.MLB PD_SMC_SPARE_SENSE PD_SMC_SPARE_SENSE - @mlb_lib.MLB 46C5 47B2 PP3V3_ENET PP3V3_ENET - @mlb_lib.MLB 6D3 26D7 26D7 37A8 37D8
NC_USB_7N NC_USB_7N - @mlb_lib.MLB 19D4 91B3 PCIE_CLK100M_AP_N PCIE_CLK100M_AP_N - @mlb_lib.MLB 17C4 35D4 84C1 PEG_B_CLKRQ_L_GPIO56 PEG_B_CLKRQ_L_GPIO56 - @mlb_lib.MLB 17B4 17B5 38C2 38D7 62B1 91C5
NC_USB_7P NC_USB_7P - @mlb_lib.MLB 19D4 91B2 PCIE_CLK100M_AP_P PCIE_CLK100M_AP_P - @mlb_lib.MLB 17C4 35D4 84C1 PEG_CLKREQ_L PEG_CLKREQ_L - @mlb_lib.MLB 17B4 17B5 PP3V3_ENET_PHY_AVDDH PP3V3_ENET_PHY_AVDDH - @mlb_lib.MLB 37C6
NC_USB_9N NC_USB_9N - @mlb_lib.MLB 19C4 91B1 PCIE_CLK100M_ENET_N PCIE_CLK100M_ENET_N - @mlb_lib.MLB 17C4 37B6 84C1 PEG_D2R_C_N<7..0> PEG_D2R_C_N<7..0> - @mlb_lib.MLB 81A3 PP3V3_ENET_PHY_BIASV PP3V3_ENET_PHY_BIASVDDH - 37D6
NC_USB_9P NC_USB_9P - @mlb_lib.MLB 19C4 91B3 PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_P - @mlb_lib.MLB 17C4 37B6 84C1 PEG_D2R_C_P<7..0> PEG_D2R_C_P<7..0> - @mlb_lib.MLB 81A3 DDH @mlb_lib.MLB
NC_USB_10N NC_USB_10N - @mlb_lib.MLB 19C4 91B2 PCIE_CLK100M_FW_N PCIE_CLK100M_FW_N - @mlb_lib.MLB 17C4 39C6 84C1 PEG_D2R_N<7..0> PEG_D2R_N<7..0> - @mlb_lib.MLB 81A3 PP3V3_ENET_PHY_XTALV PP3V3_ENET_PHY_XTALVDDH - 37D6
NC_USB_10P NC_USB_10P - @mlb_lib.MLB 19C4 91B1 PCIE_CLK100M_FW_P PCIE_CLK100M_FW_P - @mlb_lib.MLB 17C4 39C6 84C1 PEG_D2R_P<7..0> PEG_D2R_P<7..0> - @mlb_lib.MLB 81A3 DDH @mlb_lib.MLB
NC_USB_11N NC_USB_11N - @mlb_lib.MLB 19C4 91B3 PCIE_CLK100M_PCH_N PCIE_CLK100M_PCH_N - @mlb_lib.MLB 17A8 17C1 84C1 PEG_R2D_C_N<7..0> PEG_R2D_C_N<7..0> - @mlb_lib.MLB 81A3 PP3V3_FW_AVDD PP3V3_FW_AVDD - @mlb_lib.MLB 39D7
NC_USB_11P NC_USB_11P - @mlb_lib.MLB 19C4 91B2 PCIE_CLK100M_PCH_P PCIE_CLK100M_PCH_P - @mlb_lib.MLB 17A8 17C1 84C1 PEG_R2D_C_P<7..0> PEG_R2D_C_P<7..0> - @mlb_lib.MLB 81A3 PP3V3_FW_PLLVDD PP3V3_FW_PLLVDD - @mlb_lib.MLB 39D7
NC_USB_12N NC_USB_12N - @mlb_lib.MLB 19C4 91B1 PCIE_CLK100M_T29_N PCIE_CLK100M_T29_N - @mlb_lib.MLB 17B4 74C2 84C1 PEG_R2D_N<7..0> PEG_R2D_N<7..0> - @mlb_lib.MLB 81A3 PP3V3_FW_VDDA PP3V3_FW_VDDA - @mlb_lib.MLB 39D7
NC_USB_12P NC_USB_12P - @mlb_lib.MLB 19C4 91B3 PCIE_CLK100M_T29_P PCIE_CLK100M_T29_P - @mlb_lib.MLB 17B4 74C2 84C1 PEG_R2D_P<7..0> PEG_R2D_P<7..0> - @mlb_lib.MLB 81A3 PP3V3_G3H PP3V3_G3H - @mlb_lib.MLB 6B7 6D2 6D3 27D7 43D5
NC_USB_13N NC_USB_13N - @mlb_lib.MLB 19C4 91B2 PCIE_ENET_D2R_C_N PCIE_ENET_D2R_C_N - @mlb_lib.MLB 37C6 84D1 PERIPHDET_FILT PERIPHDET_FILT - @mlb_lib.MLB 58B3 45B2 46D4 47C1 47D8 48D5
NC_USB_13P NC_USB_13P - @mlb_lib.MLB 19C4 91B1 PCIE_ENET_D2R_C_P PCIE_ENET_D2R_C_P - @mlb_lib.MLB 37C6 84D1 PLT_RESET2_L PLT_RESET2_L - @mlb_lib.MLB 27D3 28B5 61C4 61D4 61D8 65C3 65D7
ODD_PWR_EN_L ODD_PWR_EN_L - @mlb_lib.MLB 20D6 20D8 PCIE_ENET_D2R_N PCIE_ENET_D2R_N - @mlb_lib.MLB 17D4 37C8 84D1 PLT_RESET_L PLT_RESET_L - @mlb_lib.MLB 19D6 27D4 91A5 91C5
P1V05_DIV_VMON P1V05_DIV_VMON - @mlb_lib.MLB 62A7 PCIE_ENET_D2R_P PCIE_ENET_D2R_P - @mlb_lib.MLB 17D4 37C8 84D1 PLT_RESET_LS1V1_L PLT_RESET_LS1V1_L - @mlb_lib.MLB 11B6 PP3V3_G3_RTC PP3V3_G3_RTC - @mlb_lib.MLB 6D7 17B8 18B5 21B8 27D6
P1V5CPU_EN P1V5CPU_EN - @mlb_lib.MLB 28C5 61B8 PCIE_ENET_R2D_C_N PCIE_ENET_R2D_C_N - @mlb_lib.MLB 17D4 37B8 84D1 PM_BATLOW_L PM_BATLOW_L - @mlb_lib.MLB 18C8 46B8 91C5
P1V5CPU_EN_L P1V5CPU_EN_L - @mlb_lib.MLB 28C6 PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_P - @mlb_lib.MLB 17D4 37C8 84D1 PM_CLK32K_SUSCLK_R PM_CLK32K_SUSCLK_R - @mlb_lib.MLB 18C5 47C6 PP3V3_S0 PP3V3_S0 - @mlb_lib.MLB 6C2 7C7 13B6 17A6 17B7

B P1V5S0FET_GATE
P1V5S0FET_GATE_R
P1V5S0FET_GATE - @mlb_lib.MLB
P1V5S0FET_GATE_R - @mlb_lib.MLB
61B7
61B6
PCIE_ENET_R2D_N
PCIE_ENET_R2D_P
PCIE_ENET_R2D_N - @mlb_lib.MLB
PCIE_ENET_R2D_P - @mlb_lib.MLB
37C6
37C6
84D1
84D1
PM_CLKRUN_L
PM_DPRSLPVR
PM_CLKRUN_L - @mlb_lib.MLB
PM_DPRSLPVR - @mlb_lib.MLB
18A4 18C5 46C5 48C5
81B3
17C5 17D5 18B5 19D8 20A5
20A8 20B8 20D2 20D7 21B4 B
P1V5S0_EN P1V5S0_EN - @mlb_lib.MLB 62C1 71A7 PCIE_FW_D2R_C_N PCIE_FW_D2R_C_N - @mlb_lib.MLB 39C6 84C1 PM_ENET_EN_L PM_ENET_EN_L - @mlb_lib.MLB 62B3 21C1 21C5 21C5 23A6 23A6
P1V5S3_CS_N P1V5S3_CS_N - @mlb_lib.MLB 50C8 66C1 PCIE_FW_D2R_C_P PCIE_FW_D2R_C_P - @mlb_lib.MLB 39C6 84C1 PM_EN_PVCORE_CPU PM_EN_PVCORE_CPU - @mlb_lib.MLB 62C4 67B3 23A8 23A8 23C6 23C8 23C8
P1V5S3_CS_P P1V5S3_CS_P - @mlb_lib.MLB 50B8 66C1 PCIE_FW_D2R_N PCIE_FW_D2R_N - @mlb_lib.MLB 17D4 39C8 84D1 PM_MEM_PWRGD PM_MEM_PWRGD - @mlb_lib.MLB 11C7 18C8 28D1 81C3 24D7 27A4 27A7 27C4 27C4
P1V5S3_IOUT P1V5S3_IOUT - @mlb_lib.MLB 50C7 PCIE_FW_D2R_P PCIE_FW_D2R_P - @mlb_lib.MLB 17D4 39C8 84D1 PM_MEM_PWRGD_L PM_MEM_PWRGD_L - @mlb_lib.MLB 28C3 30A7 30B3 31A7 31B3 34D4
P1V5VDDQCPU_RAMP_DON P1V5VDDQCPU_RAMP_DONE - 28C5 61B6 PCIE_FW_R2D_C_N PCIE_FW_R2D_C_N - @mlb_lib.MLB 17D4 39C8 84D1 PM_MEM_PWRGD_R PM_MEM_PWRGD_R - @mlb_lib.MLB 11C6 37C7 38A5 39B8 39C1 39D8
E @mlb_lib.MLB PCIE_FW_R2D_C_P PCIE_FW_R2D_C_P - @mlb_lib.MLB 17D4 39C8 84D1 PM_P3V3_G3H_PG PM_P3V3_G3H_PG - @mlb_lib.MLB 65C8 40B7 40D7 41B4 47D3 49A8
P1V5_DIV_VMON P1V5_DIV_VMON - @mlb_lib.MLB 62A7 PCIE_FW_R2D_N PCIE_FW_R2D_N - @mlb_lib.MLB 39C6 84D1 PM_P5V_S4_PG PM_P5V_S4_PG - @mlb_lib.MLB 62A6 65A8 78C8 49B3 49B5 49B8 49D5 49D8
P1V5_S0_DIV P1V5_S0_DIV - @mlb_lib.MLB 28C4 PCIE_FW_R2D_P PCIE_FW_R2D_P - @mlb_lib.MLB 39C6 84D1 PM_PCH_PWROK PM_PCH_PWROK - @mlb_lib.MLB 18C8 18C8 20B3 20B3 20C3 50B7 50B7 50D3 50D7 50D8
P1V8S0_EN P1V8S0_EN - @mlb_lib.MLB 62C1 71C8 PCIE_T29_D2R_C_N<0> PCIE_T29_D2R_C_N<0> - @mlb_lib.MLB 74D3 27A5 51C7 51D7 52B6 52D7 53A8
P1V8S0_PGOOD P1V8S0_PGOOD - @mlb_lib.MLB 62A6 71C8 PCIE_T29_D2R_C_N<3.. PCIE_T29_D2R_C_N<3..0> - 84C1 PM_PCH_SYS_PWROK PM_PCH_SYS_PWROK - @mlb_lib.MLB 18C8 24C8 27A5 53D1 57B8 58A4 58D4 60C7
P1V95_FW_NR P1V95_FW_NR - @mlb_lib.MLB 40D6 0> @mlb_lib.MLB PM_PECI_PWRGD PM_PECI_PWRGD - @mlb_lib.MLB 46A4 62C4 60C7 61C1 62A7 62B6 62C8
P3V3ENET_SS P3V3ENET_SS - @mlb_lib.MLB 62B2 PCIE_T29_D2R_C_N<1> PCIE_T29_D2R_C_N<1> - @mlb_lib.MLB 74D3 PM_PECI_PWRGD_R PM_PECI_PWRGD_R - @mlb_lib.MLB 46A5 67D2 67D5 71D8 72C7 73C5
P3V3S0_EN P3V3S0_EN - @mlb_lib.MLB 61C4 62C1 PCIE_T29_D2R_C_N<2> PCIE_T29_D2R_C_N<2> - @mlb_lib.MLB 74D3 PM_PGOOD_P3V3_2V8_A PM_PGOOD_P3V3_2V8_A - @mlb_lib.MLB 78C7 74A7 76B8 76C8 77B5 77C4
PM_SLP_S3_R_L - @mlb_lib.MLB 62C2 PCIE_T29_D2R_C_N<3> PCIE_T29_D2R_C_N<3> - @mlb_lib.MLB 74D3 PM_PGOOD_PVAXG PM_PGOOD_PVAXG - @mlb_lib.MLB 67B3 77C8 77D6 79A7 79C2 79C7
P5VS0_EN - @mlb_lib.MLB 61A4 62C1 PCIE_T29_D2R_C_P<0> PCIE_T29_D2R_C_P<0> - @mlb_lib.MLB 74D3 PM_PGOOD_PVCORE_CPU PM_PGOOD_PVCORE_CPU - @mlb_lib.MLB 27A8 62B6 67C6 79D1 89C1 91C5
PM_SLP_S3_R_L - @mlb_lib.MLB 62C2 PCIE_T29_D2R_C_P<3.. PCIE_T29_D2R_C_P<3..0> - 84C1 PM_PWRBTN_L PM_PWRBTN_L - @mlb_lib.MLB 18A6 18C8 24C8 46C8 PP3V3_S0_AUDIO_F PP3V3_S0_AUDIO_F - @mlb_lib.MLB 58A3 58A7 58B4 58B8 58C8
P5VS0_EN - @mlb_lib.MLB 61A4 62C1 0> @mlb_lib.MLB PM_RSMRST_L PM_RSMRST_L - @mlb_lib.MLB 18C8 46D8 PP3V3_S0_HS_RX PP3V3_S0_HS_RX - @mlb_lib.MLB 58D3
P3V3S0_EN_L P3V3S0_EN_L - @mlb_lib.MLB 61C3 PCIE_T29_D2R_C_P<1> PCIE_T29_D2R_C_P<1> - @mlb_lib.MLB 74D3 PM_S0_PGOOD PM_S0_PGOOD - @mlb_lib.MLB 27A7 PP3V3_S0_PCH_VCC3_3_ PP3V3_S0_PCH_VCC3_3_CLK_F - 21D8 23C3
P3V3S0_SS P3V3S0_SS - @mlb_lib.MLB 61C2 PCIE_T29_D2R_C_P<2> PCIE_T29_D2R_C_P<2> - @mlb_lib.MLB 74D3 PM_SLP_S3_L PM_SLP_S3_L - @mlb_lib.MLB 18A5 18C5 28C5 46C5 51C4 CLK_F @mlb_lib.MLB
P3V3S3_EN_RC P3V3S3_EN_RC - @mlb_lib.MLB 25B2 PCIE_T29_D2R_C_P<3> PCIE_T29_D2R_C_P<3> - @mlb_lib.MLB 74D3 62A4 62C4 91B5 PP3V3_S0_PCH_VCC3_3_ PP3V3_S0_PCH_VCC3_3_CLK_R - 23C5
P3V3S4_EN P3V3S4_EN - @mlb_lib.MLB 61D4 62D1 PCIE_T29_D2R_N<0> PCIE_T29_D2R_N<0> - @mlb_lib.MLB 74D1 PM_SLP_S4_L PM_SLP_S4_L - @mlb_lib.MLB 18A5 18C5 28D6 46C5 62D6 CLK_R @mlb_lib.MLB
P3V3S4_EN_L P3V3S4_EN_L - @mlb_lib.MLB 61D3 =PCIE_T29_D2R_N<3..0> - 8C8 91B5 PP3V3_S0_PCH_VCCA_DA PP3V3_S0_PCH_VCCA_DAC_F - 21B1 23C6
P3V3S4_GATE P3V3S4_GATE - @mlb_lib.MLB 61D3 @mlb_lib.MLB DDRREG_EN - @mlb_lib.MLB 62D4 66C8 C_F @mlb_lib.MLB
P3V3S5_EN P3V3S5_EN - @mlb_lib.MLB 61D8 62D6 PCIE_T29_D2R_N<3..0> PCIE_T29_D2R_N<3..0> - @mlb_lib.MLB 8C5 84C1 PM_SLP_S5_L PM_SLP_S5_L - @mlb_lib.MLB 18A5 18C5 46C5 62D3 91B5 PP3V3_S4 PP3V3_S4 - @mlb_lib.MLB 6B3 6D2 19C2 20B3 20C3
P3V3S5_EN_L P3V3S5_EN_L - @mlb_lib.MLB 61D7 =PCIE_T29_D2R_N<3..0> - 8C8 P5VS4_EN - @mlb_lib.MLB 62D1 65B8 20C3 25A3 25B3 25C3 25C3
P3V3S5_SS P3V3S5_SS - @mlb_lib.MLB 61D6 @mlb_lib.MLB PM_SYNC PM_SYNC - @mlb_lib.MLB 11C6 18C5 81C3 25C3 25C8 25D8 28B8 28C7
P3V3WLAN_SS P3V3WLAN_SS - @mlb_lib.MLB 35C2 PCIE_T29_D2R_N<1> PCIE_T29_D2R_N<1> - @mlb_lib.MLB 74D1 PM_SYSRST_L PM_SYSRST_L - @mlb_lib.MLB 18C8 27A3 46B8 28C7 33D8 34B6 34C5 35B3
P3V3WLAN_VMON P3V3WLAN_VMON - @mlb_lib.MLB 35B4 =PCIE_T29_D2R_N<3..0> - 8C8 PM_THRMTRIP_L PM_THRMTRIP_L - @mlb_lib.MLB 11C6 20C2 81B3 35C1 35C4 38B4 47B4 47B4
P5V0S0_EN_L P5V0S0_EN_L - @mlb_lib.MLB 61B3 @mlb_lib.MLB PM_THRMTRIP_L_R PM_THRMTRIP_L_R - @mlb_lib.MLB 20D4 47C4 49C3 49C5 50C7 50D8 61D1
P5V0S0_SS P5V0S0_SS - @mlb_lib.MLB 61B3 PCIE_T29_D2R_N<2> PCIE_T29_D2R_N<2> - @mlb_lib.MLB 74D1 PM_WLAN_EN_L PM_WLAN_EN_L - @mlb_lib.MLB 35C1 62A2 77B6 77C2 78C6 91C5
A P5VS5_EN_L
P5VS5_SS
P5VS5_EN_L - @mlb_lib.MLB
P5VS5_SS - @mlb_lib.MLB
61B3
61B2
=PCIE_T29_D2R_N<3..0> -
@mlb_lib.MLB
8C8 POWER_BTN_N
POWER_BTN_P
POWER_BTN_N - @mlb_lib.MLB
POWER_BTN_P - @mlb_lib.MLB
45A3 91B7
45B3 91B7
PP3V3_S4_BT_F PP3V3_S4_BT_F - @mlb_lib.MLB
PP3V3_S4_VREFMRGN_CT PP3V3_S4_VREFMRGN_CTRL -
35C6 91D7
33C7
A
P5V_DIV_VMON P5V_DIV_VMON - @mlb_lib.MLB 62A8 PCIE_T29_D2R_N<3> PCIE_T29_D2R_N<3> - @mlb_lib.MLB 74D1 PP0V75_S0_DDRVTT PP0V75_S0_DDRVTT - @mlb_lib.MLB 7C4 28B3 30A5 30A7 30C2 RL @mlb_lib.MLB
P12V_S5_FW_CL P12V_S5_FW_CL - @mlb_lib.MLB 41D5 =PCIE_T29_D2R_N<3..0> - 8C8 31A5 31A7 31C2 66C5 91B5 PP3V3_S4_VREFMRGN_DA PP3V3_S4_VREFMRGN_DAC - 33D7
P12V_S5_FW_R P12V_S5_FW_R - @mlb_lib.MLB 41D7 @mlb_lib.MLB PP0V75_S3_MEM_VREFCA PP0V75_S3_MEM_VREFCA_A - 30B5 30C2 33C1 C @mlb_lib.MLB
P12V_T29 P12V_T29 - @mlb_lib.MLB 78D2 PCIE_T29_D2R_P<0> PCIE_T29_D2R_P<0> - @mlb_lib.MLB 74D1 _A @mlb_lib.MLB PP3V3_S5 PP3V3_S5 - @mlb_lib.MLB 6A7 17A3 17A6 17B7 18A8
P33V_S5_FW_D P33V_S5_FW_D - @mlb_lib.MLB 41D4 =PCIE_T29_D2R_P<3..0> - 8C8 PP0V75_S3_MEM_VREFCA PP0V75_S3_MEM_VREFCA_B - 31B5 31C2 33C1 18A8 18D8 19C2 20A7 20B7
PCA9557D_RESET_L PCA9557D_RESET_L - @mlb_lib.MLB 27C1 33B7 @mlb_lib.MLB _B @mlb_lib.MLB 20C8 21B5 21B5 21C1 21D5
PCH1V05_IOUT PCH1V05_IOUT - @mlb_lib.MLB 50C6 PCIE_T29_D2R_P<3..0> PCIE_T29_D2R_P<3..0> - @mlb_lib.MLB 8C5 84C1 PP0V75_S3_MEM_VREFDQ PP0V75_S3_MEM_VREFDQ_A - 10B3 30D2 30D7 33D1 21D8 23B8 23C4 23D1 23D4
PCH_A20GATE PCH_A20GATE - @mlb_lib.MLB 20D4 =PCIE_T29_D2R_P<3..0> - 8C8 _A @mlb_lib.MLB 23D5 24B3 24B8 24C2 25C3
PCH_CLK14P3M_REFCLK PCH_CLK14P3M_REFCLK - @mlb_lib.MLB 17A8 17C1 84B3 @mlb_lib.MLB PP0V75_S3_MEM_VREFDQ PP0V75_S3_MEM_VREFDQ_B - 10B3 31D2 31D7 33D1 27A6 27A7 28D4 59C6 61D5
PCH_CLK25M_X1 PCH_CLK25M_X1 - @mlb_lib.MLB 17B1 26D1 PCIE_T29_D2R_P<1> PCIE_T29_D2R_P<1> - @mlb_lib.MLB 74D1 _B @mlb_lib.MLB 62B3 62C7 62D8 78C7 89C1
PCH_CLK25M_X2 PCH_CLK25M_X2 - @mlb_lib.MLB 17B1 26D1 =PCIE_T29_D2R_P<3..0> - 8C8 PP1V2_ENET PP1V2_ENET - @mlb_lib.MLB 6D3 37D2 38C5 91C5 91C5
TP_PCH_CLK25M_X2 - @mlb_lib.MLB 26D3 @mlb_lib.MLB PP1V2_ENET_PHY_AVDDL PP1V2_ENET_PHY_AVDDL - @mlb_lib.MLB 37D3 PP3V3_S5_AVREF_SMC PP3V3_S5_AVREF_SMC - @mlb_lib.MLB 46D4 47D6 91B5

504

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
PP3V3_S5_SMC_AVCC PP3V3_S5_SMC_AVCC - @mlb_lib.MLB 46D3 SDCONNF_CLK_FF SDCONNF_CLK_FF - @mlb_lib.MLB 34C6 85C3 SMC_RX_L SMC_RX_L - @mlb_lib.MLB 43D5 46B8 46C5 47B2 48C3 T29_D2R_N<1> T29_D2R_N<1> - @mlb_lib.MLB 74A3 77D5
PP3V3_SW_SD_PWR PP3V3_SW_SD_PWR - @mlb_lib.MLB 34D2 91C7 SDCONN_CLK SDCONN_CLK - @mlb_lib.MLB 34C7 37B1 85C3 91C7 SMC_S4_WAKESRC_EN SMC_S4_WAKESRC_EN - @mlb_lib.MLB 46B8 47B2 T29_D2R_P<0> T29_D2R_P<0> - @mlb_lib.MLB 74A3 77D5
PP3V3_T29 PP3V3_T29 - @mlb_lib.MLB 17B6 20B3 20B8 26D7 74C2 SDCONN_CLK_FF SDCONN_CLK_FF - @mlb_lib.MLB 34C4 85C3 SMC_SCI_L SMC_SCI_L - @mlb_lib.MLB 20A6 20C6 46C5 T29_D2R_P<3..0> T29_D2R_P<3..0> - @mlb_lib.MLB 86C3
74C6 74D2 75D1 76B6 76C6 SDCONN_CLK_R SDCONN_CLK_R - @mlb_lib.MLB 34C3 85C3 SMC_SYS_LED SMC_SYS_LED - @mlb_lib.MLB 6C2 45C7 46B5 T29_D2R_P<1> T29_D2R_P<1> - @mlb_lib.MLB 74A3 77D5
PP3V3_T29_DP PP3V3_T29_DP - @mlb_lib.MLB 75D3 SDCONN_CMD SDCONN_CMD - @mlb_lib.MLB 34C5 37B1 85C3 91C7 SMC_SYS_LED_DR SMC_SYS_LED_DR - @mlb_lib.MLB 45C5 91B7 T29_DP_ATEST T29_DP_ATEST - @mlb_lib.MLB 74B3
PP3V3_T29_DPBIAS PP3V3_T29_DPBIAS - @mlb_lib.MLB 75C4 SDCONN_CMD_R SDCONN_CMD_R - @mlb_lib.MLB 34C3 34D7 85C3 SMC_SYS_LED_IREF SMC_SYS_LED_IREF - @mlb_lib.MLB 45C6 T29_DP_A_PWR_EN T29_DP_A_PWR_EN - @mlb_lib.MLB 78C7 78D8
PP3V3_T29_PLL PP3V3_T29_PLL - @mlb_lib.MLB 75C4 SDCONN_DATA<0> SDCONN_DATA<0> - @mlb_lib.MLB 34C5 37B1 SMC_SYS_LED_IREF_M SMC_SYS_LED_IREF_M - @mlb_lib.MLB 45D6 T29_DP_PORTA_PWR_EN T29_DP_PORTA_PWR_EN - @mlb_lib.MLB 19C1 24D4 78C8
PP3V3_U5300 PP3V3_U5300 - @mlb_lib.MLB 50D6 SDCONN_DATA<7..0> SDCONN_DATA<7..0> - @mlb_lib.MLB 85C3 91C7 SMC_SYS_LED_IREF_S SMC_SYS_LED_IREF_S - @mlb_lib.MLB 45D5 T29_DP_RES T29_DP_RES - @mlb_lib.MLB 74B3
PP3V3_WLAN PP3V3_WLAN - @mlb_lib.MLB 35C6 35D7 47A1 91D7 SDCONN_DATA<1> SDCONN_DATA<1> - @mlb_lib.MLB 34C5 37B1 SMC_SYS_LED_L SMC_SYS_LED_L - @mlb_lib.MLB 45C6 T29_GPIO<1> T29_GPIO<1> - @mlb_lib.MLB 74C5
PP3V3_WLAN_FET PP3V3_WLAN_FET - @mlb_lib.MLB 35C3 SDCONN_DATA<2> SDCONN_DATA<2> - @mlb_lib.MLB 34C5 37B1 SMC_SYS_LED_R SMC_SYS_LED_R - @mlb_lib.MLB 45C6 T29_GPIO<2> T29_GPIO<2> - @mlb_lib.MLB 74C5
PP4V5_AUDIO_ANALOG PP4V5_AUDIO_ANALOG - @mlb_lib.MLB 53A3 53C5 53D1 53D7 91B5 SDCONN_DATA<3> SDCONN_DATA<3> - @mlb_lib.MLB 34C5 37B1 SMC_TCK SMC_TCK - @mlb_lib.MLB 46B5 47B2 48C3 T29_LSEO<0> T29_LSEO<0> - @mlb_lib.MLB 74A3 77A7
PP5V_AUDIO_HPAMP PP5V_AUDIO_HPAMP - @mlb_lib.MLB 53A6 55D6 SDCONN_DATA<4> SDCONN_DATA<4> - @mlb_lib.MLB 34C5 37B1 SMC_TDI SMC_TDI - @mlb_lib.MLB 46B5 47B2 48C3 T29_LSEO<1> T29_LSEO<1> - @mlb_lib.MLB 74A3 77A4
PP5V_G3H PP5V_G3H - @mlb_lib.MLB 6B7 45D6 47D8 61C4 65B7 SDCONN_DATA<5> SDCONN_DATA<5> - @mlb_lib.MLB 34C5 37B1 SMC_TDO SMC_TDO - @mlb_lib.MLB 46B5 47B2 48C5 T29_LSEO_LSOE0 T29_LSEO_LSOE0 - @mlb_lib.MLB 74A5
65D5 91C5 SDCONN_DATA<6> SDCONN_DATA<6> - @mlb_lib.MLB 34C5 37B1 SMC_THRMTRIP SMC_THRMTRIP - @mlb_lib.MLB 46A5 47C1 T29_LSEO_LSOE1 T29_LSEO_LSOE1 - @mlb_lib.MLB 74A5

D PP5V_HDMI_DDC_CONN
PP5V_HDMI_DDC_FUSE
PP5V_HDMI_DDC_CONN - @mlb_lib.MLB
PP5V_HDMI_DDC_FUSE - @mlb_lib.MLB
80B6 80C1 91B5
80B5 80D2
SDCONN_DATA<7>
SDCONN_DATA_R<0>
SDCONN_DATA<7> - @mlb_lib.MLB
SDCONN_DATA_R<0> - @mlb_lib.MLB
34C5
34C3
37B1
34D7
SMC_TMS
SMC_TRST_L
SMC_TMS - @mlb_lib.MLB
SMC_TRST_L - @mlb_lib.MLB
46B5 47B2 48C5
46C1 48C5
T29_LSOE<0>
T29_LSOE<1>
T29_LSOE<0> - @mlb_lib.MLB
T29_LSOE<1> - @mlb_lib.MLB
74A3
74A3
77A7
77A7
D
PP5V_S0 PP5V_S0 - @mlb_lib.MLB 7D7 23C8 24B4 24B4 41A5 SDCONN_DATA_R<7..0> SDCONN_DATA_R<7..0> - @mlb_lib.MLB 85C3 SMC_TX_L SMC_TX_L - @mlb_lib.MLB 43D5 46B8 46C5 47B2 48C5 T29_MCU_INT_L T29_MCU_INT_L - @mlb_lib.MLB 19D6 77A7
41B8 42D3 42D6 48D5 61B1 SDCONN_DATA_R<1> SDCONN_DATA_R<1> - @mlb_lib.MLB 34C3 34D7 SMC_VCCSA_ISENSE SMC_VCCSA_ISENSE - @mlb_lib.MLB 46A8 50A5 T29_MONDC0 T29_MONDC0 - @mlb_lib.MLB 74D5
62A8 64C6 67D5 68C7 68D7 SDCONN_DATA_R<2> SDCONN_DATA_R<2> - @mlb_lib.MLB 34C3 34D7 SMC_VCCSA_VSENSE SMC_VCCSA_VSENSE - @mlb_lib.MLB 46A8 50A5 T29_MONDC1 T29_MONDC1 - @mlb_lib.MLB 74D5
69D8 70C6 71B7 80D4 91B7 SDCONN_DATA_R<3> SDCONN_DATA_R<3> - @mlb_lib.MLB 34C3 34C7 SMC_VCL SMC_VCL - @mlb_lib.MLB 46D2 T29_MONOBSN T29_MONOBSN - @mlb_lib.MLB 74C5
91C5 91C7 SDCONN_DATA_R<4> SDCONN_DATA_R<4> - @mlb_lib.MLB 34C3 34C7 SMC_XTAL SMC_XTAL - @mlb_lib.MLB 46C3 47B8 T29_MONOBSP T29_MONOBSP - @mlb_lib.MLB 74D5
PP5V_S0_AUDIO PP5V_S0_AUDIO - @mlb_lib.MLB 7D7 53A8 SDCONN_DATA_R<5> SDCONN_DATA_R<5> - @mlb_lib.MLB 34C3 34C7 SMC_XTAL_R SMC_XTAL_R - @mlb_lib.MLB 47B7 T29_PCIE_WAKE_L T29_PCIE_WAKE_L - @mlb_lib.MLB 74D3
PP5V_S0_AUDIO_AMP PP5V_S0_AUDIO_AMP - @mlb_lib.MLB 7C7 56C6 SDCONN_DATA_R<6> SDCONN_DATA_R<6> - @mlb_lib.MLB 34C3 34C7 SML_PCH_0_ALERT_L SML_PCH_0_ALERT_L - @mlb_lib.MLB 17A3 17D1 T29_PWR_EN T29_PWR_EN - @mlb_lib.MLB 20B1 76A8
PP5V_S0_CPUVCCIOS0_V PP5V_S0_CPUVCCIOS0_VCC - 70C6 SDCONN_DATA_R<7> SDCONN_DATA_R<7> - @mlb_lib.MLB 34C3 34C7 SML_PCH_0_CLK SML_PCH_0_CLK - @mlb_lib.MLB 17D1 49B8 T29_PWR_EN_PCH T29_PWR_EN_PCH - @mlb_lib.MLB 17D5 20B3
CC @mlb_lib.MLB SDCONN_DETECT SDCONN_DETECT - @mlb_lib.MLB 34B6 34C3 34C7 91C7 SML_PCH_0_DATA SML_PCH_0_DATA - @mlb_lib.MLB 17D1 49B8 T29_PWR_EN_U2916 T29_PWR_EN_U2916 - @mlb_lib.MLB 76A7
PP5V_S0_CPU_VCORE_VC PP5V_S0_CPU_VCORE_VCC - 67B1 67B4 67B8 67C7 67D4 SDCONN_DETECT_L SDCONN_DETECT_L - @mlb_lib.MLB 34B5 SML_PCH_1_ALERT_L SML_PCH_1_ALERT_L - @mlb_lib.MLB 17A3 17D1 T29_R2D_C_F_N<0> T29_R2D_C_F_N<0> - @mlb_lib.MLB 77D4
C @mlb_lib.MLB SDCONN_STATE_CHANGE SDCONN_STATE_CHANGE - @mlb_lib.MLB 19C1 24C4 34B2 SML_PCH_1_CLK SML_PCH_1_CLK - @mlb_lib.MLB 17D1 49A8 84C3 T29_R2D_C_F_N<1..0> T29_R2D_C_F_N<1..0> - @mlb_lib.MLB 86B3
PP5V_S0_PCH_V5REF PP5V_S0_PCH_V5REF - @mlb_lib.MLB 21D5 23B6 SDCONN_STATE_CHANGE_ SDCONN_STATE_CHANGE_S1R - 34B4 SML_PCH_1_DATA SML_PCH_1_DATA - @mlb_lib.MLB 17D1 49A8 84C3 T29_R2D_C_F_N<1> T29_R2D_C_F_N<1> - @mlb_lib.MLB 77D4
PP5V_S0_VCCSAS0_VCC PP5V_S0_VCCSAS0_VCC - @mlb_lib.MLB 64C6 S1R @mlb_lib.MLB SMS_INT_L SMS_INT_L - @mlb_lib.MLB 46B5 47B2 T29_R2D_C_F_P<0> T29_R2D_C_F_P<0> - @mlb_lib.MLB 77D4
PP5V_S4 PP5V_S4 - @mlb_lib.MLB 6C3 28B3 28B6 43C8 43D8 SDCONN_STATE_CHANGE_ SDCONN_STATE_CHANGE_S2R - 34A4 SMT_THRM_SNS3_N SMT_THRM_SNS3_N - @mlb_lib.MLB 52A7 T29_R2D_C_F_P<1..0> T29_R2D_C_F_P<1..0> - @mlb_lib.MLB 86B3
44C6 45D4 61B4 61B8 65B2 S2R @mlb_lib.MLB SMT_THRM_SNS3_P SMT_THRM_SNS3_P - @mlb_lib.MLB 52A7 T29_R2D_C_F_P<1> T29_R2D_C_F_P<1> - @mlb_lib.MLB 77D4
66C7 78D6 78D8 91C5 SDCONN_WP SDCONN_WP - @mlb_lib.MLB 34C3 34C7 37B1 91C7 SNS_1V8S0 SNS_1V8S0 - @mlb_lib.MLB 71C6 T29_R2D_C_N<0> T29_R2D_C_N<0> - @mlb_lib.MLB 74A3 77D5
PP5V_S4_DDRREG_V5IN PP5V_S4_DDRREG_V5IN - @mlb_lib.MLB 66C7 SLG_ENET_RESET_L SLG_ENET_RESET_L - @mlb_lib.MLB 34B7 SNS_T1_ADDR SNS_T1_ADDR - @mlb_lib.MLB 52D6 T29_R2D_C_N<3..0> T29_R2D_C_N<3..0> - @mlb_lib.MLB 86C3
PP5V_S4_IR_R PP5V_S4_IR_R - @mlb_lib.MLB 44C3 44C5 SLG_ENET_RESET_R_L SLG_ENET_RESET_R_L - @mlb_lib.MLB 34B4 SNS_T1_ALERT_L SNS_T1_ALERT_L - @mlb_lib.MLB 52D6 T29_R2D_C_N<1> T29_R2D_C_N<1> - @mlb_lib.MLB 74A3 77D5
PP5V_S5 PP5V_S5 - @mlb_lib.MLB 6A7 23B8 61C1 SMBUS_PCH_CLK SMBUS_PCH_CLK - @mlb_lib.MLB 17D1 49D8 84D3 SNS_T1_TRIPSET SNS_T1_TRIPSET - @mlb_lib.MLB 52D6 T29_R2D_C_P<0> T29_R2D_C_P<0> - @mlb_lib.MLB 74A3 77D5
PP5V_SUS_PCH_V5REFSU PP5V_SUS_PCH_V5REFSUS - 21B5 23B7 SMBUS_PCH_DATA SMBUS_PCH_DATA - @mlb_lib.MLB 17D1 49D8 84C3 SNS_T2_ADDR SNS_T2_ADDR - @mlb_lib.MLB 52B6 T29_R2D_C_P<3..0> T29_R2D_C_P<3..0> - @mlb_lib.MLB 86C3
S @mlb_lib.MLB SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SCL - @mlb_lib.MLB 46B8 49D6 87D3 SNS_T2_ALERT_L SNS_T2_ALERT_L - @mlb_lib.MLB 52B6 T29_R2D_C_P<1> T29_R2D_C_P<1> - @mlb_lib.MLB 74A3 77D5
PP5V_U7100_PVCC PP5V_U7100_PVCC - @mlb_lib.MLB 64C5 =I2C_T29THMSNS_SCL - @mlb_lib.MLB 49D3 52B5 SPIROM_USE_MLB SPIROM_USE_MLB - @mlb_lib.MLB 20C6 20C7 48C3 59B5 91A5 T29_R2D_N<0> T29_R2D_N<0> - @mlb_lib.MLB 77D3 86C3
PP5V_U7700_PVCC PP5V_U7700_PVCC - @mlb_lib.MLB 70C6 SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SDA - @mlb_lib.MLB 46C5 49D6 87D3 SPI_ALT_CLK SPI_ALT_CLK - @mlb_lib.MLB 48B3 48C3 T29_R2D_N<1> T29_R2D_N<1> - @mlb_lib.MLB 77D3 86C3
PP5V_USB2_PORT0 PP5V_USB2_PORT0 - @mlb_lib.MLB 43B6 =I2C_T29THMSNS_SDA - @mlb_lib.MLB 49D3 52B5 SPI_ALT_CS_L SPI_ALT_CS_L - @mlb_lib.MLB 48B3 48C3 T29_R2D_P<0> T29_R2D_P<0> - @mlb_lib.MLB 77D3 86C3
PP5V_USB2_PORT0_F PP5V_USB2_PORT0_F - @mlb_lib.MLB 43B4 SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SCL - @mlb_lib.MLB 46A5 49C6 87D3 SPI_ALT_MISO SPI_ALT_MISO - @mlb_lib.MLB 48B3 48C5 T29_R2D_P<1> T29_R2D_P<1> - @mlb_lib.MLB 77D3 86C3
PP5V_USB2_PORT1 PP5V_USB2_PORT1 - @mlb_lib.MLB 43C6 =SMBUS_REMOTE_THMSNS_SCL - 49C3 SPI_ALT_MOSI SPI_ALT_MOSI - @mlb_lib.MLB 48B3 48C5 T29_RBIAS T29_RBIAS - @mlb_lib.MLB 74C3
PP5V_USB2_PORT1_F PP5V_USB2_PORT1_F - @mlb_lib.MLB 43C4 @mlb_lib.MLB SPI_CLK SPI_CLK - @mlb_lib.MLB 48B5 84C3 91A5 T29_RESET_L T29_RESET_L - @mlb_lib.MLB 74D2 76C6
PP5V_USB2_PORT2 PP5V_USB2_PORT2 - @mlb_lib.MLB 43C6 SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SDA - @mlb_lib.MLB 46A5 49C6 87D3 SPI_CLK_R SPI_CLK_R - @mlb_lib.MLB 17C8 48B6 84C3 T29_RSENSE T29_RSENSE - @mlb_lib.MLB 74D3
PP5V_USB2_PORT2_F PP5V_USB2_PORT2_F - @mlb_lib.MLB 43C2 =SMBUS_REMOTE_THMSNS_SDA - 49C3 SPI_CS0_L SPI_CS0_L - @mlb_lib.MLB 48B5 84C3 91A5 T29_RSVD T29_RSVD - @mlb_lib.MLB 74C5
PP5V_USB2_PORT3 PP5V_USB2_PORT3 - @mlb_lib.MLB 43D5 @mlb_lib.MLB SPI_CS0_R_L SPI_CS0_R_L - @mlb_lib.MLB 17C8 48B6 84C3 T29_SPI_CLK T29_SPI_CLK - @mlb_lib.MLB 74C5 86C3

C PP5V_USB2_PORT3_F
PP12V_G3H
PP5V_USB2_PORT3_F - @mlb_lib.MLB
PP12V_G3H - @mlb_lib.MLB
43D2
6C7 41D8 51C8 51D4 51D8
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_B_S0_SCL - @mlb_lib.MLB
SMBUS_SMC_B_S0_SDA - @mlb_lib.MLB
46A5
46A5
49A5
49A5
87D3
87D3
SPI_MISO
SPI_MLB_CLK
SPI_MISO - @mlb_lib.MLB
SPI_MLB_CLK - @mlb_lib.MLB
17C8 48A6 84C3
48B3 59C5
91A5 T29_SPI_CS_L
T29_SPI_MISO
T29_SPI_CS_L - @mlb_lib.MLB
T29_SPI_MISO - @mlb_lib.MLB
74C5
74C5
86C3
86C3
C
60D7 65B8 65C4 65D3 72C3 SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SCL - @mlb_lib.MLB 46C5 49C3 87D3 SPI_MLB_CS_L SPI_MLB_CS_L - @mlb_lib.MLB 48B3 59C5 T29_SPI_MOSI T29_SPI_MOSI - @mlb_lib.MLB 74C5 86C3
78D4 SMBUS_SMC_MGMT_SDA SMBUS_SMC_MGMT_SDA - @mlb_lib.MLB 46C8 49C3 87D3 SPI_MLB_MISO SPI_MLB_MISO - @mlb_lib.MLB 48A3 59C4 T29_SW_RESET_L T29_SW_RESET_L - @mlb_lib.MLB 20A4 20C6 76B8
PP12V_G3H_CPUDDR PP12V_G3H_CPUDDR - @mlb_lib.MLB 6C6 51C8 64D5 66D6 68D6 SMB_PCH_DIMM_SCL SMB_PCH_DIMM_SCL - @mlb_lib.MLB 49D6 84D3 SPI_MLB_MOSI SPI_MLB_MOSI - @mlb_lib.MLB 48A3 59C4 T29_TEST_EN T29_TEST_EN - @mlb_lib.MLB 74C5
69D3 70D5 =I2C_SODIMMB_SCL - @mlb_lib.MLB 31A5 49C6 SPI_MOSI SPI_MOSI - @mlb_lib.MLB 48A5 84C3 91A5 T29_TEST_POINT_3 T29_TEST_POINT_3 - @mlb_lib.MLB 74C5
PP12V_G3H_DDRS3REG_F PP12V_G3H_DDRS3REG_FILT - 66D4 =I2C_SODIMMA_SCL - @mlb_lib.MLB 30A5 49D6 SPI_MOSI_R SPI_MOSI_R - @mlb_lib.MLB 17C8 48A6 84C3 T29_THERMD_N T29_THERMD_N - @mlb_lib.MLB 89B1
ILT @mlb_lib.MLB =I2C_SODIMMB_SCL - @mlb_lib.MLB 31A5 49C6 SPI_WP_L SPI_WP_L - @mlb_lib.MLB 59C5 T29_THERMD_P T29_THERMD_P - @mlb_lib.MLB 89B1
PP12V_G3H_GPU PP12V_G3H_GPU - @mlb_lib.MLB 6C6 =I2C_SODIMMA_SCL - @mlb_lib.MLB 30A5 49D6 SPKRAMP_M_N_OUT SPKRAMP_M_N_OUT - @mlb_lib.MLB 56B3 57B2 91D5 T29_TMU_CLK_IN T29_TMU_CLK_IN - @mlb_lib.MLB 74C3

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PP12V_G3H_PSU PP12V_G3H_PSU - @mlb_lib.MLB 6C7 51D8 72B5 91D5 SMB_PCH_DIMM_SDA SMB_PCH_DIMM_SDA - @mlb_lib.MLB 49D6 84D3 SPKRAMP_M_P_OUT SPKRAMP_M_P_OUT - @mlb_lib.MLB 56B3 57B2 91D5 T29_TMU_CLK_OUT T29_TMU_CLK_OUT - @mlb_lib.MLB 74C3
PP12V_S0_AXG_FLTRD PP12V_S0_AXG_FLTRD - @mlb_lib.MLB 69D5 =I2C_SODIMMB_SDA - @mlb_lib.MLB 31A5 49C6 SS_1V8S0 SS_1V8S0 - @mlb_lib.MLB 71C7 TIPDET_UNFILT TIPDET_UNFILT - @mlb_lib.MLB 58A3 58D4
PP12V_S0_CPU_FLTRD PP12V_S0_CPU_FLTRD - @mlb_lib.MLB 67B2 68C3 68D2 =I2C_SODIMMA_SDA - @mlb_lib.MLB 30A5 49C6 SUSWARN_L SUSWARN_L - @mlb_lib.MLB 18A6 18B7 18C8 TP_1V05_S0_PCH_VCCAP TP_1V05_S0_PCH_VCCAPLLEXP - 21C4
PP12V_S0_FAN PP12V_S0_FAN - @mlb_lib.MLB 60D4 =I2C_SODIMMB_SDA - @mlb_lib.MLB 31A5 49C6 SW_1V8S0 SW_1V8S0 - @mlb_lib.MLB 71D6 LLEXP @mlb_lib.MLB
PP12V_S0_FAN0_F PP12V_S0_FAN0_F - @mlb_lib.MLB 60C3 91D5 =I2C_SODIMMA_SDA - @mlb_lib.MLB 30A5 49C6 SYSCLK_CLK25M_ENET_S SYSCLK_CLK25M_ENET_SR - 26C4 TP_AUD_DMIC_CLK TP_AUD_DMIC_CLK - @mlb_lib.MLB 53C2
PPCPUVCCIO_S0_REG_R PPCPUVCCIO_S0_REG_R - @mlb_lib.MLB 70C3 SMB_PCH_MKY_SCL SMB_PCH_MKY_SCL - @mlb_lib.MLB 49C6 84D3 R @mlb_lib.MLB TP_BCM57765_SPD100LE TP_BCM57765_SPD100LED_L - 37B6
PPDDRVREF_S3 PPDDRVREF_S3 - @mlb_lib.MLB 6A3 33D3 66B5 91C5 =I2C_MIKEY_SCL - @mlb_lib.MLB 49C6 58D5 SYSCLK_CLK25M_SB SYSCLK_CLK25M_SB - @mlb_lib.MLB 26C4 D_L @mlb_lib.MLB
PPIRRCVR_F PPIRRCVR_F - @mlb_lib.MLB 45D2 91B7 SMB_PCH_MKY_SDA SMB_PCH_MKY_SDA - @mlb_lib.MLB 49C6 84D3 SYSCLK_CLK25M_T29 SYSCLK_CLK25M_T29 - @mlb_lib.MLB 26C2 74C1 TP_BCM57765_TRAFFICL TP_BCM57765_TRAFFICLED_L - 37B6
PPIRRCVR_G3H_LED PPIRRCVR_G3H_LED - @mlb_lib.MLB 45D3 =I2C_MIKEY_SDA - @mlb_lib.MLB 49C6 58D5 SYSCLK_CLK25M_T29_R SYSCLK_CLK25M_T29_R - @mlb_lib.MLB 74C3 ED_L @mlb_lib.MLB
PPUSB_HUB1_CRFILT PPUSB_HUB1_CRFILT - @mlb_lib.MLB 25D5 SMB_PCH_STR_SCL SMB_PCH_STR_SCL - @mlb_lib.MLB 49D6 84D3 SYSCLK_CLK25M_T29_SR SYSCLK_CLK25M_T29_SR - @mlb_lib.MLB 26C4 TP_CLK98M_TS_L TP_CLK98M_TS_L - @mlb_lib.MLB 39C1
PPUSB_HUB1_PLLFILT PPUSB_HUB1_PLLFILT - @mlb_lib.MLB 25D5 SMB_PCH_STR_SDA SMB_PCH_STR_SDA - @mlb_lib.MLB 49D6 84D3 SYSCLK_CLK25M_X1 SYSCLK_CLK25M_X1 - @mlb_lib.MLB 26C6 TP_CPU_CFG<8> TP_CPU_CFG<8> - @mlb_lib.MLB 10D3
PPUSB_HUB2_CRFILT PPUSB_HUB2_CRFILT - @mlb_lib.MLB 25B5 SMB_PCH_VRF_SCL SMB_PCH_VRF_SCL - @mlb_lib.MLB 49D8 84D3 SYSCLK_CLK25M_X2 SYSCLK_CLK25M_X2 - @mlb_lib.MLB 26C7 TP_CPU_CFG<9> TP_CPU_CFG<9> - @mlb_lib.MLB 10D3
PPUSB_HUB2_PLLFILT PPUSB_HUB2_PLLFILT - @mlb_lib.MLB 25B5 =I2C_PCA9557D_SCL - @mlb_lib.MLB 33C7 49C8 SYSCLK_CLK25M_X2_R SYSCLK_CLK25M_X2_R - @mlb_lib.MLB 26C6 TP_CPU_CFG<10> TP_CPU_CFG<10> - @mlb_lib.MLB 10D3
PPVAXG_S0_CPU PPVAXG_S0_CPU - @mlb_lib.MLB 7B7 13D4 16D8 50B3 67D8 =I2C_VREFDACS_SCL - @mlb_lib.MLB 33D7 49C8 SYS_ONEWIRE SYS_ONEWIRE - @mlb_lib.MLB 46B8 47B2 TP_CPU_CFG<11> TP_CPU_CFG<11> - @mlb_lib.MLB 10D3
69C1 =I2C_PCA9557D_SCL - @mlb_lib.MLB 33C7 49C8 SYS_PWROK_R SYS_PWROK_R - @mlb_lib.MLB 27A6 TP_CPU_CFG<12> TP_CPU_CFG<12> - @mlb_lib.MLB 10D3
PPVAXG_S0_CPU_RS PPVAXG_S0_CPU_RS - @mlb_lib.MLB 69C4 SMB_PCH_VRF_SDA SMB_PCH_VRF_SDA - @mlb_lib.MLB 49D8 84D3 T29DPA_CONFIG1_RC T29DPA_CONFIG1_RC - @mlb_lib.MLB 77A4 78A8 TP_CPU_CFG<13> TP_CPU_CFG<13> - @mlb_lib.MLB 10D3
PPVBATT_G3_RTC PPVBATT_G3_RTC - @mlb_lib.MLB 6D7 27D8 =I2C_PCA9557D_SDA - @mlb_lib.MLB 33C7 49C8 T29DPA_CONFIG2_RC T29DPA_CONFIG2_RC - @mlb_lib.MLB 77A4 78A8 TP_CPU_CFG<14> TP_CPU_CFG<14> - @mlb_lib.MLB 10D3
PPVBATT_G3_RTC_R PPVBATT_G3_RTC_R - @mlb_lib.MLB 27D7 =I2C_VREFDACS_SDA - @mlb_lib.MLB 33D7 49C8 T29DPA_D2R1_AUXCH_CC T29DPA_D2R1_AUXCH_CC_N - 86A3 TP_CPU_CFG<15> TP_CPU_CFG<15> - @mlb_lib.MLB 10D3
PPVCCSA_S0_CPU PPVCCSA_S0_CPU - @mlb_lib.MLB 7B7 13B4 13C1 16B4 50A7 =I2C_PCA9557D_SDA - @mlb_lib.MLB 33C7 49C8 _N @mlb_lib.MLB TP_CPU_CFG<17> TP_CPU_CFG<17> - @mlb_lib.MLB 10D3
64C1 SMB_PCH_XDP_SCL SMB_PCH_XDP_SCL - @mlb_lib.MLB 49C8 84C3 T29DPA_D2R1_AUXCH_CC T29DPA_D2R1_AUXCH_CC_P - 86A3 TP_CPU_DC_TEST_A4 TP_CPU_DC_TEST_A4 - @mlb_lib.MLB 10C1
PPVCCSA_S0_REG_R PPVCCSA_S0_REG_R - @mlb_lib.MLB 64C3 =SMBUS_XDP_SCL - @mlb_lib.MLB 24C7 49B8 _P @mlb_lib.MLB TP_CPU_DC_TEST_A58 TP_CPU_DC_TEST_A58 - @mlb_lib.MLB 10C1
PPVCORE_S0_CPU PPVCORE_S0_CPU - @mlb_lib.MLB 7B7 10D4 10D4 13D8 15D8 SMB_PCH_XDP_SDA SMB_PCH_XDP_SDA - @mlb_lib.MLB 49C8 84C3 T29DPA_D2R1_AUXCH_N T29DPA_D2R1_AUXCH_N - @mlb_lib.MLB 78B6 86B3 TP_CPU_DC_TEST_BD1 TP_CPU_DC_TEST_BD1 - @mlb_lib.MLB 10B1
50C3 67A8 68A4 68C2 68D2 =SMBUS_XDP_SDA - @mlb_lib.MLB 24C7 49B8 T29DPA_D2R1_AUXCH_P T29DPA_D2R1_AUXCH_P - @mlb_lib.MLB 78B6 86B3 TP_CPU_DC_TEST_BD61 TP_CPU_DC_TEST_BD61 - @mlb_lib.MLB 10C1

B PPVOUT_G3_PCH_DCPRTC PPVOUT_G3_PCH_DCPRTC - @mlb_lib.MLB

91B5
21C8
SMB_SMC_B_STR_SCL
SMB_SMC_B_STR_SDA
SMB_SMC_B_STR_SCL - @mlb_lib.MLB
SMB_SMC_B_STR_SDA - @mlb_lib.MLB
49A5
49A5
87D3
87D3
T29DPA_HPD
T29DPA_HPD_R
T29DPA_HPD - @mlb_lib.MLB
T29DPA_HPD_R - @mlb_lib.MLB
77A7
78A5
78A8 TP_CPU_DC_TEST_BG4
TP_CPU_DC_TEST_BG58
TP_CPU_DC_TEST_BG4 - @mlb_lib.MLB
TP_CPU_DC_TEST_BG58 - @mlb_lib.MLB
10C1
10C1 B
PPVOUT_S0_PCH_DCPSST PPVOUT_S0_PCH_DCPSST - @mlb_lib.MLB 21B8 SMB_SMC_B_TSN_SCL SMB_SMC_B_TSN_SCL - @mlb_lib.MLB 49A3 87D3 T29DPA_ML_C_N<0> T29DPA_ML_C_N<0> - @mlb_lib.MLB 77D1 78B1 TP_CPU_DC_TEST_D1 TP_CPU_DC_TEST_D1 - @mlb_lib.MLB 10C1
PPVP_FW_PHY_CPS PPVP_FW_PHY_CPS - @mlb_lib.MLB 39B1 41D3 =I2C_CPUTHMSNS_SCL - @mlb_lib.MLB 49A3 52D5 T29DPA_ML_C_N<3..0> T29DPA_ML_C_N<3..0> - @mlb_lib.MLB 86B3 TP_CPU_DC_TEST_D61 TP_CPU_DC_TEST_D61 - @mlb_lib.MLB 10C1
PSU_TEMP PSU_TEMP - @mlb_lib.MLB 46C5 72C5 91C5 SMB_SMC_B_TSN_SDA SMB_SMC_B_TSN_SDA - @mlb_lib.MLB 49A3 87D3 T29DPA_ML_C_N<2> T29DPA_ML_C_N<2> - @mlb_lib.MLB 77D1 78B1 TP_CPU_VCC_DIE_SENSE TP_CPU_VCC_DIE_SENSE - @mlb_lib.MLB 10C4
PU_FW_VP PU_FW_VP - @mlb_lib.MLB 39D2 =I2C_CPUTHMSNS_SDA - @mlb_lib.MLB 49A3 52D5 T29DPA_ML_C_P<0> T29DPA_ML_C_P<0> - @mlb_lib.MLB 77D1 78B1 TP_CPU_VDDQ_SENSEN TP_CPU_VDDQ_SENSEN - @mlb_lib.MLB 13C1
PU_HDMI_LS_RSV1 PU_HDMI_LS_RSV1 - @mlb_lib.MLB 79B6 SMC_ADAPTER_EN SMC_ADAPTER_EN - @mlb_lib.MLB 18C8 46D5 47B2 T29DPA_ML_C_P<3..0> T29DPA_ML_C_P<3..0> - @mlb_lib.MLB 86B3 TP_CPU_VDDQ_SENSEP TP_CPU_VDDQ_SENSEP - @mlb_lib.MLB 13C1
PU_SDCONN_OC_L PU_SDCONN_OC_L - @mlb_lib.MLB 34D3 SMC_BC_ACOK SMC_BC_ACOK - @mlb_lib.MLB 46C5 47B2 T29DPA_ML_C_P<2> T29DPA_ML_C_P<2> - @mlb_lib.MLB 77D1 78B1 TP_DPAPWRSW_FLT_L TP_DPAPWRSW_FLT_L - @mlb_lib.MLB 78D1
PU_USB1_PRT4N PU_USB1_PRT4N - @mlb_lib.MLB 25C5 SMC_BIL_BUTTON_L SMC_BIL_BUTTON_L - @mlb_lib.MLB 46C5 47B2 T29DPA_ML_N<0> T29DPA_ML_N<0> - @mlb_lib.MLB 78B3 TP_FWOHCI_XO TP_FWOHCI_XO - @mlb_lib.MLB 39C2
PU_USB1_PRT4P PU_USB1_PRT4P - @mlb_lib.MLB 25C5 SMC_CASE_OPEN SMC_CASE_OPEN - @mlb_lib.MLB 46B5 47B2 T29DPA_ML_N<3..0> T29DPA_ML_N<3..0> - @mlb_lib.MLB 86B3 TP_FWPHY_CNA TP_FWPHY_CNA - @mlb_lib.MLB 39B2
PU_USB2_PRT4N PU_USB2_PRT4N - @mlb_lib.MLB 25A5 SMC_CLK32K SMC_CLK32K - @mlb_lib.MLB 46C5 47C4 T29DPA_ML_N<1> T29DPA_ML_N<1> - @mlb_lib.MLB 77B1 78B1 TP_FWXIO_GRST_L TP_FWXIO_GRST_L - @mlb_lib.MLB 39B6
PU_USB2_PRT4P PU_USB2_PRT4P - @mlb_lib.MLB 25A5 SMC_CPUDDR_HI_ISENSE SMC_CPUDDR_HI_ISENSE - @mlb_lib.MLB 46A8 51C5 T29DPA_ML_N<2> T29DPA_ML_N<2> - @mlb_lib.MLB 78B3 TP_FWXIO_JTAG_TDI TP_FWXIO_JTAG_TDI - @mlb_lib.MLB 39B6
PVCCIO_S0_SMC_R PVCCIO_S0_SMC_R - @mlb_lib.MLB 46A5 SMC_CPUP1V5_ISENSE SMC_CPUP1V5_ISENSE - @mlb_lib.MLB 46A8 50D5 T29DPA_ML_N<3> T29DPA_ML_N<3> - @mlb_lib.MLB 77B1 78B8 TP_FWXIO_JTAG_TDO TP_FWXIO_JTAG_TDO - @mlb_lib.MLB 39B6
PVCCSA_EN PVCCSA_EN - @mlb_lib.MLB 62C1 64C6 SMC_CPUVCCIO_ISENSE SMC_CPUVCCIO_ISENSE - @mlb_lib.MLB 46C5 50B5 T29DPA_ML_P<0> T29DPA_ML_P<0> - @mlb_lib.MLB 78B3 TP_FWXIO_JTAG_TMS TP_FWXIO_JTAG_TMS - @mlb_lib.MLB 39B6
PVCCSA_PGOOD PVCCSA_PGOOD - @mlb_lib.MLB 62A6 64C6 SMC_CPU_ISENSE SMC_CPU_ISENSE - @mlb_lib.MLB 46C5 50D1 T29DPA_ML_P<3..0> T29DPA_ML_P<3..0> - @mlb_lib.MLB 86B3 TP_HDMI_CEC_CONN TP_HDMI_CEC_CONN - @mlb_lib.MLB 80C4
RTC_RESET_L RTC_RESET_L - @mlb_lib.MLB 17A7 17D8 SMC_CPU_VSENSE SMC_CPU_VSENSE - @mlb_lib.MLB 46C5 50C1 T29DPA_ML_P<1> T29DPA_ML_P<1> - @mlb_lib.MLB 77B1 78B1 TP_IRUC_RCVR_PWR_EN_ TP_IRUC_RCVR_PWR_EN_L - 44C6
RT_1V8S0 RT_1V8S0 - @mlb_lib.MLB 71C6 SMC_DCIN_ISENSE SMC_DCIN_ISENSE - @mlb_lib.MLB 46A8 51D5 T29DPA_ML_P<2> T29DPA_ML_P<2> - @mlb_lib.MLB 78B3 L @mlb_lib.MLB
S0PGD_BJT_GND_R S0PGD_BJT_GND_R - @mlb_lib.MLB 62B6 SMC_DCIN_VSENSE SMC_DCIN_VSENSE - @mlb_lib.MLB 46A8 51D1 T29DPA_ML_P<3> T29DPA_ML_P<3> - @mlb_lib.MLB 77B1 78B8 TP_LPC_CLK33M_GMUX_R TP_LPC_CLK33M_GMUX_R - @mlb_lib.MLB 19C6
S0PGD_C S0PGD_C - @mlb_lib.MLB 62C7 SMC_DELAYED_PWRGD SMC_DELAYED_PWRGD - @mlb_lib.MLB 27A7 46D8 T29ROM_HOLD_L T29ROM_HOLD_L - @mlb_lib.MLB 74C8 TP_PCH_TP23 TP_PCH_TP23 - @mlb_lib.MLB 18C5
S5_PWRGD S5_PWRGD - @mlb_lib.MLB 46D8 62D7 SMC_DP_HPD_L SMC_DP_HPD_L - @mlb_lib.MLB 46B8 47B4 77A4 T29ROM_WP_L T29ROM_WP_L - @mlb_lib.MLB 74C8 TP_PCI_CLK33M_OUT3 TP_PCI_CLK33M_OUT3 - @mlb_lib.MLB 19C6
SATARDRVR_EN SATARDRVR_EN - @mlb_lib.MLB 17A5 17C5 SMC_EXTAL SMC_EXTAL - @mlb_lib.MLB 46C3 47B8 T29_A_BIAS T29_A_BIAS - @mlb_lib.MLB 76B3 77A8 77B3 78C6 TP_PM_SLP_A_L TP_PM_SLP_A_L - @mlb_lib.MLB 18C5
SATA_HDD1_D2R_CONN_N SATA_HDD1_D2R_CONN_N - @mlb_lib.MLB 42B5 42D7 83D3 91C7 SMC_FAN_0_CTL SMC_FAN_0_CTL - @mlb_lib.MLB 46B8 60C8 T29_A_BIAS0N T29_A_BIAS0N - @mlb_lib.MLB 76B1 77D4 TP_PM_SLP_SUS_L TP_PM_SLP_SUS_L - @mlb_lib.MLB 18B5
SATA_HDD1_D2R_CONN_P SATA_HDD1_D2R_CONN_P - @mlb_lib.MLB 42B5 42D7 83D3 91C7 SMC_FAN_0_TACH SMC_FAN_0_TACH - @mlb_lib.MLB 46A8 60C8 T29_A_BIAS0P T29_A_BIAS0P - @mlb_lib.MLB 76B1 77D4 TP_PPVOUT_PCH_DCPSUS TP_PPVOUT_PCH_DCPSUSBYP - 21D8
SATA_HDD1_D2R_DF_N SATA_HDD1_D2R_DF_N - @mlb_lib.MLB 42A7 83D3 SMC_GFX_ISENSE SMC_GFX_ISENSE - @mlb_lib.MLB 46C5 50B1 T29_A_BIAS1N T29_A_BIAS1N - @mlb_lib.MLB 76B1 78B8 BYP @mlb_lib.MLB
SATA_HDD1_D2R_DF_P SATA_HDD1_D2R_DF_P - @mlb_lib.MLB 42B7 83D3 SMC_GFX_OVERTEMP SMC_GFX_OVERTEMP - @mlb_lib.MLB 46B8 73B6 T29_A_BIAS1P T29_A_BIAS1P - @mlb_lib.MLB 76B1 78B8 TP_SPI_CS1_L TP_SPI_CS1_L - @mlb_lib.MLB 17C8
SATA_HDD1_D2R_N SATA_HDD1_D2R_N - @mlb_lib.MLB 17D5 42B8 83D3 SMC_GFX_VSENSE SMC_GFX_VSENSE - @mlb_lib.MLB 46C5 50B1 T29_A_BIAS2N T29_A_BIAS2N - @mlb_lib.MLB 76A1 77C4 TP_T29_MONDC0 TP_T29_MONDC0 - @mlb_lib.MLB 74D6
SATA_HDD1_D2R_P SATA_HDD1_D2R_P - @mlb_lib.MLB 17D5 42B8 83D3 SMC_GPU_HI_ISENSE SMC_GPU_HI_ISENSE - @mlb_lib.MLB 46A8 73B6 T29_A_BIAS2P T29_A_BIAS2P - @mlb_lib.MLB 76A1 77D4 TP_T29_MONDC1 TP_T29_MONDC1 - @mlb_lib.MLB 74D6
SATA_HDD1_R2D_CONN_N SATA_HDD1_R2D_CONN_N - @mlb_lib.MLB 42B5 42C7 83D3 91C7 SMC_KBC_MDE SMC_KBC_MDE - @mlb_lib.MLB 46D2 T29_A_HV_EN T29_A_HV_EN - @mlb_lib.MLB 77A3 78C4 TP_T29_MONOBSN TP_T29_MONOBSN - @mlb_lib.MLB 74C6
SATA_HDD1_R2D_CONN_P SATA_HDD1_R2D_CONN_P - @mlb_lib.MLB 42C5 42C7 83D3 91C7 SMC_LID SMC_LID - @mlb_lib.MLB 46B5 47C2 T29_A_HV_EN_R T29_A_HV_EN_R - @mlb_lib.MLB 77A5 TP_T29_MONOBSP TP_T29_MONOBSP - @mlb_lib.MLB 74D6
SATA_HDD1_R2D_C_N SATA_HDD1_R2D_C_N - @mlb_lib.MLB 17D5 42B8 83D3 SMC_LRESET_L SMC_LRESET_L - @mlb_lib.MLB 27C1 46C8 T29_A_LSX_P2R T29_A_LSX_P2R - @mlb_lib.MLB 77A5 TP_T29_TEST_POINT_0 TP_T29_TEST_POINT_0 - @mlb_lib.MLB 74C5
SATA_HDD1_R2D_C_P SATA_HDD1_R2D_C_P - @mlb_lib.MLB 17D5 42C8 83D3 SMC_MANUAL_RST_L SMC_MANUAL_RST_L - @mlb_lib.MLB 47D8 T29_A_LSX_R2P T29_A_LSX_R2P - @mlb_lib.MLB 77A5 TP_T29_TEST_POINT_1 TP_T29_TEST_POINT_1 - @mlb_lib.MLB 74C5
SATA_HDD1_R2D_DF_N SATA_HDD1_R2D_DF_N - @mlb_lib.MLB 42B7 83D3 SMC_MD1 SMC_MD1 - @mlb_lib.MLB 46D1 48C5 T29_A_RSVD_N T29_A_RSVD_N - @mlb_lib.MLB 77B3 TP_T29_TEST_POINT_2 TP_T29_TEST_POINT_2 - @mlb_lib.MLB 74C5
A SATA_HDD1_R2D_DF_P
SATA_HDD2_D2R_CONN_N
SATA_HDD1_R2D_DF_P - @mlb_lib.MLB
SATA_HDD2_D2R_CONN_N - @mlb_lib.MLB
42C7 83D3
42B1 42D4 83D3 91B7
SMC_NMI
SMC_ODD_DETECT
SMC_NMI - @mlb_lib.MLB
SMC_ODD_DETECT - @mlb_lib.MLB
46C1
46B8
48C3
47B2
T29_A_RSVD_P
T29_A_UC_ADDR
T29_A_RSVD_P - @mlb_lib.MLB
T29_A_UC_ADDR - @mlb_lib.MLB
77B3
77A4 77A8
TP_T29_THERMDP
TP_T29_XTAL25OUT
TP_T29_THERMDP - @mlb_lib.MLB
TP_T29_XTAL25OUT - @mlb_lib.MLB
74C5
74C3
A
SATA_HDD2_D2R_CONN_P SATA_HDD2_D2R_CONN_P - @mlb_lib.MLB 42B1 42D4 83D3 91B7 SMC_ONOFF_L SMC_ONOFF_L - @mlb_lib.MLB 45B2 46C5 T29_CLKREQ_ISOL_L T29_CLKREQ_ISOL_L - @mlb_lib.MLB 74C5 76B6 TP_USB_HUB1_OCS1 TP_USB_HUB1_OCS1 - @mlb_lib.MLB 25C4
SATA_HDD2_D2R_DF_N SATA_HDD2_D2R_DF_N - @mlb_lib.MLB 42A3 83D3 SMC_P1V5S3_ISENSE SMC_P1V5S3_ISENSE - @mlb_lib.MLB 46C5 50C5 T29_CLKREQ_L T29_CLKREQ_L - @mlb_lib.MLB 17B4 17B5 76B8 TP_USB_HUB1_OCS4 TP_USB_HUB1_OCS4 - @mlb_lib.MLB 25C4
SATA_HDD2_D2R_DF_P SATA_HDD2_D2R_DF_P - @mlb_lib.MLB 42B3 83C3 SMC_PA0_PU SMC_PA0_PU - @mlb_lib.MLB 46B8 47B2 T29_D2R1_BIASN T29_D2R1_BIASN - @mlb_lib.MLB 77B3 TP_USB_HUB1_PRTPWR1 TP_USB_HUB1_PRTPWR1 - @mlb_lib.MLB 25C4
SATA_HDD2_D2R_N SATA_HDD2_D2R_N - @mlb_lib.MLB 17D5 42B4 83D3 SMC_PB4 SMC_PB4 - @mlb_lib.MLB 46B8 47B2 T29_D2R1_BIASP T29_D2R1_BIASP - @mlb_lib.MLB 77B3 TP_USB_HUB1_PRTPWR2 TP_USB_HUB1_PRTPWR2 - @mlb_lib.MLB 25C4
SATA_HDD2_D2R_P SATA_HDD2_D2R_P - @mlb_lib.MLB 17D5 42B4 83D3 SMC_PCH1V05_ISENSE SMC_PCH1V05_ISENSE - @mlb_lib.MLB 46A8 50C5 T29_D2R_CC_N<0> T29_D2R_CC_N<0> - @mlb_lib.MLB 86A3 TP_USB_HUB1_PRTPWR3 TP_USB_HUB1_PRTPWR3 - @mlb_lib.MLB 25C4
SATA_HDD2_R2D_CONN_N SATA_HDD2_R2D_CONN_N - @mlb_lib.MLB 42B1 42C4 83D3 91B7 SMC_PME_S4_WAKE_L SMC_PME_S4_WAKE_L - @mlb_lib.MLB 46C5 47A4 47A6 T29_D2R_CC_P<0> T29_D2R_CC_P<0> - @mlb_lib.MLB 86A3 TP_USB_HUB1_PRTPWR4 TP_USB_HUB1_PRTPWR4 - @mlb_lib.MLB 25C4
SATA_HDD2_R2D_CONN_P SATA_HDD2_R2D_CONN_P - @mlb_lib.MLB 42C1 42C4 83D3 91B7 SMC_PM_G2_EN SMC_PM_G2_EN - @mlb_lib.MLB 46D5 47B2 62D8 91B5 T29_D2R_C_N<0> T29_D2R_C_N<0> - @mlb_lib.MLB 77D1 78B8 86C3 TP_USB_HUB2_OCS1 TP_USB_HUB2_OCS1 - @mlb_lib.MLB 25A4
SATA_HDD2_R2D_C_N SATA_HDD2_R2D_C_N - @mlb_lib.MLB 17D5 42B4 83D3 P5VS5_EN - @mlb_lib.MLB 61B4 62D6 T29_D2R_C_N<1> T29_D2R_C_N<1> - @mlb_lib.MLB 77D1 78B8 86C3 TP_USB_HUB2_OCS4 TP_USB_HUB2_OCS4 - @mlb_lib.MLB 25A4
SATA_HDD2_R2D_C_P SATA_HDD2_R2D_C_P - @mlb_lib.MLB 17D5 42C4 83D3 SMC_PROCHOT SMC_PROCHOT - @mlb_lib.MLB 46A5 47C1 T29_D2R_C_P<0> T29_D2R_C_P<0> - @mlb_lib.MLB 77D1 78B8 86C3 TP_USB_HUB2_PRTPWR1 TP_USB_HUB2_PRTPWR1 - @mlb_lib.MLB 25A4
SATA_HDD2_R2D_DF_N SATA_HDD2_R2D_DF_N - @mlb_lib.MLB 42B3 83C3 SMC_PROCHOT_3_3_L SMC_PROCHOT_3_3_L - @mlb_lib.MLB 46D5 47D1 T29_D2R_C_P<1> T29_D2R_C_P<1> - @mlb_lib.MLB 77D1 78B8 86C3 TP_USB_HUB2_PRTPWR2 TP_USB_HUB2_PRTPWR2 - @mlb_lib.MLB 25A4
SATA_HDD2_R2D_DF_P SATA_HDD2_R2D_DF_P - @mlb_lib.MLB 42C3 83C3 SMC_RESET_L SMC_RESET_L - @mlb_lib.MLB 46D3 47D6 48C3 T29_D2R_N<0> T29_D2R_N<0> - @mlb_lib.MLB 74A3 77D5 TP_USB_HUB2_PRTPWR3 TP_USB_HUB2_PRTPWR3 - @mlb_lib.MLB 25A4
SDCONNF_CLK SDCONNF_CLK - @mlb_lib.MLB 34C5 85C3 SMC_RUNTIME_SCI_L SMC_RUNTIME_SCI_L - @mlb_lib.MLB 20A4 20D6 46B8 T29_D2R_N<3..0> T29_D2R_N<3..0> - @mlb_lib.MLB 86C3 TP_USB_HUB2_PRTPWR4 TP_USB_HUB2_PRTPWR4 - @mlb_lib.MLB 25A4

505

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
U4600_ILIM U4600_ILIM - @mlb_lib.MLB 43C7 F @mlb_lib.MLB XDP_SEL XDP_SEL - @mlb_lib.MLB 24A8 24B1 24B8
U4601_ILIM U4601_ILIM - @mlb_lib.MLB 43D7 VREFMRGN_FRAMEBUF_EN VREFMRGN_FRAMEBUF_EN - @mlb_lib.MLB 33C5 XDP_TDI XDP_TDI - @mlb_lib.MLB 24B8 24C4 81D1
U5900_GAIN U5900_GAIN - @mlb_lib.MLB 56B4 VREFMRGN_MEMVREG_BUF VREFMRGN_MEMVREG_BUF - @mlb_lib.MLB 33B3 XDP_TDO XDP_TDO - @mlb_lib.MLB 24A8 24C4 81D1
USB_BT_CONN_N USB_BT_CONN_N - @mlb_lib.MLB 35C6 83B3 91D7 VREFMRGN_MEMVREG_EN VREFMRGN_MEMVREG_EN - @mlb_lib.MLB 33C5 XDP_TMS XDP_TMS - @mlb_lib.MLB 24A4 24C4 81D1
USB_BT_CONN_P USB_BT_CONN_P - @mlb_lib.MLB 35C6 83B3 91D7 VREFMRGN_MEMVREG_FBV VREFMRGN_MEMVREG_FBVREF - 33D5 XDP_VR_READY XDP_VR_READY - @mlb_lib.MLB 24C7 81C1
USB_BT_N USB_BT_N - @mlb_lib.MLB 25B4 35C4 83B3 REF @mlb_lib.MLB
USB_BT_P USB_BT_P - @mlb_lib.MLB 25B4 35C4 83B3 VREFMRGN_SODIMMA_DQ VREFMRGN_SODIMMA_DQ - @mlb_lib.MLB 33D5
USB_B_MUXED_N USB_B_MUXED_N - @mlb_lib.MLB 43D3 83B3 VREFMRGN_SODIMMB_DQ VREFMRGN_SODIMMB_DQ - @mlb_lib.MLB 33D5
USB_B_MUXED_P USB_B_MUXED_P - @mlb_lib.MLB 43D3 83B3 VREFMRGN_SODIMMS_CA VREFMRGN_SODIMMS_CA - @mlb_lib.MLB 33D5
USB_DEBUGPRT_EN_L USB_DEBUGPRT_EN_L - @mlb_lib.MLB 43C3 46B8 VRT29_VIN VRT29_VIN - @mlb_lib.MLB 78D8
USB_EXTA_N USB_EXTA_N - @mlb_lib.MLB 25A4 43A6 83C3 VR_AXG_BOOT1_RC VR_AXG_BOOT1_RC - @mlb_lib.MLB 69C6
USB_EXTA_OC_L USB_EXTA_OC_L - @mlb_lib.MLB 25A4 43C8 VR_AXG_COMP VR_AXG_COMP - @mlb_lib.MLB 67C5
USB_EXTA_P USB_EXTA_P - @mlb_lib.MLB 25A4 43A6 83C3 VR_AXG_COMP_RC VR_AXG_COMP_RC - @mlb_lib.MLB 67C7
USB_EXTB_N USB_EXTB_N - @mlb_lib.MLB 25C4 43D5 83B3 VR_AXG_DRV1_BOOT VR_AXG_DRV1_BOOT - @mlb_lib.MLB 69C7

D USB_EXTB_OC_L
USB_EXTB_P
USB_EXTB_OC_L - @mlb_lib.MLB
USB_EXTB_P - @mlb_lib.MLB
25C4
25C4
43D8
43D5 83B3
VR_AXG_DRV1_LGATE
VR_AXG_DRV1_PVCC
VR_AXG_DRV1_LGATE - @mlb_lib.MLB
VR_AXG_DRV1_PVCC - @mlb_lib.MLB
69C7
69C7
D
USB_EXTC_N USB_EXTC_N - @mlb_lib.MLB 25C4 43C3 83B3 VR_AXG_DRV1_UGATE VR_AXG_DRV1_UGATE - @mlb_lib.MLB 69C7
USB_EXTC_OC_L USB_EXTC_OC_L - @mlb_lib.MLB 25C4 43D8 VR_AXG_FB VR_AXG_FB - @mlb_lib.MLB 67C4
USB_EXTC_P USB_EXTC_P - @mlb_lib.MLB 25C4 43B3 83B3 VR_AXG_HFREQ_COMP VR_AXG_HFREQ_COMP - @mlb_lib.MLB 67C5
USB_EXTD_N USB_EXTD_N - @mlb_lib.MLB 25B4 43B6 83B3 VR_AXG_IMON VR_AXG_IMON - @mlb_lib.MLB 50B4 67B1
USB_EXTD_OC_L USB_EXTD_OC_L - @mlb_lib.MLB 25A4 43B8 VR_AXG_ISNS_N VR_AXG_ISNS_N - @mlb_lib.MLB 67C1 69B2
USB_EXTD_P USB_EXTD_P - @mlb_lib.MLB 25A4 43B6 83B3 VR_AXG_ISNS_N_R VR_AXG_ISNS_N_R - @mlb_lib.MLB 69C4
USB_HUB1_CFG_SEL0 USB_HUB1_CFG_SEL0 - @mlb_lib.MLB 25C6 VR_AXG_ISNS_P VR_AXG_ISNS_P - @mlb_lib.MLB 67C1 69C2
USB_HUB1_CFG_SEL1 USB_HUB1_CFG_SEL1 - @mlb_lib.MLB 25C6 VR_AXG_ISNS_RP VR_AXG_ISNS_RP - @mlb_lib.MLB 67C3
USB_HUB1_NONREM0 USB_HUB1_NONREM0 - @mlb_lib.MLB 25C6 VR_AXG_PH1_SNUB VR_AXG_PH1_SNUB - @mlb_lib.MLB 69C4
USB_HUB1_NONREM1 USB_HUB1_NONREM1 - @mlb_lib.MLB 25C6 VR_AXG_PHASE1 VR_AXG_PHASE1 - @mlb_lib.MLB 69C7
USB_HUB1_RBIAS USB_HUB1_RBIAS - @mlb_lib.MLB 25C5 VR_AXG_PWM VR_AXG_PWM - @mlb_lib.MLB 67D1 69C8
USB_HUB1_TEST USB_HUB1_TEST - @mlb_lib.MLB 25C6 VR_AXG_RGND VR_AXG_RGND - @mlb_lib.MLB 67C5
USB_HUB1_UP_N USB_HUB1_UP_N - @mlb_lib.MLB 19D3 25C4 83C3 VR_AXG_SW_FREQ VR_AXG_SW_FREQ - @mlb_lib.MLB 67B3
USB_HUB1_UP_P USB_HUB1_UP_P - @mlb_lib.MLB 19D3 25C4 83C3 VR_AXG_TCOMP VR_AXG_TCOMP - @mlb_lib.MLB 67C4
USB_HUB1_VBUS_DET USB_HUB1_VBUS_DET - @mlb_lib.MLB 25C5 VR_AXG_TM VR_AXG_TM - @mlb_lib.MLB 67D4
USB_HUB1_XTAL1 USB_HUB1_XTAL1 - @mlb_lib.MLB 25C6 VR_AXG_TMN VR_AXG_TMN - @mlb_lib.MLB 67C5
USB_HUB1_XTAL2 USB_HUB1_XTAL2 - @mlb_lib.MLB 25C6 VR_AXG_VSEN VR_AXG_VSEN - @mlb_lib.MLB 67C5
USB_HUB2_CFG_SEL0 USB_HUB2_CFG_SEL0 - @mlb_lib.MLB 25A6 VR_AXG_VSNS_R_N VR_AXG_VSNS_R_N - @mlb_lib.MLB 67D7
USB_HUB2_CFG_SEL1 USB_HUB2_CFG_SEL1 - @mlb_lib.MLB 25A6 VR_AXG_VSNS_R_P VR_AXG_VSNS_R_P - @mlb_lib.MLB 67D7
USB_HUB2_NONREM0 USB_HUB2_NONREM0 - @mlb_lib.MLB 25A6 VR_AXG_VSNS_XW_N VR_AXG_VSNS_XW_N - @mlb_lib.MLB 67D7
USB_HUB2_NONREM1 USB_HUB2_NONREM1 - @mlb_lib.MLB 25A6 VR_AXG_VSNS_XW_P VR_AXG_VSNS_XW_P - @mlb_lib.MLB 67D8
USB_HUB2_RBIAS USB_HUB2_RBIAS - @mlb_lib.MLB 25A5 VR_CPU_BOOT1_RC VR_CPU_BOOT1_RC - @mlb_lib.MLB 68D6
USB_HUB2_TEST USB_HUB2_TEST - @mlb_lib.MLB 25B6 VR_CPU_BOOT2_RC VR_CPU_BOOT2_RC - @mlb_lib.MLB 68C6
USB_HUB2_UP_N USB_HUB2_UP_N - @mlb_lib.MLB 19D3 25A4 83C3 VR_CPU_COMP VR_CPU_COMP - @mlb_lib.MLB 67B5
USB_HUB2_UP_P USB_HUB2_UP_P - @mlb_lib.MLB 19C3 25A4 83C3 VR_CPU_DRV1_BOOT VR_CPU_DRV1_BOOT - @mlb_lib.MLB 68D7
USB_HUB2_VBUS_DET USB_HUB2_VBUS_DET - @mlb_lib.MLB 25A5 VR_CPU_DRV1_LGATE VR_CPU_DRV1_LGATE - @mlb_lib.MLB 68D7
USB_HUB2_XTAL1 USB_HUB2_XTAL1 - @mlb_lib.MLB 25B6 VR_CPU_DRV1_PVCC VR_CPU_DRV1_PVCC - @mlb_lib.MLB 68D7
USB_HUB2_XTAL2 USB_HUB2_XTAL2 - @mlb_lib.MLB 25A6 VR_CPU_DRV1_UGATE VR_CPU_DRV1_UGATE - @mlb_lib.MLB 68D7
USB_HUB_RESET USB_HUB_RESET - @mlb_lib.MLB 25B2 VR_CPU_DRV2_BOOT VR_CPU_DRV2_BOOT - @mlb_lib.MLB 68C7
USB_HUB_RESET_L USB_HUB_RESET_L - @mlb_lib.MLB 25B1 25B6 25C6 VR_CPU_DRV2_LGATE VR_CPU_DRV2_LGATE - @mlb_lib.MLB 68B7

C USB_HUB_SOFT_RESET_L
USB_IR_N
USB_HUB_SOFT_RESET_L - @mlb_lib.MLB
USB_IR_N - @mlb_lib.MLB
19C1
25C4
24D4
44C3
25B2
83B3
VR_CPU_DRV2_UGATE
VR_CPU_DRV2_VCC
VR_CPU_DRV2_UGATE - @mlb_lib.MLB
VR_CPU_DRV2_VCC - @mlb_lib.MLB
68C7
68C7
C
USB_IR_P USB_IR_P - @mlb_lib.MLB 25C4 44C3 83B3 VR_CPU_FB VR_CPU_FB - @mlb_lib.MLB 67B5
USB_IR_R_N USB_IR_R_N - @mlb_lib.MLB 44C4 83B3 VR_CPU_FB2 VR_CPU_FB2 - @mlb_lib.MLB 67B8
USB_IR_R_P USB_IR_R_P - @mlb_lib.MLB 44C4 83B3 VR_CPU_FB_RC VR_CPU_FB_RC - @mlb_lib.MLB 67C8
USB_PORT0_N USB_PORT0_N - @mlb_lib.MLB 43A4 83B3 VR_CPU_FDVID VR_CPU_FDVID - @mlb_lib.MLB 67C5
USB_PORT0_P USB_PORT0_P - @mlb_lib.MLB 43A4 83B3 VR_CPU_HFREQ_COMP VR_CPU_HFREQ_COMP - @mlb_lib.MLB 67B5
USB_PORT1_N USB_PORT1_N - @mlb_lib.MLB 43B5 83B3 VR_CPU_IAUTO VR_CPU_IAUTO - @mlb_lib.MLB 67B5
USB_PORT1_P USB_PORT1_P - @mlb_lib.MLB 43B5 83B3 VR_CPU_IMON VR_CPU_IMON - @mlb_lib.MLB 50D4 67B5

www.teknisi-indonesia.com
USB_PORT2_N USB_PORT2_N - @mlb_lib.MLB 43C2 83B3 VR_CPU_ISNS1_N VR_CPU_ISNS1_N - @mlb_lib.MLB 67C1 68C2
USB_PORT2_P USB_PORT2_P - @mlb_lib.MLB 43B2 83B3 VR_CPU_ISNS1_N_R VR_CPU_ISNS1_N_R - @mlb_lib.MLB 68D3
USB_PORT3_N USB_PORT3_N - @mlb_lib.MLB 43D2 83B3 VR_CPU_ISNS1_P VR_CPU_ISNS1_P - @mlb_lib.MLB 67C1 68D2
USB_PORT3_P USB_PORT3_P - @mlb_lib.MLB 43D2 83B3 VR_CPU_ISNS2_N VR_CPU_ISNS2_N - @mlb_lib.MLB 67C1 68B2
USB_PWR_EN USB_PWR_EN - @mlb_lib.MLB 43C8 62D1 VR_CPU_ISNS2_N_R VR_CPU_ISNS2_N_R - @mlb_lib.MLB 68C3
VBIAS_DAC VBIAS_DAC - @mlb_lib.MLB 53D5 VR_CPU_ISNS2_P VR_CPU_ISNS2_P - @mlb_lib.MLB 67C1 68C2
VCCSAS0_AGND VCCSAS0_AGND - @mlb_lib.MLB 64B6 VR_CPU_N_PSI VR_CPU_N_PSI - @mlb_lib.MLB 67C5
VCCSAS0_BOOT_RC VCCSAS0_BOOT_RC - @mlb_lib.MLB 64C5 VR_CPU_PH1_SNUB VR_CPU_PH1_SNUB - @mlb_lib.MLB 68D4
VCCSAS0_CS_N VCCSAS0_CS_N - @mlb_lib.MLB 50A8 64B2 89D3 VR_CPU_PH2_SNUB VR_CPU_PH2_SNUB - @mlb_lib.MLB 68C4
VCCSAS0_CS_P VCCSAS0_CS_P - @mlb_lib.MLB 50A8 64B2 89D3 VR_CPU_PHASE1 VR_CPU_PHASE1 - @mlb_lib.MLB 68D7
VCCSAS0_DRVH VCCSAS0_DRVH - @mlb_lib.MLB 64C5 VR_CPU_PHASE2 VR_CPU_PHASE2 - @mlb_lib.MLB 68C7
VCCSAS0_DRVL VCCSAS0_DRVL - @mlb_lib.MLB 64C5 VR_CPU_PSICOMP VR_CPU_PSICOMP - @mlb_lib.MLB 67B5
VCCSAS0_FB VCCSAS0_FB - @mlb_lib.MLB 64C6 VR_CPU_PSICOMP1 VR_CPU_PSICOMP1 - @mlb_lib.MLB 67C8
VCCSAS0_FSEL VCCSAS0_FSEL - @mlb_lib.MLB 64B6 VR_CPU_PWM1 VR_CPU_PWM1 - @mlb_lib.MLB 67C1 68D8
VCCSAS0_LL VCCSAS0_LL - @mlb_lib.MLB 64C5 VR_CPU_PWM2 VR_CPU_PWM2 - @mlb_lib.MLB 67C1 68C8
VCCSAS0_OCSET VCCSAS0_OCSET - @mlb_lib.MLB 64C6 VR_CPU_PWM3 VR_CPU_PWM3 - @mlb_lib.MLB 67C3
VCCSAS0_SET0 VCCSAS0_SET0 - @mlb_lib.MLB 64B6 VR_CPU_PWM4 VR_CPU_PWM4 - @mlb_lib.MLB 67C3
VCCSAS0_SET1 VCCSAS0_SET1 - @mlb_lib.MLB 64B6 VR_CPU_RAMP_ADJ VR_CPU_RAMP_ADJ - @mlb_lib.MLB 67B3
VCCSAS0_SNUB VCCSAS0_SNUB - @mlb_lib.MLB 64C3 VR_CPU_RGND VR_CPU_RGND - @mlb_lib.MLB 67A7
VCCSAS0_SREF VCCSAS0_SREF - @mlb_lib.MLB 64C6 VR_CPU_SUTH VR_CPU_SUTH - @mlb_lib.MLB 67C5
VCCSAS0_VBST VCCSAS0_VBST - @mlb_lib.MLB 64C5 VR_CPU_SW_FREQ VR_CPU_SW_FREQ - @mlb_lib.MLB 67B3
VCCSAS0_VO VCCSAS0_VO - @mlb_lib.MLB 64C6 VR_CPU_TM VR_CPU_TM - @mlb_lib.MLB 67B5
VCCSAVSENSE_IN VCCSAVSENSE_IN - @mlb_lib.MLB 50A7 VR_CPU_TMN VR_CPU_TMN - @mlb_lib.MLB 67A7

B VCCSA_IOUT
VDDQ_IOUT
VCCSA_IOUT - @mlb_lib.MLB
VDDQ_IOUT - @mlb_lib.MLB
50A7
50D6
VR_CPU_VSEN
VR_CPU_VSNS_R_N
VR_CPU_VSEN - @mlb_lib.MLB
VR_CPU_VSNS_R_N - @mlb_lib.MLB
67A6
67A7 B
VDD_1V5S0 VDD_1V5S0 - @mlb_lib.MLB 71B7 VR_CPU_VSNS_R_P VR_CPU_VSNS_R_P - @mlb_lib.MLB 67A7
VMON_3V3_DIV VMON_3V3_DIV - @mlb_lib.MLB 62C8 VR_CPU_VSNS_XW_N VR_CPU_VSNS_XW_N - @mlb_lib.MLB 67A8
VMON_Q2_BASE VMON_Q2_BASE - @mlb_lib.MLB 62C7 VR_CPU_VSNS_XW_P VR_CPU_VSNS_XW_P - @mlb_lib.MLB 67A8
VMON_Q3_BASE VMON_Q3_BASE - @mlb_lib.MLB 62C7 VR_EN_PWR_OVP VR_EN_PWR_OVP - @mlb_lib.MLB 67B3
VMON_Q4_BASE VMON_Q4_BASE - @mlb_lib.MLB 62B7 VR_HOT_L VR_HOT_L - @mlb_lib.MLB 67B5
VR3V3_G3H_BST VR3V3_G3H_BST - @mlb_lib.MLB 65D5 VR_RSET VR_RSET - @mlb_lib.MLB 67B4
VR3V3_G3H_EN VR3V3_G3H_EN - @mlb_lib.MLB 65D6 VR_SEN_R2 VR_SEN_R2 - @mlb_lib.MLB 67D7
VR3V3_G3H_ENL VR3V3_G3H_ENL - @mlb_lib.MLB 65C5 VTTCLAMP_EN VTTCLAMP_EN - @mlb_lib.MLB 28B3
VR3V3_G3H_FB VR3V3_G3H_FB - @mlb_lib.MLB 65C6 VTTCLAMP_L VTTCLAMP_L - @mlb_lib.MLB 28B2
VR3V3_G3H_ILIM VR3V3_G3H_ILIM - @mlb_lib.MLB 65C5 WIFI_EVENT_L WIFI_EVENT_L - @mlb_lib.MLB 46B8 47A2
VR3V3_G3H_LXS VR3V3_G3H_LXS - @mlb_lib.MLB 65C4 WIFI_PROX_THRM_N WIFI_PROX_THRM_N - @mlb_lib.MLB 52C3 52D8
VR3V3_G3H_SW VR3V3_G3H_SW - @mlb_lib.MLB 65C5 WIFI_PROX_THRM_P WIFI_PROX_THRM_P - @mlb_lib.MLB 52C3 52D8
VR3V3_G3H_TON VR3V3_G3H_TON - @mlb_lib.MLB 65C6 WLAN_THROTTLE_L WLAN_THROTTLE_L - @mlb_lib.MLB 35D7 91D7
VR3V3_G3H_V5V VR3V3_G3H_V5V - @mlb_lib.MLB 65D6 WOL_EN WOL_EN - @mlb_lib.MLB 20B8 20C6 62A4
VR3V3_G3H_VSEN VR3V3_G3H_VSEN - @mlb_lib.MLB 65C5 XDP_BPM_L<0> XDP_BPM_L<0> - @mlb_lib.MLB 11B2 24D7
VR5V_G3H_SW VR5V_G3H_SW - @mlb_lib.MLB 65B5 XDP_BPM_L<3..0> XDP_BPM_L<3..0> - @mlb_lib.MLB 81D1
VR5V_G3H_VCC VR5V_G3H_VCC - @mlb_lib.MLB 65B5 XDP_BPM_L<1> XDP_BPM_L<1> - @mlb_lib.MLB 11B2 24D7
VR5V_S4_BOOT VR5V_S4_BOOT - @mlb_lib.MLB 65B5 XDP_BPM_L<2> XDP_BPM_L<2> - @mlb_lib.MLB 11B2 24D7
VR5V_S4_COMP VR5V_S4_COMP - @mlb_lib.MLB 65A5 XDP_BPM_L<3> XDP_BPM_L<3> - @mlb_lib.MLB 11B2 24D7
VR5V_S4_COMP_RC VR5V_S4_COMP_RC - @mlb_lib.MLB 65A5 XDP_BPM_L<4> XDP_BPM_L<4> - @mlb_lib.MLB 11B2 24C7
VR5V_S4_EN_IC VR5V_S4_EN_IC - @mlb_lib.MLB 65B6 XDP_BPM_L<7..4> XDP_BPM_L<7..4> - @mlb_lib.MLB 81D1
VR5V_S4_FB VR5V_S4_FB - @mlb_lib.MLB 65A5 XDP_BPM_L<5> XDP_BPM_L<5> - @mlb_lib.MLB 11B2 24C7
VR5V_S4_FB_RC VR5V_S4_FB_RC - @mlb_lib.MLB 65A4 XDP_BPM_L<6> XDP_BPM_L<6> - @mlb_lib.MLB 11B2 24C7
VR5V_S4_FB_SNS VR5V_S4_FB_SNS - @mlb_lib.MLB 65A3 XDP_BPM_L<7> XDP_BPM_L<7> - @mlb_lib.MLB 11B2 24C7
VR5V_S4_OCSET VR5V_S4_OCSET - @mlb_lib.MLB 65A5 XDP_CPURST_L XDP_CPURST_L - @mlb_lib.MLB 24C5 81D1
VR5V_S4_RT VR5V_S4_RT - @mlb_lib.MLB 65A6 XDP_CPU_CFG<0> XDP_CPU_CFG<0> - @mlb_lib.MLB 24C7 81D1
VR5V_S4_SS VR5V_S4_SS - @mlb_lib.MLB 65A6 XDP_CPU_CLK100M_N XDP_CPU_CLK100M_N - @mlb_lib.MLB 24C5 81C1
VREFMRGN_CA_SODIMMA_ VREFMRGN_CA_SODIMMA_BUF - 33C3 XDP_CPU_CLK100M_P XDP_CPU_CLK100M_P - @mlb_lib.MLB 24C5 81C1
BUF @mlb_lib.MLB XDP_CPU_PRDY_L XDP_CPU_PRDY_L - @mlb_lib.MLB 11C2 24D7 81D1
VREFMRGN_CA_SODIMMA_ VREFMRGN_CA_SODIMMA_EN - 33C5 XDP_CPU_PREQ_L XDP_CPU_PREQ_L - @mlb_lib.MLB 11C2 24D7 81D1
A EN
VREFMRGN_CA_SODIMMB_
@mlb_lib.MLB
VREFMRGN_CA_SODIMMB_BUF - 33B3
XDP_CPU_PWRBTN_L
XDP_CPU_PWRGD
XDP_CPU_PWRBTN_L - @mlb_lib.MLB
XDP_CPU_PWRGD - @mlb_lib.MLB
24C7
24C7
81C1
81C1
A
BUF @mlb_lib.MLB XDP_CPU_TCK XDP_CPU_TCK - @mlb_lib.MLB 11C2 24A8 24C7 24D2 81D1
VREFMRGN_CA_SODIMMB_ VREFMRGN_CA_SODIMMB_EN - 33C5 XDP_CPU_TDI XDP_CPU_TDI - @mlb_lib.MLB 11C2 24B6 24D2 81D1
EN @mlb_lib.MLB XDP_CPU_TDO XDP_CPU_TDO - @mlb_lib.MLB 11C2 24A6 24D2 81D1
VREFMRGN_DQ_SODIMMA_ VREFMRGN_DQ_SODIMMA_BUF - 33D3 XDP_CPU_TMS XDP_CPU_TMS - @mlb_lib.MLB 11C2 24A6 24D2 81D1
BUF @mlb_lib.MLB XDP_CPU_TRST_L XDP_CPU_TRST_L - @mlb_lib.MLB 11C2 24C4 24D2 81D1
VREFMRGN_DQ_SODIMMA_ VREFMRGN_DQ_SODIMMA_EN - 33C5 XDP_DBRESET_L XDP_DBRESET_L - @mlb_lib.MLB 11C2 24C4 27A4 81C1
EN @mlb_lib.MLB XDP_PCH_TCK XDP_PCH_TCK - @mlb_lib.MLB 17C8 24A4 24A8 24C7 81D1
VREFMRGN_DQ_SODIMMB_ VREFMRGN_DQ_SODIMMB_BUF - 33C3 XDP_PCH_TDI XDP_PCH_TDI - @mlb_lib.MLB 17C8 24A4 24B6 81D1
BUF @mlb_lib.MLB XDP_PCH_TDO XDP_PCH_TDO - @mlb_lib.MLB 17C8 24A4 24B6 81D1
VREFMRGN_DQ_SODIMMB_ VREFMRGN_DQ_SODIMMB_EN - 33C5 XDP_PCH_TMS XDP_PCH_TMS - @mlb_lib.MLB 17C8 24A4 24B6 81D1
EN @mlb_lib.MLB XDP_PRESENT_L XDP_PRESENT_L - @mlb_lib.MLB 24B2 24C4 81C1
VREFMRGN_FRAMEBUF_BU VREFMRGN_FRAMEBUF_BUF - 33B4 XDP_RES_RL XDP_RES_RL - @mlb_lib.MLB 24C2 81C1

506

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Title: Cref Part Report C1698 CAP_402-1 mlb[15B7] C2485 CAP_402 mlb[23A6] C3515 CAP_402 mlb[34C8]
Design: mlb C1699 CAP_402-1 mlb[15B7] C2486 CAP_402 mlb[23A6] C3516 CAP_402 mlb[34C8]
Date: Apr 7 18:57:22 2011 C1700 CAP_402-1 mlb[16D7] C2491 CAP_P_CASE-B2-SM1 mlb[23B4] C3517 CAP_402 mlb[34C8]
C1701 CAP_402-1 mlb[16D7] C2492 CAP_402-1 mlb[23B4] C3518 CAP_402 mlb[34C8]
C1702 CAP_402-1 mlb[16D6] C2493 CAP_P_CASE-B2-SM1 mlb[23A4] C3519 CAP_402 mlb[34C8]
C160X CAP_402-1 mlb[15B2] C1703 CAP_402-1 mlb[16D6] C2494 CAP_402-1 mlb[23A4] C3520 CAP_402 mlb[34C8]
C160Y CAP_402-1 mlb[15B2] C1704 CAP_402-1 mlb[16D6] C2496 CAP_402-1 mlb[23B2] C3521 CAP_402 mlb[34C8]
C160Z CAP_P_CASE-B4-SM mlb[15B2] C1705 CAP_402-1 mlb[16D5] C2499 CAP_402 mlb[23C3] C3530 CAP_402-1 mlb[34B4]
C161A CAP_402-1 mlb[15B5] C1706 CAP_402-1 mlb[16D5] C2500 CAP_402 mlb[24C6] C3535 CAP_402-1 mlb[34B4]
C161B CAP_402-1 mlb[15B4] C1707 CAP_402-1 mlb[16D5] C2501 CAP_402 mlb[24C5] C3541 CAP_402 mlb[34C6]
C161C CAP_402-1 mlb[15B4] C1708 CAP_402-1 mlb[16D4] C2557 CAP_402 mlb[24B3] C3542 CAP_402 mlb[34C7]
C161D CAP_402-1 mlb[15B4] C1709 CAP_402-1 mlb[16D4] C2602 CAP_603 mlb[25D7] C3550 CAP_402 mlb[34C3]
C161E CAP_603 mlb[15A7] C1710 CAP_402-1 mlb[16D4] C2603 CAP_402 mlb[25D6] C3551 CAP_402 mlb[34C4]
C161F CAP_0402-1 mlb[15A7] C1711 CAP_0402-1 mlb[16D7] C2607 CAP_603 mlb[25D7] C3620 CAP_0805 mlb[35B5]

D C162A
C162B
CAP_0402-1
CAP_0402-1
mlb[15A7]
mlb[15A6]
C1712
C1713
CAP_0402-1
CAP_0402-1
mlb[16D7]
mlb[16D6]
C2608
C2609
CAP_402
CAP_402
mlb[25D6]
mlb[25D6]
C3621
C3622
CAP_402
CAP_402
mlb[35B5]
mlb[35B7]
D
C162C CAP_0402-1 mlb[15A6] C1714 CAP_0402-1 mlb[16D6] C2610 CAP_402 mlb[25D6] C3623 CAP_402 mlb[35B6]
C162D CAP_0402-1 mlb[15A6] C1715 CAP_0402-1 mlb[16D6] C2611 CAP_402 mlb[25D6] C3624 CAP_402-1 mlb[35B6]
C162E CAP_0402-1 mlb[15A6] C1716 CAP_0402-1 mlb[16D5] C2612 CAP_402 mlb[25D6] C3630 CAP_402 mlb[35C5]
C167A CAP_0402-1 mlb[15A5] C1717 CAP_0603 mlb[16C7] C2615 CAP_402 mlb[25D4] C3631 CAP_402 mlb[35C5]
C167B CAP_0402-1 mlb[15A5] C1718 CAP_0603 mlb[16C7] C2616 CAP_402 mlb[25D4] C3632 CAP_402 mlb[35C6]
C167C CAP_0402-1 mlb[15A5] C1719 CAP_0603 mlb[16C6] C2617 CAP_402 mlb[25D4] C3633 CAP_402-1 mlb[35C6]
C167F CAP_402-1 mlb[15A7] C1720 CAP_0603 mlb[16C6] C2618 CAP_402 mlb[25D4] C3640 CAP_402 mlb[35B3]
C169A CAP_402-1 mlb[15B6] C1721 CAP_0603 mlb[16C6] C2619 CAP_402 mlb[25D7] C3650 CAP_402 mlb[35C3]
C169B CAP_402-1 mlb[15B6] C1722 CAP_0603 mlb[16C5] C2620 CAP_402 mlb[25D7] C3651 CAP_402 mlb[35C2]
C169C CAP_402-1 mlb[15B6] C1738 CAP_402-1 mlb[16B7] C2640 CAP_402 mlb[25B2] C3800 CAP_402 mlb[36D5]
C169D CAP_402-1 mlb[15B6] C1739 CAP_402-1 mlb[16B7] C2641 CAP_402 mlb[25B2] C3801 CAP_402 mlb[36D4]
C169E CAP_402-1 mlb[15B5] C1740 CAP_402-1 mlb[16B6] C2652 CAP_603 mlb[25B7] C3802 CAP_402 mlb[36D4]
C169F CAP_402-1 mlb[15B5] C1741 CAP_402-1 mlb[16B6] C2653 CAP_402 mlb[25B7] C3803 CAP_402 mlb[36D4]
C1330 CAP_402 mlb[13B1] C1742 CAP_402-1 mlb[16B6] C2657 CAP_603 mlb[25B7] C3810 CAP_1206 mlb[36B3]
C1600 CAP_402-LF mlb[15D7] C1743 CAP_402-1 mlb[16B5] C2658 CAP_402 mlb[25B6] C3900 CAP_402 mlb[37D6]
C1601 CAP_402-LF mlb[15D7] C1744 CAP_402-1 mlb[16B5] C2659 CAP_402 mlb[25B6] C3905 CAP_402 mlb[37D6]
C1602 CAP_402-LF mlb[15D7] C1745 CAP_402-1 mlb[16B5] C2660 CAP_402 mlb[25B6] C3910 CAP_402 mlb[37C6]
C1603 CAP_402-LF mlb[15D6] C1746 CAP_402-1 mlb[16B4] C2661 CAP_402 mlb[25B6] C3911 CAP_402 mlb[37C5]
C1604 CAP_402-LF mlb[15D6] C1747 CAP_402-1 mlb[16B4] C2662 CAP_402 mlb[25B6] C3915 CAP_603 mlb[37C5]
C1605 CAP_402-LF mlb[15D6] C1748 CAP_0402-1 mlb[16B7] C2665 CAP_402 mlb[25B4] C3916 CAP_402 mlb[37C5]
C1606 CAP_402-LF mlb[15D6] C1749 CAP_0402-1 mlb[16B7] C2666 CAP_402 mlb[25B4] C3920 CAP_603 mlb[37D3]
C1607 CAP_402-LF mlb[15D5] C1750 CAP_603 mlb[16B6] C2667 CAP_402 mlb[25B4] C3921 CAP_402 mlb[37D4]
C1608 CAP_402-LF mlb[15D5] C1751 CAP_0402-1 mlb[16B6] C2668 CAP_402 mlb[25B4] C3925 CAP_603 mlb[37D3]
C1609 CAP_402-LF mlb[15D5] C1752 CAP_0402-1 mlb[16B6] C2669 CAP_402 mlb[25B7] C3926 CAP_402 mlb[37D4]
C1610 CAP_402-LF mlb[15D5] C1753 CAP_0402-1 mlb[16B5] C2670 CAP_402 mlb[25B7] C3930 CAP_603 mlb[37C3]
C1611 CAP_402-LF mlb[15D4] C1754 CAP_603 mlb[16B5] C2702 CAP_402-1 mlb[26D6] C3931 CAP_402 mlb[37C4]
C1612 CAP_402-LF mlb[15D4] C1755 CAP_0402-1 mlb[16B5] C2705 CAP_402 mlb[26C7] C3935 CAP_0805 mlb[37C3]
C1613 CAP_402-LF mlb[15D4] C1756 CAP_P_CASE-B4-SM mlb[16B7] C2706 CAP_402 mlb[26C7] C3936 CAP_402 mlb[37C3]
C1614 CAP_402-LF mlb[15D4] C1757 CAP_402-1 mlb[16A6] C2720 CAP_402 mlb[26D6] C3950 CAP_402 mlb[37C7]
C1615 CAP_402-LF mlb[15D3] C1758 CAP_402-1 mlb[16B3] C2722 CAP_402 mlb[26D6] C3951 CAP_402 mlb[37C7]

C C1616
C1617
CAP_402-LF
CAP_402-LF
mlb[15D3]
mlb[15D3]
C1759
C1760
CAP_402-1
CAP_402-1
mlb[16B3]
mlb[16B2]
C2724
C2810
CAP_402
CAP_402
mlb[26D6]
mlb[27C6]
C3955
C3956
CAP_402
CAP_402
mlb[37C7]
mlb[37B7]
C
C1618 CAP_402-LF mlb[15D2] C1761 CAP_402-1 mlb[16B2] C2811 CAP_402 mlb[27C6] C3970 CAP_603 mlb[37C2]
C1619 CAP_402-LF mlb[15D2] C1762 CAP_402-1 mlb[16B2] C2840 CAP_402 mlb[27C3] C3971 CAP_402 mlb[37C2]
C1620 CAP_402-LF mlb[15D2] C1763 CAP_0402-1 mlb[16B3] C2850 CAP_402 mlb[27A7] C3972 CAP_402 mlb[37C2]
C1621 CAP_402-LF mlb[15D2] C1764 CAP_0402-1 mlb[16B3] C2860 CAP_402 mlb[27A6] C3990 CAP_402 mlb[37A7]
C1622 CAP_402-LF mlb[15D1] C1765 CAP_0402-1 mlb[16B2] C2880 CAP_402 mlb[27B3] C4020 CAP_603 mlb[38D7]
C1623 CAP_402-LF mlb[15D1] C1766 CAP_0402-1 mlb[16B2] C2916 CAP_402 mlb[28B5] C4021 CAP_402 mlb[38D7]
C1624 CAP_402-LF mlb[15D1] C1767 CAP_0402-1 mlb[16B2] C2920 CAP_402 mlb[28C3] C4025 CAP_603 mlb[38C6]

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C1625 CAP_402-LF mlb[15D7] C1768 CAP_P_CASE-B4-SM mlb[16B3] C2951 CAP_402 mlb[28B3] C4026 CAP_402 mlb[38C6]
C1626 CAP_402-LF mlb[15D7] C1770 CAP_201 mlb[16D3] C3100 CAP_603 mlb[30D3] C4100 CAP_402-1 mlb[39D7]
C1627 CAP_402-LF mlb[15D7] C1771 CAP_201 mlb[16D3] C3101 CAP_603 mlb[30D3] C4101 CAP_402-1 mlb[39D7]
C1628 CAP_402-LF mlb[15D6] C1772 CAP_201 mlb[16D3] C3110 CAP_402 mlb[30D3] C4102 CAP_402-1 mlb[39D6]
C1629 CAP_402-LF mlb[15D6] C1773 CAP_201 mlb[16D2] C3111 CAP_402 mlb[30D3] C4103 CAP_402-1 mlb[39D6]
C1630 CAP_402-LF mlb[15D6] C1774 CAP_201 mlb[16D2] C3112 CAP_402 mlb[30D2] C4104 CAP_402-1 mlb[39D6]
C1631 CAP_402-LF mlb[15D6] C1775 CAP_201 mlb[16D2] C3113 CAP_402 mlb[30D2] C4105 CAP_402-1 mlb[39D6]
C1632 CAP_402-LF mlb[15D5] C1776 CAP_201 mlb[16D3] C3114 CAP_402 mlb[30D2] C4106 CAP_402-1 mlb[39D6]
C1633 CAP_402-LF mlb[15D5] C1777 CAP_201 mlb[16D3] C3115 CAP_402 mlb[30D1] C4107 CAP_402-1 mlb[39D6]
C1634 CAP_402-LF mlb[15D5] C1778 CAP_201 mlb[16D3] C3116 CAP_402 mlb[30D1] C4108 CAP_402-1 mlb[39D6]
C1635 CAP_402-LF mlb[15D5] C1779 CAP_201 mlb[16D2] C3117 CAP_402 mlb[30D1] C4110 CAP_402-1 mlb[39D7]
C1636 CAP_402-LF mlb[15D4] C1780 CAP_201 mlb[16D2] C3130 CAP_402-LF mlb[30D1] C4111 CAP_402-1 mlb[39D7]
C1637 CAP_402-LF mlb[15D4] C1781 CAP_201 mlb[16D2] C3131 CAP_402 mlb[30D1] C4112 CAP_402-1 mlb[39D6]
C1638 CAP_402-LF mlb[15D4] C1782 CAP_201 mlb[16C3] C3132 CAP_402 mlb[30D1] C4113 CAP_402-1 mlb[39D6]
C1639 CAP_402-LF mlb[15D4] C1783 CAP_201 mlb[16C3] C3135 CAP_402-LF mlb[30C1] C4114 CAP_402-1 mlb[39D6]
C1640 CAP_402-LF mlb[15D3] C1784 CAP_201 mlb[16C3] C3136 CAP_402 mlb[30C1] C4115 CAP_402-1 mlb[39D6]
C1641 CAP_402-LF mlb[15D3] C1785 CAP_201 mlb[16C2] C3137 CAP_402 mlb[30C1] C4117 CAP_402-1 mlb[39C6]
C1642 CAP_402-LF mlb[15D3] C1786 CAP_201 mlb[16C2] C3140 CAP_402-LF mlb[30B2] C4118 CAP_402-1 mlb[39C6]
C1643 CAP_402-LF mlb[15D2] C1787 CAP_201 mlb[16C2] C3150 CAP_402-LF mlb[30C1] C4119 CAP_402-1 mlb[39C6]
C1644 CAP_402-LF mlb[15D2] C1802 CAP_402-1 mlb[17A7] C3151 CAP_402-LF mlb[30C1] C4120 CAP_402-1 mlb[39D2]
C1645 CAP_402-LF mlb[15D2] C1803 CAP_402-1 mlb[17A7] C3152 CAP_402 mlb[30C1] C4121 CAP_402-1 mlb[39D3]
C1646 CAP_402-LF mlb[15D2] C2150 CAP_402 mlb[20C2] C3200 CAP_603 mlb[31D3] C4122 CAP_402-1 mlb[39D3]
C1647 CAP_402-LF mlb[15D1] C2151 CAP_402 mlb[20C2] C3201 CAP_603 mlb[31D3] C4123 CAP_402-1 mlb[39D3]

B C1648
C1649
CAP_402-LF
CAP_402-LF
mlb[15D1]
mlb[15D1]
C2152
C2210
CAP_402
CAP_402
mlb[20B2]
mlb[21B8]
C3210
C3211
CAP_402
CAP_402
mlb[31D3]
mlb[31D3]
C4124
C4125
CAP_402-1
CAP_402-1
mlb[39D3]
mlb[39D2] B
C1650 CAP_402-LF mlb[15D7] C2222 CAP_402 mlb[21B8] C3212 CAP_402 mlb[31D2] C4126 CAP_402-1 mlb[39D3]
C1651 CAP_402-LF mlb[15D7] C2231 CAP_402-1 mlb[21B7] C3213 CAP_402 mlb[31D2] C4127 CAP_402-1 mlb[39D3]
C1652 CAP_402-LF mlb[15D7] C2232 CAP_402 mlb[21B7] C3214 CAP_402 mlb[31D2] C4128 CAP_402-1 mlb[39D3]
C1653 CAP_402-LF mlb[15D6] C2233 CAP_402 mlb[21B7] C3215 CAP_402 mlb[31D1] C4130 CAP_402-1 mlb[39D2]
C1654 CAP_402-LF mlb[15D6] C2401 CAP_603 mlb[23B1] C3216 CAP_402 mlb[31D1] C4131 CAP_402-1 mlb[39D2]
C1655 CAP_0603 mlb[15C7] C2407 CAP_402-1 mlb[23B2] C3217 CAP_402 mlb[31D1] C4132 CAP_402-1 mlb[39D2]
C1656 CAP_0603 mlb[15C7] C2411 CAP_402 mlb[23D6] C3222 CAP_402 mlb[31A4] C4135 CAP_402-1 mlb[39C2]
C1657 CAP_0603 mlb[15C7] C2413 CAP_402 mlb[23D4] C3224 CAP_402 mlb[31A4] C4137 CAP_402-1 mlb[39C3]
C1658 CAP_0603 mlb[15C6] C2414 CAP_402-1 mlb[23B2] C3226 CAP_402 mlb[31A3] C4138 CAP_402-1 mlb[39C3]
C1659 CAP_0603 mlb[15C6] C2416 CAP_402 mlb[23D5] C3228 CAP_402 mlb[31A2] C4139 CAP_402-1 mlb[39C2]
C1660 CAP_0603 mlb[15C6] C2417 CAP_402 mlb[23D4] C3230 CAP_402-LF mlb[31D1] C4140 CAP_402 mlb[39C7]
C1661 CAP_0603 mlb[15C5] C2419 CAP_402-1 mlb[23C5] C3231 CAP_402 mlb[31D1] C4141 CAP_402 mlb[39C7]
C1662 CAP_0603 mlb[15C5] C2420 CAP_0603 mlb[23B1] C3232 CAP_402 mlb[31D1] C4145 CAP_402 mlb[39C7]
C1663 CAP_0603 mlb[15C5] C2421 CAP_402 mlb[23A7] C3235 CAP_402-LF mlb[31C1] C4146 CAP_402 mlb[39C7]
C1664 CAP_0603 mlb[15C5] C2423 CAP_402 mlb[23A6] C3236 CAP_402 mlb[31C1] C4189 CAP_402 mlb[39A2]
C1665 CAP_0603 mlb[15C4] C2424 CAP_402 mlb[23A7] C3237 CAP_402 mlb[31C1] C4190 CAP_402 mlb[39C1]
C1666 CAP_0603 mlb[15C4] C2426 CAP_402-1 mlb[23B2] C3240 CAP_402-LF mlb[31B2] C4200 CAP_402-1 mlb[40D7]
C1667 CAP_0603 mlb[15C7] C2428 CAP_0603 mlb[23B1] C3250 CAP_402-LF mlb[31C1] C4201 CAP_402 mlb[40D6]
C1668 CAP_0603 mlb[15C7] C2429 CAP_402-1 mlb[23B2] C3251 CAP_402-LF mlb[31C1] C4202 CAP_402-LF mlb[40D6]
C1669 CAP_0603 mlb[15C7] C2430 CAP_402 mlb[23D4] C3252 CAP_402 mlb[31C1] C4250 CAP_402-1 mlb[40D3]
C1670 CAP_0603 mlb[15C6] C2434 CAP_402-1 mlb[23C2] C3331 CAP_402 mlb[32B5] C4254 CAP_402 mlb[40B3]
C1671 CAP_0603 mlb[15C6] C2438 CAP_402 mlb[23B7] C3332 CAP_402 mlb[32B4] C4300 CAP_603 mlb[41D2]
C1672 CAP_0603 mlb[15C6] C2439 CAP_402-1 mlb[23B7] C3333 CAP_402 mlb[32B4] C4305 CAP_603 mlb[41B6]
C1673 CAP_0603 mlb[15C5] C2440 CAP_402 mlb[23D3] C3334 CAP_402 mlb[32B4] C4309 CAP_402 mlb[41C7]
C1674 CAP_0603 mlb[15C5] C2441 CAP_402 mlb[23D3] C3336 CAP_402 mlb[32B3] C4310 CAP_402 mlb[41C4]
C1675 CAP_0603 mlb[15C5] C2442 CAP_402-1 mlb[23C3] C3338 CAP_402 mlb[32A5] C4311 CAP_402 mlb[41C3]
C1676 CAP_0603 mlb[15C5] C2444 CAP_402-1 mlb[23D2] C3339 CAP_402 mlb[32A5] C4312 CAP_402 mlb[41B4]
C1677 CAP_0603 mlb[15C4] C2446 CAP_402-1 mlb[23D1] C3340 CAP_402 mlb[32A4] C4313 CAP_402 mlb[41B3]
C1678 CAP_0603 mlb[15C4] C2450 CAP_603 mlb[23C7] C3341 CAP_402 mlb[32A4] C4332 CAP_402 mlb[41B1]
C1679 CAP_0603 mlb[15C4] C2451 CAP_402 mlb[23C7] C3342 CAP_402 mlb[32A4] C4335 CAP_603-1 mlb[41B2]
A C1684
C1685
CAP_402-1
CAP_402-1
mlb[15B7]
mlb[15B7]
C2452
C2453
CAP_402-1
CAP_603
mlb[23D2]
mlb[23C4]
C3400
C3401
CAP_402-LF
CAP_402
mlb[33D6]
mlb[33D6]
C4350
C4351
CAP_402
CAP_402
mlb[41A4]
mlb[41A5]
A
C1686 CAP_402-1 mlb[15B7] C2454 CAP_402-1 mlb[23C3] C3402 CAP_402 mlb[33C6] C4355 CAP_603 mlb[41A3]
C1687 CAP_402-1 mlb[15B6] C2455 CAP_402 mlb[23C7] C3403 CAP_402 mlb[33D4] C4400 CAP_0201 mlb[42C6]
C1688 CAP_402-1 mlb[15B6] C2456 CAP_402-1 mlb[23B2] C3404 CAP_402 mlb[33C4] C4401 CAP_0201 mlb[42B6]
C1689 CAP_402-1 mlb[15B6] C2460 CAP_603 mlb[23C1] C3405 CAP_402 mlb[33B4] C4402 CAP_0201 mlb[42B6]
C1690 CAP_402-1 mlb[15B5] C2463 CAP_402-1 mlb[23B1] C3500 CAP_402 mlb[34D4] C4403 CAP_0201 mlb[42A6]
C1691 CAP_402-1 mlb[15B5] C2469 CAP_402-1 mlb[23C1] C3501 CAP_603 mlb[34D4] C4420 CAP_0201 mlb[42C2]
C1692 CAP_402-1 mlb[15B5] C2475 CAP_402-1 mlb[23D2] C3505 CAP_402 mlb[34D2] C4421 CAP_0201 mlb[42B2]
C1693 CAP_402-1 mlb[15B5] C2476 CAP_402-1 mlb[23D1] C3507 CAP_603 mlb[34D3] C4422 CAP_0201 mlb[42B2]
C1694 CAP_402-1 mlb[15B4] C2481 CAP_402-1 mlb[23C2] C3511 CAP_402 mlb[34D8] C4423 CAP_0201 mlb[42A2]
C1695 CAP_402-1 mlb[15B4] C2482 CAP_402-1 mlb[23C2] C3512 CAP_402 mlb[34D8] C4431 CAP_402 mlb[42D6]
C1696 CAP_402-1 mlb[15B4] C2483 CAP_402-1 mlb[23C2] C3513 CAP_402 mlb[34D8] C4441 CAP_402 mlb[42D3]
C1697 CAP_402-1 mlb[15B7] C2484 CAP_402 mlb[23D5] C3514 CAP_402 mlb[34D8] C4450 CAP_0201 mlb[42C6]

507

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
C4451 CAP_0201 mlb[42B6] C6400 CAP_402 mlb[59C5] C7521 CAP_402 mlb[68C7] C9145 CAP_402-1 mlb[75D3]
C4452 CAP_0201 mlb[42B6] C6500 CAP_402 mlb[60C4] C7523 CAP_402 mlb[68C5] C9146 CAP_603 mlb[75D3]
C4453 CAP_0201 mlb[42B6] C6502 CAP_402 mlb[60D5] C7526 CAP_P_SM mlb[68D2] C9147 CAP_603 mlb[75D3]
C4460 CAP_0201 mlb[42C3] C6503 CAP_402 mlb[60C4] C7528 CAP_402 mlb[68B4] C9150 CAP_402-1 mlb[75C3]
C4461 CAP_0201 mlb[42B3] C6505 CAP_603 mlb[60C4] C7530 CAP_402 mlb[68C4] C9151 CAP_402-1 mlb[75C3]
C4462 CAP_0201 mlb[42B3] C6506 CAP_603 mlb[60C3] C7531 CAP_402 mlb[68C4] C9152 CAP_402-1 mlb[75C3]
C4463 CAP_0201 mlb[42B3] C6507 CAP_402 mlb[60C3] C7560 CAP_P_CASE-B4-SM mlb[68A7] C9153 CAP_402-1 mlb[75C4]
C4600 CAP_P_CASE-B2-SM mlb[43B7] C6520 CAP_402 mlb[60C4] C7561 CAP_P_CASE-B4-SM mlb[68A6] C9160 CAP_402-LF mlb[75C4]
C4601 CAP_402 mlb[43B8] C6700 CAP_402 mlb[61D2] C7562 CAP_P_CASE-B4-SM mlb[68A6] C9170 CAP_402-LF mlb[75C4]
C4603 CAP_402 mlb[43D6] C6701 CAP_402 mlb[61B7] C7563 CAP_P_CASE-B4-SM mlb[68A6] C9200 CAP_402 mlb[76C7]
C4604 CAP_402 mlb[43D8] C6702 CAP_603 mlb[61B7] C7564 CAP_P_CASE-B4-SM mlb[68A5] C9210 CAP_402-1 mlb[76B7]
C4605 CAP_402 mlb[43D2] C6709 CAP_402 mlb[61D3] C7565 CAP_P_CASE-B4-SM mlb[68A5] C9215 CAP_402-1 mlb[76A7]
C4606 CAP_P_CASE-B2-SM mlb[43D8] C6710 CAP_402 mlb[61D6] C7580 CAP_402 mlb[68D5] C9221 CAP_0201 mlb[76B2]
C4612 CAP_402 mlb[43D6] C6711 CAP_402 mlb[61D6] C7581 CAP_603 mlb[68D5] C9222 CAP_0201 mlb[76B2]

D C4615
C4623
CAP_402
CAP_402
mlb[43C2]
mlb[43B6]
C6730
C6731
CAP_402
CAP_402
mlb[61C2]
mlb[61C3]
C7582
C7601
CAP_603
CAP_402
mlb[68C4]
mlb[69C7]
C9223
C9224
CAP_0201
CAP_0201
mlb[76B2]
mlb[76B2]
D
C4625 CAP_402 mlb[43B4] C6740 CAP_402 mlb[61B2] C7602 CAP_402 mlb[69C3] C9225 CAP_0201 mlb[76A4]
C4632 CAP_402 mlb[43B6] C6741 CAP_402 mlb[61C3] C7603 CAP_402 mlb[69C6] C9226 CAP_0201 mlb[76A2]
C4635 CAP_402 mlb[43A4] C6760 CAP_402 mlb[61B2] C7607 CAP_402 mlb[69D4] C9227 CAP_0201 mlb[76A2]
C4650 CAP_402 mlb[43D5] C6761 CAP_402 mlb[61B3] C7608 CAP_402 mlb[69C4] C9228 CAP_0201 mlb[76B4]
C4790 CAP_402-1 mlb[44C4] C6810 CAP_402 mlb[62D2] C7610 CAP_402 mlb[69D4] C9230 CAP_0201 mlb[76A4]
C4791 CAP_402 mlb[44C4] C6812 CAP_402 mlb[62D3] C7615 CAP_603 mlb[69D4] C9231 CAP_0201 mlb[76B4]
C4792 CAP_402 mlb[44C5] C6821 CAP_402 mlb[62B2] C7620 CAP_P_CASE-B4-SM mlb[69C3] C9300 CAP_402 mlb[77D7]
C4793 CAP_402-1 mlb[44B4] C6822 CAP_402 mlb[62B1] C7621 CAP_P_CASE-B4-SM mlb[69C2] C9301 CAP_402 mlb[77D7]
C4794 CAP_402 mlb[44B5] C6842 CAP_402 mlb[62D7] C7622 CAP_P_CASE-B4-SM mlb[69C2] C9302 CAP_402 mlb[77D7]
C4800 CAP_402 mlb[45C3] C6860 CAP_402 mlb[62A7] C7623 CAP_402 mlb[69C1] C9303 CAP_402 mlb[77D7]
C4801 CAP_402 mlb[45D6] C6881 CAP_402 mlb[62C3] C7633 CAP_402 mlb[69D3] C9304 CAP_402 mlb[77D7]
C4802 CAP_402 mlb[45A3] C6886 CAP_402 mlb[62C2] C7634 CAP_603 mlb[69D3] C9305 CAP_402 mlb[77D7]
C4803 CAP_402 mlb[45C2] C6887 CAP_402 mlb[62C3] C7635 CAP_P_CASE-B4-SM mlb[69C2] C9306 CAP_402 mlb[77D7]
C4806 CAP_402 mlb[45C6] C6888 CAP_402 mlb[62C2] C7651 CAP_P_SM mlb[69D7] C9307 CAP_402 mlb[77D7]
C4809 CAP_402 mlb[45C4] C7101 CAP_603 mlb[64C5] C7652 CAP_P_SM mlb[69C6] C9308 CAP_402 mlb[77D7]
C4902 CAP_805 mlb[46D4] C7102 CAP_402 mlb[64B6] C7653 CAP_P_SM mlb[69C5] C9309 CAP_402 mlb[77D7]
C4903 CAP_402 mlb[46D4] C7103 CAP_402 mlb[64B6] C7701 CAP_603 mlb[70C5] C9310 CAP_402-LF mlb[77C7]
C4904 CAP_402 mlb[46D3] C7105 CAP_402 mlb[64B7] C7702 CAP_402 mlb[70B6] C9311 CAP_402 mlb[77C7]
C4905 CAP_402 mlb[46D3] C7119 CAP_402 mlb[64B3] C7703 CAP_402 mlb[70B7] C9312 CAP_402 mlb[77C7]
C4906 CAP_402 mlb[46D3] C7120 CAP_P_SM mlb[64C3] C7704 CAP_402 mlb[70B7] C9319 CAP_402-LF mlb[77B5]
C4907 CAP_402 mlb[46D2] C7121 CAP_402 mlb[64C3] C7705 CAP_402 mlb[70B7] C9330 CAP_402 mlb[77A5]
C4910 CAP_402 mlb[46A5] C7122 CAP_402 mlb[64C3] C7720 CAP_P_SM mlb[70C4] C9331 CAP_402 mlb[77A5]
C4920 CAP_402 mlb[46D3] C7123 CAP_402 mlb[64B2] C7721 CAP_P_SM mlb[70C4] C9357 CAP_402 mlb[77A7]
C5001 CAP_402 mlb[47D8] C7130 CAP_402 mlb[64C4] C7722 CAP_402 mlb[70C3] C9358 CAP_402 mlb[77C3]
C5010 CAP_402 mlb[47B7] C7140 CAP_402 mlb[64B3] C7723 CAP_402 mlb[70C2] C9359 CAP_402 mlb[77C3]
C5011 CAP_402 mlb[47B7] C7201 CAP_402 mlb[65D5] C7724 CAP_402 mlb[70C3] C9360 CAP_0201 mlb[77C3]
C5020 CAP_402 mlb[47D7] C7202 CAP_402 mlb[65D6] C7725 CAP_P_CASE-B4-SM mlb[70C2] C9361 CAP_0201 mlb[77C3]
C5025 CAP_603 mlb[47D7] C7203 CAP_402 mlb[65C5] C7726 CAP_P_CASE-B4-SM mlb[70C2] C9362 CAP_402 mlb[77C4]
C5026 CAP_402 mlb[47D6] C7204 CAP_402 mlb[65D4] C7727 CAP_P_CASE-B4-SM mlb[70C2] C9363 CAP_402 mlb[77C4]
C5300 CAP_402 mlb[50D6] C7205 CAP_P_CASED2-SM mlb[65D4] C7730 CAP_402 mlb[70C5] C9364 CAP_0201 mlb[77C3]

C C5301
C5305
CAP_402
CAP_402
mlb[50D5]
mlb[50C6]
C7208
C7209
CAP_402
CAP_805
mlb[65C4]
mlb[65C3]
C7731
C7740
CAP_402
CAP_402
mlb[70B3]
mlb[70B3]
C9365
C9366
CAP_0201
CAP_402
mlb[77C3]
mlb[77C4]
C
C5306 CAP_402 mlb[50C5] C7210 CAP_805 mlb[65C3] C7860 CAP_0805 mlb[71D7] C9367 CAP_402 mlb[77C4]
C5320 CAP_402 mlb[50C2] C7211 CAP_402 mlb[65D6] C7861 CAP_402 mlb[71D7] C9368 CAP_402 mlb[77B4]
C5322 CAP_402 mlb[50A6] C7212 CAP_402 mlb[65C3] C7862 CAP_0603 mlb[71D5] C9369 CAP_402 mlb[77B4]
C5330 CAP_402 mlb[50B2] C7213 CAP_402 mlb[65D5] C7863 CAP_402 mlb[71D5] C9370 CAP_201 mlb[77D3]
C5340 CAP_402 mlb[50D2] C7250 CAP_402 mlb[65B6] C7864 CAP_402 mlb[71C7] C9371 CAP_201 mlb[77D3]
C5341 CAP_402 mlb[50D2] C7251 CAP_P_SM mlb[65B7] C7865 CAP_402 mlb[71C8] C9372 CAP_201 mlb[77D3]
C5345 CAP_402 mlb[50D3] C7252 CAP_603 mlb[65B7] C7866 CAP_402 mlb[71D6] C9373 CAP_201 mlb[77D3]

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C5351 CAP_402 mlb[50B2] C7253 CAP_402 mlb[65B7] C7867 CAP_0805 mlb[71D7] C9380 CAP_201 mlb[77D3]
C5355 CAP_402 mlb[50B3] C7254 CAP_402 mlb[65B5] C7868 CAP_402 mlb[71C7] C9381 CAP_201 mlb[77D3]
C5360 CAP_402 mlb[50B7] C7255 CAP_402 mlb[65A6] C7870 CAP_402 mlb[71B7] C9382 CAP_201 mlb[77D3]
C5361 CAP_402 mlb[50B6] C7256 CAP_402 mlb[65B4] C7871 CAP_603 mlb[71A7] C9383 CAP_201 mlb[77D3]
C5365 CAP_402 mlb[50A7] C7257 CAP_402 mlb[65A5] C7872 CAP_603 mlb[71B6] C9390 CAP_402 mlb[77B1]
C5366 CAP_402 mlb[50A6] C7258 CAP_402 mlb[65A5] C7873 CAP_0603 mlb[71D5] C9391 CAP_402 mlb[77B1]
C5375 CAP_402 mlb[50C7] C7259 CAP_402 mlb[65A4] C7900 CAP_402 mlb[72B7] C9400 CAP_402 mlb[78C6]
C5376 CAP_402 mlb[50B6] C7260 CAP_402 mlb[65A3] C7901 CAP_402 mlb[72B7] C9401 CAP_0201 mlb[78A6]
C5401 CAP_402 mlb[51C6] C7261 CAP_0805 mlb[65A3] C7902 CAP_603 mlb[72B6] C9402 CAP_0201 mlb[78A6]
C5403 CAP_402 mlb[51C5] C7262 CAP_P_CASE-B2-SM mlb[65A3] C7920 CAP_402 mlb[72B6] C9405 CAP_201 mlb[78C2]
C5414 CAP_402 mlb[51D2] C7300 CAP_603 mlb[66C7] C7950 CAP_402 mlb[72C2] C9406 CAP_201 mlb[78B2]
C5418 CAP_402 mlb[51D6] C7301 CAP_402 mlb[66D6] C7951 CAP_402 mlb[72C2] C9410 CAP_603-1 mlb[78D3]
C5437 CAP_402 mlb[51D5] C7302 CAP_603 mlb[66D5] C7952 CAP_402 mlb[72C2] C9411 CAP_603-1 mlb[78D2]
C5500 CAP_402-1 mlb[52D6] C7305 CAP_402 mlb[66B8] C7953 CAP_402 mlb[72C1] C9420 CAP_0805 mlb[78D8]
C5510 CAP_402 mlb[52D3] C7320 CAP_402 mlb[66B7] C7962 CAP_402 mlb[72B2] C9421 CAP_402 mlb[78D8]
C5520 CAP_402 mlb[52D3] C7321 CAP_402 mlb[66B4] C7963 CAP_402 mlb[72B1] C9422 CAP_0805 mlb[78D7]
C5535 CAP_402-1 mlb[52B5] C7325 CAP_402 mlb[66C4] C7970 CAP_402 mlb[72B2] C9423 CAP_402 mlb[78D6]
C5540 CAP_402 mlb[52A6] C7330 CAP_P_SM mlb[66C5] C7971 CAP_402 mlb[72B2] C9424 CAP_805 mlb[78D5]
C5570 CAP_402 mlb[52C3] C7331 CAP_603 mlb[66C4] C7972 CAP_402 mlb[72B2] C9425 CAP_805 mlb[78D5]
C5580 CAP_402 mlb[52C3] C7332 CAP_P_SM mlb[66C4] C7973 CAP_402 mlb[72B1] C9450 CAP_603-1 mlb[78C7]
C5600 CAP_0306 mlb[53D6] C7333 CAP_402 mlb[66C4] C9000 CAP_402 mlb[74D6] C9470 CAP_201 mlb[78B2]
C5602 CAP_P_2012-LLP mlb[53D5] C7340 CAP_P_CASE-B2-SM mlb[66C3] C9001 CAP_402 mlb[74D6] C9471 CAP_201 mlb[78B2]
C5603 CAP_402 mlb[53D4] C7341 CAP_P_CASE-B2-SM mlb[66C2] C9002 CAP_402 mlb[74D6] C9472 CAP_201 mlb[78B2]

B C5604
C5605
CAP_P_2012-LLP
CAP_402
mlb[53D4]
mlb[53D3]
C7345
C7350
CAP_603
CAP_402
mlb[66C2]
mlb[66B6]
C9003
C9004
CAP_402
CAP_402
mlb[74D6]
mlb[74D6]
C9473
C9494
CAP_201
CAP_201
mlb[78B2]
mlb[78A7] B
C5606 CAP_402-1 mlb[53D3] C7355 CAP_603 mlb[66C6] C9005 CAP_402 mlb[74D6] C9495 CAP_201 mlb[78A7]
C5608 CAP_0508 mlb[53D3] C7360 CAP_0603 mlb[66B5] C9006 CAP_402 mlb[74D6] C9498 CAP_402 mlb[78A7]
C5613 CAP_P_CASE-P3-HF mlb[53B4] C7361 CAP_0603 mlb[66B5] C9007 CAP_402 mlb[74D6] C9499 CAP_402 mlb[78A6]
C5614 CAP_P_CASE-B2-SM mlb[53B4] C7398 CAP_402 mlb[66C3] C9015 CAP_402 mlb[74D5] C9710 CAP_402 mlb[79D7]
C5650 CAP_402 mlb[53A7] C7399 CAP_402 mlb[66C3] C9016 CAP_402 mlb[74C5] C9711 CAP_402 mlb[79D7]
C5651 CAP_402-1 mlb[53A6] C7400 CAP_402 mlb[67C2] C9020 CAP_402 mlb[74B7] C9712 CAP_402 mlb[79C7]
C5652 CAP_402 mlb[53A6] C7401 CAP_402 mlb[67C2] C9021 CAP_402 mlb[74B7] C9713 CAP_402 mlb[79D7]
C5653 CAP_402 mlb[53A4] C7402 CAP_402 mlb[67C2] C9022 CAP_402 mlb[74B7] C9714 CAP_402 mlb[79C7]
C5654 CAP_402-1 mlb[53A4] C7403 CAP_402 mlb[67C2] C9023 CAP_402 mlb[74B7] C9715 CAP_402 mlb[79C7]
C5700 CAP_P_CASE-M mlb[54D4] C7404 CAP_402 mlb[67C2] C9024 CAP_402 mlb[74B7] C9716 CAP_402 mlb[79C7]
C5702 CAP_P_CASE-M mlb[54C4] C7405 CAP_402 mlb[67B2] C9025 CAP_402 mlb[74B7] C9717 CAP_402 mlb[79C7]
C5703 CAP_P_CASE-M mlb[54C4] C7406 CAP_402 mlb[67C2] C9026 CAP_402 mlb[74B7] C9740 CAP_402 mlb[79D3]
C5713 CAP_201 mlb[54C5] C7409 CAP_402 mlb[67C4] C9027 CAP_402 mlb[74B7] C9741 CAP_402 mlb[79D2]
C5800 CAP_0508 mlb[55D5] C7411 CAP_402 mlb[67A2] C9028 CAP_402 mlb[74B7] C9742 CAP_402 mlb[79D2]
C5801 CAP_402 mlb[55D5] C7412 CAP_402 mlb[67B2] C9029 CAP_402 mlb[74B7] C9743 CAP_402 mlb[79D2]
C5804 CAP_402-1 mlb[55B4] C7413 CAP_402 mlb[67D5] C9040 CAP_402 mlb[74D2] C9744 CAP_402 mlb[79D4]
C5805 CAP_402-1 mlb[55B3] C7414 CAP_603 mlb[67C3] C9041 CAP_402 mlb[74D2] C9745 CAP_402 mlb[79D4]
C5806 CAP_402-1 mlb[55B3] C7416 CAP_402 mlb[67D7] C9042 CAP_402 mlb[74D2] C9746 CAP_402 mlb[79D3]
C5812 CAP_P_CASE-P mlb[55C7] C7417 CAP_402 mlb[67C7] C9043 CAP_402 mlb[74D2] C9747 CAP_402 mlb[79D3]
C5813 CAP_P_CASE-P mlb[55C7] C7418 CAP_402 mlb[67C7] C9044 CAP_402 mlb[74D2] C9748 CAP_402 mlb[79D3]
C5814 CAP_P_CASE-P mlb[55B7] C7419 CAP_402 mlb[67C8] C9045 CAP_402 mlb[74D2] C9749 CAP_402 mlb[79D2]
C5815 CAP_P_CASE-P mlb[55B7] C7420 CAP_402 mlb[67C7] C9046 CAP_402 mlb[74D2] C9750 CAP_402 mlb[79D2]
C5901 CAP_P_1206-LLP mlb[56C3] C7422 CAP_402 mlb[67B8] C9047 CAP_402 mlb[74D2] C9751 CAP_402 mlb[79D2]
C5902 CAP_402 mlb[56C3] C7423 CAP_402 mlb[67B7] C9085 CAP_402 mlb[74B2] C9760 CAP_402-LF mlb[79B5]
C5904 CAP_402-1 mlb[56C5] C7426 CAP_402 mlb[67A6] C9086 CAP_402 mlb[74B2] C9800 CAP_0603 mlb[80C4]
C5950 CAP_402 mlb[56B6] C7427 CAP_402 mlb[67A5] C9090 CAP_402-1 mlb[74C7] C9802 CAP_402 mlb[80C4]
C5951 CAP_402 mlb[56C6] C7432 CAP_402 mlb[67B7] C9100 CAP_603 mlb[75D7] C9803 CAP_603 mlb[80C3]
C6000 CAP_402-1 mlb[57A8] C7455 CAP_402 mlb[67D6] C9101 CAP_603 mlb[75D7] C9810 CAP_402 mlb[80B5]
C6050 CAP_402-1 mlb[57A8] C7456 CAP_402 mlb[67D6] C9105 CAP_402-1 mlb[75D7] C9811 CAP_402 mlb[80B6]
C6051 CAP_402 mlb[57A7] C7457 CAP_402 mlb[67D6] C9106 CAP_402-1 mlb[75D6] C9813 CAP_402 mlb[80A6]
A C6054
C6100
CAP_402
CAP_402
mlb[57A6]
mlb[58A3]
C7458
C7459
CAP_402
CAP_402
mlb[67A6]
mlb[67A7]
C9107
C9108
CAP_402-1
CAP_402-1
mlb[75D6]
mlb[75D6]
C9814
C9830
CAP_402
CAP_603
mlb[80A6]
mlb[80C2]
A
C6101 CAP_402 mlb[58B7] C7460 CAP_402 mlb[67A6] C9109 CAP_402-1 mlb[75D5] CL3601 SPRING_CLIP_1P_CLIP- mlb[35C8]
C6102 CAP_402 mlb[58B7] C7501 CAP_402 mlb[68D7] C9110 CAP_402-1 mlb[75D7] SM-K40
C6111 CAP_402 mlb[58A6] C7503 CAP_402 mlb[68D5] C9111 CAP_402-1 mlb[75D6] CL3602 SPRING_CLIP_1P_CLIP- mlb[35C8]
C6160 CAP_402 mlb[58A3] C7505 CAP_P_SM mlb[68D3] C9112 CAP_402-1 mlb[75D6] SM-K40
C6180 CAP_603 mlb[58D3] C7506 CAP_P_SM mlb[68D3] C9113 CAP_402-1 mlb[75D6] CL3603 SPRING_CLIP_1P_CLIP- mlb[35C8]
C6181 CAP_402 mlb[58C2] C7507 CAP_603 mlb[68D4] C9114 CAP_402-1 mlb[75D5] SM-K40
C6182 CAP_P_603-HF mlb[58C2] C7508 CAP_402 mlb[68D4] C9120 CAP_402-1 mlb[75C6] CL3604 SPRING_CLIP_1P_CLIP- mlb[35B8]
C6183 CAP_402 mlb[58C3] C7509 CAP_402 mlb[68D3] C9121 CAP_402-1 mlb[75C6] SM-K40
C6184 CAP_402 mlb[58C3] C7510 CAP_402 mlb[68D4] C9122 CAP_402-1 mlb[75C5] CL3606 SPRING_CLIP_1P_CLIP- mlb[35B8]
C6185 CAP_402 mlb[58C2] C7511 CAP_402 mlb[68D4] C9130 CAP_402-LF mlb[75C5] SM-K40
C6186 CAP_402 mlb[58C3] C7515 CAP_P_SM mlb[68D3] C9143 CAP_402-1 mlb[75D3] CL3608 SPRING_CLIP_1P_CLIP- mlb[35B8]
C6187 CAP_402 mlb[58D3] C7520 CAP_402 mlb[68B3] C9144 CAP_402-1 mlb[75D4] SM-K40

508

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
CL3614 SPRING_CLIP_1P_CLIP- mlb[35B8] L2406 IND_0805 mlb[23D8] 23V1K-SM R1112 RES_402 mlb[11B5]
SM-K40 L2451 IND_0603 mlb[23C4] Q4010 TRA_DUAL_SSM6N15FE_S mlb[38A4 38B3] R1113 RES_402 mlb[11B5]
CL3615 SPRING_CLIP_1P_CLIP- mlb[35B8] L2490 IND_0603 mlb[23B4] OT563 R1114 RES_402 mlb[11B5]
SM-K40 L2491 IND_0603 mlb[23B4] Q4050 TRA_SSM3K15FV_SOD-VE mlb[38C3] R1120 RES_402 mlb[11C7]
CL3616 SPRING_CLIP_1P_CLIP- mlb[35B8] L3540 IND_0402 mlb[34C6] SM-HF R1121 RES_402 mlb[11C6]
SM-K40 L3541 IND_0402 mlb[34C5] Q4300 TRA_MOSFET_PCHN_5P1_ mlb[41D5] R1125 RES_402 mlb[11B6]
CL3617 SPRING_CLIP_1P_CLIP- mlb[35B8] L3550 IND_0402 mlb[34C4] MLP3.3X3.3 R1126 RES_402 mlb[11B7]
SM-K40 L3551 IND_0402 mlb[34C3] Q4301 TRA_PNP_SOT23_SOT23 mlb[41D7] R1140 RES_402 mlb[11C2]
CL3618 SPRING_CLIP_1P_CLIP- mlb[35B8] L3601 FILTER_4P2_DLP11S mlb[35D5] Q4302 TRA_DUAL_MMDT3906_SO mlb[41C6 41C5] R1141 RES_402 mlb[11C2]
SM-K40 L3603 FILTER_4P2_DLP0NS mlb[35C5] T-363 R1300 RES_402 mlb[13B5]
D2400 DIODE_SCHOT_6PB_SOT- mlb[23B7 23C7] L3604 IND_0603 mlb[35C5] Q4303 TRA_DUAL_MMDT3904_SO mlb[41B5 41B5] R1302 RES_402 mlb[13B6]
363 L3606 IND_0402 mlb[35C5] T-363-LF R1310 RES_402 mlb[13B5]
D2600 DIODE_SCHOT_SOD-523 mlb[25B1] L3900 IND_SM mlb[37D7] Q4305 TRA_BSS84_S0T23-3-HF mlb[41D6] R1311 RES_402 mlb[13B5]
D2800 DIODE_SCHOT_6PB_SOT- mlb[27D6] L3905 IND_SM mlb[37D7] Q4370 TRA_2N7002DW_SOT-363 mlb[41C7 41C7] R1312 RES_402 mlb[13B5]

D D3800
363
RCLAMP0524P_SLP2510P mlb[36B7]
L3910
L3920
IND_SM
IND_SM
mlb[37C7]
mlb[37D2]
Q4800 TRA_SSM3K15FV_SOD-VE
SM-HF
mlb[45C6] R1313
R1314
RES_402
RES_402
mlb[13B2]
mlb[13B2]
D
8 L3925 IND_SM mlb[37D2] Q4801 TRA_DUAL_MMDT3906_SO mlb[45D5 45D5] R1320 RES_402 mlb[13B6]
D3801 RCLAMP0524P_SLP2510P mlb[36B7] L3930 IND_SM mlb[37C2] T-363 R1330 RES_402 mlb[13B1]
8 L4020 IND_2520 mlb[38D6] Q5059 TRA_DUAL_SSM6N15FE_S mlb[47D3 47C3] R1331 RES_402 mlb[13B1]
D4300 DIODE_SMB mlb[41D4] L4250 IND_0402 mlb[40D3] OT563 R1362 RES_402 mlb[13A5]
D4305 DIODE_3P_CA_SOT-523- mlb[41D5] L4251 IND_0402 mlb[40D2] Q5060 TRA_NMOSFET_NPN_6P2_ mlb[47D2 47D2] R1363 RES_402 mlb[13A5]
3 L4252 IND_0402 mlb[40C3] SOT-563 R1382 RES_402 mlb[13C1]
D4350 DIODE_SCHOT_3P_SOT32 mlb[41A4] L4253 IND_0402 mlb[40C2] Q5415 TRA_DUAL_COMP_DMG101 mlb[51D3 51C3] R1600 RES_402 mlb[15B2]
3 L4300 IND_SM mlb[41D2] 6V_SOT-563 R1601 RES_0603 mlb[15A7]
D4390 ZENER_SOT23 mlb[41B2] L4310 FILTER_4P_TCM1210-4S mlb[41C2] Q5520 TRA_BC846BM3T5G_NPN_ mlb[52D2] R1702 RES_0603 mlb[16A7]
D4600 DIODE_SCHOT_3P_A_SC- mlb[43B2] M SOT732-3 R1800 RES_201 mlb[17A8]
75 L4311 FILTER_4P_TCM1210-4S mlb[41C2] Q5540 TRA_BC846BM3T5G_NPN_ mlb[52A7] R1801 RES_201 mlb[17A8]
D4601 DIODE_SCHOT_3P_A_SC- mlb[43B4] M SOT732-3 R1802 RES_201 mlb[17B7]
75 L4600 IND_0603 mlb[43D3] Q5560 TRA_BC846BM3T5G_NPN_ mlb[52B2] R1803 RES_201 mlb[17B7]
D4602 DIODE_SCHOT_3P_A_SC- mlb[43A4] L4602 FILTER_4P_2012-HF mlb[43D3] SOT732-3 R1810 RES_201 mlb[17A5]
75 L4610 IND_0603 mlb[43C3] Q5570 TRA_BC846BM3T5G_NPN_ mlb[52C2] R1811 RES_201 mlb[17A4]
D4603 DIODE_SCHOT_3P_A_SC- mlb[43C2] L4612 FILTER_4P_2012-HF mlb[43B3] SOT732-3 R1812 RES_201 mlb[17A5]
75 L4620 IND_0603 mlb[43C5] Q5580 TRA_BC846BM3T5G_NPN_ mlb[52C2] R1813 RES_201 mlb[17A4]
D4700 DIODE_SCHOT_SOD-323 mlb[44C5] L4622 FILTER_4P_2012-HF mlb[43B5] SOT732-3 R1820 RES_201 mlb[17D5]
D9360 DIODE_TSLP-2-7 mlb[77D2] L4630 IND_0603 mlb[43A5] Q5590 TRA_BC846BM3T5G_NPN_ mlb[52B2] R1830 RES_201 mlb[17C5]
D9361 DIODE_TSLP-2-7 mlb[77C2] L4632 FILTER_4P_2012-HF mlb[43A5] SOT732-3 R1831 RES_201 mlb[17C5]
D9364 DIODE_TSLP-2-7 mlb[77D2] L4800 IND_SM mlb[45B2] Q6100 TRA_DUAL_SSM6N15FE_S mlb[58C7 58B6] R1832 RES_201 mlb[17B5]
D9365 DIODE_TSLP-2-7 mlb[77D2] L4810 IND_0402 mlb[45D2] OT563 R1833 RES_201 mlb[17A6]
D9372 DIODE_TSLP-2-7 mlb[77D2] L4811 IND_0402 mlb[45C2] Q6101 TRA_DUAL_SSM6N15FE_S mlb[58C5 58C6] R1840 RES_201 mlb[17A5]
D9373 DIODE_TSLP-2-7 mlb[77D2] L5650 IND_0402 mlb[53A7] OT563 R1841 RES_201 mlb[17A5]
D9382 DIODE_TSLP-2-7 mlb[77D2] L5651 IND_0402 mlb[53A7] Q6102 TRA_SSM3K15FV_SOD-VE mlb[58A5] R1842 RES_201 mlb[17B6]
D9383 DIODE_TSLP-2-7 mlb[77D2] L5801 IND_0402 mlb[55B5] SM-HF R1843 RES_201 mlb[17B7]
D9401 DIODE_SCHOT_POWERDI- mlb[78D6] L5900 IND_0402 mlb[56B7] Q6103 TRA_DUAL_SSM6N15FE_S mlb[58B3 58B2] R1844 RES_201 mlb[17B6]
123 L5901 IND_0402 mlb[56C7] OT563 R1845 RES_201 mlb[17B6]
D9403 ZENER_SOT23 mlb[78D3] L5902 IND_0402 mlb[56B7] Q6500 TRA_FDC638P_SM mlb[60D4] R1846 RES_201 mlb[17B6]
D9410 DIODE_SCHOT_DSN2 mlb[78D1] L6000 IND_0402 mlb[57D4] Q6501 TRA_SSM3K15FV_SOD-VE mlb[60C6] R1847 RES_201 mlb[17A6]

C D9498
D9499
DIODE_TSLP-2-7
DIODE_TSLP-2-7
mlb[78B7]
mlb[78B7]
L6001
L6002
IND_0402
IND_0402
mlb[57D4]
mlb[57D4] Q6700
SM-HF
TRA_MOSFET_PCHN_4P_S mlb[61D2]
R1848
R1849
RES_201
RES_201
mlb[17B7]
mlb[17A3]
C
D9800 RCLAMP0504F_SC70-6-1 mlb[80B7] L6003 IND_0402 mlb[57C4] C70-6L R1853 RES_201 mlb[17A3]
D9810 RCLAMP0524P_SLP2510P mlb[80D6 80C6] L6004 IND_0603 mlb[57C4] Q6701 TRA_MOSFET_NCHN_PWRP mlb[61B6] R1854 RES_201 mlb[17A3]
8 L6005 IND_0402 mlb[57C4] K-1212-8-HF R1855 RES_201 mlb[17A2]
D9811 RCLAMP0524P_SLP2510P mlb[80D6 80C6] L6006 IND_0402 mlb[57D4] Q6702 TRA_DUAL_SSM6N15FE_S mlb[61B3 61D4] R1860 RES_201 mlb[17D5]
8 L6007 IND_0402 mlb[57D4] OT563 R1861 RES_201 mlb[17D5]
DP4310 DIODE_DUAL_6P_SOT-36 mlb[41C3 41C3] L6051 IND_0402 mlb[57B4] Q6710 TRA_MOSFET_PCHN_4P_S mlb[61D6] R1862 RES_201 mlb[17D5]
3 L6052 IND_0402 mlb[57B4] C70-6L R1863 RES_201 mlb[17D5]

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DP4311 DIODE_DUAL_6P_SOT-36 mlb[41B3 41B3] L6053 IND_0402 mlb[57B4] Q6711 TRA_DUAL_SSM6N15FE_S mlb[61D7] R1864 RES_201 mlb[17D5]
3 L6054 IND_0402 mlb[57B4] OT563 R1866 RES_201 mlb[17A4]
DZ6000 SUPPR_TRANSIENT1_402 mlb[57C6] L6092 IND_0603 mlb[57C2] Q6712 TRA_DUAL_SSM6N15FE_S mlb[61C4] R1869 RES_201 mlb[17B6]
DZ6001 SUPPR_TRANSIENT1_402 mlb[57C6] L6100 IND_0402 mlb[58A3] OT563 R1870 RES_201 mlb[17A2]
DZ6002 SUPPR_TRANSIENT1_SOD mlb[57C6] L6180 IND_0402 mlb[58D3] Q6722 TRA_DUAL_SSM6N15FE_S mlb[61C4] R1871 RES_201 mlb[17A2]
882 L6500 IND_0402 mlb[60C3] OT563 R1876 RES_201 mlb[17B5]
DZ6003 SUPPR_TRANSIENT1_402 mlb[57C5] L6510 FILTER_2P_0603 mlb[60D3] Q6730 TRA_MOSFET_PCHN_4P_S mlb[61C2] R1877 RES_201 mlb[17B5]
DZ6004 SUPPR_TRANSIENT1_402 mlb[57C5] L6520 FILTER_2P_0603 mlb[60C3] C70-6L R1878 RES_201 mlb[17B6]
DZ6005 SUPPR_TRANSIENT1_SOD mlb[57C5] L7100 IND_FDV0630H-SM mlb[64C3] Q6740 TRA_MOSFET_PCHN_4P_S mlb[61C2] R1879 RES_201 mlb[17C5]
882 L7201 IND_MMD-06CZ mlb[65C4] C70-6L R1890 RES_201 mlb[17D1]
DZ6006 SUPPR_TRANSIENT1_SOD mlb[57C5] L7251 IND_PIMB065T-SM mlb[65B4] Q6760 TRA_MOSFET_PCHN_8P4_ mlb[61B2] R1891 RES_201 mlb[17A8]
882 L7302 IND_PIMB042T-COMBO mlb[66D5] 23V1K-SM R1892 RES_201 mlb[17A7]
DZ6050 SUPPR_TRANSIENT1_402 mlb[57A5] L7330 IND_PIMB103E-SM-1 mlb[66C3] Q6821 TRA_SSM3K15FV_SOD-VE mlb[62A3] R1893 RES_201 mlb[17A7]
DZ6051 SUPPR_TRANSIENT1_SOD mlb[57A7] L7500 IND_PCMB063T-MMD06CZ mlb[68D5] SM-HF R1894 RES_201 mlb[17A7]
882 -SM Q6822 TRA_SINGLE_MOSFET_PC mlb[62B1] R1895 RES_201 mlb[17A7]
DZ6052 SUPPR_TRANSIENT1_402 mlb[57A5] L7501 IND_PIMA104E-SM-1 mlb[68D3] HN_SOT-23-HF R1896 RES_201 mlb[17A7]
DZ6053 SUPPR_TRANSIENT1_402 mlb[57A5] L7521 IND_PIMA104E-SM-1 mlb[68C3] Q6825 TRA_2N7002DW_SOT-363 mlb[62A2 62A3] R1897 RES_201 mlb[17A6]
DZ6054 SUPPR_TRANSIENT1_SOD mlb[57A6] L7601 IND_PIMA104E-SM-1 mlb[69C4] Q6850 TRA_NMOSFET_NPN_8P_D mlb[62C7] R1900 RES_201 mlb[18D8]
882 L7602 IND_PIMB042T-COMBO mlb[69D3] FN2015H4-8 R1905 RES_201 mlb[18D8]
DZ6055 SUPPR_TRANSIENT1_SOD mlb[57A6] L7730 IND_PIMB104T-SM mlb[70C3] Q7100 TRA_DUAL_MOSFET_NCHN mlb[64C4] R1909 RES_201 mlb[18B7]
882 L7860 IND_2520 mlb[71D6] 9_WPAK2 R1915 RES_201 mlb[18B5]
F4300 FUSE_603 mlb[41D3] L9130 IND_0402 mlb[75C7] Q7330 TRA_MOSFET_NCHN_5P1_ mlb[66C4] R1920 RES_201 mlb[18C8]
J0900 TP1_SM-TP3P4X1P8-TOP mlb[9B5] L9170 IND_0402 mlb[75C2] HVSON-3333 R1921 RES_201 mlb[18A4]

B J0901
J2500
TP1_SM-TP3P4X1P8-TOP
CON_F60ST_D_SM1_F-ST
mlb[9B5]
mlb[24D6]
L9372
L9373
IND_0201-1
IND_0201-1
mlb[77D4]
mlb[77D4]
Q7335 TRA_MOSFET_NCHN_5P5_
HVSON-333
mlb[66C4] R1922
R1924
RES_201
RES_201
mlb[18A4]
mlb[18A4] B
-SM L9382 IND_0201-1 mlb[77D4] Q7503 TRA_DUAL_MOSFET_NCHN mlb[68D5] R1925 RES_201 mlb[18A7]
J2800 BATTERY_2P_SM mlb[27D8] L9383 IND_0201-1 mlb[77D4] 9_WPAK R1951 RES_201 mlb[18B4]
J3100 CON_F408RT_4MT_DDR3D mlb[30D6] L9400 IND_0603 mlb[78C5] Q7523 TRA_DUAL_MOSFET_NCHN mlb[68C5] R1980 RES_201 mlb[18B5]
IMM_SM1_F-RT-SM L9408 IND_0603 mlb[78A2] 9_WPAK R1981 RES_201 mlb[18C5]
J3100 CON_F408RT_4MT_DDR3D mlb[31D6] L9498 IND_0603 mlb[78B6] Q7603 TRA_DUAL_MOSFET_NCHN mlb[69C5] R1982 RES_201 mlb[18A7]
IMM_SM1_F-RT-SM L9499 IND_0603 mlb[78A6] 9_WPAK R1983 RES_201 mlb[18A7]
J3500 CON_F16RT_4MT_SDCARD mlb[34C2] L9810 IND_0402 mlb[80B6] Q7730 TRA_DUAL_MOSFET_NCHN mlb[70C4] R1985 RES_201 mlb[18A7]
_S_TH_F-RT-TH L9811 IND_0402 mlb[80A6] 9_WPAK2 R1986 RES_201 mlb[18B6]
J3601 CON_F30ST_D4MT_SM_F- mlb[35D6] L9830 IND_SM-1 mlb[80D2] Q9320 TRA_SSM3K15FV_SOD-VE mlb[77A4] R1991 RES_201 mlb[18A5]
ST-SM L9841 IND_0402 mlb[80A6] SM-HF R2010 RES_201 mlb[19D7]
J3800 CON_RJ45_8RT_D4MT_TH mlb[36C1] L9890 FILTER_4P_ACM2012H mlb[80D7] Q9415 TRA_SSM3K15FV_SOD-VE mlb[78C4] R2011 RES_201 mlb[19D7]
2_F-R-TH L9891 FILTER_4P_ACM2012H mlb[80C7] SM-HF R2012 RES_201 mlb[19D7]
J4300 CON_F9RT_D4MT_1394B_ mlb[41C1] L9892 FILTER_4P_ACM2012H mlb[80C7] Q9420 TRA_2N7002DW_SOT-363 mlb[78C6 78C6] R2013 RES_201 mlb[19D7]
TH_F-RT-TH L9893 FILTER_4P_ACM2012-SM mlb[80B7] R0600 RES_402 mlb[6D3] R2014 RES_201 mlb[19D7]
J4401 CON_F16ST_D_SM_F-ST- mlb[42D6] LED0600 LED_2.0X1.25MM-SM mlb[6C3] R0602 RES_402 mlb[6D2] R2016 RES_201 mlb[19D7]
SM-J40 LED0602 LED_2.0X1.25MM-SM mlb[6C2] R0603 RES_402 mlb[6D1] R2017 RES_201 mlb[19D7]
J4410 CON_F16ST_D_SM_F-ST- mlb[42D3] LED0603 LED_2.0X1.25MM-SM mlb[6C1] R0605 RES_402 mlb[6C1] R2018 RES_201 mlb[19D7]
SM-J40 LED0605 LED_2X125-SM mlb[6B1] R0615 RES_402 mlb[6B2] R2030 RES_201 mlb[19D7]
J4600 CON_F4RT_USB_S2MT_TH mlb[43D1] Q0603 TRA_SSM3K15FV_SOD-VE mlb[6C2] R0616 RES_402 mlb[6B3] R2031 RES_201 mlb[19D7]
_F-RT-TH SM-HF R1010 RES_402 mlb[10D5] R2052 RES_201 mlb[19A7]
J4610 CON_F4RT_USB_S2MT_TH mlb[43C1] Q0605 TRA_NMOSFET_NPN_6P2_ mlb[6B2 6B2] R1020 RES_402 mlb[10B2] R2053 RES_201 mlb[19A7]
_F-RT-TH SOT-563 R1021 RES_402 mlb[10B2] R2054 RES_201 mlb[19A6]
J4620 CON_F4RT_USB_S2MT_TH mlb[43B4] Q2520 TRA_SSM3K15FV_SOD-VE mlb[24B5] R1022 RES_402 mlb[10B2] R2060 RES_201 mlb[19C3]
_F-RT-TH SM-HF R1023 RES_402 mlb[10B3] R2061 RES_201 mlb[19C3]
J4630 CON_F4RT_USB_S2MT_TH mlb[43A3] Q2530 TRA_PNP_SOT323_SOT32 mlb[24C1] R1030 RES_402 mlb[10C8] R2062 RES_201 mlb[19C3]
_F-RT-TH 3 R1040 RES_402 mlb[10A7] R2064 RES_201 mlb[19C3]
J4800 CON_M5RT_S2MT_SMA_M- mlb[45D2] Q2550 TRA_SSM3K15FV_SOD-VE mlb[24B3] R1041 RES_402 mlb[10A6] R2065 RES_201 mlb[19C2]
RT-SM SM-HF R1042 RES_402 mlb[10A8] R2067 RES_201 mlb[19C2]
J4801 CON_M2RT_S2MT_SM_M-R mlb[45A4] Q2640 TRA_2N7002DW_SOT-363 mlb[25B2 25B1] R1043 RES_402 mlb[10A6] R2068 RES_201 mlb[19C2]
T-SM Q2900 TRA_DUAL_SSM6N15FE_S mlb[28B6 28C6] R1044 RES_402 mlb[10A8] R2069 RES_201 mlb[19C2]
A J5100 CON_M30ST_D4MT_SM_M-
ST-SM
mlb[48D4]
Q2905
OT563
TRA_DUAL_SSM6N15FE_S mlb[28C6 28C6]
R1045
R1046
RES_402
RES_402
mlb[10A7]
mlb[10A7]
R2070
R2111
RES_201
RES_201
mlb[19B4]
mlb[20D8]
A
J6000 CON_F21RT_4MT_AUDIO_ mlb[57C8] OT563 R1047 RES_402 mlb[10A7] R2112 RES_201 mlb[20D7]
SPDIF_TH1_F-RT-TH Q2910 TRA_DUAL_SSM6N15FE_S mlb[28B6 28B6] R1049 RES_402 mlb[10A6] R2113 RES_201 mlb[20D7]
J6001 CON_M2RT_S2MT_SM_M-R mlb[57B1] OT563 R1064 RES_402 mlb[10D4] R2114 RES_201 mlb[20A7]
T-SM Q2915 TRA_DUAL_SSM6N15FE_S mlb[28B7 28B6] R1065 RES_402 mlb[10C4] R2115 RES_201 mlb[20A7]
J6500 CON_M4RT_S2MT_SM_M-R mlb[60C2] OT563 R1070 RES_402 mlb[10D4] R2116 RES_201 mlb[20A3]
T-SM Q2920 TRA_NMOSFET_NPN_6P2_ mlb[28C2 28C3] R1071 RES_402 mlb[10C4] R2117 RES_201 mlb[20A6]
J7900 CON_M9RT_S_SM_M-RT-S mlb[72B8] SOT-563 R1100 RES_402 mlb[11C5] R2118 RES_201 mlb[20A2]
M Q2950 TRA_DUAL_SSM6N15FE_S mlb[28B2 28B3] R1101 RES_402 mlb[11C6] R2130 RES_201 mlb[20A3]
J9400 CON_F20RT_D16MT_DSPL mlb[78B3] OT563 R1102 RES_402 mlb[11C5] R2140 RES_201 mlb[20D3]
YPRT_TH_F-RT-TH Q3530 TRA_SSM3K15FV_SOD-VE mlb[34B5] R1103 RES_402 mlb[11C6] R2150 RES_201 mlb[20D3]
J9830 CON_F19RT_17MT_HDMI_ mlb[80C3] SM-HF R1104 RES_402 mlb[11C5] R2155 RES_201 mlb[20D3]
F-RT-SM Q3650 TRA_MOSFET_PCHN_8P4_ mlb[35C3] R1111 RES_402 mlb[11B4] R2156 RES_201 mlb[20C3]

509

8 7 6 5 4 3 2 1
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 8 7 6 5 4 3 2 1
R6881 RES_402 mlb[62C3] R7861 RES_402 mlb[71C5] R9740 RES_402 mlb[79B5] U5365 INA210_SC70 mlb[50A7]
R6886 RES_402 mlb[62C2] R7862 RES_402 mlb[71C5] R9741 RES_402 mlb[79B5] U5375 INA210_SC70 mlb[50C7]
R6887 RES_402 mlb[62C3] R7863 RES_402 mlb[71D5] R9750 RES_402 mlb[79B7] U5400 INA210_SC70 mlb[51C7]
R6888 RES_402 mlb[62C2] R7865 RES_402 mlb[71C7] R9753 RES_402 mlb[79C7] U5403 INA214_SC70 mlb[51D7]
R7101 RES_402 mlb[64C5] R7870 RES_402 mlb[71B7] R9754 RES_402 mlb[79B7] U5500 EMC1428_QFN mlb[52D6]
R7102 RES_603 mlb[64C5] R7920 RES_402 mlb[72C6] R9755 RES_402 mlb[79C7] U5535 EMC1414_MSOP10_MSOP mlb[52B6]
R7103 RES_402 mlb[64B6] R8000 RES_201 mlb[73B4] R9756 RES_402 mlb[79B6] U5600 CS4206B_QFN mlb[53D5]
R7104 RES_402 mlb[64C7] R8001 RES_201 mlb[73B4] R9757 RES_402 mlb[79C6] U5601 MAX8840_UDFN mlb[53A5]
R7120 RES_603 mlb[64C3] R9010 RES_402 mlb[74D5] R9758 RES_402 mlb[79B6] U5800 AMP_MAX97220_TQFN mlb[55C4]
R7130 RES_402 mlb[64C4] R9011 RES_402 mlb[74D5] R9759 RES_402 mlb[79C6] U5900 AUDIO_MAX98300_WLP mlb[56C5]
R7140 RES_SENSE_0612 mlb[64C2] R9021 RES_402 mlb[74C6] R9761 RES_402 mlb[79C6] U6106 CD3282A1_WCSP mlb[58D3]
R7141 RES_402 mlb[64B3] R9022 RES_402 mlb[74C6] R9762 RES_402 mlb[79B3] U6400 FLASH_MX25L6406E_SOI mlb[59C5]
R7142 RES_402 mlb[64B3] R9023 RES_402 mlb[74C6] R9763 RES_402 mlb[79C3] C
R7146 RES_402 mlb[64C6] R9025 RES_402 mlb[74C6] R9764 RES_402 mlb[79B3] U6701 SLG5AP021_TDFN mlb[61B7]

D R7147
R7148
RES_402
RES_402
mlb[64B6]
mlb[64B6]
R9029
R9030
RES_402
RES_402
mlb[74B6]
mlb[74B6]
R9765
R9766
RES_402
RES_402
mlb[79C3]
mlb[79B3]
U6860
U7100
ISL88042_TDFN
ISL95870A_UTQFN
mlb[62A7]
mlb[64C5]
D
R7160 RES_603 mlb[64B2] R9031 RES_402 mlb[74A6] R9768 RES_402 mlb[79B3] U7201 SC414_MLPQ mlb[65D6]
R7202 RES_402 mlb[65D6] R9032 RES_402 mlb[74A3] R9769 RES_402 mlb[79C3] U7251 IR3859MPBF_QFN mlb[65B6]
R7203 RES_603 mlb[65D6] R9040 RES_402 mlb[74A7] R9810 RES_402 mlb[80B5] U7300 TPS51916_QFN mlb[66C6]
R7204 RES_402 mlb[65D7] R9041 RES_402 mlb[74A7] R9811 RES_402 mlb[80B5] U7400 ISL6364_QFN mlb[67C4]
R7205 RES_402 mlb[65C6] R9051 RES_402 mlb[74D2] R9812 RES_402 mlb[80B5] U7501 ISL6620A_QFN mlb[68D7]
R7208 RES_402 mlb[65C5] R9055 RES_603 mlb[74C3] R9813 RES_402 mlb[80A5] U7521 ISL6609_QFN1 mlb[68C7]
R7209 RES_402 mlb[65C5] R9085 RES_402 mlb[74A3] R9814 RES_402 mlb[80A5] U7601 ISL6620A_QFN mlb[69C7]
R7210 RES_402 mlb[65C4] R9090 RES_402 mlb[74C8] RT7403 THERMISTER_0603 mlb[67D4] U7700 ISL95870_UTQFN mlb[70C6]
R7211 RES_402 mlb[65C4] R9091 RES_402 mlb[74C8] RT7404 THERMISTER_0603 mlb[67A7] U7860 TPS54218_QFN mlb[71D7]
R7214 RES_402 mlb[65C7] R9092 RES_402 mlb[74C6] S9200 SHLD_1P_SM mlb[76D5] U7870 LREG_TPS720XX_DRV_SO mlb[71B6]
R7215 RES_402 mlb[65C5] R9093 RES_402 mlb[74C6] S9201 SHLD_1P_SM mlb[76D3] N
R7251 RES_603 mlb[65B6] R9095 RES_402 mlb[74C2] S9202 SHLD_1P_SM mlb[76D2] U9000 T29_FCBGA mlb[74D4]
R7254 RES_402 mlb[65B6] R9096 RES_402 mlb[74C2] S9203 SHLD_1P_SM mlb[76D4] U9000 T29_FCBGA mlb[75D5]
R7255 RES_402 mlb[65A6] R9098 RES_402 mlb[74C2] S9204 SHLD_1P_SM mlb[76D3] U9090 EEPROM_M95320_MLP8_M mlb[74C7]
R7256 RES_402 mlb[65A5] R9099 RES_402 mlb[74B3] S9205 SHLD_1P_SM mlb[76D5] LP
R7257 RES_402 mlb[65A4] R9120 RES_402 mlb[75C7] S9206 SHLD_1P_SM mlb[76D3] U9200 SLG4AP016_TDFN mlb[76C7]
R7258 RES_402 mlb[65A4] R9150 RES_402 mlb[75D2] S9207 SHLD_1P_SM mlb[76D2] U9210 TPS22924_CSP mlb[76B7]
R7259 RES_402 mlb[65A4] R9160 RES_402 mlb[75C2] S9208 SHLD_1P_SM mlb[76D4] U9215 TPS22924_CSP mlb[76A7]
R7260 RES_402 mlb[65A4] R9203 RES_402 mlb[76C7] S9209 SHLD_1P_SM mlb[76D3] U9216 TPS22924_CSP mlb[76A7]
R7261 RES_402 mlb[65A3] R9207 RES_402 mlb[76C6] S9210 SHLD_1P_SM mlb[76D5] U9310 PS8301_A2_QFN mlb[77C6]
R7301 RES_603 mlb[66C7] R9210 RES_402 mlb[76A7] S9211 SHLD_1P_SM mlb[76D3] U9330 LPC1112A_HVQFN25_HVQ mlb[77A6]
R7305 RES_402 mlb[66B7] R9215 RES_402 mlb[76C7] S9212 SHLD_1P_SM mlb[76D2] FN25
R7310 RES_402 mlb[66B7] R9221 RES_201 mlb[76B2] S9213 SHLD_1P_SM mlb[76D4] U9359 SN74LVC1G04_SC70 mlb[77C3]
R7320 RES_402 mlb[66B8] R9222 RES_201 mlb[76B2] S9214 SHLD_1P_SM mlb[76D3] U9390 CBTL04DP081_HVQFN mlb[77B2]
R7321 RES_402 mlb[66B8] R9223 RES_201 mlb[76B2] S9215 SHLD_1P_SM mlb[76D5] U9401 ISL80101B_DFN mlb[78D7]
R7330 RES_402 mlb[66C5] R9224 RES_201 mlb[76B2] S9216 SHLD_1P_SM mlb[76D3] U9410 SN1010017_QFN mlb[78D2]
R7331 RES_603 mlb[66C4] R9225 RES_201 mlb[76A4] S9217 SHLD_1P_SM mlb[76D2] U9420 MC74VHC1G08_SC70-HF mlb[78C7]
R7340 RES_SENSE_0612 mlb[66C2] R9226 RES_201 mlb[76A2] S9218 SHLD_1P_SM mlb[76D4] U9740 PS8171_QFN mlb[79D4]
R7405 RES_402 mlb[67D3] R9227 RES_201 mlb[76A2] S9219 SHLD_1P_SM mlb[76D3] U9800 SWI_TPS2051B_SOT23 mlb[80D3]
R7406 RES_402 mlb[67D3] R9228 RES_201 mlb[76B4] S9220 SHLD_1P_SM mlb[76C5] XW0700 SHORT_SM mlb[7D8]

C R7408
R7418
RES_402
RES_402
mlb[67C2]
mlb[67B3]
R9230
R9231
RES_201
RES_201
mlb[76B4]
mlb[76B4]
S9221
S9222
SHLD_1P_SM
SHLD_1P_SM
mlb[76C3]
mlb[76C2]
XW0701
XW4020
SHORT_SM
SHORT_SM
mlb[7C8]
mlb[38C6]
C
R7419 RES_402 mlb[67B3] R9300 RES_402 mlb[77B5] S9223 SHLD_1P_SM mlb[76C4] XW4300 SHORT_SM mlb[41D3]
R7420 RES_402 mlb[67B3] R9301 RES_402 mlb[77B5] S9224 SHLD_1P_SM mlb[76C3] XW4301 SHORT_SM mlb[41D8]
R7422 RES_402 mlb[67B3] R9302 RES_402 mlb[77B8] S9225 SHLD_1P_SM mlb[76C5] XW4302 SHORT_SM mlb[41D7]
R7424 RES_402 mlb[67A3] R9308 RES_402 mlb[77C7] S9226 SHLD_1P_SM mlb[76C3] XW4900 SHORT_SM mlb[46C2]
R7426 RES_402 mlb[67A2] R9309 RES_402 mlb[77D7] S9227 SHLD_1P_SM mlb[76C2] XW5320 SHORT_SM mlb[50C3]
R7427 RES_805 mlb[67D4] R9310 RES_402 mlb[77B8] S9228 SHLD_1P_SM mlb[76C4] XW5322 SHORT_SM mlb[50A7]
R7428 RES_402 mlb[67D7] R9311 RES_402 mlb[77B8] S9229 SHLD_1P_SM mlb[76C3] XW5330 SHORT_SM mlb[50B3]

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R7429 RES_402 mlb[67C7] R9312 RES_402 mlb[77B8] SDF3600 PCB_STANDOFF mlb[35A7] XW5500 SHORT_SM mlb[52C7]
R7432 RES_402 mlb[67C7] R9318 RES_402 mlb[77B7] SDF3601 PCB_STANDOFF mlb[35A7] XW5501 SHORT_SM mlb[52C7]
R7433 RES_402 mlb[67C7] R9319 RES_402 mlb[77B8] SDF3602 PCB_STANDOFF mlb[35A6] XW5504 SHORT_SM mlb[52C6]
R7434 RES_402 mlb[67C8] R9330 RES_402 mlb[77A8] SL9202 SLOT_TH-SP mlb[76D6] XW5505 SHORT_SM mlb[52C6]
R7435 RES_402 mlb[67B8] R9334 RES_402 mlb[77A4] SL9203 SLOT_TH-SP mlb[76D6] XW5600 SHORT_SM mlb[53A6]
R7440 RES_402 mlb[67C5] R9335 RES_402 mlb[77A5] T3801 XFR_TLA_6T213LF_SM mlb[36C5] XW5601 SHORT_SM mlb[53A6]
R7441 RES_402 mlb[67C5] R9336 RES_402 mlb[77A5] T3802 XFR_TLA_6T213LF_SM mlb[36C5] XW5610 SHORT_SM mlb[53D2]
R7442 RES_402 mlb[67C5] R9338 RES_402 mlb[77A4] TP4700 TP_TH-TP30 mlb[44C3] XW5800 SHORT_SM mlb[55B3]
R7443 RES_402 mlb[67C6] R9339 RES_402 mlb[77A3] TP4701 TP_TH-TP30 mlb[44C3] XW6180 SHORT_SM mlb[58B2]
R7444 RES_402 mlb[67B5] R9350 RES_201 mlb[77C5] TP4702 TP_TH-TP30 mlb[44C3] XW7100 SHORT_SM mlb[64B5]
R7445 RES_402 mlb[67B8] R9351 RES_201 mlb[77C5] TP4709 TP_TH-TP30 mlb[44C3] XW7201 SHORT_SM mlb[65C5]
R7446 RES_402 mlb[67B6] R9352 RES_201 mlb[77C5] U1000 SANDY_1023BGA_BGA mlb[10D3 10D7] XW7202 SHORT12LP25_WITH_ALT mlb[65C4]
R7447 RES_402 mlb[67B6] R9353 RES_201 mlb[77C4] U1000 SANDY_1023BGA_BGA mlb[11C4] S_SHORT-12L-0.25MM-S
R7448 RES_402 mlb[67B5] R9354 RES_201 mlb[77C5] U1000 SANDY_1023BGA_BGA mlb[12D3 12D7] M
R7449 RES_402 mlb[67B5] R9355 RES_201 mlb[77C5] U1000 SANDY_1023BGA_BGA mlb[13D3 13D8] XW7251 SHORT_SM mlb[65A6]
R7450 RES_402 mlb[67B5] R9360 RES_201 mlb[77C2] U1000 SANDY_1023BGA_BGA mlb[14D5 14D7] XW7300 SHORT_SM mlb[66B6]
R7451 RES_402 mlb[67B4] R9361 RES_201 mlb[77C2] U1800 COUGARPOINT_MOBILE_F mlb[17D3 17D7] XW7335 SHORT12LP25_WITH_ALT mlb[66B3]
R7452 RES_402 mlb[67B6] R9364 RES_201 mlb[77C2] CBGA S_SHORT-12L-0.25MM-S
R7454 RES_402 mlb[67A5] R9365 RES_201 mlb[77C2] U1800 COUGARPOINT_MOBILE_F mlb[18D3 18D7] M
R7455 RES_402 mlb[67B3] R9372 RES_201 mlb[77D3] CBGA XW7360 SHORT12LP25_WITH_ALT mlb[66C5]
R7456 RES_402 mlb[67C6] R9373 RES_201 mlb[77D3] U1800 COUGARPOINT_MOBILE_F mlb[19D5] S_SHORT-12L-0.25MM-S
R7457 RES_402 mlb[67D4] R9374 RES_201 mlb[77D1] CBGA M
R7458 RES_402 mlb[67B4] R9375 RES_201 mlb[77D1] U1800 COUGARPOINT_MOBILE_F mlb[20D5] XW7401 SHORT12LP25_WITH_ALT mlb[67C5]

B R7459
R7460
RES_402
RES_402
mlb[67A8]
mlb[67D7]
R9382
R9383
RES_201
RES_201
mlb[77D3]
mlb[77D3] U1800
CBGA
COUGARPOINT_MOBILE_F mlb[21D7 21C3]
S_SHORT-12L-0.25MM-S
M B
R7461 RES_402 mlb[67D7] R9384 RES_201 mlb[77C1] CBGA XW7402 SHORT12LP25_WITH_ALT mlb[67A7]
R7462 RES_402 mlb[67D7] R9385 RES_201 mlb[77C1] U1800 COUGARPOINT_MOBILE_F mlb[22D3 22D6] S_SHORT-12L-0.25MM-S
R7463 RES_402 mlb[67D7] R9392 RES_402 mlb[77B4] CBGA M
R7464 RES_402 mlb[67D7] R9393 RES_402 mlb[77B4] U2150 MC74VHC1G08_SC70-HF mlb[20C3] XW7420 SHORT_SM mlb[67D8]
R7465 RES_402 mlb[67D7] R9396 RES_402 mlb[77B3] U2151 MC74VHC1G08_SC70-HF mlb[20B3] XW7423 SHORT_SM mlb[67A8]
R7466 RES_402 mlb[67A7] R9397 RES_402 mlb[77B3] U2152 MC74VHC1G08_SC70-HF mlb[20B3] XW7430 SHORT_SM mlb[67D8]
R7467 RES_402 mlb[67A7] R9398 RES_402 mlb[77B1] U2520 SN74LV4066ARGYR_QFN1 mlb[24A7 24A7 24B7 24B7] XW7433 SHORT_SM mlb[67A8]
R7468 RES_402 mlb[67A7] R9399 RES_402 mlb[77B2] U2600 USB2513B_QFN mlb[25D6] XW7501 SHORT_SM mlb[68D3]
R7469 RES_402 mlb[67A7] R9401 RES_201 mlb[78A5] U2650 USB2513B_QFN mlb[25B6] XW7502 SHORT_SM mlb[68D3]
R7470 RES_402 mlb[67A7] R9402 RES_201 mlb[78A5] U2700 SLG3NB148_TQFN mlb[26D5] XW7521 SHORT_SM mlb[68C3]
R7471 RES_402 mlb[67A7] R9403 RES_201 mlb[78B6] U2840 SN74LVC1G17_SOT553_S mlb[27C3] XW7522 SHORT_SM mlb[68C3]
R7479 RES_402 mlb[67A5] R9404 RES_201 mlb[78B6] OT-553 XW7700 SHORT_SM mlb[70B6]
R7480 RES_402 mlb[67B2] R9407 RES_201 mlb[78B2] U2850 MC74VHC1G08_SC70-HF mlb[27A7] XW7801 SHORT_SM mlb[71C6]
R7481 RES_402 mlb[67A3] R9408 RES_201 mlb[78A2] U2860 MC74VHC1G08_SC70-HF mlb[27A6] Y2600 CRYSTAL_5X3.2X1.4-SM mlb[25D7]
R7489 RES_402 mlb[67C5] R9410 RES_402 mlb[78C1] U2880 SN74LVC1G07_SC70 mlb[27C3] Y2650 CRYSTAL_5X3.2X1.4-SM mlb[25B7]
R7495 RES_402 mlb[67D3] R9411 RES_402 mlb[78C1] U3400 DAC5574_MSOP mlb[33D6] Y2705 CRYSTAL_4PIN_SM-3.2X mlb[26C7]
R7499 RES_402 mlb[67B5] R9412 RES_402 mlb[78C3] U3401 PCA9557RGY_QFN mlb[33C6] 2.5MM
R7501 RES_402 mlb[68D3] R9416 RES_402 mlb[78D3] U3402 OPAMP_MAX4253_UCSP_U mlb[33D3 33C3] Y2810 CRYSTAL_4PIN_SM-2 mlb[27C6]
R7504 RES_402 mlb[68D6] R9417 RES_402 mlb[78D3] CSP Y4190 OSC_4PIN_TSNC_SM mlb[39C1]
R7505 RES_603 mlb[68D7] R9418 RES_603 mlb[78D1] U3403 OPAMP_MAX4253_UCSP_U mlb[33B3 33C3] Y5010 CRYSTAL_5X3.2-SM mlb[47B7]
R7506 RES_603 mlb[68D4] R9421 RES_402 mlb[78D6] CSP ZH0930 HOLE_VIA mlb[9B8]
R7521 RES_402 mlb[68B3] R9422 RES_402 mlb[78D7] U3404 OPAMP_MAX4253_UCSP_U mlb[33B3 33A3] ZH0931 HOLE_VIA mlb[9B8]
R7524 RES_402 mlb[68C6] R9423 RES_402 mlb[78D6] CSP ZH0932 HOLE_VIA mlb[9A8]
R7525 RES_603 mlb[68C7] R9424 RES_402 mlb[78D5] U3500 SWI_TPS2065_DGN mlb[34D3] ZH0933 HOLE_VIA mlb[9A8]
R7526 RES_603 mlb[68C4] R9425 RES_402 mlb[78D5] U3530 SLG4AP014_TDFN mlb[34B5] ZH0934 HOLE_VIA mlb[9A8]
R7601 RES_603 mlb[69C7] R9426 RES_402 mlb[78C6] U3535 SLG4AP014_TDFN mlb[34B5] ZH0935 HOLE_VIA mlb[9B8]
R7604 RES_402 mlb[69C6] R9430 RES_402 mlb[78C8] U3640 SLG4AP016_TDFN mlb[35B3] ZH0936 HOLE_VIA mlb[9A8]
R7606 RES_603 mlb[69C4] R9431 RES_1206 mlb[78D8] U3900 BCM57765_1_QFN-8X8 mlb[37C5] ZH0937 HOLE_VIA mlb[9A8]
R7608 RES_402 mlb[69C3] R9432 RES_1206 mlb[78D8] U3990 FLASH_AT45DB011D_SOI mlb[37A7] ZH0938 HOLE_VIA mlb[9A8]
R7620 RES_SENSE_0612 mlb[69C3] R9441 RES_201 mlb[78A6] C-8S1 ZH0940 HOLE_VIA mlb[9B7]
A R7701
R7702
RES_402
RES_603
mlb[70C6]
mlb[70C5]
R9450
R9451
RES_603
RES_201
mlb[78D4]
mlb[78A7]
U4100
U4200
XIO2211_1SYM_BGA
LREG_TPS799195_SON
mlb[39C5]
mlb[40D7]
ZH0941
ZH0942
HOLE_VIA
HOLE_VIA
mlb[9B7]
mlb[9A7]
A
R7703 RES_402 mlb[70B6] R9452 RES_201 mlb[78A7] U4300 COMPARATOR_LM393_SOI mlb[41A7 41A4] ZH0943 HOLE_VIA mlb[9A7]
R7704 RES_402 mlb[70C8] R9470 RES_201 mlb[78B2] -HF ZH0944 HOLE_VIA mlb[9A7]
R7705 RES_402 mlb[70B8] R9471 RES_201 mlb[78B2] U4600 SWI_TPS2561_SON mlb[43C7] ZH0945 HOLE_VIA mlb[9B7]
R7730 RES_402 mlb[70C5] R9472 RES_201 mlb[78A2] U4601 SWI_TPS2561_SON mlb[43D7] ZH0946 HOLE_VIA mlb[9A7]
R7731 RES_603 mlb[70B4] R9473 RES_201 mlb[78A2] U4650 PI3USB102_TQFN mlb[43D4] ZH0947 HOLE_VIA mlb[9A7]
R7740 RES_SENSE_0612 mlb[70C3] R9494 RES_201 mlb[78B7] U4700 CY7C63833_QFN mlb[44C5] ZH0948 HOLE_VIA mlb[9A7]
R7741 RES_402 mlb[70B3] R9495 RES_201 mlb[78B7] U4900 H8S2117RP_TLP-145V mlb[46D3 46B7 46D7] ZH0949 HOLE_VIA mlb[9A7]
R7742 RES_402 mlb[70B3] R9498 RES_201 mlb[78B8] U5010 VREF_SN0903048_DFN mlb[47D7] ZH0950 HOLE_VIA mlb[9B7]
R7744 RES_402 mlb[70C7] R9499 RES_201 mlb[78B8] U5300 INA210_SC70 mlb[50D7] ZH0951 HOLE_VIA mlb[9B7]
R7745 RES_402 mlb[70B7] R9724 RES_402 mlb[79A6] U5305 INA210_SC70 mlb[50C7] ZH0952 HOLE_VIA mlb[9A7]
R7760 RES_603 mlb[70B1] R9725 RES_402 mlb[79A7] U5340 OPAMP_OPA2333_DFN mlb[50B3 50D3] ZH0953 HOLE_VIA mlb[9A7]
R7860 RES_402 mlb[71C6] R9726 RES_402 mlb[79A5] U5360 INA210_SC70 mlb[50B7] ZH0954 HOLE_VIA mlb[9A7]

511

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
ZH0955 HOLE_VIA mlb[9B6]
ZH0956 HOLE_VIA mlb[9B6]
ZH0957 HOLE_VIA mlb[9A6]
ZH0958 HOLE_VIA mlb[9A6]
ZP0900 POGO_PIN_1P_SM mlb[9D4]
ZP0901 POGO_PIN_1P_SM mlb[9D4]
ZP0902 POGO_PIN_1P_SM mlb[9D3]
ZP0903 POGO_PIN_1P_SM mlb[9D3]
ZP0907 POGO_PIN_1P_SM mlb[9D1]
ZP0920 POGO_PIN_1P_SM mlb[9C3]
ZP0921 POGO_PIN_1P_SM mlb[9C3]
ZP0922 POGO_PIN_1P_SM mlb[9C2]
ZT0840 PCB_STANDOFF mlb[8C1]
ZT0841 PCB_STANDOFF mlb[8C1]

D ZT0910
ZT0911
BOSS
BOSS
mlb[9C8]
mlb[9B8]
D
ZT0912 BOSS mlb[9C7]
ZT0913 BOSS mlb[9B7]
ZT0914 BOSS mlb[9B8]
ZT0915 BOSS mlb[9B7]
ZT0940 PCB_STANDOFF mlb[9C8]
ZT0941 PCB_STANDOFF mlb[9C6]
ZT0960 PCB_STANDOFF mlb[9D8]
ZT0961 PCB_STANDOFF mlb[9D6]
ZT0962 PCB_STANDOFF mlb[9D8]
ZT0966 PCB_STANDOFF mlb[9D7]
ZT0970 PCB_STANDOFF mlb[9C3]

C C

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B B

A A

512

8 7 6 5 4 3 2 1