Design of Lower-Error and Area-Efficient Sine

Function Generators for Image Encryptions Using

Logarithmic Number Systems (LNS)
2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT) | 979-8-3503-3416-6/23/$31.00 ©2023 IEEE | DOI: 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134022

Tso-Bing Juang, Wei-Cheng Lin, Guan-Zhong Lin, and Shi-Jie Jian

Department of Computer Science and Information Engineering
National Pingtung University
Pingtung City, Taiwan
[email protected]

Abstract— In order to protect the privacy of images, sine Compared to conventional binary implementations, in [3-
functions can be used for the encryption of images. However, the 5], the logarithmic number systems (LNS) based methods are
operations for generating sine functions are becoming the area- analyzed which are beneficial for calculating the complicated
consuming bottleneck for image encrypt/decrypt applications. In operations, such as multiplication, division, powering, etc.,
this work, lower-error and area-efficient sine function generators
where the corresponding LNS-based architecture for
are proposed using logarithmic number system (LNS).
Expressing the sine functions using LNS-based representations, performing complicated operations is shown in Fig. 1, where
we can avoid time-consuming operations. Synthesis results show the binary numbers for x and y are converted into the
that our proposed generators are area efficient than conventional logarithmic representations and then corresponding
with lower errors. computations can be performed, finally the results are
converted back to the binary representations. For example, to
Keywords: Cryptograhy, computer arithmetic, logarithmic perform x/y, x and y should be converted to log2x and log2y in
number system (LNS), VLSI digital design. the first stage, and to perform subtraction to produce log2x-
log2y, finally to be converted to the anti-logarithmic value of
I. INTRODUCTION 2log 2 x −log 2 y = x / y .
Recently, due to the developments of cryptography, in [1]
the authors have been proposed the image encryption methods
to protect the privacy of images during transmission. The
methods are based on the sine curves with some control
parameters in the encrypt/decrypt processes. To produce the
encrypted images, sine function is called for 2×M×N times in
both confusion and diffusion phases, so as the same number of
times for using sine functions in image decryption, where M
and N is denoted as the number of pixels for the row and Fig.1: The architecture for LNS-based schemes for performing complicated
column of the plain image, respectively. Therefore, the sine operations [4]
function generations are the crucial components in the image
encrypt/decrypt stages, which motivates us to design the The rest of this paper is organized as follows. In Section II
lower-error and area-efficient sine function generators. we will review the LNS-based operations, and then our
The methods for sine function generation can be proposed LNS-based sine generations will be given in Section
III. Error analysis and synthesis results are shown in Section IV,
classified into three categories, including ROM based,
and Section V concludes the paper.
function based and iterative shift-and-add based ones. In ROM
based method, the outputs for sine functions can be obtained
by ROM access directly; however, as the bit-width of the II. REVIEW OF LNS-BASED SCHEMES AND THE
inputs increases, the area will become exponentially CORRESPONDING OPERATIONS
complicated which will not be suitable for implementations. In LNS-based schemes for performing complicated
Compared to the ROM based, the function based exploits the operations shown in Fig. 1, the core is to use
property of Taylor series expansions of sine functions and to binary/logarithmic conversions. In our implementations, the
calculate the output using complicated and time-consuming methods in [4-5] are applied, which have been reported as
multipliers and dividers. For the iterative shift-and-add simple, high-speed with lower-error and area efficiency.
method [2], the hardware is very simple that only contains Referred to Fig. 1, LOG2 units are to convert x and y into
adders with small amount of ROM to generate the sine logarithmic representations using Eq. (1) [4]. Anti-Log unit is
functions. However, it will take n iterations to complete for n- to convert the logarithmic results back into binary
bit accuracy, leading to time consuming. representations using Eq. (2) [5]. We can observe that the
operations in Eq. (1-2) consist only shift-and-add operations

979-8-3503-3416-6/23/$31.00
Authorized ©2023 IEEE
licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY WARANGAL. Downloaded on September 15,2024 at 14:32:01 UTC from IEEE2023 VLSI
Xplore. TSA apply.
Restrictions
 with some wired logic, leading simple and area-efficient IV. ERROR ANALYSIS AND SYNTHESIS RESULTS
implementations. The value x-k is denoted as the k-th bit of x We test the accuracy of our LNS-based sine function
after the point. generators given in Eq. (3-4) using Python® numpy modules
with 10,000,000 randomly inputs. Table I is the error analysis,
which shows that our method could produce sine functions
with tolerable errors, which will not compromise the quality of
(1) encrypted/decrypted images. The architecture in Fig. 2 is been
designed using Verilog Hardware Design Language and
synthesized by Synopsys, it can be seen that our proposed
method could achieve less delay and area consumptions.
(2)
TABLE I. ERROR ANALYSIS OF OUR PROPOSED LNS-BASED SINE GENERATORS.

III. PROPOSED LNS-BASED SINE FUNTION GENERATORS Values

According to Taylor series expansion, the sine function Maximum Error 0.06657
can be approximated in Eq. (3) with tolerable errors, where Minimum Error 0
each term can be obtained in Eq. (4) that the binary right shift Maximum Error Percent 14.60%
operations are used to avoid more complicated divisions.
Minimum Error Percent 0.0004%
x5 x3 x7 (3)
sin( x) ≅ ( x + ) − ( + ) Average Percent Errors 0.01108
5! 3! 7!
If we directly implement the above operations shown in
TABLE II. COMPARISONS OF OUR PROPOSED LNS-BASED SINE FUNCTION
Eq. (3), there required complicated computations including GENERATORS WITH PYTHON IMPLEMENTATIONS. (TSMC 0.18 µM
higher powering of the inputs and divisions. To make the TECHNOLOGY)
computations in Eq. (3) more feasible in LNS-based
Methods Area (µm2) Delay Power Average
operations, we re-write the second to the fourth terms as (mW) Percent
follows in Eq. (4), where the values in are factored out to Errors
perform right shift (>>) operations as possible. Python® - 0.3 µs @CPU - -
x3 x3 x3 speed is 3.4GHz
= = >> 1
3! 1× 2 × 3 3 Proposed 414328.72 44.09 ns 59.61 1.11%
x5 x5 x5 x5
= = = >> 3
5! 1× 2 × 3 × 4 × 5 3 × 5 × 8 15 V. CONCLUSIONS
x7 x7 x7 x7 (4)
= = = >> 4 In this paper we have proposed lower-error and area-
7! 1 × 2 × 3 × 4 × 5 × 6 × 7 45 × 7 × 16 45 × 7 efficient LNS-based sine generators, which can be used in
In order to achieve area-efficient implementations, the image encryption applications to perform fast encrypt/decrypt
operations are simplified based on LNS operations given in with less hardware consumptions compared to conventional
Fig. 1, the architecture is shown in Fig. 2, where three implementations using binary numbers.
multipliers and seven adders are required with five logarithmic
converters and three antilogarithmic converters. In addition, the REFERENCES
logarithmic conversions for constants 3, 7, 15 and 45 can be
[1] Sujit Kmar Das and Bibhas Chandra Dhara, “An Image Encryption
further be reduced by using the fixed values of the Technique using Sine Curve,” Proc. Ninth innternational Conference on
corresponding logarithmic conversions directly to save more Advances in Pattern Recognition (ICAPR), Dec. 2017.
area and delay. [2] P. K. Meher, J. Valls, T. –B. Juang, K. Sridharan, and K. Maharatna, “50
Years of CORDIC: Algorithmic, Architectures, and Applications,”IEEE
Transacions on Circuits and Systems Part I, Vol. 56, No. 6, pp.1893-
1907, June 2009.
[3] Behrooz Parhami, “Computing with Logarithmic Number System
Arithmetic: Implementation Methods and Performance Benefits,”
Computers & Electrical Engineering, Vol. 87 106800, pp. 1-15 , Oct.
2020.
[4] T.–B. Juang, P. K. Meher and K.-S. Jan, “High-Performance
Logarithmic Converters Using Novel Two-Region Bit-Level
Manipulation Schemes,” Proc. of VLSI-DAT (VLSI Symposium on
Design, Automation, and Testing), pp. 390-393, April 2011.
[5] T.-B. Juang, H.-L. Kuo and K.-S. Jan, “Lower-Error and Area-Efficient
Antilogarithmic Converters with Bit-Correction Schemes,” Journal of
the Chinese Institute of Engineers, Vol. 39, No. 1, pp. 57-63, Jan. 2016.

Fig. 2: The proposed architecture of LNS-based sine function generators

Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY WARANGAL. Downloaded on September 15,2024 at 14:32:01 UTC from IEEE Xplore. Restrictions apply.