nit-IIT Control Unit 3.1. Instrum mn Types The basic computer has 16-bit instruction register (IR) which can denote either memory reference or register reference or input-output instruction, ‘Memory Reference ~ These instructions refer to memory address as an operand. The other operand is always accumulator. Specifies 12-bit address, 3-bit opcode (other than 111) and 1-bit addressing mode for direct and indirect addressing. 6414 win ° 1 ‘opcone MEMORY ADORESS Register Reference — These instructions perform operations on registers rather than memory addresses, The IR(4 ~ 12) is 111 (differentiates it from memory reference) and IR(IS) is 0 (Gifferemtiates it from input/output instructions). The rest 12 bits specify register operation. 6 14 win o ° 44 REGISTER OPERATION Input/Output — These insimuctions are for communication between computer and outside environment. The IR(14 — 12) is 111 (differentiates it from memory reference) and IR(IS) is 1 (differentiates it from register reference instructions). The rest 12 bits specify 1/0 operation, aT a4 0 44 INPUTIOUTPUT OPERATION 3.2. Instruction Formats A computer performs a task based on the instruction provided. Instruction in computers comprises ‘groups called fields, These fields contain different information as for computers everything is in 0 and 1 so cach field has different significance based on which a CPU decides what to perform. The most common fields are: + Operation field specifies the operation to be performed like addition, ‘* Address field which contains the location of the operand, ie., register or memory location. ‘+ Mode field which specifies how operand is to be foundedInstruction is of variable length depending upon the number of addresses it contains. Generally, CPU organization is of three types based on the mumber of address fields: + Single Accumulator organization * General register organization # Stack organization In the first organization, the operation is done involving a special register called the accumnlator. In second on multiple registers are used for the computation purpose. In the third organization the ‘work on stack basis operation due to which it does not contain any address field. Only a single organization doesn’t need to be applied, a blend of various organizations is mostly what we see generally, Based on the number of address, instructions are classified as: Note that we will use 3 (A+B)"(C+D) expression to showease the procedure i. Zero Address Instructions A stack-based computer does not use the address field in the instruction, To evaluate an expression first it is converted to reverse Polish Notation ie. Postfix Notation. Expression: X= (A+B)*(C+D) Postfixed : X= AB+CD+* TOP means top of stack M[X] is any memory location PUSH |A]TOP=A PUSH |B |TOP=B ADD TOP=AyB PUSH [C |TOP=C PUSH [D|[TOP=D ADD TOP=CD MUL |_| TOP=(C=D)AFB) POP |X|M[X]=TOP ii, One Address Instructions ~ This uses an implied ACCUMULATOR register for data manipulation. One operand is in the accumulator and the other is in the register or memory location, Lmplied means that the CPU already knows that one operand is in the accumulator so there is no need to specify it. Expression: X = (A+B)*(C*D)AC is accumulator Mf] is any memory location M(T] is temporary location LOAD [A [AC=MIAa] ADD |B [AC=AC=MIB] STORE| T [M[T]=AC LOAD | |AC=M[C] ADD |D[AC=AC=MD] MUL [T|Ac=Ac* MT] STORE | X [M[X]=AC il, Two Addvess Instructions ~ This is common in commercial computers. Here two addresses can be specified in the instruction. Unlike earlier in one address instruction, the result was stored in the accumulator, here the result can be stored at different locations rather than just accumulators, but require more number of bit to represent address Here destination address can also contain operand. Expression: X= (A+B)*(C+D) RI, R2 are registers M[Jis any memory location Mov RIA [RI=M[A] ADD [RIB |RI=RI+MB] Mov ]R2.C [RI=C ‘ADD |R2.D |R2=R2+D MUL [RI R2 [RI=RI* R2 Mov |X.RI | M[X]=RI iv. Three Address Instructions — This has three address field to specify a register or a memory location, Program created are much short in size but number of bits per instruction increase. These instructions make creation of program mush easier but it does not mean that program will run much faster because now instruction only contain more information but each micro operation (changing content of register, loading address in address bus cte.) will be performed in one cycle only.Expression: X = (A+B)*"(CD) RI, R2 are registers M{]is any memory location ADD ]RI.A.B | RI=M[A]* MIB] ADD|R2GD [R2=M[C]= Mp] MUL |X. RI R2 | M[X]=RI* RZ 3.3. Instruction Cycle and Sub Cyeles A program residing in the memory unit of a computer consists of a sequence of instructions. These instructions are executed by the processor by going through a cyele for each instruction, Instruction Cycle is subdivided into following subcycles: 1. Fetch instruction from memory.(At the beginning of the fetch cycle, the address of the next instruction to be executed is in the Program Counter(PC)) 2. Decode the instruetion.(Decoder circuit examines the opeode of the instructionResult is selecting a unique decoder output line.) 3. Read the effective address from memory. 4, Execute the instruction(Microcode for the instrustion, selected by the decoder output line, is executed by the ALU.) Ineeuctoneye eC) State Diagram for Instruction Cyele (CE (Ge) Ss)Instruction Address Calculation ~ The address of the next instruction is computed, A permanent number is inserted to the address of the eatlier instruction, Instruction Fetch ~ The instruction is read from its specific memory location to the processor. Instruction Operation Decoding ~ The instruction is interpreted and the type of operation to be implemented and the operand(s) to be used are decided. Operand Address Calculation ~ The address of the operand is evaluated if it has a reference to an operand in memory or is applicable through the Input/Output, Operand Fetch ~ The operand is read fiom the memory or the 1. Data Operation ~ The actual operation that the instruction contains is executed Store Operands ~ It can store the result acquired in the memory ot transfer it ta the 10. ‘Complete Computer Operation Flowchart: a Ma Rew a AOe REY woRIR Mee De opecte ih SGeaeed omega‘You may be speculative however the central processor is programmed. It contains a special register — the instruction register — whose bit pattern determines what the central processor unit ean do, Once that action has been completed, the bit pattem within the instruction register may be modified. and also the central processor unit can perform the operation nominative by this next bit pattern. Since direetions are simply bit pattems, they will be kept in memory. The instruction pointer register continuously has the memory address of (points to) the next instruction to be executed. so as for the management unit to execute this instruction, it’s desived into the instruction register. the case is as follows: A sequence of instructions is stored in memory. 1. The memory address wherever the first instmetion is found is copied to the instruction pointer, 2, The CPU sends the address within the instruction pointer to memory on the address bus 3. The CPU sends a “read” signal to the control bus. 4, Memory responds by sending a copy of the state of the bits at that memory location on the data bus, that the CPU then copies into its instruction register. 5. The instruction pointer is automatically incremented to contain the address of the next instruction in memory. 6, The CPU executes the instruction within the instruction register. 7. Goto step 3 3.4. Micro-operations Operation of a computer consists of a sequence of instruction cycles. with one machine instruction per cycle, Fach instruction cycle is made up of a number of smaller units —Fetch, Indirect, Execute and Interupt eyeles, Each of these cycles involves series of steps, each of which involves the processor registers. These steps are referred as micro-operations. the prefix micro refers tothe fact that each of the step is very simple and accomplishes very litle, Figure below depicts the concept being discussed here,3.5. Execution of a Complete Instructions: We have discussed about four different types of basic operations: ‘+ Fetch information from memory to CPU ‘© Store information to CPU register to memory ‘© Transfer of data between CPU registers. ‘+ Perform arithmetic or logie operation and store the result in CPU registers To execute a complete instruction, we need to take help of these basic operations and we need to ‘execute this operation in some particular order. As for example, consider the instruction: “Add contents of memory location NUM to the contents of register RI and store the result in register R1.” For simplicity, assume that the address NUM is given explicitly in the address field of the instruction, That is, inthis instruction, direct addressing mode is used, Execution of this instruction requires the following action : 1, Feteh instruction 2. Feteh first operand (Contents of memory location pointed atby the address field of the instruction) 3. Perform addition 4, Load the result into R1.Following sequence of control steps are required to Implement Steps a MOR 4 Adios ek 4 Rta Mee Walt or Fe ‘ MR. Ads, 2, 1 Zurn a ENO. 3.6. Program Control Instructions Program Control Instructions arc the machine code that are used by machine or in assembly Ianguage by user to command the processor act accordingly. These instructions are of various types. ‘These are used in assembly language by user also. But in level language, user code is translated ‘nto machine code and thus instructions are passed to instruct the processor do the task. ‘Types of Program Control Instructions: There ase different types of Program Control Instructions: 1. Compare Instruction: Compare instruction is specifically provided, which is similar to a ‘subtract instruction except the result is uot stored anywhere, but flags are set according to the sesult, Example: CMP RI,R2; 2 inconditional Branch Instruction: It causes an unconditional change of execution sequence to @ new location. Example: JUMPL2 Mov 3, RI goto L2 3. Conditional Branch Tnstrwetion: A conditional branch instruetion is used to examine the values stored in the condition code register to determine whether the specific condition exists and to branch ifit does, Example: Assembly Code : BERI.R2,L1 Compiler allocates RI for x and R2 for y High Level Code: if (x--y) goto LI:4, Subroutines: A subroutine is a program fragment that lives in user space, performs @ well-defined task. Tt is invoked by another user program and returns control to the calling program when finished Exampl CALL and RET 5. Halting Instructions: + NOP Instruction — NOP is no operation, It cause no change in the processor state other than an advancement of the program counter. Itcan be used to synchronize timing. * HALT -It brings the processor to an orderly halt, remaining in an idle state until restarted by intermupt, trace, reset or extemal action 6. Interrupt Instructions: Interrupt is a mechanism by which an VO or an instruction can suspend the normal execution of processor and get itself serviced, + RESET ~ It reset the processor. This may include any or all setting registers to an initial value or setting program counter to standard starting location. + TRAP -It is non-maskable cdge and level triggered interrupt. TRAP has the highest priority and vectored interrupt. * INTR ~I is level triggered and maskable interrupt, It has the lowest priority. It can be disabled by resetting the processor. 3.7. Reduced Instruction Set Computer RISC stands for Reduced Instruction Set Computer. In Reduced Instruction Set Computer (RISC) architecture. the instruction set of the computer is simplified to reduce the execution time, RISC has a small set of instructions, which generally include register-to-register operations. Thus, data is stored in processor registers for computations, and results of the computations are transfetred to the memory using store instructions. All operations are performed within the registers of the CPU. In RISC, all instructions have simple register addressing and hence use less number of addressing modes. RISC uses relatively a simple instruction format and is easy to decode. Here. the instruction length can be fixed and al ned on word boundaries, The RISC processors can execute one instruction per clock eycleThis is done using pipelining, which involves overlapping the fetch, decode. and execute phases of two or three instructions. As RISC takes relatively a large number of registers in the processor unit, it takes less time to execute its program when compared to CISC. Features of RISC Processor + Itcan relatively few instructions. # Itcan relatively few addressing modes It is used for memory access limited to load and store instructions. + All operations are done within the registers of the CPU. © Ttean fixed-length, easily decoded instruction format, # It is used for single-cyele instruction execution. # Ttcan be hardwired rather than micro-programmed control. 3.8. Pipelining: To improve the performance of a CPU we have two options: 1) Improve the hardware by introducing faster cireuits 2) Arrange the hardware such that more than one operation can be performed at the same time. Since there is a limit on the speed of hardware and the cost of faster cireuits is quite high, we have to adopt the 2% option, Pipelining is a process of arrangement of hardware elements of the CPU such that its overall performance is increased. Sinmultancous execution of more than one instruction takes place in a pipelined processor. Let us sce a sealife example that works on the concept of pipelined operation. Consider a water bottle packaging plant. Let there be 3 stages that a bottle should pass through, Inserting the boitle(D, Filling water in the boitle(F), and Sealing the bottle(8). Let us consider these stages as stage 1. stage 2, and stage 3 respestively. Let each stage take 1 minute to complete its operation, Now, in 2 non-pipelined operation, a bottle is first inserted in the plant, after 1 minute it is moved to stage 2 where water is filled. Now, in stage 1 nothing is happening. Similarly, when the bottle moves to stage 3, both stage 1 and stage 2 are idle, But in pipelined operation, when the bottle is in stage 2, another bottle can be londed at stage 1. Similarly, when the bottle isin stage 3, there ean be one bottle each in stage 1 and stage 2. So, after each minute, we get a new bottle atthe end of stage 3. Hence, the average time taken to manufacture 1 bottle is: /3 minutes Without pipeliningIFS) |\\|| || TFS ||| || || || TFS @ minutes) With pipelining = 3 minutes = What is RISC Pipeline in Computer Architecture? RISC stands for Reduced Instruction Set Computers, It was introduced to execute as fast as one instruction per elock eyele, This RISC pipeline helps to simplify the computer architecture’s design, Ik relates to what is known as the Semantic Gap. that is, the difference between the operations provided in the high-level languages (HLLs) and those provided in computer architectures. To avoid these consequences. the conventional response of the computer architects is to add layers of complexity to newer architectures. This also increases the mumber and complexity of instructions together with an increase in the number of addressing modes. The architecture which resulted from the adoption of this “add more complexity” are known as Complex Instruction Set Computers (CISC), ‘The main benefit of RISC to implement instructions at the cost of one per clock eyele is eontimually not applicable because each instruction cannot be fetched from memory and implemented in one clock cycle correctly under all circumstances. The method to obtain the implementation of an instruction per clock cycle is to initiate cach instruction with cach clock cycle and to pipeline the processor to manage the objective of single-cyele instruction execution RISC compiler gives support to translate the high-level Ianguage program into a machine language ‘program, There are various issues in managing complexity about data conflicts and branch penalties are taken care of by the RISC processors, which depends on the adaptability of the compiler to identify and reduce the delays encountered with these issues. Principles of RISC Pipeline There arc various principles of RISC pipeline which are as follows ~ Keep the most frequently accessed operands in CPU registers. + It can minimize the register-to-memory operations. © Trcan use a high number of registers to enhance operand referencing and decrease the processor memory traffic. ‘© Tt can optimize the design of instruction pipelines such that minimum compiler code ‘generation can be achieved3.9, Tt can use a simplified instruction set and leave out those complex and unnecessary instructions. Let us consider a three-segment instruction pipeline that shows how a compiler can optimize the machine language program to compensate for pipeline conflicts. A frequent collection of instructions for a RISC processor is of three types are as follows Data Manipulation Instructions ~ Manage the data in processor registers. Data Transfer Instructions ~ These are load and store instructions that use an effective address that is obtained by adding the contents of two registers or a register and a displacement constant provided in the instruction, Program Control Instructions ~ These instructions use register values and a constant t0 evaluate the branch address, which is transferred to a register or the program counter (PC), Hardwire and Micro Programmed control Control Units are classified into two major categories: 3941. Hardwired Control ‘Miccoprogrammed Control ‘Control Unit ae Farrred Wiere-progranmed Contr Unit ‘Contre Unit Horizontal Vector propuemed Hardwired Control Unit Instruction register ft Semcrat [—> Sina [> ‘Clock >“Here inputs are status signals, ic., any instructions’ particular status and clock input, and the output awe get is control signals. Instruction registers are used to keep track of cumrent instruction and the next instruction Control memory is absent in this control unit. This control unit uses RISC (Reduced Instruction Set Computer) mieroprocessors, Factors Considered for the design of the hardwired control unit, © Amount of harchware - Minimise the number of hardware used. ‘Speed of operation - If a single IC can replace a group of IC, seplace it. The amount of +harehware and speed of operation are i versely proportional to each other. © Cost Characteristics of Hardwired Control Unit «The characteristics of Hardwired Control Unit are following: © Combinational cizcuits are the foundation of hardwired control units ‘+ The inputs and transformations are set into control signals in this type of system. + These units are known to be quicker and to hove a more intricate structure, Designing of Hardwired Control Unit State-table method - This classical sequential design method minimises hardware and constructs @ state transition table. Every generation of states has a set of control signals. This method faces the issue of desynchronisation. Delay Element Method - Control signals follow a proper sequence. There is a specific time delay between two groups of control signals. D flip flops are controlled by a standard clock signal to ensure synchronisation. Sequence Counter Method - It uses counter for timing puxposes. PLA method - Ituses a programmable logic array to generate control signals. Advantages of Hardwired Control Unit © Extremely fast ‘+ Instruction set size is small as hardwired control unit relies om hardware more. + The supid mode of operation can be produced by optimising it sad vantages of Hardwired Control Unit ‘+ Modification becomes tougher as each time we have to play with complex circuits.‘© Difficult to handle complex instrustions. ‘© Design is complicated, and decoding is comples. 3.9.2, Mieroprogrammed Control Unit ‘As the name suggests, these control units are designed with the help of a micto-program, This micro- program is a collections of micro-instructions stored in the control memory. This control unit uses CISC (Complex Instruction Set Computer) microprocessors. Example of micro-instructic MARRS {In the above instruction, we are fetching the operand. The control signal for the above example: MAR, Rex A micro-instruction consist of one or more micro-operations to be executed and the address of the next micro-instruction, Consol Signs If the control memory grows horizontally, due to an increase in control signals, it is referred to as horizontal microprogramming. If the control memory grows vertically, due to an increase in control ‘signals, and the bits are decoded then itis referred to as vertical microprogramming. If we are using ‘two-level control memory providing both the advantage of horizontal and vertical mieroprogramming, then it is referred to as nanoprogramming. Memory access time in nono programming is increased as two levels are to be traversed.Micro programmed control unit with a single level control store passes instruction from the main ‘memory to the instruction register, then microinstruction address generation unit sends the data to the address register, from where it is decoded and sent to the control store. Then the data is stored in the operations part of the micro-instruction register and after decoding in understandable form, itis aera a ue sy Iocten Ras seceived in the form of the control signal. Characteristics of Microprogrammed Control Unit The characteristics of Microprogrammed Control Unit are following: ‘Micro programmes of procedures are used to implement these control units, The control unit used in the micro programme is a CPU nested inside of another CPU, These cirenits are straightforward yet relatively sluggish Advantages of Miero-programmed Control Unit ‘Micro-program can be updated easily. Flexible, Better in terms of scalability than hardwired Easier to handle complex instructions. Design is systematic, and decoding is pretty much straightforward. Disadvantages of the Micro-programmed Control Unit “Hardware cost is more because of control memory and its access cirenitry. Slower thon a hardwired control unit Instruction set size is comparatively large as this relies on microprogramming.3.10. Types of Micro-programmed Control Unit: Based on the type of Control Word stored in the Control Memory (CM), itis classified into two types. 3.10.1. Horizontal Micro-programmed Control Unit : The contol signals are represented inthe decoded binary fonuat thats 1 bitS. Example: If $3 Control signals ate preset inthe processor then $3 bits are required. More than | control signal can be enabled at a time. Tt supports longer control words. tis used in parallel processing applications, Trallows a higher degree of parallelism, If degree is n,n CS is enabled at atime, It requires no additional hardware(decoders), It means it is faster than Vertical Microprogrammed. Itis more flexible than vertical microprogrammed 3.10.2. Vertical Micro-programmed Control Unit : The control signals are represented in the encoded binary format. For N control signals- Log2(N) bits are required. It supports shorter control words. It supports easy implementation of new control signals therefore it is more flexible, Itallows alow degree of parallelism ie, the degre of parallelism is either 0 or I. Requites additional hardware (decoders to generate contro signals, it implies itis slower than horizontal mieroprogrammed. Itis less flexible than horizontal but more flexible than that of a hardwired control ‘unit,