UNIT 5

Input Output Organization

Input/output: Peripheral devices: A computer peripheral is a device that is connected to a computer but is
not part of the core computer architecture. The core elements of a computer are the central processing unit,
power supply, motherboard and the computer case that contains those three components. Technically
speaking, everything else is considered a peripheral device.
Types of Peripheral Devices

There are many different peripheral devices, but they fall into three general categories:
1. Input devices: An input device sends data or instructions to the computer, such as
a mouse, keyboard, graphics tablet, image scanner, barcode reader, game controller, light pen, light
gun, microphone, digital camera, webcam, dance pad, and read-only memory);
2. Output devices: An output device provides output from the computer, such as a computer
monitor, projector, printer, headphones and computer speaker);
3. Storage devices: An input/output device performs both input and output functions, such as
a computer data storage device (including a disk drive, USB flash drive, memory card and tape drive).

Note: Peripheral devices can be external or internal. For example, a printer is an external device that you
connect using a cable, while an optical disc drive is typically located inside the computer case. Internal
peripheral devices are also referred to as integrated peripherals.

Input Output Port:

Input Output Ports can be defined in two ways:
(1) An I/O port is a socket on a computer that a cable is plugged into. The port connects the CPU to a
peripheral device via a hardware interface or to the network via a network interface. For example,
USB, HDMI, VGA, Audio Video Ports, etc
(2) In a PC, an I/O port is an address used to transfer data.

I/O Interface
The method that is used to transfer information between internal storage and external I/O devices is known as
I/O interface. The CPU is interfaced using special communication links by the peripherals connected to any
computer system. These communication links are used to resolve the differences between CPU and
peripheral. There exists special hardware components between CPU and peripherals to supervise and
synchronize all the input and output transfers that are called interface units.

Mode of Transfer:
The binary information that is received from an external device is usually stored in the memory unit. The
information that is transferred from the CPU to the external device is originated from the memory unit. CPU
merely processes the information but the source and target is always the memory unit. Data transfer between
CPU and the I/O devices may be done in different modes.

Data transfer to and from the peripherals may be done in any of the three possible ways
1. Programmed I/O.
2. Interrupt- initiated I/O.
3. Direct memory access (DMA).

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Now let’s discuss each mode one by one.

1. Programmed I/O: It is due to the result of the I/O instructions that are written in the computer
program. Each data item transfer is initiated by an instruction in the program. Usually the transfer is
from a CPU register and memory. In this case it requires constant monitoring by the CPU of the
peripheral devices.
Example of Programmed I/O: In this case, the I/O device does not have direct access to the memory unit.
A transfer from I/O device to memory requires the execution of several instructions by the CPU, including
an input instruction to transfer the data from device to the CPU and store instruction to transfer the data
from CPU to memory. In programmed I/O, the CPU stays in the program loop until the I/O unit indicates
that it is ready for data transfer. This is a time consuming process since it needlessly keeps the CPU busy.
This situation can be avoided by using an interrupt facility. This is discussed below.
Drawbacks:
a. The I/O transfer rate is limited by the speed with which the processor can test and service a
device.
b. The processor is tied up in managing an I/O transfer; a number of instructions must be executed
for each I/O transfer.

2. Interrupt- initiated I/O: Since in the above case we saw the CPU is kept busy unnecessarily. This
situation can very well be avoided by using an interrupt driven method for data transfer. By using
interrupt facility and special commands to inform the interface to issue an interrupt request signal
whenever data is available from any device. In the meantime the CPU can proceed for any other
program execution. The interface meanwhile keeps monitoring the device. Whenever it is determined
that the device is ready for data transfer it initiates an interrupt request signal to the computer. Upon
detection of an external interrupt signal the CPU stops momentarily the task that it was already
performing, branches to the service program to process the I/O transfer, and then return to the task it
was originally performing.
Drawbacks:
a. The I/O transfer rate is limited by the speed with which the processor can test and service a
device.
b. The processor is tied up in managing an I/O transfer; a number of instructions must be executed
for each I/O transfer.

3. Direct Memory Access: The data transfer between a fast storage media such as magnetic disk and
memory unit is limited by the speed of the CPU. Thus we can allow the peripherals directly
communicate with each other using the memory buses, removing the intervention of the CPU. This
type of data transfer technique is known as DMA or direct memory access. During DMA the CPU is idle
and it has no control over the memory buses. The DMA controller takes over the buses to manage the
transfer directly between the I/O devices and the memory unit.

CPU Bus Signal for DMA Transfer

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Bus Request: It is used by the DMA controller to request the CPU to relinquish the control of the buses.
Bus Grant: It is activated by the CPU to inform the external DMA controller that the buses are in high
impedance state and the requesting DMA can take control of the buses. Once the DMA has taken the control
of the buses it transfers the data. This transfer can take place in many ways.

Block Diagram of DMA:

DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest rate. It allows the
device to transfer the data directly to/from memory without any interference of the CPU.
Using a DMA controller, the device requests the CPU to hold its data, address and control bus, so the device is
free to transfer data directly to/from the memory. The DMA data transfer is initiated only after receiving HLDA
signal from the CPU.

How DMA Operations are performed?

Following is the sequence of operations performed by a DMA −
 Initially, when any device has to send data between the device and the memory, the device has to send
DMA request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert the HLDA.
 Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU leaves the
control over bus and acknowledges the HOLD request through HLDA signal.

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  Now the CPU is in HOLD state and the DMA controller has to manage the operations over buses
between the CPU, memory, and I/O devices.

Features of 8257
Here is a list of some of the prominent features of 8257 −
 It has four channels which can be used over four I/O devices.
 Each channel has 16-bit address and 14-bit counter.
 Each channel can transfer data up to 64kb.
 Each channel can be programmed independently.
 Each channel can perform read transfer, write transfer and verify transfer operations.
 It generates MARK signal to the peripheral device that 128 bytes have been transferred.
 It requires a single phase clock.
 Its frequency ranges from 250Hz to 3MHz.
 It operates in 2 modes, i.e., Master mode and Slave mode.

Types of DMA transfer using DMA controller:

Burst Transfer: DMA returns the bus after complete data transfer. A register is used as a byte count,
being decremented for each byte transfer, and upon the byte count reaching zero, the DMAC will
release the bus. When the DMAC operates in burst mode, the CPU is halted for the duration of the data
transfer.
Steps involved are:
1. Bus grants request time.
2. Transfer the entire block of data at transfer rate of device because the device is usually slow than the
speed at which the data can be transferred to CPU.
3. Release the control of the bus back to CPU. So,
Total time taken to transfer the N bytes
= Bus grant request time + (N) * (memory transfer rate) + Bus release control time.

Cyclic Stealing: In this DMA controller transfers one word at a time after which it must return the control of
the buses to the CPU. The CPU merely delays its operation for one memory cycle to allow the direct memory
I/O transfer to “steal” one memory cycle.
Steps Involved are:
1. Buffer the byte into the buffer
2. Inform the CPU that the device has 1 byte to transfer (i.e. bus grant request)
3. Transfer the byte (at system bus speed)
4. Release the control of the bus back to CPU.
Before moving on transfer next byte of data, device performs step 1 again so that bus isn’t tied up and the
transfer won’t depend upon the transfer rate of device.
So, for 1 byte of transfer of data, time taken by using cycle stealing mode (T)
T = time required for bus grant + 1 bus cycle to transfer data + time required to release the bus.

In cycle stealing mode we always follow pipelining concept that when one byte is getting transferred then
Device is parallel preparing the next byte. “The fraction of CPU time to the data transfer time” if asked then
cycle stealing mode is used.

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Interleaved mode: In this technique, the DMA controller takes over the system bus when the microprocessor
is not using it. An alternate half cycle i.e. half cycle DMA + half cycle processor.

Interrupt: Interrupt is a signal which has highest priority from hardware or software which processor should
process its signal immediately.
In this mechanism processor will not check for any signal from hardware or software but instead
hardware/software will only send the signal to the processor for processing. The signal from hardware or
software should have highest priority because processor should leave the current process and process the
signal of hardware or software. This mechanism of processing the signal is called Interrupt of the system.

Types of Interrupts:
Although interrupts have highest priority than other signals, there is much type of interrupts but basic type of
interrupts is:
1. Hardware Interrupts: If the signal for the processor is from external device or hardware is called
hardware interrupts. Example: from keyboard we will press the key to do some action this pressing of
key in keyboard will generate a signal which is given to the processor to do action, such interrupts are
called hardware interrupts. Hardware interrupts can be classified into two types they are
a. Maskable Interrupt: The hardware interrupts which can be delayed when a much highest
priority interrupt has occurred to the processor. For Example: RST7.5, RST6.5, RST 5.5, etc
b. Non Maskable Interrupt: The hardware which cannot be delayed and should process by the
processor immediately. For Example: TRAP
2. Software Interrupts: Software interrupt can also divided in to two types. They are
a. Normal Interrupts: the interrupts which are caused by the software instructions are called a
software instructions.
b. Exception: unplanned interrupts while executing a program is called Exception. For example:
while executing a program if we got a value which should be divided by zero is called an
exception.
Types of Exceptions:
i. Trap: It is typically a type of synchronous interrupt caused by an exceptional condition (e.g.,
breakpoint, division by zero, invalid memory access).
ii. Fault: Fault exception is used in a client application to catch contractually-specified SOAP
faults. By the simple exception message, you can’t identify the reason of the exception,
that’s why a Fault Exception is useful.
iii. Abort: It is a type of exception occurs when an instruction fetch causes an error.

Classification of Interrupts According to Periodicity of Occurrence:

1. Periodic Interrupt: If the interrupts occurred at fixed interval in timeline then that interrupts are called
periodic interrupts
2. Aperiodic Interrupt: If the occurrence of interrupt cannot be predicted then that interrupt is called
aperiodic interrupt.
Classification of Interrupts According to the Temporal Relationship with System Clock:
1. Synchronous Interrupt: The source of interrupt is in phase to the system clock is called synchronous
interrupt. In other words interrupts which are dependent on the system clock. Example: timer service
that uses the system clock.
2. Asynchronous Interrupts: If the interrupts are independent or not in phase to the system clock is
called asynchronous interrupt.

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Exceptions and difference with Interrupts
Exceptions and interrupts are unexpected events that disrupt the normal flow of instruction execution. An
exception is an unexpected event from within the processor. An interrupt is an unexpected event from outside
the processor. You are to implement exception and interrupt handling in your multicycle CPU design.
When an exception or interrupt occurs, the hardware begins executing code that performs an action in
response to the exception. This action may involve killing a process, outputting a error message,
communicating with an external device, or horribly crashing the entire computer system by initiating a "Blue
Screen of Death" and halting the CPU.

Exceptions: Examples
For your project, there are three events that will trigger an exception: arithmetic overflow, undefined
instruction, and system call.
Arithmetic overflow occurs during the execution of an ADD, or SUB instruction. If the result of the
computation is too large or too small to hold in the result register, the Overflow output of the ALU will
become high during the execute state. This event triggers an exception.
Undefined instruction occurs when an unknown instruction is fetched. This exception is caused by an
instruction in the IR that has an unknown opcode or an R-type instruction that has an unknown function code.
System call occurs when the processor executes a syscall instruction. Syscall instructions are used to
implement operating system services (functions).

Input/output Channels
A channel is an independent hardware component that co-ordinate all I/O to a set of controllers. Computer
systems that use I/O channel have special hardware components that handle all I/O operations. I/O Channel is
an extension of the DMA concept. It has ability to execute I/O instructions using special-purpose processor
on I/O channel and complete control over I/O operations. Processor does not execute I/O instructions itself.
Processor initiates I/O transfer by instructing the I/O channel to execute a program in memory.

Input/output Processors
Channels use separate, independent and low cost processors for its functioning which are called Channel
Processors. Channel processors are simple, but contain sufficient memory to handle all I/O tasks. When I/O
transfer is complete or an error is detected, the channel controller communicates with the CPU using an
interrupt, and informs CPU about the error or the task completion. Each channel supports one or more
controllers or devices.

Categories of I/O Channels:

Following are the different categories of I/O channels:

1. Selector Channel:
Selector channel controls multiple high-speed devices. It is dedicated to the transfer of data with one of the
devices. In selector channel, each device is handled by a controller or I/O module. It controls the I/O
controllers shown in the figure.
2. Multiplexer Channel:
Multiplexer channel is a DMA controller that can handle multiple devices at the same time. It can do block
transfers for several devices at once.

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 Selector Channel

Multiplexer Channel
Two types of multiplexers are used in this channel:
1. Byte Multiplexer –
It is used for low-speed devices. It transmits or accepts characters. Interleaves bytes from several
devices.
2. Block Multiplexer –
It accepts or transmits block of characters. Interleaves blocks of bytes from several devices. Used for
high-speed devices.

Types of Data Transfer

There are two types of data transfer: Synchronous and Asynchronous data transfer

Synchronous data transfer

For synchronous data transfer, both the sender and receiver access the data according to the same clock.
Therefore, a special line for the clock signal is required. A master (or one of the senders) should provide the
clock signal to all the receivers in the synchronous data transfer.

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Asynchronous data transfer:
For asynchronous data transfer, there is no common clock signal between the sender and receivers.
Therefore, the sender and the receiver first need to agree on a data transfer speed. This speed usually does
not change after the data transfer starts. Both the sender and receiver set up their own internal circuits to
make sure that the data accessing is follows that agreement. However, just like some watches run faster than
others, computer clocks also differ in accuracy. Although the difference is very small, it can accumulate fast
and eventually cause errors in data transfer. This problem is solved by adding synchronization bits at the front,
middle or end of the data. Since the synchronization is done periodically, the receiver can correct the clock
accumulation error. The synchronization information may be added to every byte of data or to every frame of
data.

Comparison between Synchronous and Asynchronous Transmission

Point of Comparison Synchronous Transmission Asynchronous Transmission
Same Clock signal used by sender and different Clock signal used by sender
Clock Synchronization receiver and receiver
Transmits data in the form of chunks
Definition or frames Transmits 1 byte or character at a time
Speed of Transmission Quick Slow
Cost Expensive Cost-effective
Time Interval Constant Random
Gaps between the data Yes No
Chat Rooms, Telephonic
Examples Conversations, Video Conferencing Email, Forums, Letters

Interface standards
Interface standards are like traffic lights; they simplify coordination only as long as everyone follows the same
rules. Each driver must both know and follow the rules. To be effective coordination devices, interface
standards must be binding on both the platform owner and app developers; app developers must obey them
and also expect others to obey them.

Serial Communication Standards:

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Serial Communication uses only two data pins to establish communication between Microcontroller and
external devices. In this mode of communication data is transferred one bit at a time. This article describes
Interfacing of Microcontroller with PC to establish communication through its serial port RS232.
RS232 interface standard: The RS232 interface standard defines the necessary control signals and data lines
to enable information to be transmitted between computer equipment (or data terminal equipment DTE) and
the modem (or data communication equipment DCE). The modulated carrier signal is transmitted over a two-
wire telephone network by the connecting modems.
To establish communication between a controller and PC, we must use serial I/O protocol RS-232 which was
widely used in PC and several devices. PC works on RS-232 standards which operate at a logic level of -25V to
+25V. But Microcontrollers use TTL logic which works on 0-5V is not compatible with the RS-232 voltage levels.
MAX232 is a specialized IC which offers intermediate link between the Microcontroller and PC. The transmitter
of this IC will convert the TTL input level to RS-232 Voltage standards. Meanwhile the receiver of this IC will
convert RS-232 input to 5V TTL logic levels.

A modem converts or “modulates” digital information into a form suitable for transmission over the
telephone network. The receiving modem demodulates the signal back into digital data for use by
the receiving computer.
Modems transmit information using a sine wave carrier which is modulated (either through amplitude,
frequency or phase) to carry binary information.

DB – 25 Connector in Serial Communication

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 DB – 9 Connector in Serial Communication

Parallel Standards
The standard interface most commonly used for parallel communications is IEEE-488. This was originally
developed by Hewlett-Packard to link its computers and instruments and was known as the Hewlett-
Packard Instrumentation Bus. It is now often termed the General-Purpose Instrument Bus. This bus provides a
means of making interconnections so that parallel data communications can take place among listeners,
talkers, and controllers. Listeners are devices that accept data from a bus; talkers place data, on request, on
the bus; and controllers manage the flow of data on the bus and provide processing facilities.

Handshaking is the term used for the transfer of control information, such as DATA READY and INPUT
ACKNOWLEDGED signals, between two devices.
OpenMP
OpenMP is a standard interface for parallel programming based on annotating serial code so that certain
constructs, in particular loops, can be reinterpreted as parallel constructs. The basic patterns it supports
directly as features are map and reduce, although other patterns can also be implemented.
COM Automation
Component Object Model (COM) is a binary interface standard that allows objects to interact with each other
via intercrosses communication. COM objects specify well-defined interfaces that allow software
components to be reused and linked together to build end-user applications.

Differences between Serial Communication and Parallel Communication:

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The differences between Serial and Parallel communication are as follows:
1. No of paths for Data transfer: Serial link has only one path for data transfer while Parallel one has
multiple paths.
2. Distance Coverage: Serial link supports communication to long distances while Parallel data
transmission supports limited distance transmission.
3. Cross-talk: Chances of Cross-talk is less in Serial link compared to parallel one due to only one path
available.
4. Speed: Serial link is slow compared to parallel one.
5. Communication: Serial transmission is full duplex as data can be sent or received at either ends.
Parallel data is half duplex as the data can either be sent or received.
6. Cost Factor: Serial links are cheaper than Parallel one owing to more paths in parallel mode.
7. Complexity: Serial links are simple and reliable while Parallel links are complex and unreliable.

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