EE308 Power Electronics Lab

Morning Slot: Batch 2

Submitted By: Akarshi Roy Choudhury (2021EEB1149)

Ashwini Sahane (2021EEB1159)

Aim: To design a boost converter operating at boundary condition and to design

and simulate the same containing Non-Ideal diode in Matlab Simulink.

Circuit diagram:

Fig.1. Buck Boost converter MATLAB simulation.

Procedure and Readings:

We have been given the following parameters for boost converter operating on
boundary condition:

Input voltage (Vin) = 10V

Output voltage (Vo) = 18V
Switching frequency (fsw) = 10kHz
Output Power (Po) = 36 W
Voltage ripple = 3% of Vo
Parameters analyzed in MATLAB:

1. Average input current:

Avg current = 3.558A

Maximum current = 7.286A

2. RMS Diode current:

RMS value = 3.17A

Max current = 7.286A
 3. RMS switch voltage:

Max value of switch voltage is the same as output voltage = 18V

RMS value = 13.35V

4. Output voltage:

Average = 18.32 V (as per simulations, as per desired).

Let us now look for non-ideal converters:

Fig.2. MATLAB simulation for non-ideal boost converter

1) Power loss in non-ideal inductor:

RMS current as per MATLAB was 3.154A. Resistance of the inductor was
chosen to be 0.1 ohms in the simulink. Hence the power loss:
P(loss) = (Irms)^2 * Rl
= (3.154)^2 * 0.1
= 0.9948 W
 2) Power loss in diode:

Average current value (I) = 1.996A

Forward voltage in diode (V) = 1V
Thus, the power loss can be calculated to be - V*I = 1.996*1 = 1.996 W

3) Efficiency of the converter:

For first calculating the input power, we see the current waveform across the
inductor:

Average current = 3.0412A

Average voltage across the inductor = 15V
Input Power = 3.0412*15 = 45.618.

For calculating the output power:

Output current waveform across the inductor:

Average current = 1.996A

Output voltage waveform across the inductor:

Average output voltage = 22.01V

Power consumed = 1.996 * 22.01 = 42.508W

Thus, Efficiency = (Pin/Po)*100 = (42.508/45.618) *100 = 93.19%

Results:
We thus analyzed the voltage, current waveforms & power dissipated across
various components (particularly the diode and the inductor) for boost converter at
both, the boundary condition & with non-idealities.

Part A: Implementing ADCs

Aim: Implementing the ADC and DAC modules on TMS320F28379D as a new

project and hence show the output of the same on oscilloscope.

Theory & Working:

● We are performing the Analog-to-Digital conversion (ADC) of the obtained

intermediate output i.e. the sine wave. We are performing successive
approximations to ADC. Here we first compare the voltage value of DAC
and Vin. According to the error produced the control logic gives an output
(high or 1 when Vdac > Vin, low or 0 when Vin > Vdac). This output is then
stored in the successive approximation register that further generates our
final binary output.

● We can see below the proper working of successive approximation ADC.

The first bit of the binary output is always 1. When S1 is turned on, the
capacitor charges and on turning S2 on, it starts discharging. The voltage
across the capacitor (Vsh) on turning on S2 is compared with the full scale
 output of DAC via the comparator and accordingly the further bits are
generated.

● Also, for ADC we first perform its sampling. In the code below, we have set
40 samples per cycle. Highest amplitude of the sine wave is 3.3V and min is
0V. We are trying to discretise it to a 12 bit output. Hence, 0V will
correspond to 0 and 3.3V to 2^12 = 4096.
● The register after control logic is the ADCresult register array in the code
that’ll store the feedback output. Its size here is 40 (for storing the 40
samples per cycle). Control is important here because many times a 3V
input/ output can be 2V etc which affects other circuitries. Control logic and
feedback fix the same.
● In ADC, we have start of conversion (SOC) and end of conversion (EOC).
Moment the EOC is done, an interrupt is called which converts the analog
signal into a digital signal.

We have to first create a new project, one can refer the following flow chart for the
same:
Components:
1. CHSEL (Channel Selection Register): It tells which input we want to give to the
ADC. Eg, if CHSEL=3, means we are using ADCIN3. These 16 inputs are either
for ADCA or ADCB or ADCC.
2. Sample and Hold Circuit: It works on acquisition window, so it is in terms of
system clocks. The signal source needs to charge the sampling capacitor to within
0.5LSBs of the signal voltage. Acquisition window time is the time for allowing
the input capacitor to get charged and store the sample. This sample-and-hold
capacitor is collecting the input samples. Once 1 acquisition window is over, the
sample and hold circuit opens and the data gets stored. Again the circuit closes at
the next window.

Acquisition Window = (ACQPS+1)*(SYSCLK)

The selected acquisition window duration must be at least as long as one ADCCLK
cycle, i.e. 1/50MHz = 20nsec.
3. TRIGSEL: It is used for SOC selection. This trigger defines the sampling
frequency of the ADC. Eg: let 50Hz signal be used i.e. 20 msec be the time period
and let the sampling frequency be 100Hz, i.e. sampling time 10 msec. So, we will
be able to acquire 2 samples this way.
4. ADC Event: It is used to generate certain events.
5. Interrupt Block: There are 4 interrupts to ADC- ADCINT1, ADCINT2,
ADCINT3 and ADCINT4. Every time the signal gets converted, after that, an
ADC interrupt is called. So, if the sampling frequency is 10KHz, then ADC
interrupt will be called after every 1/10k = 0.1msec and the result will be available.
The ADC result register is there within ADC interrupt only.

Logic:
1. ADC Configuration: EALLOW protected registers: The system first sets up
the ADC (Analog-to-Digital Converter) by configuring its registers
protected by the EALLOW directive. This directive likely ensures safe
register access and prevents unintended modifications during critical
configuration steps. Clock, resolution, and mode: The configuration involves
setting the ADC clock speed, resolution (likely 12 or 16 bits), and signal
mode (e.g., single-ended or differential). Power up: The ADC is then
powered up to make it operational.

2. PWM Configuration: SOC signal: The system configures the Pulse Width
Modulation (PWM) module and assigns it as the Start-of-Conversion (SOC)
signal for the ADC. This means the rising edge of the PWM pulse triggers
the ADC to initiate a conversion. 50 kHz frequency: The PWM is set to a
frequency of 50 kHz, determining the sampling rate of the ADC (50,000
samples per second).

3. DAC Configuration: DAC configuration: The Digital-to-Analog Converter

(DAC) is then configured, likely involving setting its output range and other
operational parameters.

4. ADC Initialization: Channel selection: The specific ADC channel used to

convert the analog input signal is chosen (likely channel 0 based on
ADCINA0 mentioned later).
 5. Acquisition window: The acquisition window (the time allowed for the ADC
to charge its internal capacitor) is defined in nanoseconds. This parameter is
crucial for accurate conversion and depends on the signal characteristics.
Trigger selection: The trigger source for the ADC is selected. Since PWM is
already assigned as the SOC signal, this step might involve confirming that
trigger selection is set to use the PWM signal.

6. Signal Acquisition and Processing: Triangle wave input: A triangle wave is

generated using a function generator and applied to the ADC's input pin
(ADCINA0, likely J3-30 on the board). ADC conversion: The ADC starts
converting the analog triangle wave into digital values at a rate of 50 kHz,
triggered by the PWM signal. These digital values are stored in an array
named "AdcaResults" with a size of 256, indicating that 256 samples of the
waveform are captured.

7. Digital-to-Analog Conversion and Output: DAC update: The digital values

stored in the "AdcaResults" array are fed into the DAC's "DACVALS"
register. This updates the DAC's output value with the corresponding digital
sample from the array. Analog output: The updated value from the DAC is
converted back into an analog signal and appears on the designated output
pin (likely J7-70 on the board).

8. Oscilloscope observation: The reconstructed analog signal can be observed

on an oscilloscope connected to the output pin, allowing you to verify if the
converted and reconstructed signal resembles the original triangle wave.

Overall, this system demonstrates a data acquisition process where an analog signal
is sampled by the ADC, converted into digital form, and then reconstructed back
into an analog signal using the DAC.

Modules:

1. void ConfigureADC(void): To configure the ADC, i.e., set clock, resolution

(12/16 bits), define signal mode, power up the ADC, etc. using its registers.
 2. void ConfigureEPWM(void): To configure PWM, i.e., assign it as SOC
signal. We generate pulse after every triangle of counter (TBPRD).
3. void ConfigureDAC(void): To configure DAC.
4. void SetupADCEpwm(void): To setup the ADC for ePWM triggered
conversions on channel 0.
5. interrupt void adca1_isr(void): To generate sine wave, feed it to DAC and
plot it. Then provide this input to ADC and generate an array of size 256
storing its values.
6. void main(void): Execution of the code.

Code:
Results:
Output signal of the oscilloscope at 1kHz (input signal given by a function
generator):

Distortion is observed at sampling frequencies lesser than the input signal

frequency due to undersampling. The same can be observed below:

Fig: Input signal frequency = 70kHz and sampling frequency = 50kHz hence a distorted output

Conclusion:
We understood implementing DAC and ADC models on our own by creating a
new project and building the same on the TMS320F28379D board.