IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 11, NO.

2, APRIL 2023 1627

Compact MV-Insulated MHz Transformer-Coupled

Gate Driver With Staged Turn-Off Scheme for
Series-Connected Power Devices in DC
Circuit Breaker Applications
Jian Liu , Graduate Student Member, IEEE, Lakshmi Ravi , Graduate Student Member, IEEE,
Rolando Burgos , Senior Member, IEEE, Steve C. Schmalz, Andy Schroedermeier , Member, IEEE
and Dong Dong , Senior Member, IEEE

Abstract— The short-circuit protection equipment of dc circuit protection strategy and equipment short-circuit faults are the
breaker (DCCB) is important for the dc grid. Also, the series- major obstacles in the development of dc distribution system
connected power devices are usually employed in the solid- [4], [5]. The main reasons are the much smaller dc line
state circuit breaker (SSCB) or hybrid circuit breaker (HCB)
to meet the clamping voltage requirement. A simple passive impedance and the lack of natural zero crossing point, which
gate driver and power supply solution is a critical component brings the arcing issue of the traditional mechanical ac switch.
to drive the circuit breakers more cost-effective and reliable. Besides, a proper dc circuit breaker (DCCB) should consider
This article proposed a novel compact MV-insulated transformer- the key features of fast response, low conduction loss, low cost,
coupled gate driver method, which combines the auxiliary power and high reliability. Currently, the solid-state circuit breaker
and gate signal together. The proposed high-frequency-modulated
multilevel transformer voltage enables both the simultaneous and (SSCB) and hybrid circuit breaker (HCB) [6] are two main
the staged turn-off schemes. Besides, the cascade high- and low- solutions, which employ the semiconductor power devices to
voltage transformer structures simplify the insulation design and interrupt the fault current quickly without any arc issue.
demonstrate better scalability. The common-mode current could Different types of semiconductor technologies, such as
be suppressed as well using this structure. The design example silicon (Si), silicon carbide (SiC), and gallium nitride (GaN)
of a compact 2-MHz high-voltage planar transformer with
>13-kV partial-discharge-free insulation capability is illustrated. devices, have already been applied to the DCCB [7]. Their
Finally, the simulation and experimental results are also given to unique properties drive the corresponding design method and
demonstrate the feasibility of the proposed gate driver method. working range. For example, the Si bipolar devices, including
Index Terms— Cascade transformer, dc circuit breaker silicon-controlled rectifier (SCR), insulated-gate bipolar tran-
(DCCB), gate driver, series-connected power devices, staged sistor (IGBT), and injection-enhanced gate transistor (IEGT),
turn-off. are characterized by good reliability and overcurrent capability
[8], [9], whereas the wide bandgap (WBG) devices with lower
I. I NTRODUCTION losses, higher temperature capability, and higher voltage rating
could improve the power density and efficiency [10].
N OWADAYS, the low-voltage (LV) and medium-voltage
(MV) dc distribution system is considered as a viable
alternative of ac system to improve efficiency, cost, and
In the LV range, single device could meet the blocking
voltage requirement easily. However, in the MV or high-
voltage (HV) range, HV IGBT suffers from the current bump
reliability [1], [2], [3]. Despite the numerous benefits, the
issue and lower power density compared to devices with lower
Manuscript received 8 August 2022; revised 13 October 2022; accepted voltage rating [11]. Therefore, the series-connected power
17 November 2022. Date of publication 7 December 2022; date of current devices have been widely adopted in DCCB at different
version 4 April 2023. This work was supported by the Advanced Research
Projects Agency-Energy (ARPA-E) through the BREAKER Program moni- voltage ratings. For instance, Zhangbei ±500-kV HCB, the
tored by Dr. Isik Kizilyalli under Award DE-AR0001111. Recommended for world’s largest capacity DCCB in 2020, utilizes 320 series
publication by Associate Editor Anshuman Shukla. (Corresponding author: IEGTs [12]. Then, the most challenging issue is the voltage
Dong Dong.)
Jian Liu, Lakshmi Ravi, Rolando Burgos, and Dong Dong are with the sharing among the series power devices. There are three
Center for Power Electronics Systems, Virginia Polytechnic Institute and State major factors causing the voltage unbalance: device parameter
University, Blacksburg, VA 24060 USA (e-mail: [email protected]; [email protected]; inconsistency, ON / OFF gate driver signal mismatch, and the
[email protected]; [email protected]).
Steve C. Schmalz and Andy Schroedermeier are with Eaton Cor- parasitic capacitors. Various methods have been investigated
poration, Milwaukee, WI 53051 USA (e-mail: [email protected]; to address this issue, such as the passive snubber, active
[email protected]). clamping, dynamic dv/dt control, and timing control [13], [14],
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/JESTPE.2022.3227278. [15]. Different from the normal pulsewidth modulation (PWM)
Digital Object Identifier 10.1109/JESTPE.2022.3227278 converter, the voltage clamping device [e.g., metal oxide
2168-6777 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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1628 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 11, NO. 2, APRIL 2023

Fig. 1. (a) Series power devices with individual voltage clamping circuit and
gate driver units. (b) Series power devices based on single gate driver.

varistor (MOV)] is necessary for DCCB to absorb energy.

Therefore, a modular structure of discrete MOV paralleled
with individual device as shown in Fig. 1(a) is proposed to
eliminate the voltage unbalance problem [16]. In this case, the
RC snubber is designed to suppress the voltage overshoot of
MOV due to the high di/dt. This method has good modularity
and scalability to be used in the arbitrary voltage rating.
However, lots of gate driver units, fiber optics, and isolated Fig. 2. (a) Structure of an HCB. (b) Operation sequence of simultaneous
turn-off for PEI and waveforms of HCB. (c) Waveforms of staged turn-off
power supplies are required for all devices, which increases for PEI.
the cost and complexity. Besides, fiber optics may not work
in the harsh environment of high temperature.
In order to reduce the component number, single gate side to the secondary side simultaneously, featuring a lower
driver solution as shown in Fig. 1(b) has been investigated cost and higher reliability in the harsh environment. Besides,
[17]. Different single gate driver structures utilize different the cascade transformer structure simplifies the insulation
coupling components to drive the upper side devices. For design for MV and HV applications and demonstrates good
example, the capacitor-coupled scheme takes advantage of the scalability.
charge difference among the capacitors to drive upper side This article is organized as follows. In Section II, the
devices, thus achieving higher compactness [18], [19], [20]. traditional transformer-coupled gate driver structures and the
However, this method cannot connect MOV in parallel with corresponding limitations are introduced. Then, the working
each device for voltage clamping due to the voltage overshoot, principles of the proposed method are illustrated in detail.
which will cause the turn-off failure of upper device [18]. Next, in Section III, the hardware design of the gate driver
Therefore, a single gate driver utilizing MOV as the turn- as well as a planar compact transformer with >13-kV insu-
off path is proposed in [21], and this method simplifies the lation capability is explained. Then, the simulation as well
parameter design significantly. In this case, all series power as experimental results of five series devices with two turn-
devices are turned on and turned off almost simultaneously, off strategies are presented in Section IV. Finally, Section V
which is preferred in SSCB. However, in HCB, the total discusses the conclusions and future developments.
clamping voltage should be lower than the dielectric strength
of the mechanical switch (MS) to avoid the breakdown of II. T RANSFORMER -C OUPLED G ATE D RIVER
MS. With this limitation, a staged turn-off scheme to reshape
the wave of clamping voltage could help to reduce the total A. HCB Structure and Staged Turn-Off Strategy
absorption energy and fault clearing time [22]. In order to Fig. 2(a) shows the topology of a typical HCB [23], which
simplify the gate driver design and implement the staged consists of three parts: the vacuum switch (VS), the current
turn-off scheme, a transformer-coupled gate driver method is commutation circuit (CC), and the power electronic interrupter
proposed in this article. The proposed scheme transmits the (PEI) with a certain number of series modules. The CC could
gate signal together with the driving power from the primary be regarded as a controllable current source, which can follow

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LIU et al.: COMPACT MV-INSULATED MHz TRANSFORMER-COUPLED GATE DRIVER 1629

Fig. 3. PEI circuit based on the traditional transformer-coupled gate driver.

the line current and inject the same current in the PEI branch.
As a result, the current of VS branch reduces to 0, and VS
could open without arc. Several circuits could be adopted to
implement such function, such as the transient commutation
current injector (TCCI) in [24] or the current commutation
drive circuit (CCDC) in [25].
The operation sequence and waveforms of a conven-
tional simultaneous turn-off strategy for PEI are presented in
Fig. 2(b). At the normal state, the current flows through the Fig. 4. Schematic of the proposed transformer-coupled gate driver method.
closed VS. After the short circuit happens at t0 , the line current (a) Overall structure. (b) Detailed secondary gate circuit.
Iline will rise quickly due to the small line inductance L line .
When the short-circuit fault is detected at t1 , the CC starts to
transfer the current from the VS to the PEI branch. After the [31], [32]. The later solution uses the modulation frequency
VS current is zero, it starts to open the contactor gradually, from hundreds of kilohertz up to tens of megahertz, which
and the dielectric strength across the VS also increases at the can deliver the gate signal through the amplitude modulation
same time. Once a sufficient gap builds at t2 , all the modules of (AM) or frequency modulation (FM). At the same time, the
PEI could be turned off simultaneously. Then, the fault current secondary side could obtain the auxiliary energy via a rectifier.
commutates to the voltage clamping circuit, which generates a Referring to this idea, this article extends the transformer-
clamping voltage higher than the dc bus voltage, and the line coupled gate driver solution to multiple series devices with
current Iline starts to reduce. After Iline reduces to zero at t3 , the cascade transformer structure.
the snubber circuit in PEI will resonate with line inductance,
leading to the oscillation across PEI and line current Iline . B. Proposed Transformer-Coupled Gate Driver
Since the PEI is modular, there is freedom to turn off The schematic of the proposed gate driver with three series
modules and shape the wave of clamping voltage in different IGBTs is shown in Fig. 4(a). The primary side uses a bipolar
ways, as shown in Fig. 2(c). Once a small gap exists at t2 , square wave of frequency f m as the input signal, while the
the first module of PEI could be turned off first, and the other same square waveform with different voltage amplitudes from
series modules could be turned off sequentially. Between t2 the resistor divider is connected to the input of the analog
and t2  , the total clamping voltage VPEI should be smaller than switch. After changing the control signal v c , the single output
the dielectric strength of VS to avoid the breakdown. Since v o of the analog switch becomes a magnitude-variable square
the PEI turns off earlier compared to the simultaneous turn- wave, which could convey the gate signal information. Next,
off strategy, the clearing time as well as the total absorbed this high-frequency-modulated signal is sent to a class B
energy by MOV could be reduced [23]. amplifier to boost power and followed by an HV transformer
The traditional transformer-coupled gate driver is presented (HVT) for the isolation.
in Fig. 3, which transfers the ON / OFF gate signal to the sec- Since the gate drivers for the series-connected devices
ondary side directly [26]. However, this method is sensitive to should be isolated from each other, the secondary winding
leakage inductance, and bad transformer coupling will distort number in the traditional transformer-coupled structure equals
the driver output [27]. Besides, the long-term ON - or OFF-state the device number [33]. In the MV or HV cases, not only
operation will cause the saturation of the core, and this is the insulation between primary and secondary windings but
exactly the special requirement of the SSCB and HCB. In order also insulation among the different secondary windings should
to avoid the core saturation, the symmetric pulse operation be considered. In [33], the multiwinding pulse transformer
is proposed, such as the edge-triggered method [28], [29] (PT) used the wire coating and core coating to avoid the
and the high-frequency-modulated gate signal strategy [30], breakdown, but the partial-discharge (PD)-free operation could

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1630 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 11, NO. 2, APRIL 2023

not be guaranteed. Besides, the window area utilization of

this toroidal core is low, and this design cannot be easily
applied to higher voltage applications. Therefore, an HV, high-
frequency and low-power multiwinding compact PT design is
very challenging.
In order to solve this issue, a new transformer structure with
a single HVT and several cascade LV transformers (LVTs) in
Fig. 4(a) is proposed in this article. Both the HVT and LVTs
have only one secondary winding to interface the secondary
circuits, which means that the total transformer number equals
the device number. Since the voltage potential difference
between two adjacent devices cannot exceed the clamping
voltage of MOV, the LVTs need to withstand only single
MOV clamping voltage, whereas the HVT needs to handle
the sum of all MOV voltages. Compared to the multiwinding
PT, the design difficulty of this HVT is reduced significantly.
Besides, this cascade structure has good scalability. More
series devices and cascade LVTs as well as corresponding
secondary circuits could be added to reach higher voltage.
The LVT does not need to change, and only HVT should be
redesigned to handle higher voltage. An example of the planar
HVT will be illustrated later.
The secondary circuit in Fig. 4(b) should decode the
gate driver command signal and obtain the driver power from
the high-frequency square wave. Therefore, two sets of diode
bridges (DRs) are utilized here. One DR could reconstruct Fig. 5. Modulation signal, rectifier output, and three gate voltages.
the signal v rec with a small output capacitor C1 and discharge
signal v rec drop to 0. Since the low-level reference voltage
resistor R1 , While the other DR with large output capacitor
Vref_l is designed to be the same for all modules, the gate volt-
C2 can provide the supply voltage Vss for both the signal
age becomes Vss and all modules are turned on simultaneously.
processing circuit and the gate driver power supply. Since the
Then, the primary side generates the maximum amplitude at
on-time duration is not long, the capacitor C2 is large enough
t2 so that the gate side becomes the OFF state again. These
to store the energy to drive the gate side. The capacitance of
gate-side waveforms match the required function, as shown in
C2 should meet the following requirement of the gate charge
Fig. 2(b).
during the turn-on or turn-off process
As for the staged turn-off, the control signals are the same
1 1 except for the turn-off transition. Therefore, the square waves
2
C2 VC2 ≥ (Vss − Vee ) · Q g . (1)
2 2 with different voltage levels are generated sequentially with
the designed stage duration. Since the hysteresis controller
A hysteresis comparator with low reference voltages Vref_l
reference voltage v ref_h is designed to match the voltage levels
and high reference voltage Vref_h is employed here to extract
of v rec , the turn-off command will be different so that IGBTs
the gate voltage signal. If v rec is lower than Vref_l , the com-
are turned off sequentially required in Fig. 2(c). Once the
parator output is 0, and when v rec is higher than Vref_h , the
parameters of hysteresis controller are determined, the stage
output is Vss . Different turn-off signals could be generated by
duration can be adjusted easily by changing the control signal
tuning the resistance network to change the voltage reference
of the analog switch.
values, thus realizing the staged turn-off strategy. A dc/dc chip
is employed to produce a negative turn-off voltage Vee so that
the device could be turned off safely. In order to suppress the C. Nonideal Factors and Common-Mode Current
gate voltage overshoot during the turn-off transient, a transient The previous analysis is based on the ideal condition, where
voltage suppressor (TVS) or Zener diode Dp could be added the turn-on and turn-off delays of the class B amplifier, the
across the voltage source. parasitic capacitor of DR, and the leakage inductance of
The typical waveforms from the primary to secondary side the transformer are neglected. When these nonideal factors
of two turn-off strategies are plotted in Fig. 5. In the normally are taken into consideration, the voltage ripple will appear in
OFF state, the analog switch outputs the square waves with the reconstructed signal v rec . As a result, there is a tradeoff
the maximum amplitude, which corresponds to the maximum to select the filter parameters. A larger R1 (or C1 ) will bring
reconstructed signal v rec of the secondary circuit and is higher a smaller voltage ripple of each voltage level but slower the
than the reference voltage Vref_h of all modules. According to discharge speed of v rec .
the principle of the hysteresis comparator, this OFF command In addition, the voltage ripple of different voltage
will make gate driver generate the turn-off voltage of Vee . At t1 , levels should not overlap with each other so that the dif-
the class B amplifier output voltage v pri and the reconstructed ferent threshold values could be designed to identify them.

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LIU et al.: COMPACT MV-INSULATED MHz TRANSFORMER-COUPLED GATE DRIVER 1631

TABLE I
PART N UMBERS OF S INGLE M ODULE

Fig. 6. Interleaved operation and scalability of two sets of gate drivers.

Fig. 7. CM model for the proposed gate driver with five series devices.

This requirement also limits the total voltage level between

0 and Vss . In order to increase the total number of series
modules, 2 or 3 modules could adopt the same comparator
parameters and have the same gate signals. However, it should
be noted that the total number of IGBTs is limited by the
voltage drop across the leakage inductor and the increased
Fig. 8. Hardware picture of the primary circuit.
power consumption of HVT and LVT. Since the first LVT
needs to deliver all the power for subsequent stages, a larger
core and thicker wire should be used to ease higher thermal gate driver solution. As the most important component of PEI,
stress. the solid-state devices should be determined first. According
Besides, several sets of the proposed transformer-coupled to [5], the 1.7-kV discrete IGBT from IXYS is selected here
gate driver could be interleaved with each other to increase due to the good surge current conduction and interruption
the total stage number. As shown in Fig. 6, the second set of capability. Besides, the RC snubber is paralleled with the MOV
primary circuit could delay the turn-on command until the last to suppress the current bump and avoid device failure.
stage of first set of gate driver ends. In this way, the total stage In the primary circuit, the modulation frequency is selected
number is doubled compared to the configuration in Fig. 5. as 2 MHz due to the tradeoff between the transformer size
The common-mode (CM) noise is a big concern for the MV and the switching speed of BJT in class B amplifier. Ultrahigh
and HV converters, where high dv/dt causes severer electro- modulation frequency such as 20 MHz in [32] could achieve
magnetic interference (EMI) issues. The CM current amplitude a better duty resolution in the PWM converter. However,
is directly related to the parasitic capacitance between the such high resolution is not necessary for the PEI and will
primary side and the jumping node. The CM current path cause higher losses instead. Therefore, the specific components
of the proposed gate driver could be plotted in Fig. 7. CHVT chosen for Fig. 3 are listed in Table I. The 2-MHz square
and CLVT are the parasitic capacitances of the HVT and LVT, source comes from the function generator or a clock chip, and
respectively. L p refers to the parasitic inductance. It can be the control signals of 3–8 encoder inside the analog switch
seen that in this cascade structure, all the parasitic capacitor come from the fiber optics. Since the switching characteristics
is connected in series, which reduced the total equivalent of the complementary BJTs are not totally same, a dc-blocking
value [34]. Therefore, the CM current is lower than the single capacitor is inserted into the HVT to avoid saturation. The
transformer structure. In addition, a small CM choke could be hardware picture of the primary circuit is shown in Fig. 8.
inserted between each LVT to increase the impedance of each As for the secondary circuit, the LVT uses a toroidal ferrite
CM path. core with a turn ratio of 1. Since this LVT only needs
to withstand 700 V, this LVT could be very compact. The
III. E XPERIMENTAL P ROTOTYPE
LVT adopts the toroidal core from fair rite (5980000201)
A. Primary and Secondary Circuits’ Design with the turn number of 10:10. It features a small size of
This section will introduce a practical PEI design and 9.5 mm diameter and 3.18 mm height and has the transformer
implementation based on the proposed transformer-coupled inductance of 24 μH and the coupling effect of 0.99.
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1632 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 11, NO. 2, APRIL 2023

Fig. 9. Hardware picture of the secondary circuit.

DR 1 uses four Schottky diodes with the small capacitors

to suppress the voltage ripple of v rec . A high-bandwidth
operational amplifier (OA) LM7171 is selected to build the
hysteresis comparator, and the resistance network is deter-
mined by the designed reference voltages Vref_l and Vref_h
 
VTH = Vref_h + Vref_l /2, VHYS = Vref_h − Vref_l (2)
R3 = R2 · VTH /(Vss − VTH ) (3)
Vss − VHYS
R4 = R2 · R3 · . (4)
(R2 + R3 ) · VHYS
The gate driver UCC23511 from TI is selected to interface
the HV output of the comparator, and the gate resistance is
set as 10 . In order to produce −5 V for the safe turn-off, a
charge pump dc–dc converter is used here. Then, the hardware
picture of three series IGBTs is given in Fig. 9.

B. HVT Design Based on PCB Winding

The most important function of HVT is the insulation
Fig. 10. (a) Drawing of the designed HVT with two ELP cores and PCB
capability between the primary and secondary sides. Various winding. (b) Front view and layer allocation of the PCB board. (c) PCB
kinds of material have already been utilized to improve this winding design of layers 2, 4, and 6 from top view.
capability, including the Kaptan tape [35], FR4 [36], [37] and
polymeric materials such as epoxy, silicone, and resins [38],
[39], [40]. Considering the film effective thickness of Kaptan 3) Proper shielding design could force the E-field gradient
tape and the possible PD of the air between multiple layers applied inside PCB.
of Kaptan tape, some researchers have turned to polymeric Following this concept, Fig. 10(a) gives the dimension
materials. However, a complicated impregnation or vacuum and the assembly of this planar HVT. Two ELP cores
potting process is necessary to remove all the air bubbles [38], (B66455G0000X608) are selected to achieve the desired
[39], [40]. The vacuum high-temperature lamination process power density and form factor [42]. The voltage potential of
enables printed circuit board (PCB) as a novel high-density the core as well as the shield layer is tied to the primary side.
insulation solution [41]. The PCB-based electric-field (E-field) The distance of 35.7 mm between the secondary terminal and
shielding and shaping design can be easily applied to control the core is designed for the creepage distance requirement
the E-field distribution within a complex geometry and reduce [36]. Fig. 10(b) shows the front sectional view of the designed
the E-field stress exposure in the air [41]. Therefore, the PCB- six-layer PCB winding. The thickness of the dielectric layer
planar-based winding solution is adopted to enable compact between the primary (or shield) and secondary winding is
but MV-insulated capability. set as 1.5 mm, which is much smaller than the required
The key insulation design point considerations of the planar distance in air. In order to connect the secondary winding in
HVT could be summarized as follows. layers 3 and 4, a buried via should be used here to avoid a
1) The voltage potential of the magnetic core should be small creepage distance between the through hole via and the
tied to the primary low voltage side. core.
2) The high-side secondary winding is placed in the PCB The detailed winding and shield deign of layers 2, 4, and 6
inner layers impregnated by FR4, which has much are shown in Fig. 10(a). The winding structure in layers 2 and
higher dielectric strength than air. layer 4 is simple and similar to a traditional planar transformer.

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LIU et al.: COMPACT MV-INSULATED MHz TRANSFORMER-COUPLED GATE DRIVER 1633

maximum E-field of the air surface layer above PCB is only

1.5 kV/mm as in Fig. 11(b), which locates at the cross point
of the shield polygon and the secondary winding. In order to
demonstrate the shield wire effect in the secondary winding
layer, the E-field distribution of layer 3 is given in Fig. 11(c).
With two different scales, it can be observed that almost all
the E-field is limited inside the PCB successfully, and the
maximum value of 22 kV/mm is still lower than the strength
of FR4 (25 kV/mm). Above all, the proposed HVT design has
good performance to withstand 6 kV.
In order to verify the feasibility of designed HVT, the peak
transformer flux density B p should be checked. The magnitude
of the sinusoidal voltage applied to the primary winding is
estimated to be the fundamental component of the square
waveform. Thus, the peak transformer flux density B p can
be calculated as [38]
2v m
Bp = 2 (5)
π N p Am fm
where v m (15 V) is the amplitude of the square wave and Am
(78.3 mm2 ) denotes the surface area of the core. It can be
calculated that B p = 3.2 mT, smaller than the recommended
the upper limit of 50 mT. Therefore, the design is feasible
from a transformer perspective.

C. Test of the HVT Properties

The built HVT shown in Fig. 12(a) has been characterized
via the impedance analyzer Agilent 4294A. The measure-
ment of the primary- and secondary-side inductances indicates
L p = 69.8 μH and L s = 119.2 μH and together with a
measured leakage inductance of L k = 3.25 μH (referenced
to the primary side). As a result, the transformer coupling
factor can be calculated as

Lk
k = 1− = 0.97. (6)
Lp
Fig. 11. FEM simulation of the designed HVT showing the E-field
distribution of (a) front sectional view, (b) top view of air surface layer above Therefore, the designed HVT has good coupling and low
PCB, and (c) top view of layer 3.
leakage inductance. In fact, this gate driver solution is not
sensitive to the leakage inductance, which means that HVT
However, the shield design is unique and more important here. could be designed with more flexibility. For example, another
On one hand, the meshed shield polygon in layer 2 could HVT structure [39] with separate windings for the primary
suppress the E-field in the air above the PCB top surface and secondary cores is also feasible and can achieve higher
and avoid more eddy current losses. On the other hand, the insulation voltage.
shield wire surrounds the secondary winding in layer 4 without In addition to the inductance, the parasitic coupling capac-
forming a closed loop. In this way, the most E-field is forced itance CHVT between the primary side and the secondary
inside the PCB instead of the air gap between the PCB and side is also measured to be 9.7 pF. This is caused by the
the magnetic core. In addition to the winding, the E-field overlap of primary and secondary winding, but it is acceptable
around the corner of the top layer secondary terminal could considering the relatively low dv/dt of the PEI clamping
be suppressed with a larger polygon area in layer 2 [40]. voltage. The turn-off speed of IGBT and the snubber circuit
In order to analyze the E-field distribution of the designed can help to reduce dv/dt too.
HVT, a finite-element method (FEM) simulation process is The insulation performance of the designed HVT is also
performed through the ANSYS Maxwell solver. The model validated using the HV PD test setup shown in Fig. 12(b). A
primarily implemented in Altium Designer was exported into 60-Hz ac source is applied between the primary and secondary
ANSYS SIWAVE and then Maxwell with the assigned voltage terminals of the HVT. Besides, a high-frequency current
excitation difference of 6 kV. The corresponding simulation transformer (HFCT) is employed to capture the PD impulse
results are presented in Fig. 11. As can be seen from the front currents, and the threshold discharge value is set as 20 pC. The
sectional view of Fig. 11(a), the shield polygon in layer 2 corresponding result shown in Fig. 12(c) demonstrates the plot
could effectively limit most E-field inside FR4. In this way, the of charge versus time as well as the PD pattern with the PD

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1634 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 11, NO. 2, APRIL 2023

Fig. 13. (a) Schematic of the surge current test structure. (b) Experimental
setup of surge current test.

Fig. 12. (a) Hardware picture of the designed HVT. (b) PD test setup to
measure HVT. (c) PD test waveform.

inception voltage (PDIV) of 13.3 kV, much higher than the

expected value.
IV. S IMULATION AND E XPERIMENT VALIDATION
A. Simulation Results
The simulation study was performed using PSpice to val-
idate the effectiveness of the proposed method. The surge
current test shown in Fig. 13(a) has been chosen as the
simulation topology and the experimental verification in the
following. The dc bus voltage is set as 1.5 kV, and the line
inductance is set as 0.4 mH to limit the fault current rise rate.
The simulation results are shown in Fig. 13. Compared to the
ideal waveforms as shown in Fig. 5, the voltage ripple becomes
larger, but as long as two adjacent stages do not overlap
with each other, the hysteresis controller could still distinguish
five stages. Besides, the staged turn-off strategy demonstrates
lower peak current as well as total energy compared to the Fig. 14. (a) Simulation waveforms of PEI with simultaneous strategy.
simultaneous turn-off strategy. (b) Simulation waveforms of PEI with staged turn-off strategy.

B. Gate Driver Signal Verification

In the first experimental test, the basic gate driver func- (two secondary circuit boards in Fig. (8) with parameters
tions and performance are verified using five series modules in Table I.

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LIU et al.: COMPACT MV-INSULATED MHz TRANSFORMER-COUPLED GATE DRIVER 1635

TABLE II
R ELATIONSHIP B ETWEEN THE C ONTROL S IGNAL AND HVT P RIMARY
O UTPUT A MPLITUDE

TABLE III
PARAMETERS OF T EST S ETUP
Fig. 15. Thermal cameral picture of the gate driver.

Fig. 17. Experimental waveforms of surge current test with (a) simultaneous
and (b) turn-off strategies.

Before testing the surge current characteristics of this gate

driver, the normally OFF state is measured first to evaluate the
thermal performance. It is observed that the total power con-
sumption for five modules is 6 W for the OFF-state operation
of the IGBTs and the corresponding thermal camera results
are given in Fig. 15. Obviously, the maximum temperature
(60 ◦ C) is located at the first LVT, which needs to deliver all
the power for subsequent stages.
Fig. 16. (a) Experimental waveforms of PEI with simultaneous strategy. The simultaneous turn-off strategy is implemented, and the
(b) Experimental waveforms of PEI with staged turn-off strategy. corresponding results are shown in Fig. 16(a). The ON-state
duration is set as 500 μs. It can be seen that the charging
The waveforms of the analog switch control signals v c1−3 , speed of v rec is much faster than the discharging speed, which
the transformer primary voltage v pri , the reconstructed voltage matches the previous analysis. Another staged turn-off strategy
from rectifier of secondary circuit v rec , and the gate-emitter with the stage duration of 10 μs is also implemented, as shown
voltage v ge1−5 are plotted in Fig. 14. The analog switch digital in Fig. 16(b).
control signal v c could select one of the eight input channels
as the output signal. For clarification, the relationship between
C. Surge Current Test
the control signal and the HVT primary-side signal amplitude
is given in Table II. For example, when v c3 v c2 v c1 = 111, the In order to experimentally demonstrate the feasibility of
analog switch output has the maximum amplitude. the proposed transformer-coupled gate driver method and the

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1636 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 11, NO. 2, APRIL 2023

structure. With the good scalability, the DCCB with higher

blocking voltage can be achieved more easily based on the
proposed gate driver method.

ACKNOWLEDGMENT
The views and opinions of authors expressed herein do
not necessarily state or reflect those of the United States
Government or any agency thereof.

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Oct. 2020, pp. 6016–6023. China, in 2016 and 2019, respectively. He is cur-
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current injection,” IEEE J. Emerg. Sel. Topics Power Electron., vol. 9, Mr. Liu was a recipient of the Best Paper Award of
no. 3, pp. 2500–2509, Jun. 2021. ECCE-Asia 2020 and the Outstanding Presentation
[25] W. Wen, Y. Huang, Y. Sun, J. Wu, M. Al-Dweikat, and W. Liu, Award of APEC 2021.
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[26] V. Zorngiebel, E. Spahn, G. Buderer, A. Welleman, and W. Fleischmann, received the bachelor’s degree in electrical engi-
“Compact high voltage IGBT switch for pulsed power applications,” neering from Anna University, Chennai, India,
IEEE Trans. Magn., vol. 45, no. 1, pp. 531–535, Jan. 2009. in 2011, and the M.S. degree in electrical engineer-
[27] K. S. Muhammad and D. D.-C. Lu, “Magnetically isolated gate driver ing from the University of Minnesota, Minneapolis,
with leakage inductance immunity,” IEEE Trans. Power Electron., MN, USA, in 2015. She is currently pursuing the
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design for > 100◦ C ambient temperature,” in IEEE Trans. Power Blacksburg, VA, USA.
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isolated gate drive topologies for silicon carbide (SiC) JFET,” in Proc. WI, USA, as a Power Electronics Engineer. Her research interests include
34th Annu. Conf. IEEE Ind. Electron., Nov. 2008, pp. 2867–2872. insulation design and circuit protection of medium-voltage power converters.
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[31] A. Seidel, M. Costa, J. Joos, and B. Wicht, “Isolated 100% PWM gate
driver with auxiliary energy and bidirectional FM/AM signal transmis- Rolando Burgos (Senior Member, IEEE) received
the B.S. degree in electronics engineering, the Elec-
sion via single transformer,” in Proc. IEEE Appl. Power Electron. Conf.
Expo. (APEC), Mar. 2015, pp. 2581–2584. tronics Engineering Professional degree, and the
[32] Z. Guo and H. Li, “A MHz-pulse-transformer isolated gate driver with M.S. and Ph.D. degrees in electrical engineering
signal-power integrated transmission for medium-voltage SiC MOS- from the University of Concepción, Concepción,
FETs,” IEEE Trans. Power Electron., vol. 37, no. 8, pp. 9415–9427, Chile, in 1995, 1997, 1999, and 2002, respectively.
Aug. 2022. In 2002, he joined the Center for Power Electron-
[33] F. Zhang, Y. Ren, X. Yang, W. Chen, and L. Wang, “A high input ics Systems (CPES), Virginia Tech, Blacksburg, VA,
voltage auxiliary power supply utilizing automatic balanced MOSFET USA, as Post-Doctoral Fellow, where he became a
stack,” IEEE Trans. Ind. Electron., vol. 68, no. 11, pp. 10654–10665, Research Scientist in 2003 and a Research Assis-
Nov. 2021. tant Professor in 2005. In 2009, he joined ABB
[34] V.-S. Nguyen, P. Lefranc, and J.-C. Crebier, “Gate driver supply architec- Corporate Research, Raleigh, NC, USA, where he was a Scientist from
tures for common mode conducted EMI reduction in series connection of 2009 to 2010 and a Principal Scientist from 2010 to 2012. In 2010, he was
multiple power devices,” IEEE Trans. Power Electron., vol. 33, no. 12, appointed as an Adjunct Associate Professor at the Future Renewable Electric
pp. 10265–10276, Dec. 2018. Energy Delivery and Management (FREEDM) Systems Center, Electrical and
[35] A. Anurag, S. Acharya, N. Kolli, and S. Bhattacharya, “Gate drivers for Computer Engineering Department, North Carolina State University, Raleigh.
medium-voltage SiC devices,” IEEE J. Emerg. Sel. Topics Ind. Electron., In 2012, he returned to the Bradley Department of Electrical and Computer
vol. 2, no. 1, pp. 1–12, Jan. 2021. Engineering, Virginia Tech as an Associate Professor, where he earned his
[36] L. Makki et al., “Equivalent circuit model of a pulse planar transformer tenure in 2017 and was promoted to a Professor in 2019. Since 2021, he has
and endurance to abrupt dv/dt,” IEEE Trans. Power Electron., vol. 37, been the Director of CPES. His research interests include high power density
no. 9, pp. 10585–10593, Sep. 2022. wide bandgap semiconductor-based power conversion—low- and medium-
[37] O. C. Spro et al., “Optimized design of multi-MHz frequency isolated voltage applications, packaging and integration, electromagnetic interference
auxiliary power supply for gate drivers in medium-voltage converters,” (EMI) and electromagnetic compatibility (EMC), multiphase multilevel power
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[38] N. Yan, D. Dong, and R. Burgos, “A multichannel high-frequency stability of ac and dc power systems.
current link based isolated auxiliary power supply for medium-voltage Dr. Burgos is a member of the IEEE Power Electronics Society, where he
applications,” IEEE Trans. Power Electron., vol. 37, no. 1, pp. 674–686, currently serves as Associate Editor for the IEEE T RANSACTIONS ON P OWER
Jan. 2022. E LECTRONICS and the IEEE J OURNAL OF E MERGING AND S ELECTED
[39] D. Rothmund, D. Bortis, and J. W. Kolar, “Highly compact isolated T OPICS IN P OWER E LECTRONICS . He is also a member of the IEEE Industry
gate driver with ultrafast overcurrent protection for 10 kV SiC MOS- Applications Society, the IEEE Industrial Electronics Society, and the IEEE
FETs,” CPSS Trans. Power Electron. Appl., vol. 3, no. 4, pp. 278–291, Power and Energy Society. He is the past Chair of the Technical Committee
Dec. 2018. on Power and Control Core Technologies.

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1638 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 11, NO. 2, APRIL 2023

Steve C. Schmalz received the bachelor’s and Dong Dong (Senior Member, IEEE) received
master’s degrees in electrical engineering from the B.S. degree from Tsinghua University,
Marquette University, Milwaukee, WI, USA, in 1993 Beijing, China, in 2007, and the M.S. and Ph.D.
and 2000, respectively. degrees in electrical engineering from Virginia
He is currently a Senior Specialist with the Tech, Blacksburg, VA, USA, in 2009 and 2012,
Research Labs, Eaton Corporation, Milwaukee, WI, respectively.
USA. In his 30 years with Eaton’s research group, From 2012 to 2018, he was with the GE Global
his experience spans many domains focusing on Research Center (GRC), Niskayuna, NY, USA,
electrical protection, motor control and diagnostics, as an Electrical Engineer. At GE, he participated
sensing technology, and energy management. He has in and led multiple technology programs, including
served as a Principal Investigator on multiple U.S. medium-voltage (MV)/HVdc power distribution
Government-funded research programs developing technology for both terres- and power delivery, silicon carbide (SiC) high-frequency high-power
trial and aerospace power applications. He holds 35 issued patents and one conversion systems, solid-state transformers, and energy storage systems.
trade secret. Since 2018, he has been with the Bradley Department of Electrical and
Mr. Schmalz is a fellow of the Eaton Society of Inventors. He is a licensed Computer Engineering, Virginia Tech. He has published over 45 referred
Professional Engineer in the State of Wisconsin and is also a Certified Eaton journal publications and more than 100 IEEE conference publications.
Design For Six Sigma (DFSS) Green Belt. He currently holds 34 granted U.S. patents. His research interests include
wide bandgap power semiconductor-based high-frequency power conversion,
Andy Schroedermeier (Member, IEEE) received soft-switching and resonant converters, high-frequency transformers, and
the B.S. degree in engineering from the Dordt MV and high-voltage (HV) power conversion systems for grid, renewable,
College, Sioux Center, IA, USA, in 2008, and and transportation applications.
the M.S. and Ph.D. degrees in electrical engineer- Dr. Dong received multiple technology awards, including the GE Silver
ing from the University of Wisconsin–Madison, and Gold Medallion Patent Awards and the GE Technology Transition
Madison, WI, USA, in 2016 and 2019, respectively. Awards. He received two Transaction Prize Paper Awards from the IEEE
At the University of Wisconsin–Madison, his grad- T RANSACTIONS ON P OWER E LECTRONICS and IEEE T RANSACTIONS
uate work in power electronics and passive compo- ON I NDUSTRY A PPLICATIONS, the William Portnoy Prize Paper Award
nent integration was performed with the Wisconsin and Transportation Systems Prize Paper Award from IEEE IAS, and the
Electric Machines and Power Electronics Consor- NSF CAREER Award. He served as the Vice Chair for the IEEE Industry
tium. He is currently a Power Electronics Research Application Society Schenectady Region Chapter in 2017 and the General
Engineer with Eaton Corporation, Milwaukee, WI, USA. His research interests Chair for IEEE International Conference on DC Microgrids in 2021.
include power electronics, power electronic component integration, and solid- He is currently an Associate Editor of IEEE T RANSACTIONS ON P OWER
state circuit protection. E LECTRONICS .

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