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Chapter 1 – Introduction

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1.1 Electronic Design Automation (EDA)

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Moore’s Law

Moore: „Cramming more components onto integrated circuits"

In 1965, Gordon Moore (Fairchild)
stated that the number of
transistors on an IC would double
every year. 10 years later, he
revised his statement, asserting
that they double every 18 months.
Since then, this “rule” has been

Electronics, Vol. 38, No. 8, 1965

famously known as Moore’s Law.

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1.1 Electronic Design Automation (EDA)

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Time Period Circuit and Physical Design Process Advancements

1950 -1965 Manual design only.

1965 -1975 Layout editors, e.g., place and route tools, first developed for
printed circuit boards.

1975 -1985 More advanced tools for ICs and PCBs, with more sophisticated
algorithms.

1985 -1990 First performance-driven tools and parallel optimization algorithms

for layout; better understanding of underlying theory (graph theory,
solution complexity, etc.).

1990 -2000 First over-the-cell routing, first 3D and multilayer placement and
routing techniques developed. Automated circuit synthesis and
routability-oriented design become dominant. Start of parallelizing
workloads. Emergence of physical synthesis.

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2000 - now Design for Manufacturability (DFM), optical proximity correction
(OPC), and other techniques emerge at the design-manufacturing
interface. Increased reusability of blocks, including intellectual
property (IP) blocks.

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 1.3 VLSI Design Styles

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Layout editor
Menu Bar Toolbar

Drawing Tools

Layer Palette
Locator

Cell Browser

Mouse Buttons Bar Text Windows

Layout Windows
Status Bar

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 1.3 VLSI Design Styles Vdd Contact

Metal layer

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Vdd IN2 Poly layer
IN2
IN1 OUT Diffusion layer
OUT
IN1 p-type
transistor

n-type
GND
transistor
GND
IN1
OUT
IN2

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 1.3 VLSI Design Styles

© KLMH
Standard cell layout with Standard cell layout using
a feedthrough cell over-the-cell (OTC routing

Power Standard Ground Power Standard Ground

Pad Pad
Pad Cells Pad Pad Cells Pad

A A
VDD VDD

GND
A’ GND

A’

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Feedthrough Routing
Cell Channel
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1.3 VLSI Design Styles

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Field-programmable gate
array (FPGA)

Logic Element
LB LB LB
Switchbox Connection
SB SB

LB LB LB

SB SB

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LB LB LB LB

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 1.4 Layout Layers and Design Rules

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Categories of design rules

• Size rules, such as minimum width: The dimensions of any component (shape),
e.g., length of a boundary edge or area of the shape, cannot be smaller than given
minimum values. These values vary across different metal layers.

• Separation rules, such as minimum separation: Two shapes, either on the same
layer or on adjacent layers, must be a minimum (rectilinear or Euclidean diagonal)
distance apart.

• Overlap rules, such as minimum overlap: Two connected shapes on adjacent layers
must have a certain amount of overlap due to inaccuracy of mask alignment to
previously-made patterns on the wafer.

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 1.5 Physical Design Optimizations

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Types of constraints

• Technology constraints enable fabrication for a specific technology node and are
derived from technology restrictions. Examples include minimum layout widths and
spacing values between layout shapes.

• Electrical constraints ensure the desired electrical behavior of the design. Examples
include meeting maximum timing constraints for signal delay and staying below
maximum coupling capacitances.

• Geometry (design methodology) constraints are introduced to reduce the overall

complexity of the design process. Examples include the use of preferred wiring
directions during routing, and the placement of standard cells in rows.

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 1.6 Algorithms and Complexity

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Runtime complexity

• Example: Exhaustively Enumerating All Placement Possibilities

− Given: n cells
− Task: find a single-row placement of n cells with minimum total wirelength by using
exhaustive enumeration.
− Solution: The solution space consists of n! placement options. If generating and
evaluating the wirelength of each possible placement solution takes 1 µs and
n = 20, the total time needed to find an optimal solution would be 77,147 years!

• A number of physical design problems have best-known algorithm complexities that

grow exponentially with n, e.g., O(n!), O(nn), and O(2n).
• Many of these problems are NP-hard (NP: non-deterministic polynomial time)
− No known algorithms can ensure, in a time-efficient manner, globally optimal solution
⇒ Heuristic algorithms are used to find near-optimal solutions

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1.6 Algorithms and Complexity

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Heuristic algorithms

Problem Instance
Constructive Algorithm
Initial Solution

Iterative Improvement

no
Termination
Criterion Met?

yes
Return Best-Seen Solution

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1.7 Graph Theory Terminology

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Directed graphs with cycles Directed acyclic graph

c f c f
a a
a b
b d g b d g

e e

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 1.7 Graph Theory Terminology

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Rectilinear minimum spanning Rectilinear Steiner minimum
tree (RMST) tree (RSMT)

b (2,6) b (2,6)

Steiner point

c (6,4) c (6,4)

a (2,1) a (2,1)

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 1.8 Common EDA Terminology

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Connectivity graph

a x a x
N3 N5
N1 N2 z c z c
N4
y
b b y

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 1.8 Common EDA Terminology

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Distance metric between two points P1 (x1,y1) and P2 (x2,y2)

n n
d = x2 − x1 + y2 − y1
n

with n = 2: Euclidean distance d E ( P1 , P2 ) = ( x2 − x1 ) 2 + ( y 2 − y1 ) 2

n = 1: Manhattan distance d M ( P1 , P2 ) = x2 − x1 + y 2 − y1

P1 (2,4) dM = 7

dE = 5

dM = 7 P2 (6,1)

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