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Traffic Light Controller

The Traffic Light Controller (TLC) project utilizes a finite state machine (FSM) to manage traffic lights for East-West and North-South directions based on sensor input. It features six states for different light combinations and includes a testbench to simulate various traffic scenarios. The design aims to provide dynamic traffic control in real-time conditions.

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saitezha
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20 views

Traffic Light Controller

The Traffic Light Controller (TLC) project utilizes a finite state machine (FSM) to manage traffic lights for East-West and North-South directions based on sensor input. It features six states for different light combinations and includes a testbench to simulate various traffic scenarios. The design aims to provide dynamic traffic control in real-time conditions.

Uploaded by

saitezha
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Traffic Light Controller Project

Design Overview: Traffic Light Controller (TLC)

The TLC is designed using a finite state machine (FSM) to


control traffic lights for East-West (EW) and North-South (NS)
directions based on sensor input.

1. States: The system has six states (s0 to s5) for different
traffic light combinations (Green, Yellow, Red) for EW and NS.

2. Inputs: clk (Clock), reset (Asynchronous reset), and x


(Traffic sensor for NS road).

3. Outputs: EW and NS, each representing the traffic light


states (Red, Yellow, Green).

4. FSM: The state transitions based on the traffic sensor x.


If x = 1, the controller adjusts for NS traffic. Otherwise, it
follows a fixed sequence.

5. Testbench: Simulates different traffic scenarios (no


traffic, traffic detected, traffic stops) to validate the
design.

This FSM-based approach ensures dynamic traffic light control


based on real-time conditions.

Design Code:
module tlc(
input clk, reset, x,
output reg [1:0] EW, NS
);
parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010,
s3 = 3'b011, s4 = 3'b100, s5 = 3'b101;
parameter red = 2'b00, yellow = 2'b01, green = 2'b10;
reg [2:0] state, next_state;

always @ (posedge clk or posedge reset) begin


if (reset)
state <= s0;
else
state <= next_state;
end

always @ (state or x) begin


case (state)
s0: next_state = (x)? s1: s0;
s1: next_state = s2;
s2: next_state = s3;
s3: next_state = (x)? s3: s4;
s4: next_state = s5;
s5: next_state = s0;
default: next_state = s0;
endcase
end

always @ (state) begin


case (state)
s0: begin
EW = green;
NS = red;
end

s1: begin
EW = yellow;
NS = red;
end

s2: begin
EW = red;
NS = red;
end

s3: begin
EW = red;
NS = green;
end

s4: begin
EW = red;
NS = yellow;
end

s5: begin
EW = red;
NS = red;
end

endcase
end
endmodule
TestBench Code:
module tlc_tb( );
reg clk;
reg reset;
reg x;
wire [1: 0] EW;
wire [1: 0] NS;
tlc uut (
.clk (clk) ,
.reset (reset),
.x (x),
.EW (EW),
.NS (NS)
);
always #10 clk = ~clk;
task apply_reset;
begin
reset = 1;
#40;
reset = 0;
end
endtask

initial begin
clk=0;
reset = 0;
x= 0;
apply_reset;
$display("Test case 1: No traffic on NS road(x = 0)");
x = 0;
#100;
$display("Test case 2: Traffic detected on NS road(x = 1)") ;
x = 1;
#100;
$display("Test case 3: Traffic stops on NS road (x = 0)");
x= 0;
#100;
$display("Simulation complete.");
$stop;
end
initial begin
$monitor ("Time: %t | State: EW=tb NS=tb | Sensor
x=tb",$time, EW, NS, x);
end
endmodule
Output:
# Time: 0 | State: EW=tb NS=tb | Sensor x=tb200
# Test case 1: No traffic on NS road (x = 0)
run
# Test case 2: Traffic detected on NS road (x = 1)
# Time: 140 | State: EW=tb NS=tb | Sensor x=tb201
# Time: 150 | State: EW=tb NS=tb | Sensor x=tb101
# Time: 170 | State: EW=tb NS=tb | Sensor x=tb001
# Time: 190 | State: EW=tb NS=tb | Sensor x=tb021
run
# Test case 3: Traffic stops on NS road (x = 0)
# Time: 240 | State: EW=tb NS=tb | Sensor x=tb020
# Time: 250 | State: EW=tb NS=tb | Sensor x=tb010
# Time: 270 | State: EW=tb NS=tb | Sensor x=tb000
# Time: 290 | State: EW=tb NS=tb | Sensor x=tb200
run
# Simulation complete.

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