22 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO.

1, JANUARY 2011

Linearization Techniques for CMOS Low Noise

Amplifiers: A Tutorial
Heng Zhang, Student Member, IEEE, and Edgar Sánchez-Sinencio, Life Fellow, IEEE

(Invited Paper)

Abstract—This tutorial catalogues and analyzes previously digital TV tuners has propelled interest in broadband LNA de-
reported CMOS low noise amplifier (LNA) linearization tech- sign. Radios in the same platform interfere with each other, and
niques. These techniques comprise eight categories: a) feedback; multiple channels applied simultaneously to an LNA without
b) harmonic termination; c) optimum biasing; d) feedforward; e)
derivative superposition (DS); f) IM2 injection; g) noise/distortion filtering act as in-band interferences. Consequently, broadband
cancellation; and h) post-distortion. This paper also addresses LNAs must maintain sufficient linearity over a wide frequency
broadband-LNA-linearization issues for emerging reconfigurable range. Emphasis on highly linear transceivers has sparked recent
multiband/multistandard and wideband transceivers. Further- interest in linearizing LNAs [2]. Even though most previously
more, we highlight the impact of CMOS technology scaling
on linearity and outline how to design a linear LNA in a deep reported techniques target narrowband applications and prin-
submicrometer process. Finally, general design guidelines for cipally improve only the third-order intercept point (IIP3), we
high-linearity LNAs are provided. demonstrate why broadband systems require high second-order
Index Terms—Broadband, CMOS technology scaling, derivative intercept point (IIP2) and 1 dB compression point as
superposition, design guidelines, distortion canceling, feedback, well. Because a broadband LNA is exposed to a wide frequency
feedforward, harmonic termination, IIP2, IIP3, IM2 injection, range, we investigate the dependence of IIP2/IIP3 on two-tone
linearity, linearization, low noise amplifier (LNA), , multiband, (center) frequency and frequency spacing.
multistandard, noise canceling, 1 dB compression point, optimum Since LNAs typically have low-amplitude, high frequency in-
biasing, post-distortion, tutorial. puts, the amplifier operates as a weakly nonlinear system with
few relevant harmonics (typically only second and third). Thus,
I. INTRODUCTION
Volterra-series analysis [3] can capture the frequency-dependent
distortion of LNAs and provide insight into how to compensate
T HE plethora of wireless communication standards em-
ployed in a single geographic region and moreover oc-
cupying narrow frequency bands tightly constrains RF-system
that distortion.
CMOS is the most promising technology for systems on a
chip. Although MOSFETs are intrinsically more linear than
linearity. Furthermore, the trend in radio research is to sim-
plify/eliminate the expensive front-end module (FEM), which bipolar transistors [4], they require higher dc current to achieve
demands a highly linear receiver. In particular, since the low the necessary transconductance and linearity, thus linearization
noise amplifier (LNA) is the first block in the receiver chain, it techniques must be employed to reduce the dc power. Deep
must be sufficiently linear to suppress interference and maintain submicrometer (DSM) technology challenges include nonlinear
high sensitivity. output conductance, mobility degradation, velocity saturation,
LNA linearization methods should be simple, should con- and poly-gate depletion; which complicate CMOS LNA lin-
sume minimum power, and should preserve noise figure (NF), earization, especially in the face of low supply voltages. We
gain, and input matching. Many traditional linearization tech- present multidimensional Taylor analysis to evaluate the effects
niques are not feasible for LNAs. For example, resistive source of these nonidealities.
degeneration and floating-gate input attenuation reduce the gain This paper is organized as follows. Section II analyzes previ-
and worsen NF or input matching. Hence, LNA linearization ously reported CMOS LNA linearization techniques. Section III
proves significantly more challenging than that of baseband cir- discusses new broadband-LNA-linearization issues arising in
cuits [1], often requiring innovative techniques. multiband/multistandard/wideband transceivers. Section IV in-
Growing research on reconfigurable multiband/multistandard vestigates the impact of CMOS technology scaling on linearity,
and broadband transceivers such as ultrawideband (UWB) and and provides insights into the design of linear LNAs in DSM
processes. Remarks for high linearity LNA design are provided
in Section V, and Section VI concludes the paper.
Manuscript received December 10, 2009; revised April 20, 2010; accepted
June 02, 2010. Date of current version December 30, 2010. This paper was rec-
ommended by Editor-in-Chief W. A. Serdijn.
II. LINEARIZATION TECHNIQUES
H. Zhang was with the Analog and Mixed-Signal Center, Department of Elec- A weakly nonlinear amplifier with input X and output Y can
trical & Computer Engineering, Texas A&M University, College Station, TX be approximated by the first three power series terms
77843-3128 USA. She is now with Broadcom Corporation, Irvine, CA 92617
USA (e-mail: [email protected]). (1)
E. Sánchez-Sinencio with the Analog and Mixed-Signal Center, Department
of Electrical & Computer Engineering, Texas A&M University, College Station,
TX 77843-3128 USA (e-mail: [email protected]).
where are the linear gain and the second/third-order
Color versions of one or more of the figures in this paper are available online nonlinearity coefficients of the amplifier, respectively. The goal
at http://ieeexplore.ieee.org. of linearization is to make small enough to be negligible,
Digital Object Identifier 10.1109/TCSI.2010.2055353 keeping only the linear term , hence . The purpose
1549-8328/$26.00 © 2010 IEEE
ZHANG AND SÁNCHEZ-SINENCIO: LINEARIZATION TECHNIQUES FOR CMOS LOW NOISE AMPLIFIERS: A TUTORIAL 23

TABLE I A. Feedback
OVERVIEW OF DISTORTION SOURCES AND LINEARIZATION TECHNIQUES
Fig. 1 shows the negative feedback scheme with a nonlinear
amplifier A and a linear feedback factor , where X and Y are
the input and output signals, respectively. is the feedback
signal, and is the difference between X and .
Assuming the nonlinear amplifier A can be modeled by (1),
we obtain the third-order closed-loop power series for Y
(2)

(3)

where are the closed-loop linear gain and second/third-

order nonlinearity coefficients, respectively, and is
the linear open-loop gain. The IIP2 and IIP3 [5] of the amplifier
A and the closed loop system are

(4a)

(4b)

Fig. 1. Nonlinear amplifier with negative feedback. (4c)

of this paper is to discuss the main linearization techniques for

LNAs.
LNA nonlinearity originates from two major sources:
1) nonlinear transconductance , which converts linear
input voltage to nonlinear output drain current; this effect (4d)
is also termed “input limited”;
2) nonlinear output conductance , whose effect becomes
apparent under large output voltage swing and small drain- Hence, negative feedback improves by a factor of
source voltage (i.e., when the device operates near ; it also improves by a factor of when
linear region); also referred to as “output limited.” . As shown by (4d), nonzero degrades IIP3 when
The MOSFET capacitances (the gate-source capacitance , and have opposite signs (this is the case for typical MOSFET
the gate-drain capacitance , the drain-bulk capacitance ) biases). This phenomenon is called “second-order interaction”
are roughly linear when the transistor operates in the saturation [6]. In other words, whenever the amplifier is in feedback, the
region, and when the frequency is less than [44]. Thus, third-order nonlinearity originates from two sources:
for the most part, the capacitors contribute less distortion than 1) intrinsic amplifier third-order nonlinearity;
[43]; however, influences the linearity indirectly 2) “second-order interaction” (originated from intrinsic
through feedback, which will be discussed later. second-order nonlinearity of the amplifier combined with
The IIP3 is degraded by both the intrinsic third-order dis- feedback).
tortion and the “second-order interaction” (caused by intrinsic However, feedback linearity improvement is not as effective
second-order distortion combined with feedback), while IIP2 for LNAs as for baseband circuits because:
originates from intrinsic second-order distortion. 1) the open loop gain cannot be large due to stringent LNA
We categorize previously reported CMOS LNA linearization gain, noise, and power requirement;
techniques into eight clusters: a) feedback; b) harmonic termi- 2) the second-order nonlinearity contributes to the IM3 indi-
nation; c) optimum biasing; d) feedforward; e) derivative su- rectly through “second-order interaction.”
perposition (DS); f) IM2 injection; g) noise/distortion cancella- To illustrate the “second-order interaction,” we use the in-
tion; and h) post-distortion. Note that DS, IM2 injection, and ductively source degenerated LNA [5] as an example. Fig. 2(a)
noise/distortion cancellation are special cases of the feedfor- presents the circuit, and Fig. 2(b) shows its small-signal model
ward technique. using the notation from Fig. 1. The inductor acts as a fre-
Table I illustrates the distortion sources and the corresponding quency-dependent feedback element with , creating
linearization methods. Most of the reported linearization tech- a feedback path between the output current and the gate-
niques focus on suppressing second- and third-order distortion source voltage . For simplicity, we analyze these effects with
of transconductance. Therefore, linearization of higher order a Taylor series—for a more accurate, frequency-dependent anal-
terms (beyond third order) and output conductance still remains ysis refer to the results obtained using Volterra series in [11],
an open problem. [14], [23].
24 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 1, JANUARY 2011

Fig. 3. A versus source-degeneration inductance.

matching resonant network will also contribute to distortion in

practice.
Reducing the degeneration inductance or adding a termina-
tion network such that at the IM2 frequency can mit-
igate “second-order interaction;” the latter approach is called
“harmonic termination.”
B. Harmonic Termination
“Harmonic termination” adds a termination network to ac-
complish one of two effects:
1) BJT case: sets in (3) with the “second-order-inter-
Fig. 2. (a) Inductively source-degenerated LNA. (b) Small-signal model. action” term;
2) CMOS case: forces a certain node voltage to zero at the
First, can be expressed as IM2 frequency.
Equation (3) was obtained assuming a frequency-independent
(5) feedback factor , which is only valid for pure resistive net-
works. For frequency-dependent networks as the case in Fig. 2,
where is the -order coefficient of obtained by taking
Volterra series [3] should be used to capture the memory effects.
the derivative of the drain-source dc current with respect to
To obtain the third-order coefficient in the Volterra series, de-
the gate-to-source voltage at the dc bias point
fined as , a three-dimensional Fourier transform
is performed on the third-order impulse response
(6) of the system. Thus, (3) becomes (7), as shown at the bottom
of the page. is the frequency-dependent linear
Assume input has two frequency components and ; loop gain, which also depends on the feedback components and
thus contains components , , and due to termination impedances , , and shown in Fig. 4. The ex-
the second-order distortion. The product term from pressions and give the mag-
generates IM3 terms and . nitude and phase of a tone at frequency generated
Therefore, the intrinsic second-order nonlinearity contributes to by third-order nonlinearity. For example, given two input tones
third-order intermodulation, IM3, when a feedback mechanism at , to get the IM3 products at , choose
is employed. Note that this “second-order interaction” problem and . Assuming two closely spaced tones,
exists even if the LNA topology is differential because the term i.e., , and , we obtained (8),
is an odd term and cannot be rejected by differential as shown at the bottom of the next page. From (8), the contribu-
operation. tion of second-order distortion to IM3 is defined by the loop gain
Though source degeneration mostly improves linearity, in- at subharmonic frequency and second-harmonic frequency
ductive source degeneration actually has two opposing effects , i.e., and . Therefore, by tuning the termina-
on linearity: tion impedances at and/or , the amplitude and phase of
1) increases by ; the second-order interaction terms can be adjusted to cancel
2) degrades due to “second-order interaction.” the intrinsic third-order distortion term , so that . For
Fig. 3 shows versus source-degeneration inductor Ls for narrowband applications, and are usually out-of-band,
two cases: input tones at 2.4 GHz, 2.41 GHz, and at 5 GHz, keeping the in-band operation unaffected, hence the “harmonic
5.01 GHz. Note that this simulation only includes the distor- termination” technique is also called “out-of-band tuning/termi-
tion from input transconductance, while the loading and input- nation” [7], [8].

(7)
ZHANG AND SÁNCHEZ-SINENCIO: LINEARIZATION TECHNIQUES FOR CMOS LOW NOISE AMPLIFIERS: A TUTORIAL 25

Fig. 4. Common-source LNA with termination impedances. Fig. 5. Harmonic termination: (a) Common-emitter stage with low-frequency-
trap network (L is the package inductance) [9]. (b) Common-gate stage with
TABLE II “RF current source”[13].
THREE INTRINSIC FEEDBACK PATHS.

capacitive cross coupling in the cascode stage further reduces

to [14]. Although their IIP3 improvement is not as
great as that attainable from large passive LC components, it
is more feasible. In [10] and [13] an LC-resonant RF current
source reduces . Fig. 5 shows some termination examples,
in which Lt and Ct form low-frequency/second-harmonic trap
networks [Fig. 5(a)] and [Fig. 5(b)].
Harmonic termination only works well in narrowband sys-
tems because the tuning network is optimized at and , and
The second-order nonlinear current can mix with the input only works for a narrow range of two-tone spacing/center fre-
through three intrinsic feedback paths, as listed in Table II quencies [7]. For wideband applications, and vary con-
for the common source LNA(CS-LNA) and common gate siderably, so it is difficult to tune out the termination impedance.
LNA(CG-LNA). Furthermore, and may fall in-band, affecting the normal
The CG-LNA inherently has less drain-to-gate feedback operations.
than the CS-LNA since its gate is ac grounded, therefore the In summary, to improve CMOS LNA linearity, we should en-
CG-LNA usually has better linearity. sure a small intrinsic third-order coefficient of the transistor,
Resonant tanks can be added to optimally tune and relax the “second-order interaction.” Adding a harmonic
and/or such that the second-order remixing term can- termination network alleviates the latter. Next, we will discuss
cels the IM3 term. Techniques have been reported to tune the a few techniques to reduce the third-order coefficient .
input terminal for bipolar LNAs [7]–[9]. The termina-
tions are commonly implemented with dedicated LC networks, C. Optimal Biasing
which provide high impedance at but small impedance paths
to ground at or . However, the required inductance value Assume the main nonlinearity of a MOS transistor arises
is usually quite large. The low Q factors of the on-chip passive from transconductance nonlinearity, as modeled in (5). To
inductors limit their distortion-cancellation effectiveness and characterize this single-transistor nonlinearity, we fixed its
also affect noise and input matching. Furthermore, on-chip drain-source voltage , swept the gate-source voltage ,
active inductors add noise and nonlinearity, so in practice and then took the first three derivatives of the drain-source
off-chip inductors are employed. dc current with respect to [as defined in (6)] at every
Though popular in BJT LNAs, harmonic termination is less dc bias point to obtain the plots in Fig. 6. While is always
effective for CMOS LNAs [8], [12]. For a stable design, the positive, has a sign inversion.
term in (8) has a positive real part. Thus, can be — Small : because the transistor operates in weak
reduced below only if is positive, which is true for a BJT, inversion, where the vs relation is exponential.
but not for a MOSFET in saturation. Therefore, both and — Large : because mobility degradation/velocity
must be reduced to improve a CMOS LNA’s IIP3. saturation cause gain compression. The key idea of “op-
One way to reduce is to reduce both and timum biasing” is to bias the transistor at the “sweet spot”
[13]. A cascode configuration can reduce to [13], and [44].

(8)
26 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 1, JANUARY 2011

Fig. 8. Proposed dual-auxiliary-path feedforward linearization technique.

4) Due to the “second-order interaction,” the IIP3 peak at the

“sweet spot” decreases and will finally disappear as source
degeneration inductance increases.
W L = 20 0 08 m V = 1 V
Fig. 6. NMOS transconductance characteristics (UMC 90 nm CMOS process, 5) The sweet spot is frequency-dependent, and the IIP3 peak
= = :  , ).
decreases due to parasitic effects [44].
6) Biasing the transistor at restricts the input-stage
transconductance, lowering gain and increasing NF.
An automatic bias circuit could mitigate some of these effects
[15]; however, this “automatic” bias circuit itself is prone to
process variations and requires manual tuning in practice. The
bias point for optimum IIP3 is shifted from the bias for zero
due to “second-order interaction.”
In summary, the “sweet spot” is a single transistor character-
istic and only signifies optimum intrinsic third-order transcon-
ductance nonlinearity. Many other factors will weaken the IIP3
improvement at the “sweet spot.” Furthermore, some claim that
no “sweet spot” exists in practical LNAs because of input/output
networks and parasitics [44].

D. Feedforward

From (5), note that simultaneous cancellation of and

with minimum effects on requires more degrees of freedom.
Generating additional nonlinear currents/voltages, and sub-
sequently summing (subtracting) them accomplishes such
simultaneous cancellation. These actions constitute feedfor-
ward, as illustrated in Fig. 7(a) [16]. An auxiliary path includes
a replica amplifier and signal-scaling factors b and at its
input/output, respectively, to replicate the distortion in the main
path. We use or depending on whether IM2 or IM3 is
to be canceled. Note that if the amplifiers are differential, the
second-order distortion is ideally zero, and yields a linear
output. Without loss of generality, the following discusses the
single-ended case. To obtain the total output Y, we subtract the
output of the auxiliary amplifier from that of the
Fig. 7. Three representations of the feedforward linearization technique. main amplifier . Assuming , by changing the
location and value of scaling factor, we propose two alternate
Though simple in principle, the optimal biasing technique has implementations, shown in Fig. 7(b) and 7(c), respectively.
the following limitations. Assuming the main and auxiliary amplifiers have the same
1) The cancellation is sensitive to process variations (e.g., nonlinearity coefficients , we have
), so we recommend constant-current or constant-gm a) See equation (9)–(11) at the bottom of the next page.
biasing over constant-voltage biasing. b) See equation (12)–(14) at the bottom of the next page.
2) The technique is sensitive to operating point, resulting in c) See equation (15)–(17) at the bottom of the next page.
a limited input-signal amplitude range for effective distor- In these equations, for differential amplifiers. Com-
tion cancellation. paring (11), (14), and (17), the implementation in a) has a gain-
3) The sweet spot shifts to a lower bias current level as the attenuation factor of , thus gain is reduced by 2.5
gain increases, since the output swing increases and non- dB with and as in [16]. On the other hand, the
linear output conductance starts to play a role. proposed implementations in b) and c) increase the gain. Note
ZHANG AND SÁNCHEZ-SINENCIO: LINEARIZATION TECHNIQUES FOR CMOS LOW NOISE AMPLIFIERS: A TUTORIAL 27

that c)’s input attenuator 1/b worsens its NF. The implementa- 3) Highly sensitive to mismatch between the main and auxil-
tions in Fig. 7 can only cancel one type of harmonic at a time; to iary gain stages.
reduce both second- and third-order distortion simultaneously, 4) Power is doubled or tripled since the auxiliary amplifier is
we need an additional degree of freedom, which we could attain an exact copy of the main amplifier.
with two auxiliary paths as shown in Fig. 8. [17] reports an improved feedforward technique, where the
Assuming the main and auxiliary amplifiers have the same auxiliary path only passes the IM3 products. Hence, its dynamic
nonlinearity coefficients , we have (18)–(20), at the bottom range is relaxed, resulting in only 21% power overhead. Next,
of the page. In (20), we have two equations (second and third we will discuss three special cases of the feedforward tech-
term equals zero) and four variables (b, c, n, m), resulting in nique: derivative superposition, IM2 injection, and noise/distor-
multiple solutions. A possible additional constraint is to bound tion cancellation.
the reduction in linear gain to be less than, say, 20%, and one
reasonable solution set is: , , , . E. Derivative Superposition (DS)
This choice causes the linear gain to double. The derivative superposition (DS) method [10], [11], [13],
Note that if the amplifiers are differential, all even order har- [18]–[20] is a special case of the feedforward technique. Notice
monics are ideally zero, and the implementation in Fig. 8 can that the DS method is obtained when in Fig. 7 and when
cancel both third- and fifth-order distortion. the main/auxiliary amplifiers are implemented with transistors
This general feedforward technique improves linearity operating in different regions. Fig. 9(a) depicts a dual-NMOS
without relying on the amplifier’s linearity characteristics; implementation of the DS method. denotes the main/aux-
however, it has several disadvantages. iliary transistor, respectively, and the input matching network is
1) Accurate, noiseless, and highly linear scaling factors (b, c) omitted for simplicity.
are often not feasible. For instance, the off-chip coaxial as- This method is called “derivative superposition” because it
sembly used in [16] is expensive and cannot be integrated. adds the third derivatives of drain current from the main
2) The added active components introduce more noise. and auxiliary transistors to cancel distortion. As discussed in

(9)
(10)

(11)

(12)
(13)
(14)

(15)

(16)
(17)

(18)

(19)

(20)
28 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 1, JANUARY 2011

Fig. 9. (a) DS method with dual-NMOSs. (b) Third-order distortion

terms of the main transistor (g ), auxiliary transistor (g ), and total
output (g ) (UMC 90 nm CMOS process, (W=L) = 20=0:08 m,
(W=L) = 12=0:08 m, V = 1 V ).

Fig. 11. (a) Complementary DS with common-source configuration [21]. (b)

Complementary DS with common-gate configuration [28].

[21]. Since the ac input signal for NMOS/PMOS are out of

phase, the output current is expressed as
(21)
(22)

(23)
Fig. 10. DS method. (a) Additional transistor works in triode region [18]. (b)
Use of a bipolar transistor [19]. The total transconductance increases, the IM2 term decreases
because and have the same sign, and the IM3 term de-
Section II-C, ’s sign changes at the boundary of moderate creases because and have different signs. Fig. 12 com-
and strong inversion region. Thus, proper biasing creates net pares the conventional DS and complementary DS in terms of
zero , as shown in Fig. 9(b). Linearity is improved within a second-order and third-order distortion of the output
finite bias-voltage range instead of just a point. Hence the DS current. A cancellation window for exists in both cases at
method is less sensitive to process variations than the optimum around 500 mV, but is maximized for conventional DS
biasing technique. Moreover, the auxiliary path contains only and minimized for complementary DS. Note that the cancel-
one weak-inversion transistor, resulting in much smaller power lation window is narrower and less flat for complementary DS
consumption than the general feedforward technique. Since the since PMOS and NMOS devices have different linearity char-
DS method employs multiple transistors in parallel with their acteristics, so the IIP3 improvement is not as good as that in
gates connected together, it is also called the “multiple gated a dual-NMOS implementation. Furthermore, as shown in (23),
transistor technique” (MGTR) [10], [11], [13]. Note that since we can either match and for a good IIP3 while slightly
positive and negative characteristic of are not symmetric, the canceling , or we can match and for optimum IIP2,
-cancellation window is fairly narrow with only one auxiliary because IIP2 and IIP3 do not share the same optimum bias. The
transistor, but the window widens with more auxiliary transis- differential DS method is essentially the same as complemen-
tors at the cost of degraded input matching, NF, and gain [11], tary DS, which also alleviates IIP2 problem [19], [22].
[20]. “Second-order interaction” ultimately limits the IIP3 im-
Fig. 10(a) and 10(b) show alternate implementations of the provement at higher frequencies after the intrinsic -induced
DS method that use a triode region [18] or bipolar [19] tran- third-order distortion is canceled by the DS method. The
sistor as the auxiliary device. In Fig. 10(a), and are “modified DS method” alleviates this issue [23], [24].
driven by differential input signals. is biased in deep triode 2) Modified DS: As discussed in Section II-B, three feed-
region, and helps to boost the positive peak of to back paths exist for “second-order interaction”: source-to-gate,
be sufficiently large to cancel the negative peak in of input drain-to-gate, and input-to-gate. The modified DS methods [23],
transistor . In Fig. 10(b), a bipolar transistor provides [24] provide an on-chip solution to minimize the source-to-gate
the positive , and emitter degeneration resistor reduces feedback. The vector diagram in Fig. 13 graphically explains
to match that of for optimum distortion cancellation. the modified-DS concept. In conventional DS, the anti-parallel
1) Complementary DS: Fig. 6 shows that the second-order and result in a zero total , but residual IM3 exists due
term has a positive sign for transistors working in either to contributions (Note: here we neglect ). In the modi-
moderate or strong inversion region. Therefore, techniques, fied DS method, is rotated properly such that the composite
such as conventional DS, that improve third-order distortion vector of and contribution is 180 out of phase with the
usually worsen second-order distortion. The “complementary contribution, yielding zero net IM3. Fig. 14(a) shows the
DS method” employs an NMOS/PMOS pair to improve IIP3 circuit implementation of the modified DS method from [23].
without hurting IIP2 [21], [28]. Note that choice of determines the angle of .
Fig. 11 shows the common-source and common-gate imple- Although the channel noise of weak inversion transistor
mentations, respectively. The ac current combiner in Fig. 11(b) is negligible, its gate-induced noise is inversely proportional to
could be either a large coupling capacitor with negligible drain current, and is added directly to the main transistor’s
impedance within signal bandwidth [28], or a current mirror gate noise because their gates are connected together. also
ZHANG AND SÁNCHEZ-SINENCIO: LINEARIZATION TECHNIQUES FOR CMOS LOW NOISE AMPLIFIERS: A TUTORIAL 29

Fig. 15. Measured IIP3 of LNAs with/without DS method [18] (© 2003 IEEE).

2) The weak-inversion transistor cannot handle large signals

or it will be turned off, resulting in a very limited distortion-
cancellation range.
3) Weak-inversion transistor models are generally not accu-
rate, resulting in considerable discrepancy between simu-
lation and measurement.
4) Triode-region transistors’ positive peaks decrease as
technology scales down, thus complicating the task of
matching their amplitudes with the negative peaks of
in main transistors.
5) Matching transistors working in different regions or
matching bipolar with MOS transistors is difficult if not
impossible, resulting in a linearity improvement sensitive
Fig. 12. Comparison of g , g as a function of gate bias for conventional to PVT variations. Current bias with digital control bits
(dual-NMOS) DS and complementary (PMOS/NMOS) DS (UMC 90 nm
CMOS process, V = 1 V ). [13] or manual adjustment is required for good results in
practice.
Fig. 15 shows an example IIP3 measurement plot [18]. Al-
though it is from a conventional DS method, similar characteris-
tics can be observed with complementary, differential, and mod-
ified DS methods. We observe the following.
1) The DS method works well within the -cancellation
window annotated in Figs. 9(b) and 12 .
2) Even for inputs outside the -cancellation window, the DS
Fig. 13. Vector diagram for the distortion components of: (a) conventional DS method can still reduce the third-order tone below that of
method; (b) modified DS method [23]. the conventional LNA having a main transistor with nega-
tive as long as of the auxiliary transistor is positive.
3) The third-order curve shows a greater-than-three slope
at much smaller input amplitudes after applying the DS
method, because the fifth- and higher odd-order-distortion
terms contribute more appreciably after is canceled.
4) The DS method does not improve the compression point.

F. IM2 Injection
The IM2 injection method eliminates the explicit auxiliary
path entirely by merging it with the main path to reuse the ac-
tive devices and the dc current [25]. To understand the con-
Fig. 14. Circuit implementation of modified DS method [23], [24]. cept, we first recall (8). To reduce IM3, we should minimize
the term. As previously discussed in Section II-B,
affects the input impedance matching. An alternate implemen- making cancel is difficult for CMOS LNAs because these
tation of the modified DS method reported in [24] [Fig. 14(b)] two terms are out-of-phase in a typical design. Furthermore, the
moves to the source of instead of directly connecting self-generated IM2 term has too small an amplitude to suppress
it to the input, thus minimizing the degradation in NF and input sufficiently.
matching. The IM2 injection technique externally generates and injects
Limitations of the DS methods include the following. a low-frequency IM2 component into the circuit. The injected
1) The weak-inversion transistor may not operate at suffi- IM2 phase is inverted with boosted amplitude for IM3 cancel-
ciently high frequency. lation. Hence, IM2 injection could also be viewed as a smart
30 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 1, JANUARY 2011

Fig. 17. Noise/distortion cancellation. (a) Differential output [27], [29]. (b)
Single ended output [28].

Fig. 16. Block diagram and basic cell implementation of “IM2 injection” [25].

implementation of harmonic termination. Fig. 16 illustrates the

concept and basic cells. M1 and M2 are the input transistors of
the LNA, and M4, M5, R, and C compose a squaring circuit to
generate a low-frequency IM2 current at , which is then
injected through M3 into the common source node of the
LNA. This technique utilizes second-order interaction to gen-
erate tones at and to cancel the IM3 tones
arising from intrinsic third-order distortion. The design equa-
tion is

(24) Fig. 18. Post-distortion. (a) Conceptual view. (b) Circuit implementation in
[30]. (c) Circuit implementation in [31]. (d) Circuit implementation in [32].

G. Noise/Distortion Cancellation
where is the i transconductance coefficient of . The
injected IM2 tone should be in phase with the envelope of the Noise/distortion cancellation parallels CG and CS
RF input signal. Frequency component is chosen over stages, as shown in Fig. 17 [26]–[29]. The circuit is
other IM2 components because it is easier to driven by a voltage at node “IN.” The nonlinearity of can
match the phase at low frequency. Since the linear gain is added be modeled as a current source between its drain and source
in phase, and the noise injected from the IM2 generator appears controlled by both and . Hence, both the channel
as common mode noise (suppressed by differential operation), thermal noise and distortion of flowing through the CG
IM2 injection circumvents gain and NF penalties. and CS paths are subtracted at the output, whereas the signal
Limitations of IM2 injection include the following. is added. Noise/distortion cancellation requires that ,
1) NMOS/PMOS transistors and resistors have independent i.e.,
PVT variations—hence more difficult to satisfy the IM3
cancellation criteria in (24) robustly.
2) Since R and C in the IM2 generator introduce extra phase (25a)
shift, two tone spacing must be smaller than the RC-filter (25b)
cutoff frequency for negligible phase mismatch. Cancella-
tion performance degrades as tone spacing increases. Note this technique can cancel all intrinsic distortion generated
3) Frequency components at and injected by by , including both and nonlinearity, while previous
the IM2 generator may fall into signal band and degrade techniques could only compensate nonlinearity.
the IIP2. After canceling the distortion from , ’s distor-
4) Noise from the IM2 generator is negligible only for differ- tion dominates the residual nonlinearity, which comprises
ential LNAs, but would result in appreciable NF degrada- two terms: 1) ’s intrinsic third-order distortion and 2)
tion for single-ended LNAs. second-order interaction originating from the CG-CS cascade.
In short, IM2 injection applies chiefly to narrowband, differ- Optimal biasing of [27], [29] or employing complementary
ential systems with small two-tone spacing. DS [28] could further improve the linearity.
ZHANG AND SÁNCHEZ-SINENCIO: LINEARIZATION TECHNIQUES FOR CMOS LOW NOISE AMPLIFIERS: A TUTORIAL 31

TABLE III
PERFORMANCE COMPARISON OF SILICON-VERIFIED LINEARIZATION TECHNIQUES FOR CMOS LNAS.

H. Post-Distortion matched very well in layout. In Fig. 18(c), NMOS/PMOS tran-

sistors must have commensurate nonlinearity, but are hard to
Similar to the DS method, the post-distortion (PD) technique
match across PVT.
also utilizes an auxiliary transistor’s nonlinearity to cancel that
of the main device, but it is more advanced in two aspects. I. Summary
1) The auxiliary transistor is connected to the output of main
Table III compares the IIP2/IIP3 improvement and gain/NF/
device instead of directly to the input, minimizing the im-
power penalties of the previously discussed, state-of-the-art lin-
pact on input matching.
earization techniques. We chose only one representative refer-
2) All transistors operate in saturation, resulting in more ro-
ence for each technique for brevity. The best performance per
bust distortion cancellation.
row has been marked with gray color. The modified DS method
Fig. 18 displays a conceptual diagram of PD as well as three
achieves the best IIP ; the IM2 injection method
implementations [30]–[32]. The auxiliary transistor taps
yields minimum degradation in NF, gain, and power; and the PD
voltage and replicates the nonlinear drain current of the main
method renders robust linearity improvement.
transistor , partially canceling both second- and third-order
Note that transconductance linearization methods are inher-
distortion terms. The nonlinear drain currents of and
ently broadband, however, to apply it on wideband LNAs, we
can be modeled as
should match the delays and phases from the main and auxiliary
(26) paths, including input matching/loading network, at the desired
frequency band, so that the distortion cancellation is carried out
with sufficient accuracy. Most reported techniques (e.g., IM2
(27) injection, modified DS, and harmonic termination) dealing with
second-order interaction are only limited to narrowband appli-
Next, suppose is related to by cations.
IIP2 calibration is another linearization technique that has
(28) been extensively reported for mixers, but still remains an open
problem for LNAs. The concept of IIP2 calibration is to sense
where are generally frequency dependent and can be and correct the dc offset with an analog or digital feedback loop
extracted from simulation. In Fig. 18(a), the cascode devices [33]–[36]. Some correction approaches for mixers include ad-
were assumed to be ideal current buffers [30]. The two nonlinear justing the LO bias [33], the load resistor/capacitor banks [34],
currents and sum at node , yielding : the current source load [35], or injecting current at the mixer
output [36]. It might be possible to apply some of the methods
currently employed in mixers to differential LNAs.
III. NEW ISSUES FOR WIDEBAND APPLICATIONS
Growing research on reconfigurable multiband/multistandard
(29) and broadband transceivers has increased interest in broadband
LNA design. In these transceivers, hundreds of channels could
enter the LNA without any prefiltering, acting as in-band inter-
Note that in the PD method, both the main and auxiliary transis- ferers. Moreover, nearby radios and on-chip transmitter leakage
tors operate in saturation with the same polarity. Hence, cause increased adjacent blockers, creating severe cross mod-
partially cancels the linear term as well; however, it does ulation, intermodulation, and desensitization. Therefore, a big
not substantially degrade the gain/NF because is designed design challenge for broadband LNAs is to achieve high lin-
to be more nonlinear than (i.e., ). earity over a wide frequency range, lest the SNDR at the LNA
Finally, note that among the three implementations, Fig. 18(b) output be dominated by distortion instead of noise. Furthermore,
and 18(d) probably have better performance in practical imple- the old textbook argument that the LNA receives a small input
mentations, since both and are NMOS, which can be signal amplitude is not valid for wideband LNAs. We consider
32 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 1, JANUARY 2011

three main concerns: IIP2, , and IIP2/IIP3 vs. two-tone

frequency and spacing.
A. IIP2
Most linearization methods target narrowband applica-
tions and only cancel the third-order distortion, since the
second-order nonlinearity is generally out of band in narrow-
band system. However, for wideband receivers, many channels
are present concurrently and act as in-band interferences. Thus,
the second-order intermodulation products generated by certain
combination of interferences are highly likely to fall into the
signal band. Hence, broadband LNAs should have a good
IIP2 as well as IIP3. Often, in applications like digital TV, the
required IIP2/3 must be derived from a multitone test such as
complex second-order distortion (CSO) and composite triple
beat distortion (CTB) [21].
A fully differential LNA will improve IIP2, but requires
a transformer, which is expensive for wideband systems. Fig. 19. Experimental and theoretical results of LNA IIP3 as a function of fre-
Other IIP2 improvement techniques include the complemen- quency spacing [32] (© 2009 IEEE).
tary/differential DS method [21], [22], [28] and post-distortion 3) Add source degeneration at the cost of extra noise.
[30]–[32]. Moreover, in DSM processes, biasing a CS-stage at 4) Dynamic bias/dynamic supply [42].
the maximum gain yields a high IIP2 [29]. 5) Reduce the output voltage swing to relax the limitation
B. 1 dB Compression Point from nonlinear output conductance. One option is to use a
The “large-signal” 1 dB compression point has tra- low-impedance load for the LNA, for example by choosing
ditionally not been a major concern for LNA designers because a passive mixer over an active mixer as the following stage.
the LNA typically has a small input signal. However, in wide- However, this choice requires a larger stage and hence
band receivers, LNAs receive the accumulated power from mul- greater difficulty to linearize the transconductance.
tiple channels, which could range from to 0 dBm. For ex-
ample, in the A/74 standard developed by the Advanced Televi- C. IIP2/IIP3 Vs. Two Tone Frequency and Spacing
sion Systems Committee (ATSC), many transmitters are in close Broadband LNAs have flat gain/NF over the whole band-
spectral proximity, so the receiver is exposed to more multicar- width. Likewise, IIP2/IIP3 should also be relatively flat over the
rier adjacent energy. The maximum input power (the average of signal band. Therefore, while narrowband systems typically use
multiple tones) could even exceed 0 dBm [41]. Furthermore, se- a specific interference frequency and a small tone spacing for the
vere transmitter leakage, poor isolation between antennas, and two-tone test, broadband systems require IIP2/IIP3 to be exam-
single-tone blockers with large peak-to-average ratio all require ined at various two-tone-spacing and center frequencies [32].
a high signal-handling capability, i.e., high , for the LNA Fig. 19 shows an example plot.
to prevent desensitization, gain compression, and clipping. Reactive components, such as those in the matching network,
IIP2/IIP3-improvement techniques typically only work over cause the frequency-dependence of IIP2/IIP3. Note that typi-
small signal ranges, and do not improve because it is a cally, this frequency-dependence is mild for operating frequen-
large-signal parameter. At higher input amplitudes clipping oc- cies below 1 GHz, so it is more of a concern for UWB systems
curs, and the worsens due to limited supply voltage/dc- (3.1–10.6 GHz) than for digital TV (54–880 MHz), for example.
bias current. IIP2 depends on two-tone-spacing. For two input-signal tones
-improvement techniques include at , the upper-frequency IM2 component is at ,
1) Increasing above nominal values to maximize the while the lower-frequency component is at . The IIP2
voltage headroom and performing substantial PVT simu- dependence on two-tone spacing is subtle when is very
lation to guarantee breakdown/overstress will not occur. small. There are two situations in which this dependence be-
2) Using low , thick-oxide transistors to handle larger comes more significant.
voltage swings to allow even larger . Using such 1) Large two-tone spacing, where larger frequency spacing
transistors degrades NF and high-frequency performance yields correspondingly larger reactive effects.
and raises cost. 2) Narrowband IM2 cancellation scheme. For example, in the
Achieving high with thin-oxide devices and low supply complementary DS method with CG configuration shown
voltages remains an open problem. Some possible approaches in Fig. 11(b), the impedance from coupling capacitors in-
include creases with smaller two-tone spacing. Thus the ac-short
1) Cancel higher-order distortion, e.g., IM5 & IM7, since condition worsens and degrades the IM2-cancellation ef-
these become prominent at larger inputs and contribute to fectiveness [21], [28].
. The IIP3 dependence on two-tone spacing is mainly attributed
2) Extend the effective input range of IM2/IM3 cancellation. to the “second-order interaction“ as shown in (8). Therefore,
One solution is to employ more auxiliary transistors in par- the variations of cause the optimum point of the second-
allel in the DS method [11], [20]. Note that weak-inversion order interaction cancellation to change, resulting in worse lin-
transistors being turned on and off at large voltage swing earity. For example, in the IM2-injection method [25] (Fig. 16),
will add more high-order harmonic components to the cir- the squaring circuit experiences more phase shift at larger two-
cuit. A more robust solution is to combine triode and weak tone spacing, which degrades IIP3. In the harmonic-termination
inversion transistors as auxiliary transistors [20]. method [7], IIP3 degrades noticeably at larger .
ZHANG AND SÁNCHEZ-SINENCIO: LINEARIZATION TECHNIQUES FOR CMOS LOW NOISE AMPLIFIERS: A TUTORIAL 33

IV. LNA LINEARIZATION IN DSM TECHNOLOGY

A. Nonlinearity From Output Conductance

Distortion of MOS transistors is mainly caused by the non-
linear transconductance and output conductance .
Previously published linearization techniques mainly focus on
linearizing , assuming that (1) drain current is controlled
only by the gate-source voltage , and (2) nonlinearity
is negligible. These assumptions are valid for small load resis-
Fig. 20. Vector diagram showing the 180 out-of-phase contribution of ! 0! tance, small voltage gain, small input signal, and a drain-source
term on the upper and lower IM3 components [38]. voltage sufficiently large that the small-signal variation
of does not appreciably perturb the bias point.
However, as technology scales down, the nonlinearity be-
comes more prominent. Current is controlled not only by
but also the , which can be approximated by the two-dimen-
sional Taylor series [29], [44]

(30)

where is the -order transconductance as defined in (6);

represents the nonlinear output conductance effect which is pro-
portional to the derivatives with respect to ; is the
cross modulation term describing the dependence of on
or on , as formulated in (31)

(31)

To characterize the nonlinearity for a single transistor, we fix

its , and sweep the , by taking the first three derivatives of
the drain-source dc current with respect to [as defined in
W L = 20 0 08 m V = 0 5 V V = 0 26 V
Fig. 21. NMOS output conductance nonlinearity characteristics (UMC 90 nm
CMOS process, = =:  , : , : ). (31)] at every dc bias point, we can obtain Fig. 21. It is observed
that the drain current is modulated a lot by . is large
Another major contributor to this dependence is the IM3 when the transistor operates at small ; while it decreases for
asymmetry, also called “sideband asymmetry.” IM3 asymmetry large values.
is attributed to various types of memory effects [37]–[40], but Here we assume a negligible nonlinearity contribution from
for CMOS LNAs specifically, it is because the reactive part of , otherwise three-dimensional Taylor series should be used
the circuit impedance (e.g., termination impedance) at instead.
has a 180 -out-of-phase contribution to the IM3 components at From (30), the distortion is contributed by four parts.
and . This concept is qualitatively illus- 1) nonlinearity due to nonlinear relation.
trated by the vector diagram in Fig. 20 [38], where the 2) nonlinearity from channel length modulation effect.
refers to the first-, second-, and third-order Volterra-Series co- Note that contributes less nonlinearity when device op-
efficients. The IM3 components at and erates deeper into saturation region.
have different imaginary parts (i.e., reactance), resulting in IM3 3) the dependence of on , (partially due to the drain
asymmetry. induced barrier lowering (DIBL) effect [29].
Note that this IM3 asymmetry depends on bias and frequency. 4) the dependence of on , especially in saturation re-
For very small two-tone spacing, it is hard to see any IM3 asym- gion [44].
metry since the reactive-impedance effect at is negligible; The cross modulation effect remains fairly constant for a
but for larger , the reactive impedances at the second-har- broad range of , while is more linear and becomes
monic frequency also contribute differently to the lower/upper more nonlinear as increases, decreases, and transistors
IM3 components, which worsens the IM3 asymmetry [7] and operate close to the linear region. In [29] the . cross
also indicates a more obvious IIP3 dependence on two-tone- term cancels the intrinsic second-order distortion to
spacing. However, proper bias can reduce this IM3 asymmetry obtain an amplifying stage with high IIP2. Note that when
[40]. Note that in the multitone case, Adjacent channel power nonlinearity dominates (i.e., output limited), the tradeoff
ratio (ACPR) asymmetry is defined correspondingly. between gain and linearity becomes more severe.
34 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 1, JANUARY 2011

TABLE IV the reduced values result in the device being bi-

DOMINANT CONTRIBUTOR TO DISTORTION UNDER VARIOUS CONDITIONS ased closer to the triode-saturation boundary, which worsens the
nonlinearity. Consequently, the maximum OIP3 occurs with
smaller load impedance (which mitigates the distortion contri-
bution from nonlinear ) and the peak IIP3 shifts to lower
[47], since a smaller overdrive voltage allows the device
to stay far away from the triode-saturation boundary while still
keeping nonlinearity small.
The “sweet spot” in the optimal biasing technique(discussed
B. MOSFET Capacitance in Section II-C) will systematically shift to higher bias-current
density (i.e., larger overdrive voltage) as technology
For the most part, the capacitances of a saturation-region scales down [44], which means larger power is required to
transistor are linear at an operating frequency less than preserve linearity.
[44]. Therefore they do not directly contribute to distortion As oxide thickness decreases, poly-gate depletion increases,
[43]. However, if a strong blocker is present (e.g., in the and the nonlinear gate capacitance develops strong second-order
order of 0dBm), varies significantly around the threshold derivatives with respect to , which contribute to sig-
voltage, and its nonlinearity becomes significant. Also, as nificant third-order distortion in drain current, as shown in
previously mentioned, provides a feedback path for the (36) and (37) [46]
“second-order interaction,” and this effect becomes more
visible as the load impedance increases. At high frequency, (36)
and reduce total output impedance and hence the output
voltage swing, helping to mitigate the nonlinear effect.
Therefore, nonlinearity dominates at high frequency, while (37)
nonlinearity dominates at low frequency [43]. However,
in those circuits where capacitive components are tuned out where Q is the channel charge density along the current direc-
for a matched load, nonlinearity is still prominent at high tion, v is the carriers’ velocity, and is the saturated velocity
frequencies. The substrate affects linearity through with for sufficiently high field. Thus, distortion increases with thinner
higher operating frequency, and this effect varies with different oxides.
substrate-doping profiles [43]. Generally, IIP3 improves as DIBL becomes more severe in DSM process, besides a
substrate doping increases [47]. The effect from substrate -dependent , DIBL also affects the linearity by changing
leakage current can typically be neglected [45]. the effective [48]. Measured results in [48] shows that
Table IV provides a summary: the mark “ “ denotes whether the distortion is more sensitive to DIBL effect when the drain
or dominates the distortion under the given conditions. voltage increases and the MOSFET operates in moderate region
(i.e., is slightly higher than ).
C. Impact of Technology Scaling On Linearity Finally, each process has a “low frequency limit” (LFL),
As channel length decreases, the velocity saturation effect be- below which the MOSFET exhibits fairly frequency-indepen-
comes prominent, i.e., the drain current saturates at smaller . dent linearity. LFL is closely related to the device speed and
Thus, the long-channel equation for drain current in saturation can be approximated as [48]. Therefore, it is easier to
region needs to be modified as [5] achieve IIP2/IIP3 flatness over the signal band in smaller-size
technology.
In summary, as technology scales down, lower supply volt-
ages reduce the headroom and can lead to greater nonlinearity
(32) from , necessitating multidimensional Taylor analysis to
model the nonlinear . Higher-order effects such as DIBL,
where is the field strength at which the carrier velocity velocity saturation, and poly-gate depletion all affect linearity.
drops to half the value extrapolated from low-field mobility. A key challenge resides in delivering high linearity with core
becomes more linear transistors and with a low supply voltage in the DSM processes.
(33) V. REMARKS FOR HIGH LINEARITY LNA DESIGN
Besides applying explicit linearization techniques to the cir-
The vertical-field mobility degradation effect also helps to cuit, some general guidelines are helpful for designing a high-
linearize in DSM process. The long-channel equation for linearity LNA.
drain current can be modified as
A. To Reduce -Induced Distortion
(34)
From (34), the low-frequency expressions for second- and
third-order intercept points and are [3], [5]:
where models vertical-field mobility degradation.
Equation (34) reduces to as in-
creases, resulting in a linear I-V curve, and becomes con- (38)
stant with respect to bias voltage:
(35)
On the other hand, is more nonlinear for shorter channel
(39)
length, as proven by the experimental data in [43]. Furthermore,
ZHANG AND SÁNCHEZ-SINENCIO: LINEARIZATION TECHNIQUES FOR CMOS LOW NOISE AMPLIFIERS: A TUTORIAL 35

where . Equations (38) and (39) indicate that ACKNOWLEDGMENT

increasing improves both IIP2 and IIP3. Therefore, given The authors wish to thank W. He, E. Pankratz, X. Chen, M.
sufficient voltage headroom, maximizing and minimizing Onabajo, M. Mobarak, Dr. C. Xin, Dr. S. Krishnamurthy, and
transistor sizes helps to minimize parasitics and to linearize the A. Amer for proofreading the manuscript. The authors also wish
circuit at the cost of increased dc current. to thank Dr. S. Lou, J. Wardlaw, and J. Kim for helpful discus-
B. To Reduce -Induced Distortion sions. The authors also want to acknowledge support from the
TI Wireless Group.
Increasing supply voltage mitigates the effect and also im-
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IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1164–1176, May 2008. Heng Zhang (S’07) was born in Guangzhou, China.
[29] S. C. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts, and B. She received the B.S. degree in electrical engineering
Nauta, “Wideband balun-LNA with simultaneous output balancing, from Peking University, Beijing, China, in 2004, and
noise-canceling and distortion-canceling,” IEEE J. Solid-State Cir- the Ph.D. degree in electrical engineering from Texas
cuits, vol. 43, no. 6, pp. 1341–1350, Jun. 2008. A&M University, College Station, in 2010.
Post-distortion In the summer and fall of 2006, she was an Analog
[30] N. Kim, V. Aparin, K. Barnett, and C. Persico, “A cellular-band CDMA IC Design Engineer (Co-op) with Texas Instrument,
0 25 m
:  CMOS LNA linearized using active post-distortion,” IEEE J. Dallas, TX, where she designed a low power ADC
Solid-State Circuits, vol. 41, no. 7, pp. 1530–1534, Jul. 2006. for hard disk applications. In summer 2007, she was
[31] T.-S. Kim and B.-S. Kim, “Post-linearization of cascode CMOS LNA with the RF and Analog Technologies Department,
using folded PMOS IMD sinker,” IEEE Microw. Wireless Comp. Lett., UMC, Sunnyvale, CA, where she researched digital
vol. 16, no. 4, pp. 182–184, Apr. 2006. calibration techniques for ADCs. Since August 2010, she has been with the
[32] H. Zhang, X. Fan, and E. Sánchez-Sinencio, “A low-power, linearized, Analog and Mixed Signal Group, Broadcom Corporation, Irvine, CA, working
ultra-wideband LNA design technique,” IEEE J. Solid-State Circuits, on high-speed transceivers for optical and backplane/cable applications. Her re-
vol. 44, no. 2, pp. 320–330, Feb. 2009. search interests include data converters and high-speed/RF circuits. Her Web
site can be found at http://www.ece.tamu.edu/~hzhang.
IIP2 calibration
[33] D. Kaczman, M. Shah, M. Alam, M. Rachedine, D. Cashen, L. Han,
and A. Raghavan, “A single-chip 10-Band WCDMA/HSDPA 4-Band Edgar Sánchez-Sinencio (S’72–M’74–SM’83–
GSM/EDGE SAW-less CMOS receiver with DigRF 3 G interface F’92–LF’10) was born in Mexico City, Mexico. He
and +90 dBm IIP2,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. received the degree in communications and elec-
tronic engineering (Professional degree) from the
718–739, Mar. 2009.
[34] M. Hotti, J. Ryynanen, K. Kivekas, and K. Halonen, “An IIP2 cali- National Polytechnic Institute of Mexico, Mexico
bration technique for direct conversion receivers,” in Proc. IEEE Int. City, the M.S.E.E. degree from Stanford University,
Circuits Syst. Symp., Vancouver, BC, Canada, May 2004, vol. 4, pp. Stanford, CA, and the Ph.D. degree from the Univer-
257–260. sity of Illinois at Champaign-Urbana, in 1966, 1970,
[35] W. Kim, S. Yang, Y. Moon, J. Yu, H. Shin, W. Choo, and B. Park, and 1973, respectively.
“IP2 calibrator using common mode feedback circuitry,” in Proc. Eur. He is currently the TI J. Kilby Chair Professor and
Solid-State Circuits Conf., 2005, pp. 231–234. Director of the Analog and Mixed-Signal Center at
[36] H. Darabi, H. Kim, J. Chiu, B. Ibrahim, and L. Serrano, “An IP2 Texas A&M University. His research work has more than 2636 citations ac-
improvement technique for zero-if down-converters,” in IEEE Int. cording to the Thomson Reuters Scientific Citation Index. He has graduated 42
Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2006, pp. M.Sc. and 34 Ph.D. students. He is a coauthor of six books on different topics,
464–465. such as RF circuits, low-voltage low-power analog circuits, and neural networks.
His present interests are in the area of power management, RF-communication
IIP2/IIP3 dependence on two-tone spacing circuits, analog and medical electronics circuit design.
[37] W. Bosch and G. Gatti, “Measurement and simulation of memory ef- Dr. Sánchez-Sinencio is a former Editor-in-Chief of IEEE TRANSACTIONS ON
fects in predistortion linearizers,” IEEE Trans. Microw. Theory Tech., CIRCUITS AND SYSTEMS II. In November 1995 he was awarded a Honoris Causa
vol. 37, no. 12, pp. 1885–1890, Dec. 1989. Doctorate by the National Institute for Astrophysics, Optics and Electronics,
[38] J. F. Sevic, K. L. Burguer, and M. B. Steer, “A novel envelope-ter- Mexico. This degree was the first honorary degree awarded for microelectronic
mination load-pull methods for ACPR optimization of RF/microwave circuit design contributions. He is a corecipient of the 1995 Guillemin-Cauer
power amplifiers,” in IEEE MTT-S Int. Microwave Symp. Dig., Balti- Award for his work on cellular networks. He was also the corecipient of the 1997
more, MD, 1998, pp. 601–605. Darlington Award for his work on high-frequency filters. He received the IEEE
[39] N. B. de Carvalho and J. C. Pedro, “Two-tone IMD asymmetry in mi- Circuits and Systems Society Golden Jubilee Medal in 1999. He also received
crowave power amplifiers,” in IEEE MTT-S Int. Microwave Symp. Dig., the prestigious IEEE Circuits and Systems Society 2008 Technical Achievement
Boston, MA, 2000, pp. 445–448. Award. His Web site can be found at http://amesp02.tamu.edu/~sanchez/.