International Journal of Power Electronics and Drive Systems (IJPEDS)

Vol. 13, No. 3, September 2022, pp. 1922~1950

ISSN: 2088-8694, DOI: 10.11591/ijpeds.v13.i3.pp1922-1950  1922

Load current balancing for 4-wire systems using harmonic

treated TCR based SVCs

Abdulkareem Mokif Obais1, Ali Abdulkareem Mukheef2

1
Department of Biomedical Engineering, College of Engineering, University of Babylon, Babylon, Iraq
2
English Department, Almustaqbal University College, Babylon, Iraq

Article Info ABSTRACT

Article history: In this paper, a harmonic-treated thyristor-controlled reactor TCR is
presented as a linearized harmonic-free compensating susceptance
Received Jun 25, 2022 controllable in inductive and capacitive modes. The harmonic-treated TCR is
Revised Jun 30, 2022 a traditional TCR conditioned in such a manner that it can respond
Accepted Jul 6, 2022 continuously and linearly to capacitive and inductive reactive current
demands without noticeable harmonic association or active power
contribution. The conditioned configuration is produced by equipping the
Keywords: TCR with self-harmonic suppressing and filtering circuitries, which
guarantee harmonic cancellation with minimal no load operating losses. The
Energy saving harmonic treated TCR avoids the need to high power harmonic filters
Harmonic cancellation required to treat the harmonics of the traditional TCR. The devised
Load compensation susceptances are used to build a load current balancing system for grounded
Power quality loads in a 380-V, 50Hz power distribution system. Both the compensating
Reactive power control susceptances and the load current balancing system were designed and tested
on PSpice. The simulation results have demonstrated the linearity, control
continuity, and harmonic cancellation of the proposed harmonic-treated TCR
as a fast response compensating susceptance reliable for load current
balancing purposes. The proposed load current balancing system revealed
superior treatment to various unbalance conditions, thus it is deservedly
promoted to have the feasibility of supporting grids having fast varying
loads.
This is an open access article under the CC BY-SA license.

Corresponding Author:
Abdulkareem Mokif Obais
Department of Biomedical Engineering, College of Engineering, University of Babylon
Al Najaf's Street, Al Hillah, Babylon, Iraq
Email: [email protected]

1. INTRODUCTION
Unbalanced loads and loads with poor power factor are two challenging issues facing the power
quality of power system networks. Reactive power (Var) is mainly controlled by static Var compensators.
Var control is usually employed to meet power quality requirements such as voltage regulation and power
factor correction. Many power quality issues such as harmonic minimization and load compensation can be
solved by using static Var compensators or static compensators [1]-[7]. The difference between a static Var
compensator (SVC) and static compensator is that a static Var compensator is a reactive device used to
control Var in both modes of operations (inductive and capacitive), while a static compensator is capable of
controlling both real power and reactive power. A static compensator may be constructed of several SVCs.
The increase in electricity demand nowadays makes focusing on power quality greater than ever. Today,
there is an urgent need to increase the efficiency of transmission systems by minimizing their losses through
load compensation and power factor correction [8], [9]. Static Var compensators and static compensators are

Journal homepage: http://ijpeds.iaescore.com

Int J Pow Elec & Dri Syst ISSN: 2088-8694  1923

efficient tools to accomplish load compensation and power factor correction for better power quality
purposes [10]. The thyristor-controlled reactor TCR is simply a reactor connected in series to two anti-
parallel thyristors and the series combination is supplied by a phase or line to line voltage of the AC power
system network. It is controlled continuously by the symmetrical firing angles of its thyristors. TCR usually
injects odd harmonic current components [1], thus it requires installation of harmonic filters at its location
[5]. Poor power factor and unbalanced loads cause extra losses in transmission systems and power generation
stations. In addition, they may restrict the transmission capability of transmission systems. Therefore, load
compensation and power factor correction are effective remedies to these challenging issues. The benefits of
load compensation and power factor correction are involved in energy saving, transmission loss reduction,
voltage stabilization, and the feasibility of operating transmission lines closer to their thermal limits [11]-[25].
Load compensation and power factor correction systems have great impacts in transmission loss
reduction and energy saving in power generation stations [11]-[25]. Load currents balancing process is
involved in two steps; load reactive currents compensation which means power factor correction and load
active power compensation which means load balancing [8]-[11]. Load compensation and power factor
correction were firstly approached by using static Var compensators in 1978 by [25]. At that time the TCR
was available as controllable inductive reactive device. It was used beside a fixed capacitor to devise a static
Var compensator controllable in inductive and capacitive modes of operation. Three identical fixed capacitor-
thyristor controlled reactor based switched virtual circuit SVCs were connected in delta-form and used to
compensate load unbalances for ungrounded loads. In this work load balancing mechanism was studied and
its compensating susceptances basic equations were derived in terms of load conductances and susceptances
using symmetrical components. The compensation system was designed for load balancing of three-wire
unbalanced loads. The compensation process comprised two steps; unity power correction and real power
balancing. Although the compensation system released a wide spectrum of odd current harmonics, it opened
wide spaces of interest in load compensation by using static Var compensators. Actually, static Var
compensators employing TCRs in their construction require high power harmonic filters which add
additional costs and energy losses [1]. Large fluctuating loads are intended to be balanced for two main
reasons: 1- the AC power system is too weak to support its terminal voltage within acceptable range of
variation and 2- it is not economical or practical to supply Var demand from the AC system [23]. Load
current balancing systems require pure compensating susceptances in order to compensate the load reactive
current components and balance its active current components. Load current balancing for 4-wire systems
can be achieved using power converter based Var devices like distribution static synchronous compensators
STATCOMs distribution static synchronous compensator (DSTATCOM) [2], [8], [25]. Other approaches
adopted shunt power converted based Var compensating devices for accomplishing voltage and current
compensation in addition to harmonic minimization [2], [4], [6], [7], [12], [13], [20]. Series compensation
systems can be used for treating voltage and current imbalance conditions beside the treatment of harmonic
issues [15]. Separate compensating susceptances connected in delta and star forms are capable of
accomplishing more flexible compensation for voltage and current imbalance conditions compared to
systems using lumped compensation systems like DSTATCOMs [1], [3], [5], [8]-[11], [14]-[19], [21], [22].
Newton-Raphson method was used in [26] to model the TCR in frequency domain for
accomplishing fast convergence to steady state with high accuracy. A cascaded single-phase converter having
seven voltage levels was built by [27] using a hybrid of two-level cells This scheme requires reduced number
of switching devices compared traditional ones. It is designed to integrate two-stage cells for shaping the
intended voltage profile. Similar topology was approached by [28] to reduce the harmonic effect on the
converter voltage profile. A shunt active power filter was proposed by [29] for treating the problem
harmonics current in the AC source as a result of nonlinear loads. This filter was designed to improve the
power quality of the AC grid via compensating harmonic currents and reactive power. A single-phase voltage
source converter equipped with a shunt active filter was proposed by [30] to accomplish optimal
minimization of current disturbance and harmonic reduction. A DSTATCOM equipped with Icos𝜙
controlling modality was proposed by [30] to enhance voltage regulation, power factor improvement, load
balancing, and harmonic suppression of non-linear loads, whereas a system in [31].
In this work, a new configuration of compensating susceptances characterized by control continuity,
broad range of linearity, negligible no load operating losses, very low operating losses, considerable fast
response to current demand, and negligible harmonic injection. The proposed susceptances are built of
harmonic-treated TCRs and employed in the construction of two static compensators for balancing phase
currents in 4-wire systems. Applying the new proposed compensating devices in the construction of the
proposed load balancing system, results in wide range of compensation capability, high speed response in fast
varying environments, perfect balancing of AC source line currents, and stiff synchronization with utility grid.

Load current balancing for 4-wire systems using harmonic treated … (Abdulkareem Mokif Obais)
1924  ISSN: 2088-8694

2. LOAD CURRENT BALANCING FOR THREE-PHASE, 4-WIRE LOADS

For an unbalanced grounded wye-connected load, a current flow through the neutral wire.
Therefore, load current balancing for three-phase, 4-wire loads requires two static compensators in order to
achieve active phase currents balancing and reactive currents compensation [9], [14]. The first static
compensator is connected in delta-form using three identical compensating susceptances controlled
continuously in capacitive and inductive modes of operation. The second static compensator is similar to first
one except its compensating susceptances are connected in star-form. Figure 1 shows the layout of the
balancing mechanism of a three-phase, 4-wire load (grounded load) fed by a balanced three phase voltages
VA, VB, and VC. The mechanism of this technique is involved in two steps. In the first step, the active current
components of the load phase currents are balanced by the active current components of the line currents
produced by the delta-connected static compensator. In the second step, the reactive current components
produced by the delta-connected static compensator and the reactive current components of the load phase
currents are compensated by the reactive phase currents produced by the star-connected static compensator.
BS1AB, BS1BC, and BS1CA are the compensating susceptances of the first compensator (delta-connected static
compensator), while BS2A, BS2B, and BS2C are compensating susceptances of the second static compensator
(star-connected static compensator). IS1A, IS1B, and IS1C are the first static compensator line currents, while IS2A,
IS2B, and IS2C are the phase currents of the second static compensator. ILA, ILB, and ILC are load phase or line
currents.

Figure 1. Layout of load current balancing system for grounded loads

The AC phase voltages VA, VB, and VC of the three-phase power system network are assumed to be
balanced, thus they can be given by:

𝑉𝐴 = 𝑉 (1)

2𝜋
𝑉𝐵 = 𝑉∠ (− ) (2)
3

4𝜋
𝑉𝐶 = 𝑉∠ (− ) (3)
3

Where, V is the rms magnitude of each phase voltage and ∠ represents the phase angle symbol. The phase
currents of the unbalanced three-phase 4-wire load can be given by

𝐼𝐿𝐴 = |𝐼𝐿𝐴 |∠𝜙𝐿𝐴 = |𝐼𝐿𝐴 | 𝑐𝑜𝑠 𝜙𝐿𝐴 + 𝑗|𝐼𝐿𝐴 | 𝑠𝑖𝑛 𝜙𝐿𝐴 (4)

Int J Pow Elec & Dri Syst, Vol. 13, No. 3, September 2022: 1922-1950
Int J Pow Elec & Dri Syst ISSN: 2088-8694  1925

2𝜋 2𝜋
𝐼𝐿𝐵 = |𝐼𝐿𝐵 |∠ (− + 𝜙𝐿𝐵 ) = (|𝐼𝐿𝐵 | 𝑐𝑜𝑠 𝜙𝐿𝐵 + 𝑗|𝐼𝐿𝐵 | 𝑠𝑖𝑛 𝜙𝐿𝐵 )∠ (− ) (5)
3 3

4𝜋 4𝜋
𝐼𝐿𝐶 = |𝐼𝐿𝐶 |∠ (− + 𝜙𝐿𝐵 ) = (|𝐼𝐿𝐶 | 𝑐𝑜𝑠 𝜙𝐿𝐶 + 𝑗|𝐼𝐿𝐵 | 𝑠𝑖𝑛 𝜙𝐿𝐶 )∠ (− ) (6)
3 3

Where, φLA, φLB, and φLC are the power factor angles of phases A, B, and C respectively. |ILA|, |ILB|, and |ILC|,
are the absolute rms values of ILA, ILB, and ILC respectively. IA, IB, and IC are the rms line currents of the AC
source. According to the main objective of this research, the AC source currents should be balanced and
active. Consequently, they can be expressed as:

𝐼𝐴 = 𝐼 (7)

2𝜋
𝐼𝐵 = 𝐼∠ (− ) (8)
3

4𝜋
𝐼𝐶 = 𝐼∠ (− ) (9)
3

Where, I is the rms magnitude of each phase current. The active power PL supplied to the unbalanced load
and the active power P that should be supplied by the AC source after balancing can be given by:

𝑃𝐿 = 𝑉(|𝐼𝐿𝐴 | 𝑐𝑜𝑠 𝜙𝐿𝐴 + |𝐼𝐿𝐵 | 𝑐𝑜𝑠 𝜙𝐿𝐵 + |𝐼𝐿𝐶 | 𝑐𝑜𝑠 𝜙𝐿𝐶 ) (10)

𝑃 = 3𝑉𝐼 (11)

The active power supplied by the AC source should be equal to the power consumed by the unbalanced load
or in other words:

𝑃 = 3𝑉𝐼 = 𝑃𝐿 = 𝑉(|𝐼𝐿𝐴 | 𝑐𝑜𝑠 𝜙𝐿𝐴 + |𝐼𝐿𝐵 | 𝑐𝑜𝑠 𝜙𝐿𝐵 + |𝐼𝐿𝐶 | 𝑐𝑜𝑠 𝜙𝐿𝐶 ) (12)

In (12) for I, gives

|𝐼𝐿𝐴 | 𝑐𝑜𝑠 𝜙𝐿𝐴 +|𝐼𝐿𝐵 | 𝑐𝑜𝑠 𝜙𝐿𝐵 +|𝐼𝐿𝐶 | 𝑐𝑜𝑠 𝜙𝐿𝐶

𝐼= (13)
3

The compensating currents IS1A, IS1B, and IS1C of the delta-connected static compensator can be expressed in
terms of its compensating susceptances and phase voltages as:

𝜋 𝜋
𝐼𝑆1𝐴 = √3𝑉 𝑐𝑜𝑠 ( ) (𝐵𝑆1𝐶𝐴 − 𝐵𝑆1𝐴𝐵 ) + 𝑗√3𝑉 𝑠𝑖𝑛 ( ) (𝐵𝑆1𝐴𝐵 + 𝐵𝑆1𝐶𝐴 ) (14)
3 3

𝜋 𝜋 −2𝜋
𝐼𝑆1𝐵 = (√3𝑉 𝑐𝑜𝑠 ( ) (𝐵𝑆1𝐴𝐵 − 𝐵𝑆1𝐵𝐶 ) + 𝑗√3𝑉 𝑠𝑖𝑛 ( ) (𝐵𝑆1𝐵𝐶 + 𝐵𝑆1𝐴𝐵 )) ∠ ( ) (15)
3 3 3

𝜋 𝜋 4𝜋
𝐼𝑆1𝐶 = (√3𝑉 𝑐𝑜𝑠 ( ) (𝐵𝑆1𝐵𝐶 − 𝐵𝑆1𝐶𝐴 ) + 𝑗√3𝑉 𝑠𝑖𝑛 ( ) (𝐵𝑆1𝐶𝐴 + 𝐵𝑆1𝐵𝐶 )) ∠ (− ) (16)
3 3 3

According to [9], [14], the compensating susceptances BS1AB, BS1BC, and BS1CA can be expressed in terms of
load active current components as:
2
𝐵𝑆1𝐴𝐵 = (|𝐼𝐿𝐴 | 𝑐𝑜𝑠 𝜙𝐿𝐴 − |𝐼𝐿𝐵 | 𝑐𝑜𝑠 𝜙𝐿𝐵 ) (17)
3√3𝑉

2
𝐵𝑆1𝐵𝐶 = (|𝐼𝐿𝐵 | 𝑐𝑜𝑠 𝜙𝐿𝐵 − |𝐼𝐿𝐶 | 𝑐𝑜𝑠 𝜙𝐿𝐶 ) (18)
3√3𝑉

2
𝐵𝑆1𝐶𝐴 = (|𝐼𝐿𝐶 | 𝑐𝑜𝑠 𝜙𝐿𝐶 − |𝐼𝐿𝐴 | 𝑐𝑜𝑠 𝜙𝐿𝐴 ) (19)
3√3𝑉

Both the delta-connected static compensator (the first static compensator) and the Y-connected compensator
(the second static compensator) are built of pure susceptances and don’t consume any active power at all. The
susceptance currents IS2A, IS2B, and IS2C of the second compensator are pure reactive and should compensate
for the reactive currents generated by the first compensator and the load reactive currents. Doing this for each
phase of the second compensator and substituting for BS1AB, BS1BC, and BS1CA by its values expressed in (17)-
Load current balancing for 4-wire systems using harmonic treated … (Abdulkareem Mokif Obais)
1926  ISSN: 2088-8694

(19) give positive values of compensating susceptances denote capacitive susceptances, while negative
values mean inductive susceptances.

|𝐼𝐿𝐵 | 𝑐𝑜𝑠 𝜙𝐿𝐵 −|𝐼𝐿𝐶 | 𝑐𝑜𝑠 𝜙𝐿𝐶 −√3|𝐼𝐿𝐴 | 𝑠𝑖𝑛 𝜙𝐿𝐴

𝐵𝑆2𝐴 = (20)
√3𝑉

|𝐼𝐿𝐶 | 𝑐𝑜𝑠 𝜙𝐿𝐶 −|𝐼𝐿𝐴 | 𝑐𝑜𝑠 𝜙𝐿𝐴 −√3|𝐼𝐿𝐵 | 𝑠𝑖𝑛 𝜙𝐿𝐵

𝐵𝑆2𝐵 = (21)
√3𝑉

|𝐼𝐿𝐴 | 𝑐𝑜𝑠 𝜙𝐿𝐴 −|𝐼𝐿𝐵 | 𝑐𝑜𝑠 𝜙𝐿𝐵 −√3|𝐼𝐿𝐶 | 𝑠𝑖𝑛 𝜙𝐿𝐶

𝐵𝑆2𝐶 = (22)
√3𝑉

2.1. The harmonic-treated TCR based SVC

The harmonic-treated TCR is built of a harmonic-suppressing circuit connected in series with a
traditional TCR shunted by a filtering circuit as shown in Figure 2. The filtering circuit is responsible for the
cancellation of the harmonics released by the TCR and generating the capacitive reactive power demanded
from the SVC. The harmonic-treated TCR is a reliable replacement of the traditional fixed-capacitor thyristor
controlled-reactor shunted by high power harmonic filters. In addition, the harmonic-treated TCR current
fundamental is linearized with reactive current demand.

Figure 2. Layout of the harmonic-treated TCR based SVC

The harmonic-suppressing circuit is built of the series RLC circuit represented by CS, LS, and RS. It
is designed to resonate at the AC source fundamental angular frequency ω. RS represents the self-resistance
of the reactor LS. The filtering circuit is built of the series RLC filters R1L1CI, R2L2C2, and R3L3C3 which are
designed to eliminate, respectively the third, fifth, and seventh odd current harmonics released by the TCR.
R1, R2, and R3 are the self-resistances of L1, L2, and L3, respectively. The currents iS, iT, and iF are representing
the instantaneous currents of the SVC, TCR, and the filtering circuit, respectively. The traditional TCR and
its current waveform are shown in Figure 3. In this figure, the TCR is represented by the reactor LT and the
two anti-parallel thyristors X1 and X2. The AC instantaneous voltage applied across the TCR is vT, while α
represents its firing angle which is measured from positive peak point of vT toward its next negative slope
zero-crossing point. This angle varies in the range of 0≤ α≤π/2. The fundamental component of iT can be
given by [1], [5], [26].
𝑉𝑚 𝑉𝑚
𝐼1 = (𝜋 − 2𝛼 − 𝑠𝑖𝑛 2 𝛼) = 𝐹(𝛼) (23)
𝜋𝜔𝐿𝑇 𝜔𝐿𝑇

Where F(α) is defined by:

Int J Pow Elec & Dri Syst, Vol. 13, No. 3, September 2022: 1922-1950
Int J Pow Elec & Dri Syst ISSN: 2088-8694  1927

2𝛼 𝑠𝑖𝑛 2𝛼
𝐹(𝛼) = (1 − − ) (24)
𝜋 𝜋

Figure 3. The traditional TCR and its actual current waveforms

The instantaneous value of fundamental component of iT is i1, which can be expressed as in (25):
𝑉𝑚
𝑖1 = −𝐼1 𝑐𝑜𝑠(𝜔𝑡) = − 𝐹(𝛼) 𝑐𝑜𝑠(𝜔𝑡) (25)
𝜔𝐿𝑇

Since iT is symmetrical around the ωt axis, it only contains odd harmonic current components. The absolute
value of its nth current harmonic is given by [1], [5].

4𝑉𝑚 𝑠𝑖𝑛 𝛼 𝑐𝑜𝑠(𝑛𝛼)−𝑛 𝑐𝑜𝑠 𝛼 𝑠𝑖𝑛(𝑛𝛼)

𝐼𝑛 = ( ) (26)
𝜋𝜔𝐿𝑇 𝑛(𝑛2 −1)

Where, n is a non-unity positive odd integer. Since the harmonic-suppressing circuit is designed such that it
resonates at the AC fundamental frequency ω, it can be written.
1
𝑋𝑆 = 𝜔𝐿𝑆 = (27)
𝜔𝐶𝑆

Where, XS is the characteristic impedance of the harmonic-suppressing circuit. Since the harmonic filters
R1L1CI, R2L2C2, and R3L3C3 resonate at 3ω, 5ω, and 7ω, respectively, the following can be deduced.
1
𝑋3 = 3𝜔𝐿1 = (28)
3𝜔𝐶1

1
𝑋5 = 5𝜔𝐿2 = (29)
5𝜔𝐶2

1
𝑋7 = 7𝜔𝐿3 = (30)
7𝜔𝐶3

Where, X3, X5, and X7 are the characteristic impedances of the harmonic filters R1L1CI, R2L2C2, and R3L3C3,
respectively. At frequencies of order higher than that of the 7 th harmonic, the self-resistances of the reactors
building the filtering and the harmonic-suppressing circuits become negligible compared to their
corresponding reactances. Consequently, the nth harmonic impedances of the filtering circuit ZF(nω) and
harmonic-suppressing circuit ZS(nω) can be expressed as:
𝑗
𝑍𝐹 (𝑛𝜔) = 1 1 1 ,n >7 (31)
1 + 1 + 1
𝑛𝜔𝐿1 −𝑛𝜔𝐶 𝑛𝜔𝐿2 −𝑛𝜔𝐶 𝑛𝜔𝐿3 −𝑛𝜔𝐶
1 2 3

1 𝑛2 −1
𝑍𝑆 (𝑛𝜔) = 𝑗𝑛𝜔𝐿𝑆 + = 𝑗𝑋𝑆 ,n > 7 (32)
𝑗𝑛𝜔𝐶𝑆 𝑛

Load current balancing for 4-wire systems using harmonic treated … (Abdulkareem Mokif Obais)
1928  ISSN: 2088-8694

The nth harmonic impedance of the harmonic-suppressing circuit is required to be very much greater than
that of the filtering circuit at frequencies above the 7 th harmonic in order to protect AC grid from the injection
of higher current harmonics. This implies that as in (33):

|𝑍𝑆 (𝑛𝜔)| ≥ 10|𝑍𝐹 (𝑛𝜔)| (33)

If the filtering circuit is designed such that its harmonic filters have the same characteristic impedances at
their corresponding resonance frequencies, then ZF(nω) can be simplified to:

𝑗 𝑗𝑍0
𝑍𝐹 (𝑛𝜔) = 1 1 1 = 3𝑛 5𝑛 7𝑛 ,n>7 (34)
𝑛𝑍0 3𝑍0 +𝑛𝑍0 5𝑍0 +𝑛𝑍0 7𝑍0 + +
𝑛2 −9 𝑛2 −25 𝑛2 −49
3 − 𝑛 5 − 𝑛 7 − 𝑛

Where Z0 is defined by:

𝑍0 = 𝑋3 = 𝑋5 = 𝑋7 (35)

Substituting (32) and (34) into (33) gives:

10𝑍0
𝑋𝑆 ≥ 3 5 7 ,n >7 (36)
(𝑛2 −1)( 2 + 2 + )
𝑛 −9 𝑛 −25 𝑛2 −49

Changing the (≥) operation to (=) in (36) and taking n=9 yield:
84
𝑋𝑆 = 𝑍0 (37)
235

The harmonic filters in the SVC depicted in Figure 2 are responsible for supplying the capacitive reactive
current demand. The maximum value of this current is supplied when the TCR firing angle is π/2. At zero
reactive current demand, the TCR must be fired at an angle such that it compensates for the capacitive
current generated by the filtering circuit. On the other hand, this SVC must be capable of satisfying its
inductive reactive current demand. The reactive current ratings (capacitive and inductive) of the SVC
employed in the star-connected compensator are mainly dependent on the reactive current rating of the SVC
employed in the delta-connected compensator and the average power factor of the three-phase load intended
to be balanced. Since the SVC employed in delta-connected compensator represents a bipolar compensating
susceptance, it should have similar inductive and capacitive current ratings, i.e. the TCR reactive current
rating should be twice that of the filtering circuit. Generally, taking the TCR and filtering circuit reactive
current ratings into accounts, implies that:

|𝑍𝐹 (𝜔)| = 𝑘𝑅 𝜔𝐿 𝑇 (38)

Where, kR is the rating factor which indicates how much the TCR reactive rating is greater than that of the
filtering circuit. At the supply fundamental angular frequency ω, the filtering circuit becomes to some extent
pure capacitive. In other words, the harmonic filters self-resistances become negligible compared to their
corresponding net capacitive reactances. Taking n=1 in (34) and substituting for ZF(ω) in (38) give:
35
𝑍0 = 𝑘𝑅 𝜔𝐿 𝑇 (39)
48

Subtitling (37) into (39) and equating for L1, L2, and L3 in (28)-(30), respectively, give:
35
𝐿1 = 𝑘𝑅 𝐿 𝑇 (40)
144

7
𝐿2 = 𝑘𝑅 𝐿 𝑇 (41)
48

5
𝐿3 = 𝑘𝑅 𝐿 𝑇 (42)
48

Substituting (39) into (37) and equating for LS in (27) give:

Int J Pow Elec & Dri Syst, Vol. 13, No. 3, September 2022: 1922-1950
Int J Pow Elec & Dri Syst ISSN: 2088-8694  1929
49
𝐿𝑆 = 𝑘𝑅 𝐿 𝑇 (43)
188

The capacitor’s design values can be determined using the expressions identified in (27)-(30). The self-
resistances of reactors are chosen such that their corresponding reactors are revealing almost pure reactive
responses at the AC source fundamental frequency. The harmonic-suppressing and filtering circuits function
coherently to block the flowing of TCR current harmonics in the AC source side. In addition, these circuitries
achieve cost and energy savings compared with the high power harmonic filters required for the traditional
TCR applications.

2.1.1. SVC current controlling scheme

The current controlling strategy of the SVC built of a harmonic-treated TCR is shown in Figure 4.
The input signals in this figure are k2BS and k3vAC. The analogue signal k2BS is actually proportional to the
reactive current demanded from the SVC. VCT is an analogue voltage controlling the TCR firing angle and is
determined as:

𝑉𝐶𝑇 = 5𝐴1 − 𝐴2 𝑘2 𝐵𝑆 (44)

Where, A1 and A2 are constants depending on the rating factor KR. VCT varies in the range of zero to +5V.
The zero value corresponds to the maximum positive value of k2BS, while +5V is corresponding to its lowest
negative value. The voltage signal k3vAC is firstly zero-crossed to produce the rectangular waveform VS1 and
secondly delayed by 5msec and then zero-crossed to produce the rectangular waveform VS2. The rectangular
waveform VS3 is obtained through the X-NOR operation on VS1 and VS2. VS3 is processed in F(α) block which
produces a waveform representing the analogue simulation of in (24). The output of F(α) is multiplied by 5 to
obtain V(α). VCT is compared with V(α) to obtain VCX which is logically multiplied by VS2 and its complement
to obtain the TCR firing signals VX1 and VX2 shown in Figure 5. The TCR firing signals can be given by:

𝑉𝑋1 = 𝑉𝐶𝑋 𝑉𝑆2 (45)

𝑉𝑋2 = 𝑉𝐶𝑋 𝑉𝑆2 (46)

Figure 4. The harmonic-treated TCR controlling scheme

Load current balancing for 4-wire systems using harmonic treated … (Abdulkareem Mokif Obais)
1930  ISSN: 2088-8694

The static Var compensator absolute rms current rating |ISR| can be given by (47):

|𝐼𝑆𝑅 | = |𝐵𝑆 𝑉𝐴.𝐶 | (47)

Where, VAC is the rms voltage applied across the SVC and BS is its compensating susceptance. For the
harmonic-treated TCR, BS represents the compensating susceptance constituted by the filtering circuit and the
TCR circuit. The rms current of the harmonic-treated TCR based SVC can be expressed in terms of the
filtering circuit parameters, TCR reactance, and VCT as:

1 1 1 0.2𝑉𝐶𝑇
𝐼𝑆 = 𝑗𝐵𝑆 𝑉𝐴.𝐶 = −𝑗𝑉𝐴.𝐶 ( 1 + 1 + 1 + ) (48)
𝜔𝐿1 − 𝜔𝐿2 − 𝜔𝐿3 − 𝜔𝐿𝑇
𝜔𝐶1 𝜔𝐶2 𝜔𝐶3

When VCT is zero, this SVC is supplying its maximum capacitive current, while it absorbs its maximum
inductive current when VCT is +5V.

Figure 5. The TCR firing signals determination process

2.2. Circuit design of the 380-V, 50-Hz harmonic-treated TCR based SVC
The harmonic-treated TCR based SVC represents the building block of the load current balancing
system of the three-phase unbalanced grounded load. This system is designed for load currents balancing of a
100-kVA, 11kV/ 380V power transformer in 380-V, 50-Hz Iraqi distribution network. The rated line (phase)
current of this transformer at it secondary side (consumer side), is about 214A (peak value). The average
power factor for its phase currents is considered to be about 0.8 lagging. The load current balancing system
for grounded loads has two static compensators; the first is built of three identical SVCs of type SVC1
connected in delta-form, while the second compensator is built of three identical SVCs of type SVC2
connected in star-form. Actually, SVC1 and SVC2 have different design values. The circuit diagram of the
380-V, 50-Hz harmonic-treated TCR based SVC is shown in Figure 6.
If the delta-connected static compensator is designed such that it can balance the active current
components of the load phase currents when one of them is zero and the other two phase currents are
carrying their rated currents with unity power factor, this will imply according to (13) that the balanced active
line currents drawn from the AC supply are of 142.67A (peak value). Assuming that the phase of zero current
is Phase C and applying (17)-(19) for calculating the compensating susceptances result in: BS1AB = 0, BS1BC =
0.265Ʊ, and BS1CA = -0.265 Ʊ. According to these calculated susceptances, SVC1 should be designed such
that its capacitive and inductive reactive current ratings are equal. This implies that the factor kR employed in
(38) should be of a value of 2. Using (47) after substituting for VAC by 537V and for BS by 0.265Ʊ results in a
reactive current rating of 142.67A (peak value). Note that 537V stands for the peak value of an rms value of
380V. Consequently, the TCR reactor of SVC1 should carry a reactive current of 283.333A (peak value).
Since the peak value of the AC voltage across the TCR is 537V, the following design values are computed:
LT=6mH, L1=2.916mH, L2=1.75mH, L3=1.25mH, LS=3.07mH, CS=3300µF, C1=387 µF. C2=231µF, and
C3=165 µF. Note that LT is calculated by dividing 537 by 283.333ω and other design quantities are calculated
using (27)-(30) and (40)-(43). Self-resistances of reactors are chosen such that for each reactor the resistance
to inductance ratio is about 10Ω per Henry. The thyristor used for TCR design is of the type T627121574DN.
It has continuous voltage and current ratings of 2200V and 300A, respectively. This SVC is excited by the
instantaneous line voltage vL which is of peak to peak value of 1075V. Its phase is chosen to be zero for
simplicity. The currents iS, iF, and iT stand for the instantaneous currents of SVC1, filtering circuit, and the

Int J Pow Elec & Dri Syst, Vol. 13, No. 3, September 2022: 1922-1950
Int J Pow Elec & Dri Syst ISSN: 2088-8694  1931

TCR, respectively. vT represents the instantaneous voltage across the TCR. SVC1 current controller and
thyristor driving circuit are represented by electronic parts saved in certain locations on PSpice libraries.
The controller of the harmonic-treated TCR current is driven by the analogue voltage k2BS shown in
Figure 4. The controller of Figure 4 represents a general controlling scheme of the harmonic-treated TCR.
The basic controlling signal in the 380-V, 50-Hz harmonic-treated TCR is k4BS which is represented by a DC
voltage supply varying in the range of -10V to +10V. The controlling circuit of SVC1 is shown in Figure 7.
This circuit is thoroughly emulating the controlling scheme depicted in Figure 4. Since kR for SVC1 is 2, the
constant A1 and A2 are calculated to be 0.5 and 0.25, respectively. The electronic part F(ALPHA) is saved in
a separate library on PSpice. The constant k4 is calculated as follows: k4=10V/(142.67A/537V)=37.64VΩ.

Figure 6. The circuit diagram of the 380-V, 50-Hz harmonic-treated TCR based SVC (type SVC1)

Figure 7. The controlling circuit of SVC1

Load current balancing for 4-wire systems using harmonic treated … (Abdulkareem Mokif Obais)
1932  ISSN: 2088-8694

The driving circuit of the thyristor T627121574DN used in the design of SVC1 is shown in Figure 8.
The circuit supplies the sufficient gate current to the thyristor during the active pulse across the gate and
cathode. In addition, it offers through its opto-coupler the suitable electrical isolation between the power
circuit and the low voltage electronic circuits.

5V V1

R3 R1 R2 V2
Q1
100 U1 7 V+ 22k 650 10V
3 0 R4
VX + U2
33 Q2 R7
max998/mxm 6 A4N26 1
C1 OUT MPSA28
2 G
1nF Q2N2222A
- 4

2
V- C2 0 R5
0 1nF D1 820
5V R6 120NQ045

1
k
V3 5k
0 0

Figure 8. The driving circuit of the thyristor T627121574DN

The electronic part that stands for F(ALPHA) in the SVC1 controlling circuit is generated on PSpice
using the electronic circuit shown in Figure 9. In this figure, a signal analogous to the mathematical behavior
of in (24) is produced. The input to this circuit is the rectangular waveform VS3 which is generated through
the X-NOR operation on VS1 and VS2. Many electronic operations are used in the simulation of F(α). A ramp
signal is produced due the exertion of VS3 on the ramp generator. Many electronic processes are made on the
ramp signal such that a positive half-cycle of a sinusoidal signal running at double frequency of the AC
source is produced. Comparing VCT with 5F(α) makes the TCR current fundamental respond linearly to the
reactive current demand, thus the overall response of SVC1 is linearized due to such a comparison.
Linearizing the reactive current response of the harmonic-treated TCR based SVC to the reactive current
demand is considered as another modification beside the harmonic treatment made on the traditional TCR.
These two modifications promote such kinds of SVCs to be continuously and linearly controlled harmonic-
free compensating susceptances. Figure 10 shows the waveforms of the analogue simulation of F(α).

Figure 9. The analogue simulation of F(α)

Int J Pow Elec & Dri Syst, Vol. 13, No. 3, September 2022: 1922-1950
Int J Pow Elec & Dri Syst ISSN: 2088-8694  1933
5.0V

VS3
2.5V

0V
0s 10ms 20ms 30ms 40ms
V(VS3)
0.5V Time

0.0V
V1
-0.5V

-1.0V
0s 10ms 20ms 30ms 40ms
V(R23:2)
0.5V Time

0.0V
V2
-0.5V

-1.0V
0s 10ms 20ms 30ms 40ms
V(R10:1)
500mV
Time
V3
250mV

0V
0s 10ms 20ms 30ms 40ms
V(R5:1)
5.0V
Time
V4
2.5V

0V
0s 10ms 20ms 30ms 40ms
V(U8:+)
5.0V
Time
V5
2.5V

0V
0s 10ms 20ms 30ms 40ms
1.0V V(U9:OUT)
Time

0.5V
F(alpha)
0V
0s 10ms 20ms 30ms 40ms
V(FALPHA)
Time

Figure 10. Waveforms indicating the production processes of F(α)

2.3. Circuit design of the 220-V, 50-Hz harmonic-treated TCR based SVC
This harmonic-treated TCR based SVC is the building block of the star-connected static
compensator which is built to compensate for load reactive current components in addition to the reactive
current components released by the first static compensator. It is classified as SVC2 type. The inductive and
capacitive ratings for this SVC can be determined by considering the severe unbalance case associating the
open circuit occurring on one phase of a three-phase load and the other two phases remain carrying the rated
current with 0.8 lagging power factor. The maximum active current component of the line current of the first
static compensator is 0.8(214+214)/3=114A (peak value). The reactive current component associating this
current is 99A (peak value). The number 99 corresponds to 114 times sin (π/3). The reactive component of
the first static compensator line current is either capacitive or inductive. Since the connected phases are
carrying rated currents with 0.8 lagging power factor, an additional capacitive reactive of about 128A (peak
value) should be added to the reactive current of 99A released by the first static compensator. The maximum
expected capacitive current demanded from SVC2 is 227A (peak value), while the maximum expected
inductive current is about 123A (peak value) which corresponds to 142.67 times sin (π/3). The TCR should
satisfy a reactive current rating equal to the sum of the capacitive and inductive current ratings, i, e it should
Load current balancing for 4-wire systems using harmonic treated … (Abdulkareem Mokif Obais)
1934  ISSN: 2088-8694

be capable of carrying a maximum reactive current of 350A (peak value). Since the voltage applied across
the TCR of SVC2 is a phase voltage of an rms value of 220V, the inductance of the TCR reactor (LT) is
calculated to be about 2.83mH. The rating factor kR of SVC2 is calculated according to its reactive currents
rating to be 350/227=1.542. Using Equations (40)-(43) results in the following design quantities: L1=1.06mH,
L2=0.63mH, L3=0.45mH, and LS=1.13mH. The inductance value of LS corresponds to a CS value of more than
8000µF. An inductance of about 2mH for LS is a better choice for the harmonic-suppressing circuit, since it
results in better reduction of harmonics and more acceptable value for CS. Using the above design values for
reactors and substituting them in (27)-(30) yield the following values for capacitors: CS=5000µF,
C1=1060µF, C2=645µF, and C3=460µF. Self-resistances of reactors are chosen in the same manner adopted
in SVC1. The circuit diagram of SVC2 is shown in Figure 11. The thyristor used in the circuit design of 220-
V. 50-Hz harmonic-suppressed TCR based SVC is T627121574DN. The basic controlling signal in this SVC
is k5BS which is varying in the range of -5.4V to +10V. SVC2 is excited by the phase voltage VP which is of a
peak to peak value of 622V. Since the maximum capacitive current of SVC2 corresponds to k5BS of 10V,
then k5 is calculated as 10V/(227A/311V)=13.7VΩ. 311V corresponds to the amplitude of 220V rms voltage.
Since kR for SVC2 is of a value of about 1.542, the constants A1 and A2 are calculated to be 0.649 and 0.325,
respectively.

Figure 11. The circuit of the 220-V, 50-Hz harmonic-treated TCR based SVC (type SVC2)

2.4. Circuit design of the proposed load current balancing system for grounded loads
Figure 12 shows the circuit diagram of a complete load current balancing system for grounded loads
using two configurations of harmonic-treated TCR based SVCs. The first configuration represents a static
compensator built of three SVCs type SVC1 connected in delta-form, while the second configuration is a
static compensator built of three SVCs type SVC1 connected in star-form. The functions of the two

Int J Pow Elec & Dri Syst, Vol. 13, No. 3, September 2022: 1922-1950
Int J Pow Elec & Dri Syst ISSN: 2088-8694  1935

compensators are already discussed. Each SVC has its individual controller and driving circuit. The
controllers are also discussed and the two driving circuits of the TCR thyristors are merged into one
electronic part and saved in PSpice libraries. The circuit diagram includes a circuit called AC signals
detection circuit which extracts low voltage analogue signals proportional to the phase and line voltages of
the AC power system. The computation circuit in this circuit diagram is represented by a single electronic part.

VA VA
U1
K3VA k3VA VA iA i LA
K3VB k3VB
U2
k3VC VA R1
K3VC 1 2
VB VB IN OUT

K1I
K3VAB k3VAB
DAMPING = 0 0.001 LA RA

VC VC
K3VBC

K3VCA
k3VBC

k3VCA
DELAY = 0
FREQ_HZ = 50Hz
PP_AMPLITUDE = 622V
OFFSET = 0
VB iB iLB k1iLA
CURRENT TRANSFORMER (LV)
2.77mH 1.16

PHASE = 0 U3
AC v oltages detection cct (LV) VB R2
1 2
IN OUT
AC voltages detection circuit

K1I
DAMPING = 0 0.001 LB RB

k1iLA K1ILA
U4
K4BSAB k4BSAB
DELAY = 0
FREQ_HZ = 50Hz
PP_AMPLITUDE = 622V
OFFSET = 0
VC iC iLC k1iLB
CURRENT TRANSFORMER (LV)
2.77mH 1.16

PHASE = -120 U5
VC R3
k1iLB K1ILB 1 2
K4BSBC k4BSBC IN OUT

K1I
k1iLC K1ILC DAMPING = 0 0.001 LC1 RC
k4BSCA DELAY = 0
VS1A VS1A K4BSCA FREQ_HZ = 50Hz 2.77mH 1.16
k1iLC
PP_AMPLITUDE = 622V
VS1B VS1B OFFSET = 0 CURRENT TRANSFORMER (LV)
K5BSA k5BSA
PHASE = -240
VS1C VS1C

VS2A VS2A K5BSB k5BSB

VS2B VS2B
K5BSC k5BSC
N
VS2C VS2C 0

COMPUTATION CCT (LV)

Susceptances computation circuit Power system voltage Load currents detection circuit Three-phase load

U6
k3VAB K3VAB VX1AB VX1AB

k4BSAB K4BSAB VX2AB VX2AB

H-SUPP TCR CONTROLLER LIMB AB

U7
k3VBC K3VBC VX1BC VX1BC G2AB k2AB k2A G2A
X2AB X2A
T627121574DN

T627121574DN
k4BSBC K4BSBC VX2BC VX2BC

H-SUPP TCR CONTROLLER LIMB BC

10nF

10nF
RTAB LTAB
50

50
U8 LTA RTA
2 1 1 2
k3VCA K3VCA VX1CA VX1CA
T627121574DN

T627121574DN
RSNAB

CSNAB

CSNA

RSNA
0.06 6mH 2.82mH 0.0282
k4BSCA K4BSCA VX2CA

H-SUPP TCR CONTROLLER LIMB CA

VX2CA

X1AB
iS1A iS 2 A X1A
3P-controlling circuit (delta) RSAB LSAB CSAB
CSA LSA RSA
k1AB G1AB 2 2 1 1 1 21 2 G1A k1A

U9 R3AB L3AB C3AB 0.0307 3.07mH 3300uF R4 R5 5000uF 2mH 0.02 C3A L3A R3A
2 12 1 0.001 0.001 1 21 2
k3VA K3VA VS1A VS1A

VS2A 0.0125 1.25mH 165uF 460uF 0.45mH 0.0045

VS2A

VX1A VX1A

k5BSA K5BSA VX2A VX2A

R2AB L2AB C2AB C2A L2A R2A
2 12 1 1 21 2
H-SUPP TCR CONTROLLER LIMB A
0.0175 1.75mH 231uF 645uF 0.63mH 0.0063
U10
k3VB K3VB VS1B VS1B

VS2B VS2B
R1AB L1AB C1AB C1A L1A R1A
2 12 1 1 21 2
VX1B VX1B

VX2B 0.0291 2.91mH 387uF 1060uF 1.06mH 0.0106

k5BSB K5BSB VX2B

H-SUPP TCR CONTROLLER LIMB B

U11
k3VC K3VC VS1C VS1C G2BC k2BC k2B G2B

VS2C X2BC X2B

VS2C
T627121574DN

T627121574DN

VX1C VX1C

k5BSC K5BSC VX2C VX2C

10nF

10nF

RTBC LTBC
50

50

LTB RTB
H-SUPP TCR CONTROLLER LIMB C 2 1 1 2
T627121574DN

T627121574DN

CSNB

RSNB

3P-controlling circuit (star)

RSNBC

CSNBC

0.06 6mH 2.82mH 0.0282

U12
iS1B iS 2 B
VX1AB X1BC X1B
VX1AB G1AB G1AB
RSBC LSBC CSBC
k1BC G1BC CSB LSB RSB G1B k1B
K1AB k1AB
N

2 2 1 1 1 21 2

G2AB G2AB
R3BC L3BC C3BC R6 R7 5000uF 2mH 0.02 C3B L3B R3B
2 12 1 0.0307 3.07mH 3300uF 0.001 0.001 1 21 2
VX2AB VX2AB K2AB k2AB
0.0125 1.25mH 165uF 460uF 0.45mH 0.0045
LIMB AB DRIVING CIRCUIT

U13
VX1BC VX1BC G1BC G1BC
R2BC L2BC C2BC C2B L2B R2B
2 12 1 1 21 2
K1BC k1BC
0.0175 1.75mH 231uF 645uF 0.63mH 0.0063
G2BC G2BC

VX2BC VX2BC K2BC k2BC

LIMB BC DRIVING CIRCUIT R1BC L1BC C1BC C1B L1B R1B

2 12 1 1 21 2
U14
VX1CA 0.0291 2.91mH 387uF 1060uF 1.06mH 0.0106
VX1CA G1CA G1CA

K1CA k1CA

G2CA G2CA

VX2CA VX2CA K2CA k2CA G2CA k2CA k2C G2C

X2CA X2C
T627121574DN

T627121574DN

LIMB CA DRIVING CIRCUIT

3P-driving circuit (delta)

10nF

10nF
50

50

RTCA LTCA LTC RTC

U15 2 1 1 2
T627121574DN

T627121574DN

VX1A VX1A G1A G1A

iS 2 C
RSNCA

CSNCA

CSNC

RSNC

iS1C
0.06 6mH 2.82mH 0.0282
K1A k1A

G2A G2A

VX2A X1CA X1C

VX2A K2A k2A
RSCA LSCA CSCA
k1CA G1CA CSC LSC RSC G1C k1C
LIMB A DRIVING CIRCUIT 2 2 1 1 1 21 2

U16 R3CA L3CA C3CA 0.0307 3.07mH 3300uF R8 R9 5000uF 2mH 0.02 C3C L3C R3C
2 12 1 0.001 0.001 1 21 2
VX1B VX1B G1B G1B
0.0125 1.25mH 165uF 460uF 0.45mH 0.0045
K1B k1B

G2B G2B

VX2B VX2B K2B k2B

R2CA L2CA C2CA C2C L2C R2C
2 12 1 1 21 2
LIMB B DRIVING CIRCUIT
0.0175 1.75mH 231uF 645uF 0.63mH 0.0063
U17
VX1C VX1C G1C G1C

K1C k1C
R1CA L1CA C1CA C1C L1C R1C
2 12 1 1 21 2
G2C G2C

VX2C 0.0291 2.91mH 387uF 1060uF 1.06mH 0.0106

VX2C K2C k2C

LIMB C DRIVING CIRCUIT

3P-driving circuit (star) Delta-connected Harmonics-suppressed TCRs Star-connected Harmonics-suppressed TCRs

Figure 12. Circuit diagram of load current balancing system for grounded loads in 380-V, 50-Hz power
system network using harmonic-treated TCR based SVCs

Load current balancing for 4-wire systems using harmonic treated … (Abdulkareem Mokif Obais)
1936  ISSN: 2088-8694

The AC voltage’s detection circuit is shown in Figure 13. The phase voltages are detected through
potential dividers which are buffered through three voltage followers. The buffers outputs are processed
through difference amplifiers for demining the k3vAB, k3vBC, and k3vCA which are necessary for the controllers
of the delta-connected SVCs. According to this circuit, k3 is calculated to be 0.00892. The buffer outputs
k3vA, k3vB, and k3vC are necessary for the star-connected SVCs controllers and the computation circuit.
The current transformer used in this load current balancing system is shown in Figure 14. Its
primary to secondary turn ratio is 1:100. The value of the resistance R1 is chosen such that the maximum
amplitude of the analogue voltage k1i is about 14.14V when the load line current is 214A (peak value).
Accordingly, k1 is calculated to be 0.066Ω.

+5V k3VA +5V

R1 R3

7
+5V 300k U1 10k U2
3 3

V+

V+
VA + +
R2 max998/mxm 6 R5 max998/mxm 6
OUT OUT k3VAB
R4 2.7k 10k
0.001 2 2
- 4 - 4
V1 0 V- 0 V-
5V R6 R7
-5V 10k 10k -5V

+5V k3VB +5V

R8 R10
7

7
300k U3 10k U4
3 3
V+

V+
VB + +
R9 max998/mxm 6 R11 max998/mxm 6
OUT OUT k3VBC
2.7k 10k
2 2
- 4 - 4
0 V- 0 V-
R12 R13
-5V 10k 10k -5V

-5V

R14 +5V k3VC +5V

0.001 R15 R17
7

300k U5 10k U6
3 3
V+

V+

VC + +
V2
5V R16 max998/mxm 6 R18 max998/mxm 6
OUT OUT k3VCA
2.7k 10k
2 2
0 - 4 - 4
0 V- 0 V-
R19 R20
-5V 10k 10k -5V

Figure 13. AC voltages detection circuit for load current balancing system using harmonic-treated TCR based
SVCs

TX1
IN OUT

k1i
TN33_20_11_2P90

R1
6.6 0

Primary to secondary turn ratio=1:100

Figure 14. Current transformer for 380-V, 50-Hz load current balancing system

The computation circuit is used to determine the compensating susceptances required for load
current balancing. Its circuit diagram is shown in Figure 15. Firstly, the current signals are sampled at the

Int J Pow Elec & Dri Syst, Vol. 13, No. 3, September 2022: 1922-1950
Int J Pow Elec & Dri Syst ISSN: 2088-8694  1937

positive peaks of their corresponding phase voltages to obtain their active components. The current signals
are also sampled at the negative slope zero-crossing points of their corresponding phase voltages to obtain the
negative values of their reactive components. The delta-connected compensator susceptances are computed
using (17)-(19), while the star-connected compensator susceptances are computed by using (20)-(22). The
difference and summing amplifiers perform the computation process for all compensating susceptances.

+15V
5
1 V+ +15V +15V +15V
k1iLA + k5BSA
S1 LM675 U1 4 R1 R2 5 5 5

-
+ OUT 10.2k 3.9k 1 V+ 1 V+ 1 V+
+ Sbreak
- C1 2 + + +
U5A C2 D1
0 - 3 U2 4 R3 0 U3 4 R4 0 U4 4
500nF
1uF BAW62 V- 0 LM675 OUT 15k LM675 OUT 5k LM675 OUT
1 2 2 2 2
VS1A 0 -15V - 3 - 3 - 3
V- V- V-
74ACT04 R5 D2 R6 R7 R8 R9
33 BAW62 10.2k 3.9k -15V 10k 10k -15V -15V

R10
0 0 5k

Sample and hold circuit (1) Summing amolifier (1)

+15V

5
1 V+ +15V +15V +15V
k1iLB + k5BSB
S2 LM675 U6 4 R11 R12 5 5 5
-
+

OUT 10.2k 3.9k 1 V+ 1 V+ 1 V+

Sbreak
+
-

C3 2 + + +
U5B C4 D3
0 - 3 U7 4 R13 0 U8 4 R14 0 U9 4
500nF
1uF BAW62 V- 0 LM675 OUT 15k LM675 OUT 5k LM675 OUT
3 4 2 2 2
VS1B 0 -15V - 3 - 3 - 3
V- V- V-
74ACT04 R15 D4 R16 R17 R18 R19
33 BAW62 10.2k 3.9k -15V 10k 10k -15V -15V

R20
0 0 5k

Sample and hold circuit (2) Summing amolifier (2)

+15V

5
1 V+ +15V +15V +15V
k1iLC + k5BSC
S3 LM675 U10 4 R21 R22 5 5 5
-
+

OUT 10.2k 3.9k 1 V+ 1 V+ 1 V+

Sbreak
+
-

C5 2 + + +
U5C C6 D5
0 - 3 U11 4 R23 0 U12 4 R24 0 U13 4
500nF
1uF BAW62 V- 0 LM675 OUT 15k LM675 OUT 5k LM675 OUT
5 6 2 2 2
VS1C 0 -15V - 3 - 3 - 3
V- V- V-
74ACT04 R25 D6 R26 R27 R28 R29
33 BAW62 10.2k 3.9k -15V 10k 10k -15V -15V

R30
0 0 5k

Sample and hold circuit (3) Summing amolifier (3)

+15V R31 +15V

5k
5 +15V 5
1 V+ 1 V+
k1iLA + 5 +
R32
S4 LM675 U14 4 5k 1 V+ R33 0 U15 4
-
+

OUT + OUT k4BSAB

Sbreak 14.14k LM675
+
-

C7 2 U16 4 2
C8 D7
0 - 3 0 LM675 OUT - 3 +15V
500nF V- V-
1uF BAW62 2
- 3 R34
VS2A 0 -15V V- -15V
10k
R37 R38 R36
R35 D8 5k 5k -15V 0.001
33 BAW62
V1
15V
0 0
0
Sample and hold circuit (4) Difference amplifier (1)

+15V R39 +15V

5k
5 +15V 5
1 V+ 1 V+
k1iLB + 5 +
R40
S5 LM675 U17 4 5k 1 V+ R41 0 U18 4
-
+

OUT + OUT k4BSBC

Sbreak 14.14k LM675
+
-

C9 2 U19 4 2
C10 D9
0 - 3 0 LM675 OUT - 3 -15V
500nF V- V-
1uF BAW62 2
- 3 R43
VS2B 0 -15V V- -15V
10k
R45 R46 R44
R42 D10 5k 5k -15V 0.001
33 BAW62

V2
15V
0 0
0
Sample and hold circuit (5) Difference amplifier (2)

+15V R47 +15V

5k
5 +15V 5
1 V+ 1 V+
k1iLC + 5 +
R48
S6 LM675 U20 4 5k 1 V+ R49 0 U21 4
-
+

OUT + OUT k4BSCA

Sbreak 14.14k LM675
+
-

C11 2 U22 4 2
C12 D11
0 - 3 0 LM675 OUT - 3
500nF V- V-
1uF BAW62 2
- 3 R50
VS2C 0 -15V V- -15V
10k
R52 R53
R51 D12 5k 5k -15V
33 BAW62

0 0

Sample and hold circuit (6) Difference amplifier (3)

Figure 15. The computation circuit of load current balancing system using harmonic-treated TCR

Load current balancing for 4-wire systems using harmonic treated … (Abdulkareem Mokif Obais)
1938  ISSN: 2088-8694

3. RESULTS AND DISCUSSION

The circuits of Figures 6, 11, 12 were tested on PSpice to show the performance of the proposed
compensating susceptances and load current balancing system.

3.1. Performance results of the 380-V, 50-Hz harmonic-treated TCR based SVC
The 380-V, 50-Hz harmonic-treated TCR based SVC is classified as type SVC1. The circuit
diagram of SVC1 is shown in Figure 6. This circuit was tested on PSpice for the investigation of harmonic
contents, control continuity and linearity. The parameters measured through PSpice tests where the SVC
current iS, the TCR current iT, the AC voltage vL, the TCR voltage vT, the SVC current frequency spectrum
F(S), and the TCR current frequency spectrum F(T). The AC voltage vL was of amplitude of 537V (peak
value) and zero phase angle. The basic controlling signal of the compensator is k4BS which is represented by
a separate DC source. Figure 16 shows SVC1 response to zero reactive current demand which corresponded
to k4BS=0. It is obvious that SVC1 fundamental current is almost zero and F(S) is free from any sort of
current harmonics. Figure 17 shows SVC1 response to an inductive current demand of 36A (peak value),
which corresponded to k4BS of -2.5V. Figure 18 reflects SVC1 performance during its response to an
inductive reactive current demand of 72A (peak value), which corresponded to k4BS of -5V. Figure 19 shows
the performance of SVC1 during its response to an inductive reactive current demand of 108A (peak value)
which corresponded to k4BS of -7.5V.

Figure 16. SVC1 response to zero reactive current demand

Figure 17. SVC1 response to an inductive current demand of 36A (peak value)

Int J Pow Elec & Dri Syst, Vol. 13, No. 3, September 2022: 1922-1950
Int J Pow Elec & Dri Syst ISSN: 2088-8694  1939

Figure 20 shows the performance of SVC1 during its response to an inductive current demand of
144A (peak value), which corresponded to k 4BS of -10V. This inductive reactive current demand corresponds
to the compensator maximum inductive current rating. The TCR was operating at zero firing angle at this
test. In all these tests, the compensator current was purely inductive. Even though the frequency spectrum of
the TCR current F(T) exhibits significant odd current harmonics, SVC1 current spectrum F(S) is free from
noticeable current harmonics except the fundamental component. This is due to the harmonic cancellation
efficiency of the filtering circuit and the harmonic suppression efficiency of the harmonic suppressing circuit.
During zero reactive current demand, SVC1 current frequency spectrum exhibits a fundamental current
component of a less than 3A (peak value). This amount of current is responsible for no load operating losses
of this compensator.

Figure 18. SVC1 response to an inductive current demand of 72A (peak value)

Figure 19. SVC1 response to an inductive current demand of 108A (peak value)

Here is the performance of SVC1 during capacitive mode of operation. Figure 21 shows the
performance of SVC1 during its response to a capacitive reactive current demand of 36A (peak value), which
corresponded to k4BS of 2.5V. It is obvious that the compensator current waveform is purely capacitive.
Figures 22-24 show the responses of SVC1 to capacitive reactive current demand of 72A, 108A, and 144A
Load current balancing for 4-wire systems using harmonic treated … (Abdulkareem Mokif Obais)
1940  ISSN: 2088-8694

(peak values) which, corresponded to k4BS of 5V, 7.5V, and 10V, respectively. The figures exhibit purely
capacitive responses. During capacitive mode of operation, the frequency spectrum of SVC1 current
indicates no noticeable current harmonics beside the fundamental component. In addition, the compensator
current exhibits peaks at the positive slope zero crossing points of the AC voltage supplying the compensator.
Consequently, SVC1 current is verified as purely capacitive and free from any sort of noticeable current
components except the fundamental component. In Figure 24, the amount of current corresponds to SVC1
maximum capacitive current rating. In this test, the TCR was fully relaxed and filtering circuit was supplying
the capacitive reactive current demand. The frequency spectrum of this test shows that the TCR current
indicates no signs of harmonic association.

Figure 20. SVC1 response to an inductive current demand of 144A (peak value)

Figure 21. SVC1 response to a capacitive current demand of 36A (peak value)

Int J Pow Elec & Dri Syst, Vol. 13, No. 3, September 2022: 1922-1950
Int J Pow Elec & Dri Syst ISSN: 2088-8694  1941

Figure 22. SVC1 response to a capacitive current demand of 72A (peak value)

Figure 23. SVC1 response to a capacitive current demand of 108A (peak value)

Load current balancing for 4-wire systems using harmonic treated … (Abdulkareem Mokif Obais)
1942  ISSN: 2088-8694

Figure 24. SVC1 response to a capacitive current demand of 144A (peak value)

According to the above tests, SVC1 is demonstrated as a harmonic-free pure reactive device which
can be represented by a harmonic-free compensating susceptance. The nonexistence of any sort of current
harmonics beside SVC1 reactive current fundamental reflects the effectiveness of the filtering technique
adopted in the design of the harmonic-treated TCR. The linearity of the devised compensating susceptance is
verified by the graph shown in Figure 25. This graph is obtained by plotting the actual values of SVC1
current against reactive current demand. The minus sign denotes inductive reactive current. The performance
of this compensating susceptance during sudden change in reactive current demand from maximum
capacitive to maximum inductive is shown in Figure 26.

Figure 25. SVC1 actual reactive current against reactive current demand

Int J Pow Elec & Dri Syst, Vol. 13, No. 3, September 2022: 1922-1950
Int J Pow Elec & Dri Syst ISSN: 2088-8694  1943

Figure 26. The treatment of SVC1 to sudden change in reactive current demand from maximum capacitive to
maximum inductive. The change occurred at t=200ms and the transition period was 20ms

3.2. Performance results of the 220-V, 50-Hz harmonic-treated TCR based SVC
The 220-V, 50-Hz harmonic-treated TCR based SVC is classified as type SVC2. The circuit
diagram of this SVC is shown in Figure 11. The AC voltage supplying SVC2 was the phase voltage vP which
was of amplitude of 311V (peak value) and zero phase angle. SVC2 is controlled by the analogue voltage
k5BS. A capacitive current of 227A (peak value) corresponds to k5BS of 10V; while an inductive current of
123A (peak value) corresponds to k5BS of -5.4V. A zero reactive current demand corresponds to k5BS of zero
value. SVC2 was tested on PSpice for the investigation of harmonic contents, control continuity and linearity.
SVC2 shows similar performance compared to SVC1 in capacitive and inductive modes of operation, except
different in reactive current ratings. SVC2 responses to reactive current demand variations in the range of
123A (peak value) inductive to 227A (peak value) capacitive are summarized as shown in Figure 27. The
linearity of this susceptance is verified by the graph of this figure. This graph is obtained by plotting the
actual current of SVC2 against reactive current demand. The minus sign in Figure 27 denotes inductive
current. Finally, it has been demonstrated that the 220-V, 50-Hz harmonic-treated TCR based SVC (SVC2)
can be represented by a continuously and linearly controlled harmonic-free compensating susceptance.

Figure 27. SVC2 reactive current against reactive current demand

Load current balancing for 4-wire systems using harmonic treated … (Abdulkareem Mokif Obais)
1944  ISSN: 2088-8694

3.3. Performance results of the proposed load current balancing system

This load balancing system is shown in Figure 12. The system was tested on PSpice at different
loading conditions. The basic parameters measured were the AC source currents iA, iB, and iC; the load
currents iLA, iLB, and iLC; the first compensator currents iS1A, iS1B, and iS1C; the second compensator currents
iS2A, iS2B, and iS2C. The AC source was a 100-kVA, 11 kV/380 V, 50-Hz power transformer having a rated
current of 214 A (peak value). Figure 28 shows the compensator performance during balanced rated resistive
load. It is obvious that the load current balancing system was relaxed through this test since both its
compensators were carrying almost zero currents.

Figure 28. The proposed load current balancing system was relaxed during balanced resistive load

Figure 29 shows the treatment of the load current balancing system to a balanced three-phase load
carrying the power transformer rated current at a lagging power factor of 0.707. The treatment had resulted in
balanced resistive load drawn from the power transformer. During this load, the first compensator of the load
current balancing system was fully relaxed. The figure shows big reduction in the AC source currents.

Int J Pow Elec & Dri Syst, Vol. 13, No. 3, September 2022: 1922-1950
Int J Pow Elec & Dri Syst ISSN: 2088-8694  1945

Figure 29. The proposed load current balancing system during its treatment to a balanced rated load at 0.707
lagging power factor

The system can correct to unity the power factor of the load phase currents as long as the load
reactive current components are within the reactive current capability of the second compensator. If the
reactive current contents required to be compensated are exceeding the second compensator capability, then
the expected action will be power factor improvement of the load phase currents. Figure 30 shows the
performance of the load current balancing system during a load unbalance resulted from disconnecting one
phase of a balanced rated load at a lagging power factor of 0.8. Even though, the load unbalance was severe,
it had been recovered with balanced pure real currents drawn from the AC source (power transformer).

Load current balancing for 4-wire systems using harmonic treated … (Abdulkareem Mokif Obais)
1946  ISSN: 2088-8694

Figure 30. Performance of the proposed load current balancing system during the disconnection of one phase
of a balanced rated load at 0.8 lagging power factor

Figure 31 shows the treatment of a load unbalance resulted from the disconnection of two phases of
a rated three-phase load at 0.8 lagging power factor. The above load unbalance is actually severe, but the load
current balancing system had easily involved it with the production of balanced active AC source phase
currents. Figure 32 shows the treatment of a significant unbalance in phase and magnitude of a three-phase
load having phase currents exceeding the power transformer current rating. The load balancing system had
brought the AC source currents below their rated values. The compensation mechanism of the load unbalance
depicted in Figures 32 is clarified by the phasor diagram shown in Figure 33.

Int J Pow Elec & Dri Syst, Vol. 13, No. 3, September 2022: 1922-1950
Int J Pow Elec & Dri Syst ISSN: 2088-8694  1947

Figure 31. Performance of the proposed load current balancing system during the disconnection of two
phases of a three-phase load and leaving the third carrying a rated current at 0.8 lagging power factor

Load current balancing for 4-wire systems using harmonic treated … (Abdulkareem Mokif Obais)
1948  ISSN: 2088-8694

Figure 32. Performance of the load current balancing system during its treatment to a load unbalance in
which all phase currents were exceeding the power transformer rating

VC

I S1C

IC I S 2C = 0
I LC Rated current margin

IA VA

I LB
I S 1B
IS2A
I LA
I S 2B IB

I S1 A
VB

Figure 33. A phasor diagram showing the balancing mechanism of the load unbalance treated in Figure 32

Int J Pow Elec & Dri Syst, Vol. 13, No. 3, September 2022: 1922-1950
Int J Pow Elec & Dri Syst ISSN: 2088-8694  1949

4. CONCLUSION
The harmonic-treated TCR based SVC is devised from the traditional TCR, which is characterized
by the injection of wide spectrum of odd current harmonics. Equipping the traditional TCR with efficient
harmonic-suppressing and filtering circuits beside the devised controlling scheme makes it respond linearly
to reactive current demand (capacitive and inductive) without noticeable harmonic association. The filtering
efficiency of the devised SVC is invulnerable to the adjacent harmonic sources in the power system network
where the SVC is installed. The 3rd, 5th, and 7th current harmonics are completely cancelled in the SVC
current, while the 9th odd harmonic and forth are minimized to at least one tenth their magnitudes in the TCR
current. The harmonic-treated TCR based SVC represents a reliable replacement of the FC-TCR based SVC
equipped with high power harmonic filters, thus using harmonic-treated TCR based SVC achieves energy
and cost savings. In addition, this devised SVC is capable of satisfying reactive current demand during
sudden change from maximum capacitive to maximum inductive with a transition time less than 20msec. The
devised continuously and linearly controlled harmonic-free compensating susceptances are employed in the
design of a transformerless load current balancing system for a 100-kVA power transformer in a 380-V, 50-
Hz distribution network. The devised compensating susceptances and the designed load current balancing are
characterized by controlling linearity and compensation quality superior to those proposed by previous
works. The proposed load current balancing system had showed excellent treatment to different unbalance
conditions.

REFERENCES
[1] J. E. R. Alves, L. A. S. Pilotto and E. H. Watanabe, “Thyristor-Controlled Reactors Nonlinear and Linear Dynamic Analytical
Models,” IEEE Transactions on Power Delivery, vol. 23, no. 1, pp. 338-346, 2008, doi: 10.1109/TPWRD.2007.911131.
[2] B. Singh, P. Jayaprakash, T. R. Somayajulu and D. P. Kothari, “Reduced Rating VSC With a Zig-Zag Transformer for Current
Compensation in a Three-Phase Four-Wire Distribution System,” IEEE Transactions on Power Delivery, vol. 24, no. 1, pp. 249-
259, 2009, doi: 10.1109/TPWRD.2008.2005398.
[3] A. Luo, Z. Shuai, W. Zhu and Z. J. Shen, “Combined System for Harmonic Suppression and Reactive Power Compensation,”
IEEE Transactions on Industrial Electronics, vol. 56, no. 2, pp. 418-428, 2009, doi: 10.1109/TIE.2008.2008357.
[4] Y. Xu, L. M. Tolbert, J. D. Kuek, and D. T. Rizy, “Voltage and current unbalance compensation using a static VAR
compensator,” IET Power Electronics, vol. 3, no. 6, pp. 977-988, 2010, doi: 10.1049/iet-pel.2008.0094.
[5] A. Hamadi, S. Rahmani and K. Al-Haddad, “A Hybrid Passive Filter Configuration for VAR Control and Harmonic
Compensation,” IEEE Transactions on Industrial Electronics, vol. 57, no. 7, pp. 2419-2434, 2010, doi:
10.1109/TIE.2009.2035460.
[6] B. Singhy and P. Venkateswarlu, “A Simplified Control Algorithm for Three-Phase, Four-Wire Unified Power Quality
Conditioner,” Journal Power Electronics, vol. 10, no. 1, pp. 91-96, 2010, doi: 10.6113/JPE.2010.10.1.091.
[7] J. Wu, H. Jou, H. Hsaio and S. Xiao, “A New Hybrid Power Conditioner for Suppressing Harmonics and Neutral-Line Current in
Three-Phase Four-Wire Distribution Power Systems,” IEEE Transactions on Power Delivery, vol. 29, no. 4, pp. 1525-1532, 2014,
doi: 10.1109/TPWRD.2014.2322615.
[8] W.N. Chang and K.D. Yeh, “Real-time load balancing and power factor correction of three-phase, four-wire unbalanced systems
with DSTATCOM,” Journal Marine Science Technology, vol. 22, no. 5, pp. 598-605, 2014, doi:10.6119/JMST-013-0926-1.
[9] L. S. Czarnecki and P. M. Haley, “Unbalanced Power in Four-Wire Systems and Its Reactive Compensation,” IEEE Transactions
on Power Delivery, vol. 30, no. 1, pp. 53-63, 2015, doi: 10.1109/TPWRD.2014.2314599.
[10] A. Hintz, U. R. Prasanna and K. Rajashekara, “Comparative Study of the Three-Phase Grid-Connected Inverter Sharing
Unbalanced Three-Phase and/or Single-Phase systems,” IEEE Transactions on Industry Applications, vol. 52, no. 6, pp. 5156-
5164, 2016, doi: 10.1109/TIA.2016.2593680.
[11] X. Zhao, C. Zhang, X. Chai, J. Zhang, F. Liu and Z. Zhang, “Balance control of grid currents for UPQC under unbalanced loads
based on matching-ratio compensation algorithm,” Journal of Modern Power Systems and Clean Energy, vol. 6, no. 6, pp. 1319-
1331, 2018, doi: 10.1007/s40565-018-0383-7.
[12] Y. Hoon and M. A. M. Radzi, “PLL-Less Three-Phase Four-Wire SAPF with STF-dq0 Technique for Harmonics Mitigation
under Distorted Supply Voltage and Unbalanced Load Conditions,” Energies, vol. 11, no. 8, pp. 1–27, 2018, doi:
10.3390/en11082143.
[13] C. Cai, P. An, Y. Guo, and F. Meng, “Three-Phase Four-Wire Inverter Topology with Neutral Point Voltage Stable Module for
Unbalanced Load Inhibition,” Journal of Power Electronics, vol. 18, no. 5, pp. 1315-1324, 2018, doi:
10.6113/JPE.2018.18.5.1315.
[14] L. S. Czarnecki, “CPC – Based Reactive Balancing of Linear Loads in Four-Wire Supply Systems with Nonsinusoidal Voltage,”
Przegląd Elektrotechniczny, vol. 95, no. 4, pp. 1-8, 2019, doi:10.15199/48.2019.04.01.
[15] H. Yoon, D. Yoon, D. Choi, and Y. Cho, “Three-Phase Current Balancing Strategy with Distributed Static Series Compensators,”
Journal of Power Electronics, vol. 19, no. 3, pp. 803-814, 2019, doi: 10.6113/JPE.2019.19.3.803.
[16] G. Bao and S. Ke, “Load Transfer Device for Solving a Three-Phase Unbalance Problem under a Low-Voltage Distribution
Network,” Energies, vol. 12, no. 15, pp. 1-18, 2019, doi: 10.3390/en12152842.
[17] Z. Sołjan, G. Hołdyński, and M. Zajkowski, “Balancing reactive compensation at three-phase four-wire systems with a sinusoidal
and asymmetrical voltage source,” Bulletin of the Polish Academy of Sciences, vol. 68, no. 1, pp. 71-79, 2020, doi:
10.24425/bpasts.2020.131831.
[18] Z. Zhang, “Design of alternating current voltage–regulating circuit based on thyristor: Comparison of single phase and three
phase,” Measurement and Control, vol. 53, no. 5-6, pp. 884-891, 2020, doi: 10.1177/0020294020909123.
[19] A. A. Goudah, D. Schramm, M. El-Habrouk, A. A. Farag, and Y. G. Dessouky, “Smart Electric Grids Three-Phase Automatic
Load Balancing Applications Using Genetic Algorithms,” Journal of Renewable Energy and Sustainable Development (RESD),
vol. 6, no. 1, 2020, doi: 10.21622/RESD.2020.06.1.018.
[20] C. Li, Z. Xia, F. Li, X. Chen, H. Li, Z. Liu, and G. Wang, “Unbalanced current analysis of three-phase AC–DC converter with

Load current balancing for 4-wire systems using harmonic treated … (Abdulkareem Mokif Obais)
1950  ISSN: 2088-8694

power factor correction function based on integrated transformer,” IET Power Electronics, vol. 13, no. 12, pp. 2461-2468, 2020,
doi: 10.1049/iet-pel.2019.1415.
[21] R. M. Mira, P. A. Blasco, J. M. Diez, R. Montoya, and M. J. Reig, “Unbalanced and Reactive Currents Compensation in Three-
Phase Four-Wire Sinusoidal Power Systems,” Applied Sciences, vol. 10, no. 5, pp. 1-23, 2020, doi:10.3390/app10051764.
[22] P. A. Blasco, R. Montoya-Mira, J. M. Diez, and R. Montoya, “An Alternate Representation of the Vector of Apparent Power and
Unbalanced Power in Three-Phase Electrical Systems,” Applied Sciences, vol. 10, no. 11, pp. 1-16, 2020, doi:
10.3390/app10113756.
[23] K. Ma, L. Fang and W. Kong, “Review of distribution network phase unbalance: Scale, causes, consequences, solutions, and
future research directions,” CSEE Journal of Power and Energy Systems, vol. 6, no. 3, pp. 479-488, 2020, doi:
10.17775/CSEEJPES.2019.03280.
[24] M. N. Ansari, and R. K. Singh, “Application of D-STATCOM for Harmonic Reduction using Power Balance Theory,” Turkish
Journal Computer and Mathmetics Education, vol. 12 no. 6, pp. 2496-2503, 2021, doi: 10.17762/turcomat.v12i6.5694.
[25] R. A. Otto, T. H. Putman and L. Gyugyi, “Principles and Applications of Static, Thyristor-Controlled Shunt Compensators,” IEEE
Transactions on Power Apparatus and Systems, vol. PAS-97, no. 5, pp. 1935-1945, 1978, doi: 10.1109/TPAS.1978.354690.
[26] L. T. G. Lima, A. Semlyen and M. R. Iravani, “Harmonic domain periodic steady state modeling of power electronics apparatus:
SVC and TCSC,” IEEE Transactions on Power Delivery, vol. 18, no. 3, pp. 960-967, 2003, doi: 10.1109/TPWRD.2003.813805.
[27] S. S. A. Dangeti, C. K. P. Sekharamantry, V. K. Bayanti, B. A. R. Ch, K. R. Murthy, and A. Tirupathi, “A cascaded converter
using hybrid cells and H-bridge structure,” Bulletin of Electrical Engineering and Informatics, vol. 10, no. 6, pp. 2972-2979,
2021, doi: 10.11591/eei.v10i6.2783.
[28] K. M. Abdulhassan and O. Y. K. Al-Atbee, “Improved modified a multi-level inverter with a minimum total harmonic distortion,”
Bulletin of Electrical Engineering and Informatics, vol. 11, no. 2, pp. 672-680, 2022, doi: 10.11591/eei.v11i2.3466.
[29] A. K. Mishra, S. R. Das, P. K. Ray, R. K. Mallick, A. Mohanty and D. K. Mishra, “PSO-GWO Optimized Fractional Order PID
Based Hybrid Shunt Active Power Filter for Power Quality Improvements,” IEEE Access, vol. 8, pp. 74497-74512, 2020, doi:
10.1109/ACCESS.2020.2988611.
[30] K. V. G. Rao and M. Kiran Kumar, “The harmonic reduction techniques in shunt active power filter when integrated with non-
conventional energy sources,” Indonesian Journal of Electrical Engineering and Computer Science, vol. 25, no. 3, pp. 1236-1245,
2022, doi: 10.11591/ijeecs.v25.i3.pp1236-1245.
[31] A. Ram, P. R. Sharma, and R. K. Ahuja, “Performance evaluation of different configurations of system with DSTATCOM using
proposed 𝐈𝐜𝐨𝐬𝝓 technique,” Indonesian Journal of Electrical Engineering and Computer Science, vol. 25, no. 1, pp. 1-13, 2022,
doi: 10.11591/ijeecs.v25.i1.pp1-13.

BIOGRAPHIES OF AUTHORS

Abdulkareem Mokif Obais was born in Iraq in 1960. He received his BSc. and
M.Sc. degrees in Electrical Engineering from the University of Baghdad, Baghdad, Iraq, in
1982 and 1987, respectively. He received his PhD degree in Electrical Engineering from
Universiti Tenaga Nasional, Kajang, Malaysia in 2013. He is interested in electronic circuit’s
design and power electronics. He had supervised and examined a number of postgraduate
students. He had published many papers in Iraqi academic and international Journals. Dr.
Obais was promoted to Professor at University of Babylon in April 2008. He can be contacted
at email: [email protected].

Ali Abdulkareem Mukheef was born in Iraq in 1995. He received his BSc. and
M.Sc. degrees from University of Babylon, Iraq in 2016 and 2020, respectively. He is one of
the Academic Staff of Almustaqbal University College, Babylon, Iraq. Presently, he is a PhD
student at University of Babylon, Babylon, Iraq. He can be contacted at email:
[email protected].

Int J Pow Elec & Dri Syst, Vol. 13, No. 3, September 2022: 1922-1950