UNIT IV Digital Modulation

Amplitude Shift Keying :

ASK is a type of Amplitude Modulation which represents the binary data in the form of
variations in the amplitude of a signal.

Any modulated signal has a high frequency carrier. The binary signal when ASK modulated,
gives a zero value for Low input while it gives the carrier output for High input.

The following figure represents ASK modulated waveform along with its input.

To find the process of obtaining this ASK modulated wave, let us learn about the working of the
ASK modulator.

ASK Modulator:

The ASK modulator block diagram comprises of the carrier signal generator, the binary sequence
from the message signal and the band-limited filter. Following is the block diagram of the ASK
Modulator.
The carrier generator, sends a continuous high-frequency carrier. The binary sequence from the
message signal makes the unipolar input to be either High or Low. The high signal closes the
switch, allowing a carrier wave. Hence, the output will be the carrier signal at high input. When
there is low input, the switch opens, allowing no voltage to appear. Hence, the output will be
low.

The band-limiting filter, shapes the pulse depending upon the amplitude and phase
characteristics of the band-limiting filter or the pulse-shaping filter.

ASK Demodulator:

There are two types of ASK Demodulation techniques. They are −

 Asynchronous ASK Demodulation/detection

 Synchronous ASK Demodulation/detection

The clock frequency at the transmitter when matches with the clock frequency at the receiver, it
is known as a Synchronous method, as the frequency gets synchronized. Otherwise, it is known
as Asynchronous.

Asynchronous ASK Demodulator:

The Asynchronous ASK detector consists of a half-wave rectifier, a low pass filter, and a
comparator. Following is the block diagram for the same.
The modulated ASK signal is given to the half-wave rectifier, which delivers a positive half
output. The low pass filter suppresses the higher frequencies and gives an envelope detected
output from which the comparator delivers a digital output.

Synchronous ASK Demodulator:

Synchronous ASK detector consists of a Square law detector, low pass filter, a comparator, and a
voltage limiter. Following is the block diagram for the same.

The ASK modulated input signal is given to the Square law detector. A square law detector is
one whose output voltage is proportional to the square of the amplitude modulated input voltage.
The low pass filter minimizes the higher frequencies. The comparator and the voltage limiter
help to get a clean digital output.

Phase Shift Keying:

PSK is the digital modulation technique in which the phase of the carrier signal is changed by
varying the sine and cosine inputs at a particular time. PSK technique is widely used for wireless
LANs, bio-metric, contactless operations, along with RFID and Bluetooth communications.

PSK is of two types, depending upon the phases the signal gets shifted. They are −
Binary Phase Shift Keying (BPSK):

This is also called as 2-phase PSK or Phase Reversal Keying. In this technique, the sine wave
carrier takes two phase reversals such as 0° and 180°.

BPSK is basically a Double Side Band Suppressed Carrier DSBSC modulation scheme, for
message being the digital information.
Quadrature Phase Shift Keying (QPSK):

This is the phase shift keying technique, in which the sine wave carrier takes four phase reversals
such as 0°, 90°, 180°, and 270°.

If this kind of techniques are further extended, PSK can be done by eight or sixteen values also,
depending upon the requirement.

BPSK Modulator

The block diagram of Binary Phase Shift Keying consists of the balance modulator which has the
carrier sine wave as one input and the binary sequence as the other input. Following is the
diagrammatic representation.

The modulation of BPSK is done using a balance modulator, which multiplies the two signals
applied at the input. For a zero binary input, the phase will be 0° and for a high input, the phase
reversal is of 180°.

Following is the diagrammatic representation of BPSK Modulated output wave along with its
given input.
The output sine wave of the modulator will be the direct input carrier or the
inverted 180°phaseshifted input carrier, which is a function of the data signal.

BPSK Demodulator:

The block diagram of BPSK demodulator consists of a mixer with local oscillator circuit, a
bandpass filter, a two-input detector circuit. The diagram is as follows.

By recovering the band-limited message signal, with the help of the mixer circuit and the band
pass filter, the first stage of demodulation gets completed. The base band signal which is band
limited is obtained and this signal is used to regenerate the binary message bit stream.

In the next stage of demodulation, the bit clock rate is needed at the detector circuit to produce
the original binary message signal. If the bit rate is a sub-multiple of the carrier frequency, then
the bit clock regeneration is simplified. To make the circuit easily understandable, a decision-
making circuit may also be inserted at the 2nd stage of detection.
Quadrature Phase Shift Keying :
QPSK is a variation of BPSK, and it is also a Double Side Band Suppressed
Carrier DSBSC modulation scheme, which sends two bits of digital information at a time, called
as bigits.

Instead of the conversion of digital bits into a series of digital stream, it converts them into bit
pairs. This decreases the data bit rate to half, which allows space for the other users.

QPSK Modulator:

The QPSK Modulator uses a bit-splitter, two multipliers with local oscillator, a 2-bit serial to
parallel converter, and a summer circuit. Following is the block diagram for the same.

At the modulator’s input, the message signal’s even bits (i.e., 2 nd bit, 4th bit, 6th bit, etc.) and odd
bits (i.e., 1st bit, 3rd bit, 5th bit, etc.) are separated by the bits splitter and are multiplied with the
same carrier to generate odd BPSK (called as PSKI) and even BPSK (called as PSKQ).
The PSKQ signal is anyhow phase shifted by 90° before being modulated.

The QPSK waveform for two-bits input is as follows, which shows the modulated result for
different instances of binary inputs.
QPSK Demodulator:

The QPSK Demodulator uses two product demodulator circuits with local oscillator, two band
pass filters, two integrator circuits, and a 2-bit parallel to serial converter. Following is the
diagram for the same.

The two product detectors at the input of demodulator simultaneously demodulate the two BPSK
signals. The pair of bits are recovered here from the original data. These signals after processing,
are passed to the parallel to serial converter.

Frequency Shift Keying:

FSK is the digital modulation technique in which the frequency of the carrier signal varies
according to the digital signal changes. FSK is a scheme of frequency modulation.
The output of a FSK modulated wave is high in frequency for a binary High input and is low in
frequency for a binary Low input. The binary 1s and 0s are called Mark and Space frequencies.
The following image is the diagrammatic representation of FSK modulated waveform along with
its input.

To find the process of obtaining this FSK modulated wave, let us know about the working of a
FSK modulator.

FSK Modulator:

The FSK modulator block diagram comprises of two oscillators with a clock and the input binary
sequence. Following is its block diagram.

The two oscillators, producing a higher and a lower frequency signals, are connected to a switch
along with an internal clock. To avoid the abrupt phase discontinuities of the output waveform
during the transmission of the message, a clock is applied to both the oscillators, internally. The
binary input sequence is applied to the transmitter so as to choose the frequencies according to
the binary input.
FSK Demodulator:

There are different methods for demodulating a FSK wave. The main methods of FSK detection
are asynchronous detector and synchronous detector. The synchronous detector is a coherent
one, while asynchronous detector is a non-coherent one.
Asynchronous FSK Detector:

The block diagram of Asynchronous FSK detector consists of two band pass filters, two
envelope detectors, and a decision circuit. Following is the diagrammatic representation.

The FSK signal is passed through the two Band Pass Filters BPFs, tuned
to Space and Mark frequencies. The output from these two BPFs look like ASK signal, which is
given to the envelope detector. The signal in each envelope detector is modulated
asynchronously.

The decision circuit chooses which output is more likely and selects it from any one of the
envelope detectors. It also re-shapes the waveform to a rectangular one.

Synchronous FSK Detector:

The block diagram of Synchronous FSK detector consists of two mixers with local oscillator
circuits, two band pass filters and a decision circuit. Following is the diagrammatic
representation.

The FSK signal input is given to the two mixers with local oscillator circuits. These two are
connected to two band pass filters. These combinations act as demodulators and the decision
circuit chooses which output is more likely and selects it from any one of the detectors. The two
signals have a minimum frequency separation.

For both of the demodulators, the bandwidth of each of them depends on their bit rate. This
synchronous demodulator is a bit complex than asynchronous type demodulators.
Regenerative Repeaters:

As we are probably aware, pulses passing down a digital transmission line suffer attenuation and
are badly distorted by the frequency characteristic of the line. A regenerative repeater amplifies
and reconstructs such a badly distorted digital signal and develops a nearly perfect replica of the
original at its output. Regenerative repeaters are an essential key to digital transmission in that
we could say that the "noise stops at the repeater."

Figure 6.11 is a simplified block diagram of a regenerative repeater and shows typical
waveforms corresponding to each functional stage of signal processing. As illustrated in the
figure, at the first stage of signal processing is amplification and equalization. With many
regenerative repeaters, equalization is a two-step process. The first is a fixed equalizer that
compensates for the attenuation-frequency characteristic (attenuation distortion), which is caused
by the standard length of transmission line between repeaters (often 6000 ft or 1830 m). The
second equalizer is variable and compensates for departures between nominal repeater section
length and the actual length as well as loss variations due to temperature. The adjustable
equalizer uses automatic line build-out (ALBO) networks that are automatically adjusted
according to characteristics of the received signal.9

The signal output of the repeater must be precisely timed to maintain accurate pulse width and
space between the pulses. The timing is derived from the incoming bit stream. The incoming
signal is rectified and clipped, producing square waves that are applied to the timing extractor,
which is a circuit tuned to the timing frequency. The output of the circuit controls a clock-pulse
generator that produces an output of narrow pulses that are alternately positive and negative at
the zero crossings of the square-wave input.

The narrow positive clock pulses gate the incoming pulses of the regenerator, and the negative
pulses are used to run off the regenerator. Thus the combination is used to control the width of
the regenerated pulses.
Regenerative repeaters are the major source of timing jitter in a digital transmission system. Jitter
is one of the principal impairments in a digital network, giving rise to pulse distortion and
intersymbol interference. Jitter is discussed in more detail in Section 6.9.2.

Figure 6.11 Simplified functional block diagram of a regenerative repeater for use with
PCM cable systems.

Line build-out is the adding of capacitance and/or resistance to a transmission line to look
"electrically" longer or shorter than it actually is physically.

Most regenerative repeaters transmit a bipolar (AMI) waveform (see Figure 6.10). Such signals
can have one of three possible states in any instant in time—positive, zero, or negative (volts)—
and are often designated +, 0, —. The threshold circuits are gates to admit the signal at the
middle of the pulse interval. For instance, if the signal is positive and exceeds a positive
threshold, it is recognized as a positive pulse. If it is negative and exceeds a negative threshold, it
is recognized as a negative pulse. If it has a (voltage) value between the positive and negative
voltage thresholds, it is recognized as a 0 (no pulse).

When either threshold is exceeded, the regenerator is triggered to produce a pulse of the
appropriate duration, polarity, and amplitude. In this manner the distorted input signal is
reconstructed as a new output signal for transmission to the next repeater or terminal facility.