p-ISSN 2083-0157, e-ISSN 2391-6761 IAPGOŚ 4/2024 63

http://doi.org/10.35784/iapgos.6355 received: 29.06.2024 | revised: 21.11.2024 | accepted: 22.11.2024 | available online: 21.12.2024

DSTATCOM-BASED 15 LEVEL ASYMMETRICAL MULTILEVEL

INVERTER FOR IMPROVING POWER QUALITY
Panneerselvam Sundaramoorthi1, Govindasamy Saravana Venkatesh2
1
Periyar Maniammai Institute of Science and Technology, Research Scholar, Thanjavur, India, 2Periyar Maniammai Institute of Science and Technology, Department
of Electrical and Electronics Engineering, Thanjavur, India

Abstract. This study suggests an asymmetric multilevel inverter based on DSTATCOM that employs SVPWM techniques to produce higher output levels.
There are two steps in the suggested inverter. One full bridge and two half bridges make up the inverter's main stage. A full bridge converter had four
switches and a single DC source, while half bridges have separate DC sources with a voltage ratio of 1:3:3. Every cell has a fixed neutral point
and is connected in a cascaded fashion. The inverter's performance is not improved by setting the DC source values equally. A folded cascaded H-bridge
circuit running at a line frequency makes up the second circuit. Control plan PWM's space vector modulation was used to verify the suggested topology.
Each control scheme's specific methodology as well as switching pulses are covered in great detail. In MATLAB/Simulink, the suggested system has been
simulated with an output voltage of 350 V and an output current of roughly 3.5 A.
Keywords: DSTATCOM, THD reduction, PWM scheme, multicarrier PWM scheme, SVPWM scheme

15-POZIOMOWY ASYMETRYCZNY FALOWNIK WIELOPOZIOMOWY OPARTY

NA TECHNOLOGII DSTATCOM POPRAWIAJĄCY JAKOŚĆ ZASILANIA
Streszczenie. W niniejszym opracowaniu zaproponowano asymetryczny falownik wielopoziomowy oparty na DSTATCOM, który wykorzystuje techniki
SVPWM do wytwarzania wyższych poziomów wyjściowych. Proponowany falownik składa się z dwóch stopni. Jeden pełny mostek i dwa półmostki tworzą
główny stopień falownika. Przetwornica z pełnym mostkiem ma cztery przełączniki i pojedyncze źródło prądu stałego, podczas gdy półmostki mają
oddzielne źródła prądu stałego o stosunku napięć 1:3:3. Każde ogniwo ma stały punkt neutralny i jest połączone kaskadowo. Ustawienie jednakowych
wartości źródeł prądu stałego nie poprawia wydajności falownika. Złożony kaskadowy obwód mostka H pracujący z częstotliwością sieciową tworzy drugi
obwód. Do weryfikacji proponowanej topologii wykorzystano modulację wektora przestrzennego PWM. Szczegółowo omówiono metodologię każdego
schematu sterowania, a także impulsy przełączające. W programie MATLAB/Simulink zasugerowany system został zasymulowany przy napięciu
wyjściowym 350 V i prądzie wyjściowym około 3,5 A.
Słowa kluczowe: DSTATCOM, redukcja THD, schemat PWM, schemat PWM z wieloma nośnymi, schemat SVPWM

Introduction method based on SVPWM is provided along with simulation

results. Furthermore, a comparative suggested topology
"Multilevel voltage source inverters had a practical option for and the current topology is provided [4, 8]. The final section
high-power Direct Current to Alternating Current conversion discusses potential changes that could be made to this recently
applications during the past few years" [11]. A Multilevel created MLI. The multilayer inverters' overall harmonic distortion
Converter (MLI) is an apparatus that creates a staircase waveform of voltage. Research indicates that evaluating multilevel voltage
by connecting numerous input DC levels (from capacitors quality might be challenging when dealing with numerically
or DC sources) and power semiconductors. When compared derived voltage THD values, which are susceptible to computation
to traditional inverters, the power switches in MLIs undergo less errors [4, 5]. The smooth hyperbolic voltage THD upper and lower
voltage stress [13]. Furthermore, the harmonic profile bound approximations for closest synchronous switching 1-phase
of the multilevel waveform is superior than that of the two-level and 3-phase inverters are described here. They can be used
waveform derived using traditional inverters. The reduction realistically as good reference values and are valid for uniformly
in voltage stress and the fault-tolerant operation are two added distributed level counts and arbitrary modulation indices. From
advantages of MLIs [14]. Additionally, scientists are investigating that shown for a 3-phase star connected balanced load
how to employ MLIs for less-power applications. By improving with isolated neutral and phase symmetrical modulation, line
the levels improves the quality of the multilayer waveform [9]. and phase voltage THD are nearly the same for multilevel inverter
On the other hand, it negatively impacts a lot of power utilized [2, 10].
semiconductor devices and related gate driver circuits. This tends
to lower system efficiency and dependability while also increasing 1. Design of DSTATCOM based multilevel
system complexity and cost. Therefore, in practical applications
requires a fail in the power switches and gate driver circuits A D-STATCOM, a distributed static compensation device,
for a high resolution waveform. NPC, CHB and FC converters uses a two-level voltage source converter (VSC) to convert
are the topologies for multilevel voltage output that have been a single DC voltage to three-phase AC outputs. It consist
thoroughly researched and made commercially accessible. of a storage device & coupling transformer. The VSC and AC
However, with more output levels comes a increase in power system are connected in parallel, as seen in Figure 1 [1].
switches, conducting at once, and the total cost of the system It serves three main works:
[6, 7]. As a result researchers are still concentrating on finding 1. Regulation of voltage and compensation of reactive power.
new ways to lower the number of components in multilevel 2. Power factor improvement.
topologies. These methods fall into three categories: using 3. The current's harmonics are eliminated.
asymmetric sources with topological modifications, combining
topological modifications with asymmetric source configurations.
Here, a topology with alternating DC sources is devised.
Furthermore, the suggested topology has resemblance to the CHB
topology for symmetric input DC sources. Therefore, in renewable
resources with a significant number of available isolated DC
sources, the topology can serve as a utility interface [1, 3]. It can
be applied to middle order voltage drive application, where
separate battery sources are given by a phase shifting transformer
with numerous secondary windings, which is typically utilized
to reduce line current distortion [12, 15]. For the inverter, a control Fig. 1. Schematic Diagram of a DSTATCOM

artykuł recenzowany/revised paper IAPGOS, 4/2024, 63–70

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2. Asymmetrical cascaded multilevel inverter 2.2. Modes of operation

MLI describes a three-level DC source multilevel inverter Mode 1
here. The actual number of levels in this architecture is determined The output voltage V0 = 0, where zero has 8th voltage level
on how the DC sources are arranged. This innovative topology obtained by operating the device in mode 1. The diodes D1 and D2
is used in my project to achieve the suggested MLI. Thus, fifteen as well as the switches S1 and S3 conduct in order to provide
output voltage levels are generated with this design. This topology this output voltage. There is no current flow in this level; Figure 3
significantly lowers the total number of devices for a given shows the current flow in mode-1 operation.
number of output levels [12].

2.1. Concept and topology

Due to their low THD output voltage wave shape
and decreased voltage stress across power switches, MLIs
are becoming more and more popular these days. On the other
hand, the number of devices increases along with the level.
Here we are providing a revolutionary topology to get maximum
output level with a restricted no of elements. It can produce
an output voltage waveform with 15 levels using this topology.
In the voltage ratio of 1:3:3, is the necessary DC source.
Two cascaded circuits are used in a single-phase hybrid multilevel
topology to provide output voltages. The first circuit, dubbed
the level creation circuit, consists of two diodes and six switches
and is in charge of producing levels in positive polarity. Another
circuit, known as the polarity generation circuit (marked cascaded
circuit), consists of four switches and is in charge of determining
the output voltage's polarity.

Fig. 3. Circulation of current in Mode 1 operation

Mode 2
The resultant voltage, V0 = V1, is obtained by using the fifteen
level inverter in mode 2, where k is the seventh voltage level.
The switches S1 and S2, as well as the diodes D1 and D2, conduct
in order to provide this output voltage. The current flow in mode-2
operation is shown in Figure 4. Way of circulation path
of the current flow is +V1-S1-Q1-LOAD-Q2-D1-D2-S2-V1

Fig. 2. Proposed configuration for 1 phase fifteen level inverter

A construction like this is seen in Figure 2 [10]. It is,

in the conventional sense, a single-phase, 15-level inverter.
The suggested inverter would be implemented with power
switches like MOSFETs. To reach expected voltage level,
this topology consists of 6+4 switches. The switches in the level
generation circuit are S1, S2, S3, S4, S5, and S6, and the switches
Q1, Q2, Q3, and Q4 are depicted in Figure 2. The ON/OFF
switching procedure from 0 to 7k is displayed in Table 1.
Asymmetrical cascade MLI consist of 6 switches in level
generation circuit having three DC source for each bridges, here it
is designed with one H-bridge and two half bridge. In polarity Fig. 4. Current direction in Mode 2 operation
generation circuit it consist of an H-bridge and load [4].
Mode 3
Table 1. ON/OFF switching operation
The fifteen level inverter is operated in mode 3 to produce
State No. VPN SW1 SW2 SW3 SW4 SW5 SW6 the output voltage, V0 = V2–V1, where the sixth voltage level
1 0 1 0 1 0 0 0
2 k 1 1 0 0 0 0
is represented by 3k-k = 2k. This output voltage is created
3 2k 0 0 1 1 1 0 by conducting the switches S3, S4, S5, and D2. Figure 5 depicts
4 3k 1 0 1 0 1 0 the current flow for the mode-3 operation. The present flow
5 4k 1 1 0 0 0 1 pattern is as follows: LOAD-Q2-D2-V2 – +V2-S5-S3-V1-S4-Q1.
6 5k 0 0 1 1 1 1
7 6k 1 0 1 0 1 1
8 7k 1 1 0 0 1 1
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Fig. 5. Flow of current in Mode 3 operation

Fig. 7. Current flow direction in Mode 5 operation

Fig. 6. Current way in Mode 4 operation

Mode 4
Where output voltage V0 = V2, where 3k made as 5th output
level, is obtained by operating the inverter in mode 4. This output Fig. 8. Mode 6 current path operation
voltage is obtained by conducting D2 and the switches S1, S3, S5,
and S3. The current flow in mode-4 operation is shown
in Figure 6. The current flow's trajectory is such that V 2-S5-S3-Q1-
S1-LOAD-Q2-D2-V2.
Mode 5
When V0 = V2+V1, where 4k is the fourth voltage level
of the 15 level inverter, is obtained by operating inverter
in mode 5. This output voltage is obtained by conducting D2
and the switches S1, S2, S6, and S2. The current flow in mode-5
operation is shown in Figure 7. The current flow's route is such
-S6-S1-V2-Q1-LOAD-Q2-D2- and V3.
Mode 6
Where V0 = V3+V2-V1, where 5k as third level the third voltage
level is obtained by using Mode 6 operation. To achieve
this output voltage, conduct the switches S3, S4, S5, and S6.
The current flow in mode-6 operation is shown in Figure 8.
The current flow's trajectory is such that +V3-S6-V2-S5-S3-V1-S4-
Q1-LOAD-Q2-V3. Fig. 9. Current direction in Mode 7 operation

Mode 7 Mode 8
The output voltage V0 = V2+V3, where 3k+3k=6k is the second The output voltage V0 = V1+V2+V3 is obtained by operating
voltage level is obtained by operating the inverter in mode 7. the fifteen level inverter in mode 8, where the first voltage level
To achieve this output voltage, conduct the switches S 1, S3, S5, is represented by the formula k+3k+3k=7k. To achieve this output
and S6. The current flow in mode 7 operation is shown in Figure 9. voltage, conduct the switches S1, S2, S5, and S6. The current flow
The current flow's trajectory is such that +V3-S6-V2-S5-S3-V1-S4- in mode-8 operation is shown in Figure 10. The way of the current
Q1-LOAD-Q2-V3. direction is such that +V1-S1-Q1-LOAD-Q2-V3-S6-V2-S5-S2-V1.
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Fig. 10. Current flow in Mode 8 operation Fig. 12.Current direction in Mode 10 operation

Fig. 11. Current direction in Mode 9 operation Fig. 13. Current direction in Mode 11 operation

Mode 9 Mode 12
By running the inverter in mode 9, one can achieve the output The output voltage V0 = V2+V1, where -4k as twelfth voltage
voltage V0 = V1+V2+V3, where -7k is the ninth voltage level sequence level obtained by operating inverter in mode 12.
of the fifteen level inverter. The switches S1, S2, S5, and S6 This output voltage is obtained by conducting D2 and the switches
must be conducted in order to obtain this output voltage. S1, S2, S6, and S2. The current flow in mode 12 operation is shown
Figure 11 displays the current flow in mode-9 operation. in Figure 14. Current flow follows the following path: +V 3-S6-S1
Current flow follows the following path: +V1-S1-Q3-LOAD-Q4- +V1-V1-S2-Q3+LOAD-Q4-D2-V3.
V3-S6-V2-S5-S2-V1.
Mode 13
Mode 10 The final voltage V0 = V2 is obtained by operating the fifteen
Mode 10 operation is used to obtain output voltage level inverter in mode 13, where -3k represents the 13th voltage
V0 = V2+V3 where -6k is the tenth voltage sequence of the fifteen level. This output voltage is obtained by conducting D2
level. In order to obtain this output voltage the switches S 1, S3, S5 and the switches S1, S3, S5, and S3. The current flow in mode 13
and S6 conducts. Figure 12 depicts the current flow in mode 10 operation is shown in Figure 15. The present flow path
operation. The path of the current flow is such +V3-S6-V2-S5-S3- is as follows: +V2-S5-S3-S1-Q3+LOAD-Q4-D2-V2.
S1-Q3-LOAD-Q4-V3.
Mode 14
Mode 11 The output voltage V0 = V2-V1, where -2k has fourteenth
The output voltage V0 = V3+V2-V1, where -5k has eleventh sequence of voltage in fifteen level inverter, is obtained
voltage level of the 15 level inverter, is obtained by operating by operating the inverter in mode 14. This output voltage
the inverter in mode 11. To achieve this output voltage, conduct is obtained by conducting D2 and the switches S3, S4, and S5.
the switches S3, S4, S5, and S6. The current flow in mode 11 The current flow in mode-14 operation is shown in Figure 16.
operation is shown in Figure 13. +V 3-S6-V2+V2-S5-S3+V1-V1-S4- +V2-S5-S3+V1-V1-S4-Q3+LOAD-Q4-D2-V2 is the current flow
Q3+LOAD-Q4-V3 is the current flow path. channel.
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Fig. 14. Current direction in Mode 12 operation Fig. 17. Current direction in Mode 15 operation

3. Experimental analysis and simulation

3.1. Model of thirteen level inverter using
SVPWM control scheme
To using a multicarrier PWM technique, the current
multilayer inverter structure can be modified. Utilizing
the MATLAB/Simulink tool, a block model of a 1-phase thirteen-
level inverter is created to assess the effectiveness of the current
topology with control scheme. There are three input DC sources
that are used: Edc1 = 40 V, Edc2 = 80 V, and Edc3 = 120 V.
This simulation model includes a power circuit, a pulse generator,
and a modulation control circuit. A voltage of around 240 V
is generated by running the model. Figure 18 displays the 13 level
inverter's entire simulation model.

Fig. 15. Current direction in Mode 13 operation

Fig. 18. Overall Model of single 13 Level InverterModel of fifteen level inverter using
SVPWM control scheme

The control of the suggested structure is represented

by a multi-carrier system with low switching frequency.
The multi-carrier PWM method in a switching device determines
each voltage level by comparing the carrier signal to a reference
signal. However, the several switches in the suggested structure
Fig. 16. Current direction in Mode 14 operation are not independent of each other. Therefore, in contrast to a two-
level inverter, switching requires a suitable modulation. Figure 19
Mode 15 depicts the modulation control method [11–16]. The aggregated
The received voltage V0 = V1 is obtained by operating signal is produced by comparing the signals between carrier
the fifteen level inverter in mode 15, where -k represents and sine wave. "In the output waveform, the aggregated signal
the fifteenth voltage level. The switches S1 and S2, as well "As" has the necessary number of levels. C1, C2, C3, and C4
as the diodes D1 and D2, conduct in order to provide this output are the carrier waveforms above the time axis, and C5, C6, C7,
voltage. The current flow in mode-15 operation is shown and C8 are the carrier waveforms below it". They are utilized
in Figure 17. Current flow follows the following path: to determine the k voltage value of the DC source and to produce
+V1-S1-Q3+LOAD-Q4-D1-D2-S2-V1. the output voltage levels (0 to ±7k).
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Fig. 19. Generation of simulation model of suggested fifteen level inverter

Fig. 20. Simulation Model of Modified Fifteen Level Inverter

The Figure 20 displays the MATLAB Simulink model of a diode bridge rectifier, the stepped down AC voltage
of updated fifteen-level inverter, which includes the multilevel is transformed into DC voltage. The voltage can be maintained
inverter that is being presented. The SVPWM method provides by connecting a voltage regulator to the DC output. Voltage
the gating signals for each switch. V1 = 50 V, V2 = 150 V, regulators L7812cv and L7815 are employed in this instance.
and V3 = 150 V are the input voltages that are provided. Through The controller unit uses the L7812cv regulator, whereas the driver
model simulation, a voltage of ±350 V is produced [3, 12, 15]. circuit uses the L7815 regulator. To supply enough voltage to turn
Figure 21 depicts the hardware portion of the fifteen-level on the MOSFET switches in the multilayer inverter, a driver
multilevel inverter. Power, driver circuit, and controller units circuit is employed. The driver increases the microcontroller's
are all included. Using a step down transformer, the AC input voltage. Additionally, it has an optocoupler for isolation purposes,
from the main supply is reduced in voltage. Through the use preventing MOSFET damage [6, 9].
p-ISSN 2083-0157, e-ISSN 2391-6761 IAPGOŚ 4/2024 69

Fig. 25. Proposed fifteen level output

Fig. 21. Hardware Section

4. Result and discussions

4.1. Thirteen level inverter based on SPWM
control scheme
Figure 22 displays the output waveforms for the 13-level
inverter that is currently in use. This figure displays both Fig. 26. Output voltage THD for proposed fifteen level
the output voltage and the output voltage level that were produced
from the multilayer inverter.

Fig. 22. Thirteen level output

Figures 23 and 24 display the THD for the output voltage

and current, respectively, which are both approximately 28.74%. Fig. 27. Output current THD for proposed fifteen level
The input voltages are S1 = 40V, S2 = 80V, and S3 = 120V,
and the output voltage is ±240V in order to provide 13 levels 4.3. Comparison of existing and modified MLI
at the output.
By Through a comparison of the output waveforms produced
by the modeled systems, we can see that, in comparison
to the current systems, the suggested system yields higher output
voltage levels (15) and lower THDs (10.83%) with fewer
components. Table 2 presents a comparison between the current
and modified MLI [15].
Table 2. Comparative analysis of different MLI

Different
Conventional MLI Proposed MLI
Parameters
E1=40V E1=50V
Fig. 23. Output Voltage THD for 13 Level Source input E2=80V E2=150V
E3=120V E3=150V
Output
±240V ±350V
voltage
Number
13 15
of output level
Output voltage
28.74% 10.83%
value of THD
THD for output
28.74% 10.83%
current
3dc Sources and 11 Switching 3dc Sources and 10
Component count
Devices Switches

5. Experimental results
Fig. 24. Output current THD for thirteen level
The multilayer inverter circuit takes a 40 V or 80 V or 120 V
4.2. 15 level inverter based on SVPWM control battery source as its input. A digital storage oscilloscope was used
scheme to measure the signals from each terminal; the resulting
waveforms are shown below. Figure 28 shows the pulse's output
The waveform in Figure 25 depicts the output of the improved waveform that was generated for the switches, and Figure 29
15-level inverter. shows the prototype with fifteen levels.
Figures 26 and 27 display the THD for the output voltage The improved fifteen-level MLI experimental setup
and current, respectively, and are both approximately 10.83%. with DSO, which produced the 15-level output across load
The input voltage is Vdc1 = 50V, Vdc2 = 150V, and Vdc3 = 150V resistor, as depicted in Figure 30. The controller board, driving
to obtain 15 levels at output. The output voltage is ±350V [5]. circuit, and power circuit make up the experimental setup.
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Fig. 30. Prototype model of fifteen level M.Sc. Panneerselvam Sundaramoorthi

e-mail:[email protected]
With an input of 50 V, 150 V, and 150 V, the produced
He was born in Rajapalayam, Tamil Nadu, India
prototype yields an output voltage of ±350 V, or voltage level on March 17, 1982. He received his B.E. degree from
of fifteen. This developed prototype has fewer components Madurai Kamarajar University in 2003 and his M.E.
and lower total harmonic distortions. degree from Anna University Tirunelveli in 2010.
He is currently employed as an associate professor
in EEE at Kerala, Nehru College of Engineering
6. Conclusion and Research Centre, Thrissur. He has taught for over
18 years and has written in a number of international
A fifteen-level Using MATLAB/Simulink, the simulation journals and conferences. Power quality, multilevel
inverters, and renewable energy systems are among
model for the suggested level multilevel inverter has been
his current research interests. He is an ISTE, SEEM,
constructed and confirmed. To obtain maximum level of output, IAE, and IRED life member.
hence reduction in component count, since MLIs are becoming https://orcid.org/0000-0002-9321-140x
more and more popular. Numerous surveys of MLIs were carried Ph.D. Govindasamy Saravana Venkatesh
out in support of this, and comparisons between various e-mail: [email protected]
topologies were made using the results of those surveys. A unique
multilevel inverter that uses the SVPWM technique can be built He was born in Tirunelveli, Tamil Nadu, India
in 1980. He obtained his B.E. degree from
based on these surveys. Improve the reliability by putting Manonmaniam Sundaranar University in 2002, as well
this strategy into practice. The hardware prototype created as his M.E. and Ph.D. degrees from Anna University
and the hardware result was obtained with the suggested topology. 2004, 2019 respectively. Currently he is working
as assistant professor in Electrical and Electronics
At the end, a comparison between the multilevel inverters Engineering at Thanjavur, Periyar Maniammai
that are now in use and those that are being suggested is done. Institute of Science and Technology. He has been
A hardware prototype was created using the suggested topology, teaching for over 19 years and has written in a number
and hardware outcomes were attained. Lastly, we will contrast of international magazines and conferences. Solar
energy systems, electrical machines, and power
the updated multi-level inverter with the multi-level inverter electronics are his current research interests.
that is currently in place. https://orcid.org/0000-0002-0154-2974