M29F100T

M29F100B
1 Mbit (128Kb x8 or 64Kb x16, Boot Block)
Single Supply Flash Memory
NOT FOR NEW DESIGN

M29F100T and M29F100B are replaced

respectively by the M29F100BT and
M29F100BB.
5V ± 10% SUPPLY VOLTAGE for PROGRAM,
ERASE and READ OPERATIONS
FAST ACCESS TIME: 70ns 44

FAST PROGRAMMING TIME

– 10µs by Byte / 16µs by Word typical
1
PROGRAM/ERASE CONTROLLER (P/E.C.)
TSOP48 (N) SO44 (M)
– Program Byte-by-Byte or Word-by-Word 12 x 20 mm
– Status Register bits and Ready/Busy Output
MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI-BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES Figure 1. Logic Diagram
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
VCC
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION 16 15
– Defectivity below 1ppm/year
A0-A15 DQ0-DQ14
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
W DQ15A–1
– Device Code, M29F100T: 00D0h
M29F100T
– Device Code, M29F100B: 00D1h E M29F100B BYTE

G RB
DESCRIPTION
The M29F100 is a non-volatilememory that may be RP
erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byteor Word-
by-Word basis using only a single 5V VCC supply.
For Program and Erase operations the necessary
high voltages are generated internally. The device VSS
can alsobe programmedin standardprogrammers. AI01974

The array matrix organisation allows each block to

be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment,

July 2000 1/30

Tihs is information on a product still in production but not recommendedfor new design.
M29F100T, M29F100B

Figure 2A. TSOP Pin Connections Figure 2B. TSOP Reverse Pin Connections

A15 1 48 NC NC 1 48 A15
A14 BYTE BYTE A14
A13 VSS VSS A13
A12 DQ15A–1 DQ15A–1 A12
A11 DQ7 DQ7 A11
A10 DQ14 DQ14 A10
A9 DQ6 DQ6 A9
A8 DQ13 DQ13 A8
NC DQ5 DQ5 NC
NC DQ12 DQ12 NC
W DQ4 DQ4 W
RP 12 M29F100T 37 VCC VCC 12 M29F100T 37 RP
M29F100B M29F100B
NC 13 36 DQ11 DQ11 13 36 NC
(Normal) (Reverse)
NC DQ3 DQ3 NC
RB DQ10 DQ10 RB
NC DQ2 DQ2 NC
NC DQ9 DQ9 NC
A7 DQ1 DQ1 A7
A6 DQ8 DQ8 A6
A5 DQ0 DQ0 A5
A4 G G A4
A3 VSS VSS A3
A2 E E A2
A1 24 25 A0 A0 24 25 A1
AI01975 AI01976

Warning: NC = Not Connected. Warning: NC = Not Connected.

Figure 2C. SO Pin Connections Table 1. Signal Names

A0-A15 Address Inputs
NC 1 44 RP
DQ0-DQ7 Data Input/Outputs, Command Inputs
RB 2 43 W
NC 3 42 A8
DQ8-DQ14 Data Input/Outputs
A7 4 41 A9
A6 5 40 A10
DQ15A–1 Data Input/Output or Address Input
A5 6 39 A11
A4 7 38 A12 E Chip Enable
A3 8 37 A13
A2 9 36 A14 G Output Enable
A1 10 35 A15
A0 11 M29F100T 34 NC W Write Enable
E 12 M29F100B 33 BYTE
VSS 13 32 VSS RP Reset / Block Temporary Unprotect
G 14 31 DQ15A–1
DQ0 15 30 DQ7 RB Ready/Busy Output
DQ8 16 29 DQ14
DQ1 17 28 DQ6 BYTE Byte/Word Organisation
DQ9 18 27 DQ13
DQ2 19 26 DQ5 VCC Supply Voltage
DQ10 20 25 DQ12
DQ3 21 24 DQ4 VSS Ground
DQ11 22 23 VCC
AI01977

Warning: NC = Not Connected.

2/30
 M29F100T, M29F100B

Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit
(3)
TA Ambient Operating Temperature –40 to 125 °C
TBIAS Temperature Under Bias –50 to 125 °C
TSTG Storage Temperature –65 to 150 °C
(2)
VIO Input or Output Voltages –0.6 to 7 V
VCC Supply Voltage –0.6 to 7 V
(2)
V(A9, E, G, RP) A9, E, G, RP Voltage –0.6 to 13.5 V
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltagemay undershoot to –2V during transition and for less than 20ns.
3. Depends on range.

DESCRIPTION (Cont’d) DQ2 provide Toggle signals to indicate the state of

the P/E.C operations. A Ready/Busy RB output
and temporarily unprotected to make changes in indicates the completion of the internal algorithms.
the application. Each block can be programmed
and erased over 100,000 cycles. Memory Blocks
Instructionsfor Read/Reset,Auto Select for reading The devices feature asymmetrically blocked archi-
the Electronic Signature or Block Protection status, tecture providing system memory integration.Both
Programming, Block and Chip Erase, Erase Sus- M29F100T and M29F100B devices have an array
pend and Resume are written to the device in of 5 blocks, one Boot Block of 16 KBytes or 8
cycles of commandsto a CommandInterface using KWords, two Parameter Blocks of 8 KBytes or 4
standard microprocessor write timings. KWords, one Main Block of 32 KBytes or 16
KWords and one Main Blocks of 64 KBytes or 32
The device is offered in TSOP48 (12 x 20mm) and KWords. The M29F100T has the Boot Block at the
SO44 packages.Both normal and reverse pinouts top of the memory address space and the
are available for the TSOP48 package. M29F100B locates the Boot Block starting at the
Organisation bottom.The memory maps are showed in Figure 3.
Each block can be erased separately, any combi-
The M29F100 is organised as 128Kb x8 or 64Kb nation of blocks can be specified for multi-block
x16 bits selectable by the BYTE signal.WhenBYTE erase or the entire chip may be erased.The Erase
is Low the Byte-wide x8 organisation is selected operations are managed automatically by the
and the address lines are DQ15A–1 and A0-A15. P/E.C. The block erase operation can be sus-
The Data Input/Output signal DQ15A–1 acts as pended in order to read from or program to any
address line A–1 which selects the lower or upper block not being ersased, and then resumed.
Byte of the memory word for output on DQ0-DQ7,
DQ8-DQ14 remain at High impedance. When Block protection provides additional data security.
BYTE is High the memory uses the address inputs Each block can be separately protected or unpro-
A0-A15 and the Data Input/Outputs DQ0-DQ15. tected against Program or Erase on programming
Memory control is provided by Chip Enable E, equipment.All previously protected blocks can be
Output Enable G and Write Enable W inputs. temporarily unprotected in the application.
A Reset/BlockTemporary Unprotection RPtri-level Bus Operations
input provides a hardware reset when pulled Low, The following operations can be performed using
and when held High (at VID) temporarily unprotects the appropriate bus cycles: Read (Array, Electronic
blocks previously protected allowing them to be Signature, Block Protection Status), Write com-
programed and erased.Erase and Program opera- mand, Output Disable, Standby, Reset, Block Pro-
tions are controlled by an internal Program/Erase t e ct io n , Un p ro t e ct ion , P ro t ec t ion Ve rif y,
Controller (P/E.C.). Status Register data output on UnprotectionVerify and Block TemporaryUnprotec-
DQ7 provides a Data Polling signal, and DQ6 and tion. See Tables 4 and 5.

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M29F100T, M29F100B

Figure 3. Memory Map and Block Address Table (x8)

M29F100T M29F100B

1FFFFh 1FFFFh
16K BOOT BLOCK 64K MAIN BLOCK
1C000h 10000h
1BFFFh 0FFFFh
8K PARAMETER BLOCK 32K MAIN BLOCK
1A000h 08000h
19FFFh 07FFFh
8K PARAMETER BLOCK 8K PARAMETER BLOCK
18000h 06000h
17FFFh 05FFFh
32K MAIN BLOCK 8K PARAMETER BLOCK
10000h 04000h
0FFFFh 03FFFh
64K MAIN BLOCK 16K BOOT BLOCK
00000h 00000h

AI01978

Table 3A. M29F100T Block Address Table

Address Range (x8) Address Range (x16) A15 A14 A13 A12

00000h-0FFFFh 0000h-7FFFh 0 X X X

10000h-17FFFh 8000h-BFFFh 1 0 X X

18000h-19FFFh C000h-CFFFh 1 1 0 0

1A000h-1BFFFh D000h-DFFFh 1 1 0 1

1C000h-1FFFFh E000h-FFFFh 1 1 1 X

Table 3B. M29F100B Block Address Table

Address Range (x8) Address Range (x16) A15 A14 A13 A12

00000h-03FFFh 0000h-1FFFh 0 0 0 X

04000h-05FFFh 2000h-2FFFh 0 0 1 0

06000h-07FFFh 3000h-3FFFh 0 0 1 1

08000h-0FFFFh 4000h-7FFFh 0 1 X X

10000h-1FFFFh 8000h-FFFFh 1 X X X

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 M29F100T, M29F100B

Command Interface When A9 is raised to VID, either a Read Electronic

Instructions, made up of commands written in cy- SignatureManufactureror Device Code, Block Pro-
cles, can be given to the Program/Erase Controller tection Status or a Write Block Protection or Block
through a Command Interface (C.I.). For added Unprotection is enabled depending on the combi-
data protection, program or erase execution starts nation of levels on A0, A1, A6, A12 and A15.
after 4 or 6 cycles.The first, second, fourth and fifth Data Input/Outputs (DQ0-DQ7). T he s e I n-
cycles are used to input Coded cycles to the C.I. puts/Outputsare used in the Byte-wide and Word-
This Coded sequence is the same for all Pro- wide organisations. The input is data to be
gram/EraseControllerinstructions.The’Command’ programmed in the memory array or a command to
itself and its confirmation, when applicable, are be written to the C.I. Both are latched on the rising
given on the third, fourth or sixth cycles. Any incor- edge of Chip Enable E or Write Enable W. The
rect command or any improper command se- output is data from the Memory Array, the Electronic
quence will reset the device to Read Array mode. SignatureManufacturer or Device codes, the Block
Instructions ProtectionStatusor the Status register Data Polling
bit DQ7, the ToggleBits DQ6 and DQ2, the Error bit
Seven instructions are defined to perform Read DQ5 or the Erase Timer bit DQ3. Outputs are valid
Array, Auto Select (to read the Electronic Signature when Chip Enable E and Output Enable G are
or Block Protection Status), Program, Block Erase, active.The output is high impedance when the chip
Chip Erase, Erase Suspend and Erase Resume. is deselectedor the outputs are disabled and when
The internal P/E.C.automaticallyhandlesall timing RP is at a Low level.
and verification of the Program and Erase opera-
tions. The Status Register Data Polling, Toggle, Data Input/Outputs (DQ8-DQ14 and DQ15A–1).
Error bits and the RB output may be read at any These Inputs/Outputs are additionally used in the
time, during programming or erase, to monitor the Word-wide organisation.When BYTE is High DQ8-
progress of the operation. DQ14 and DQ15A–1 act as the MSB of the Data
Input or Output, functioning as described for DQ0-
Instructions are composed of up to six cycles. The DQ7 above, and DQ8-DQ15 are ’don’t care’ for
first two cycles input a Coded sequence to the command inputs or status outputs.When BYTE is
Command Interfacewhich is common to all instruc- Low, DQ8-DQ14 are high impedance,DQ15A–1 is
tions (see Table 8). The third cycle inputs the in- the Address A–1 input.
struction set-up command. Subsequent cycles
output the addressed data, Electronic Signature or Chip Enable (E). The Chip Enable input activates
Block Protection Status for Read operations. In the memory control logic, input buffers, decoders
order to give additional data protection,the instruc- and sense amplifiers.E High deselects the memory
tions for Program and Block or Chip Erase require and reduces the power consumptionto the standby
further command inputs.For a Program instruction, level. E can also be used to control writing to the
the fourth command cycle inputs the address and command register and to the memory array, while
data to be programmed. For an Erase instruction W remains at a low level. The Chip Enable must be
(Block or Chip), the fourth and fifth cycles input a forced to VID during the Block Unprotection opera-
further Coded sequence before the Erase confirm tion.
command on the sixth cycle. Erasure of a memory Output Enable (G). The Output Enable gates the
block may be suspended,in order to read data from outputs through the data buffers during a read
another block or to program data in another block, operation. When G is High the outputs are High
and then resumed. impedance. G must be forced to VID level during
When power is first applied or if VCC falls below Block Protection and Unprotection operations.
VLKO, the command interface is reset to Read Array. Write Enable (W). This input controlswriting to the
Command Register and Addressand Data latches.
Byte/Word Organization Select (BYTE). The
SIGNAL DESCRIPTIONS BYTE input selects the output configuration for the
device: Byte-wide (x8) mode or Word-wide (x16)
See Figure 1 and Table 1. mode. When BYTE is Low, the Byte-wide mode is
Address Inputs (A0-A15). The address inputs for selected and the data is read and programmed on
the memory array are latched during a write opera- DQ0-DQ7. In this mode, DQ8-DQ14 are at high
tion on the falling edge of Chip Enable E or Write impedance and DQ15A–1 is the LSB address.
Enable W. In Word-wide organisation the address When BYTE is High, the Word-wide mode is se-
lines are A0-A15, in Byte-wide organisation lected and the data is read and programmed on
DQ15A–1 acts as an additional LSB address line. DQ0-DQ15.

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M29F100T, M29F100B

Ready/Busy Output (RB). Ready/Busy is an Output Disable. The data outputs are high imped-
open-drain output and gives the internal state of the ance when the Output Enable G is High with Write
P/E.C.of the device.When RB is Low, the device is Enable W High.
Busy with a Program or Erase operation and it will Standby. The memory is in standby when Chip
not acceptany additional program or erase instruc- Enable E is High and the P/E.C. is idle. The power
tions except the Erase Suspend instruction. When consumption is reduced to the standby level and
RB is High, the device is ready for any Read, the outputsare high impedance,independentof the
Program or Erase operation. The RB will also be Output Enable G or Write Enable W inputs.
High when the memory is put in Erase Suspend or
Standby modes. Automatic Standby. After 150ns of bus inactivity
and when CMOS levels are driving the addresses,
Reset/Block Temporary Unprotect Input (RP). the chip automatically enters a pseudo-standby
The RP Input provides hardware reset and pro- mode where consumptionis reduced to the CMOS
tected block(s) temporary unprotection functions. standby value, while outputs still drive the bus.
Reset of the memory is acheived by pulling RP to
VIL for at least 500ns.When the resetpulse is given, Electronic Signature. Two codes identifying the
if the memory is in Read or Standby modes, it will manufacturer and the device can be read from the
be available for new operations in 50ns after the memory.The manufacturer’scode for STMicroelec-
rising edge of RP. If the memory is in Erase, Erase tronics is 20h, the device code is D0h for the
Suspend or Program modes the resetwill take 10µs M29F100T (Top Boot) and D1h for the M29F100B
during which the RB signal will be held at VIL. The (Bottom Boot). These codes allow programming
end of the memory reset will be indicated by the equipment or applications to automatically match
rising edge of RB. A hardware reset during an their interface to the characteristics of the
Erase or Program operation will corrupt the data M29F100. The Electronic Signature is output by a
being programmed or the sector(s) being erased. Read operation when the voltage applied to A9 is
at VID and address input A1 is Low. The manufac-
Temporary block unprotection is made by holding turer code is output when the Address input A0 is
RP at VID. In this condition previously protected Low and the device code when this input is High.
blocks can be programmed or erased. The transi- Other Address inputs are ignored. The codes are
tion of RP from VIH to VID must slower than 500ns. output on DQ0-DQ7.
When RP is returned from VID to VIH all blocks
temporarily unprotected will be again protected. The Electronic Signature can also be read, without
raising A9 to VID, by giving the memory the Instruc-
VCC Supply Voltage. The power supply for all op- tion AS. If the Byte-wide configuration is selected
erations (Read, Program and Erase). the codes are output on DQ0-DQ7 with DQ8-DQ14
VSS Ground. VSS is the reference for all voltage at High impedance; if the Word-wide configuration
measurements. is selected the codes are output on DQ0-DQ7 with
DQ8-DQ15 at 00h.
Block Protection. Each block can be separately
DEVICE OPERATIONS protected against Program or Erase on program-
See Tables 4, 5 and 6. ming equipment. Block protection provides addi-
tional data security, as it disables all program or
Read. Read operations are used to output the con- erase operations.This mode is activatedwhen both
tentsof the Memory Array,the ElectronicSignature, A9 and G are raised to VID and an address in the
the Status Register or the Block Protection Status. block is applied on A12-A15.The Block Protection
Both Chip Enable E and Output Enable G must be algorithm is shown in Figure 14.Block protection is
low in order to read the output of the memory. initiated on the edge of W falling to VIL. Then after
Write. Write operationsare used to give Instruction a delay of 100µs, the edge of W rising to VIH ends
Commands to the memory or to latch input data to the protection operations. Block protection verify is
be programmed.A write operation is initiated when achievedby bringing G, E, A0 and A6 to VIL and A1
Chip Enable E is Low and Write Enable W is Low to VIH, while W is at VIH and A9 at VID. Under these
with Output Enable G High. Addresses are latched conditions, reading the data output will yield 01h if
on the falling edge of W or E whichever occurs last. the block defined by the inputs on A12-A15 is
Commandsand InputData are latched on the rising protected. Any attempt to program or erase a pro-
edge of W or E whichever occurs first. tected block will be ignored by the device.

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 M29F100T, M29F100B

Table 4. User Bus Operations (1)

DQ15 DQ8-
Operation E G W RP BYTE A0 A1 A6 A9 A12 A15 DQ0-DQ7
A–1 DQ14
Data Data Data
Read Word VIL VIL VIH VIH VIH A0 A1 A6 A9 A12 A15
Output Output Output
Address Data
Read Byte VIL VIL VIH VIH VIL A0 A1 A6 A9 A12 A15 Hi-Z
Input Output
Data
Write Word VIL VIH VIL VIH VIH A0 A1 A6 A9 A12 A15 Data Input Data Input
Input

Write Byte VIL VIH VIL VIH VIL A0 A1 A6 A9 A12 A15 Address Hi-Z Data
Input Input
Output Disable VIL VIH VIH VIH X X X X X X X Hi-Z Hi-Z Hi-Z
Standby VIH X X VIH X X X X X X X Hi-Z Hi-Z Hi-Z
Reset X X X VIL X X X X X X X Hi-Z Hi-Z Hi-Z
Block
Protection(2,4) VIL VID VIL Pulse VIH X X X X VID X X X X X

Blocks
VID VID VIL Pulse VIH X X X X VID VIH VIH X X X
Unprotection(4)
Block Block
Protection VIL VIL VIH VIH X VIL VIH VIL VID A12 A15 X X Protect
Verify(2,4) Status (3)
Block Block
Unprotection VIL VIL VIH VIH X VIL VIH VIH VID A12 A15 X X Protect
(2,4) (3)
Verify Status
Block
Temporary X X X VID X X X X X X X X X X
Unprotection
Notes: 1. X = VIL or VIH
2. Block Address must be given on A12-A15 bits.
3. See Table 6.
4. Operation performed on programming equipment.

Table 5. Read Electronic Signature (following AS instruction or with A9 = VID)

Other DQ15 DQ8 - DQ0 -
Org. Code Device E G W BYTE A0 A1
Addresses A–1 DQ14 DQ7
Manufact.
VIL VIL VIH VIH VIL VIL Don’t Care 0 00h 20h
Word- Code
wide M29F100T VIL VIL VIH VIH VIH VIL Don’t Care 0 00h D0h
Device
Code
M29F100B VIL VIL VIH VIH VIH VIL Don’t Care 0 00h D1h
Manufact. Don’t
VIL VIL VIH VIL VIL VIL Don’t Care Hi-Z 20h
Code Care
Byte-
Don’t
wide M29F100T VIL VIL VIH VIL VIH VIL Don’t Care Hi-Z D0h
Device Care
Code
Don’t
M29F100B VIL VIL VIH VIL VIH VIL Don’t Care Hi-Z D1h
Care

Table 6. Read Block Protection with AS Instruction

Other
Code E G W A0 A1 A12 - A15 DQ0 - DQ7
Addresses
Protected Block VIL VIL VIH VIL VIH Block Address Don’t Care 01h
Unprotected Block VIL VIL VIH VIL VIH Block Address Don’t Care 00h

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M29F100T, M29F100B

Block Temporary Unprotection. Any previously Any read attempt during Program or Erase com-
protected block can be temporarily unprotected in mand execution will automatically output these five
order to change stored data.The temporary unpro- Status Register bits. The P/E.C. automatically sets
tection mode is activated by bringing RP to VID. bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits
During the temporary unprotection mode the pre- (DQ0, DQ1 and DQ4) are reserved for future use
viously protected blocks are unprotected. A block and should be masked. See Tables 9 and 10.
can be selected and data can be modified by exe- Data Polling Bit (DQ7). When Programming op-
cuting the Erase or Programinstruction with the RP erations are in progress, this bit outputs the com-
signal held at VID. When RP is returned to VIH, all plement of the bit being programmed on DQ7.
the previouslyprotectedblocksare again protected. During Erase operation, it outputs a ’0’. After com-
pletion of the operation, DQ7 will output the bit last
Block Unprotection. All protected blocks can be programmed or a ’1’ after erasing. Data Polling is
unprotected on programming equipment to allow valid and onlyeffectiveduring P/E.C.operation,that
updating of bit contents. All blocks must first be is after the fourth W pulse for programming or after
protected before the unprotection operation. Block the sixth W pulse for erase.It must be performed at
unprotection is activated when A9, G and E are at the address being programmed or at an address
VID and A12, A15 at VIH. The Block Unprotection within the block being erased. If all the blocks se-
algorithm is shown in Figure 15. Unprotection is lected for erasure are protected, DQ7 will be set to
initiated by the edge of W falling to VIL.After a delay ’0’ for about 100µs, and then return to the previous
of 10ms,the unprotectionoperationwill end.Unpro- addressed memory data value. See Figure 11 for
tection verify is achieved by bringing G and E to VIL the Data Polling flowchart and Figure 10 for the
while A0 is at VIL, A6 and A1 are at VIH and A9 Data Polling waveforms. DQ7 will also flag the
remains at VID. In these conditions, reading the Erase Suspend mode by switching from ’0’ to ’1’ at
output data will yield 00h if the block defined by the the start of the Erase Suspend. In order to monitor
inputs A12-A15 has been succesfully unprotected. DQ7 in the EraseSuspend mode an address within
Each block must be separatelyverified by giving its a block being erased must be provided.For a Read
address in order to ensure that it has been unpro- Operationin Erase Suspendmode, DQ7 will output
tected. ’1’ if the read is attempted on a block being erased
and the data value on other blocks.During Program
operation in Erase Suspend Mode, DQ7 will have
INSTRUCTIONS AND COMMANDS the same behaviour as in the normal program
The Command Interfacelatches commandswritten execution outside of the suspend mode.
to the memory. Instructions are made up from one
or more commandsto perform ReadMemory Array,
Read Electronic Signature, Read Block Protection,
Program,Block Erase, Chip Erase, Erase Suspend
and Erase Resume. Commands are made of ad- Table 7. Commands
dress and data sequences.The instructionsrequire
from 1 to 6 cycles, the first or first three of which are Hex Code Command
always write operations used to initiate the instruc-
tion.They are followed by either further write cycles 00h Invalid/Reserved
to confirm the first command or execute the com- 10h Chip Erase Confirm
mand immediately.Command sequencing must be
followed exactly. Any invalid combination of com- 20h Reserved
mands will reset the device to Read Array. The
increased number of cycles has been chosen to 30h Block Erase Resume/Confirm
assure maximum data security. Instructions are 80h Set-up Erase
initialised by two initial Coded cycles which unlock
the Command Interface. In addition, for Erase, in- 90h
Read Electronic Signature/
struction confirmation is again preceded by the two Block Protection Status
Coded cycles. A0h Program
Status Register Bits
B0h Erase Suspend
P/E.C.status is indicated during execution by Data
Polling on DQ7, detection of Toggle on DQ6 and F0h Read Array/Reset
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.

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 M29F100T, M29F100B

Table 8. Instructions (1)

Mne. Instr. Cyc. 1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.
(3,7)
Addr. X
1+ Read Memory Array until a new write cycle is initiated.
(2,4) Read/Reset Data F0h
RD Memory Array
Byte AAAAh 5555h AAAAh
Addr. (3,7) Read Memory Array until a new write cycle
3+ is initiated.
Word 5555h 2AAAh 5555h

Data AAh 55h F0h

Byte AAAAh 5555h AAAAh Read Electronic Signature or Block

Addr. (3,7)
AS (4) Auto Select 3+ Protection Status until a new write cycle is
Word 5555h 2AAAh 5555h initiated. See Note 5 and 6.
Data AAh 55h 90h

Byte AAAAh 5555h AAAAh Program

Addr. (3,7)
Address Read Data Polling or Toggle Bit
PG Program 4 Word 5555h 2AAAh 5555h until Program completes.
Program
Data AAh 55h A0h Data

Byte AAAAh 5555h AAAAh AAAAh 5555h Block Additional

Addr. (3,7)
BE Block Erase 6 Address Block (8)
Word 5555h 2AAAh 5555h 5555h 2AAAh

Data AAh 55h 80h AAh 55h 30h 30h

Byte AAAAh 5555h AAAAh AAAAh 5555h AAAAh

Addr. (3,7)
CE Chip Erase 6 Note 9
Word 5555h 2AAAh 5555h 5555h 2AAAh 5555h

Data AAh 55h 80h AAh 55h 10h

(3,7)
Erase Addr. X Read until Toggle stops, then read all the data needed from any
ES (10) 1
Suspend Block(s) not being erased then Resume Erase.
Data B0h

Erase Addr. (3,7) X Read Data Polling or Toggle Bits until Erase completes or Erase is
ER 1
Resume suspended another time
Data 30h
Notes: 1. Commands not interpreted in this table will default to read array mode.
2. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode
before starting any new operation (see Table 14 and Figure 9).
3. X = Don’t Care.
4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after
the command cycles.
5. Signature Address bits A0, A1 at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1 at VIL will output
Device code.
6. Block Protection Address: A0 at VIL, A1 at VIH and A12-A15 within the Block will output the Block Protection status.
7. For Coded cycles address inputs A15 is don’t care.
8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry,
timeout status can be verified through DQ3 value (see Erase Timer Bit DQ3 description).
When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.
9. Read Data Polling, Toggle bits or RB until Erase completes.
10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.

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M29F100T, M29F100B

Table 9. Status Register Bits

DQ Name Logic Level Definition Note

Erase Complete or erase

’1’
block in Erase Suspend
Indicates the P/E.C.status, check during
Data ’0’ Erase On-going Program or Erase, and on completion
7
Polling before checking bits DQ5 for Program or
Program Complete or data Erase Success.
DQ of non erase block during
Erase Suspend

DQ Program On-going
’-1-0-1-0-1-0-1-’ Erase or Program On-going Successive reads output complementary
data on DQ6 while Programming or Erase
DQ Program Complete operations are on-going. DQ6 remains at
6 Toggle Bit
constant level when P/E.C. operations are
Erase Complete or Erase completed or Erase Suspend is
’-1-1-1-1-1-1-1-’ Suspend on currently acknowledged.
addressed block

’1’ Program or Erase Error This bit is set to ’1’ in the case of
5 Error Bit
Programming or Erase failure.
’0’ Program or Erase On-going
4 Reserved
P/E.C. Erase operation has started. Only
’1’ Erase Timeout Period Expired possible command entry is Erase
Erase Suspend (ES).
3
Time Bit
Erase Timeout Period An additional block to be erased in parallel
’0’
On-going can be entered to the P/E.C.
Chip Erase, Erase or Erase
Suspend on the currently
addressed block.
’-1-0-1-0-1-0-1-’
Erase Error due to the
currently addressed block
(when DQ5 = ’1’). Indicates the erase status and allows to
2 Toggle Bit
identify the erased block
Program on-going, Erase
1 on-going on another block or
Erase Complete

Erase Suspend read on

DQ
non Erase Suspend block
1 Reserved
0 Reserved
Notes: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.

Toggle Bit (DQ6). When Programming or Erasing Erase. If the blocks selected for erasure are pro-
operations are in progress, successive attempts to tected, DQ6 will toggle for about 100µs and then
read DQ6 will output complementary data.DQ6 will return back to Read.DQ6 will be set to ’1’ if a Read
toggle following toggling of either G, or E when G operationis attemptedon an EraseSuspend block.
is low. The operation is completed when two suc- When erase is suspended DQ6 will toggle during
cessive reads yield the same output data. The next programming operations in a block different to the
read will output the bit last programmedor a ’1’after block in Erase Suspend.Either E or G toggling will
erasing. The toggle bit DQ6 is valid only during cause DQ6 to toggle. See Figure 12 for Toggle Bit
P/E.C. operations, that is after the fourth W pulse flowchart and Figure 13 for Toggle Bit waveforms.
for programming or after the sixth W pulse for

10/30
 M29F100T, M29F100B

Table 10. Polling and Toggle Bits During the second cycle the Coded cycles consist
of writing the data 55h at address 5555h in the
Mode DQ7 DQ6 DQ2 Byte-wide configuration and at address 2AAAh in
Program DQ7 Toggle 1 the Word-wide configuration.In the Byte-wide con-
figuration the address lines A–1 to A14 are valid, in
Erase 0 Toggle Note 1 Word-wide A0 to A14 are valid, other address lines
are ’don’t care’. The Coded cycles happen on first
Erase Suspend Read
(in Erase Suspend 1 1 Toggle and second cycles of the command write or on the
block) fourth and fifth cycles.
Instructions
Erase Suspend Read
(outside Erase Suspend DQ7 DQ6 DQ2 See Table 8.
block) Read/Reset (RD) Instruction. The Read/Reset
Erase Suspend Program DQ7 Toggle N/A instruction consists of one write cycle giving the
command F0h. It can be optionally precededby the
Note: 1. Toggle if the address is within a block being erased. two Coded cycles.Subsequentread operationswill
’1’ if the address is within a block not being erased.
read the memory array addressed and output the
data read. A wait state of 10µs is necessary after
Toggle Bit (DQ2). This toggle bit, together with Read/Reset prior to any valid read if the memory
DQ6, can be used to determine the device status was in an Erase mode when the RD instruction is
during the Erase operations.It can also be used to given.
identify the block being erased. During Erase or Auto Select (AS) Instruction. This instruction
Erase Suspend a read from a block being erased uses the two Coded cycles followed by one write
will cause DQ2 to toggle. A read from a block not cycle giving the command 90h to address AAAAh
being erased will set DQ2 to ’1’ during erase and to in the Byte-wide configuration or address 5555h in
DQ2 during Erase Suspend. During Chip Erase a the Word-wide configuration for command set-up.
read operation will cause DQ2 to toggle as all A subsequent read will output the manufacturer
blocksare being erased.DQ2 will be set to’1’during code and the device code or the block protection
program operation and when erase is complete. status depending on the levels of A0 and A1. The
After erase completion and if the error bit DQ5 is manufacturer code, 20h, is output when the ad-
set to ’1’, DQ2 will toggle if the faulty block is dresses lines A0 and A1 are Low, the device code,
addressed. D0h for Top Boot, D1h for Bottom Boot is output
when A0 is High with A1 Low.
Error Bit (DQ5). This bit is set to ’1’ by the P/E.C.
when thereis a failureof programming, blockerase, The AS instruction also allows access to the block
or chip erase that results in invalid data in the protectionstatus.After giving the AS instruction,A0
memory block.In case of an error in block erase or is set to VIL with A1 at VIH, while A12-A15 define the
program, the block in which the error occured or to address of the block to be verified. A read in these
which the programmed data belongs, must be dis- conditions will output a 01h if the block is protected
carded. The DQ5 failure condition will also appear and a 00h if the block is not protected.
if a user tries to program a ’1’ to a location that is Program (PG) Instruction. This instruction uses
previouslyprogrammed to ’0’.Other Blocks may still four write cycles. Both for Byte-wide configuration
be used. The error bit resets after a Read/Reset and for Word-wide configuration. The Program
(RD) instruction.In case of success of Program or command A0h is written to address AAAAh in the
Erase, the error bit will be set to ’0’ . Byte-wide configuration or to address 5555h in the
Word-wide configurationon the third cycle after two
Erase Timer Bit (DQ3). This bit is set to ’0’ by the Coded cycles. A fourth write operation latches the
P/E.C. when the last block Erase command has Address on the falling edge of W or E and the Data
been entered to the Command Interface and it is to be writtenon the rising edge andstarts the P/E.C.
awaiting the Erase start. When the erase timeout Read operations output the Status Register bits
period is finished, after 80µs to 120µs, DQ3 returns after the programming has started. Memory pro-
to ’1’. gramming is made only by writing ’0’ in place of ’1’.
Coded Cycles Status bits DQ6 and DQ7 determine if program-
ming is on-going and DQ5 allows verification of any
The two Coded cycles unlock the Command Inter- possible error. Programming at an address not in
face. They are followed by an input command or a blocks being erased is also possible during erase
confirmation command. The Coded cycles consist suspend. In this case, DQ2 will toggle at the ad-
of writing the data AAh at address AAAAh in the dress being programmed.
Byte-wide configuration and at address 5555h in
the Word-wide configuration during the first cycle.

11/30
M29F100T, M29F100B

Table 11. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 10ns

Input Pulse Voltages 0 to 3V 0.45V to 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 4. AC Testing Input Output Waveform Figure 5. AC Testing Load Circuit

1.3V
High Speed

3V 1N914

1.5V

0V 3.3kΩ

DEVICE
Standard UNDER OUT
TEST
2.4V CL
2.0V

0.8V
0.45V
CL = 30pF for High Speed
AI01275B
CL = 100pF for Standard
CL includes JIG capacitance AI01276B

Table 12. Capacitance (1) (TA = 25 °C, f = 1 MHz )

Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 12 pF
Note: 1. Sampled only, not 100% tested.

Block Erase (BE) Instruction. This instruction additional Erase Confirm commands for other
uses a minimum of six write cycles. The Erase blocks must be given within this delay. The input of
Set-up command 80h is written to address AAAAh a new Erase Confirm command will restart the
in the Byte-wide configuration or address 5555h in timeout period. The status of the internal timer can
the Word-wide configuration on third cycle after the be monitored through the level of DQ3, if DQ3 is ’0’
two Coded cycles. The Block Erase Confirm com- the Block Erase Command has been given and the
mand 30h is similarlywritten on the sixth cycle after timeout is running, if DQ3 is ’1’, the timeout has
another two Coded cycles. During the input of the expired and the P/E.C.is erasing the Block(s).If the
second command an address within the block to be second command given is not an erase confirm or
erased is given and latched into the memory. Addi- if the Coded cycles are wrong, the instruction
tional block Erase Confirm commands and block aborts, and the device is reset to Read Array. It is
addresses can be written subsequently to erase not necessary to program the block with 00h as the
other blocks in parallel, without further Coded cy- P/E.C.will do this automaticallybefore to erasing to
cles. The erase will start after the erase timeout FFh. Read operations after the sixth rising edge of
period(see EraseTimer BitDQ3 description).Thus, W or E output the status register status bits.

12/30
 M29F100T, M29F100B

Table 13. DC Characteristics

(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C; VCC = 5V ± 10%)

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Current (Read) TTL Byte E = VIL, G = VIH, f = 6MHz 20 mA

ICC1 Supply Current (Read) TTL Word E = VIL, G = VIH, f = 6MHz 20 mA

ICC2 Supply Current (Standby) TTL E = VIH 1 mA

ICC3 Supply Current (Standby) CMOS E = VCC ± 0.2V 100 µA

Byte program, Block or

ICC4 (1) Supply Current (Program or Erase) 20 mA
Chip Erase in progress

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2 VCC + 0.5 V

VOL Output Low Voltage IOL = 5.8mA 0.45 V

Output High Voltage TTL IOH = –2.5mA 2.4 V

VOH
Output High Voltage CMOS IOH = –100µA VCC –0.4V V

VID A9 Voltage (Electronic Signature) 11.0 12.0 V

IID A9 Current (Electronic Signature) A9 = VID 100 µA

Supply Voltage (Erase and

VLKO 3.2 4.2 V
Program lock-out)
Note: 1. Sampled only, not 100% tested.

During the executionof the erase by the P/E.C., the configurationon the third cycle after the two Coded
memory accepts only the Erase Suspend ES and cycles. The Chip Erase Confirm command 10h is
Read/Reset RD instructions. Data Polling bit DQ7 similarly written on the sixth cycle after another two
returns ’0’ while the erasure is in progress and ’1’ Coded cycles. If the second command given is not
when it has completed. The Toggle bit DQ2 and an erase confirm or if the Coded cycles are wrong,
DQ6 toggle during the erase operation. They stop the instruction aborts and the device is reset to
when erase is completed. After completion the Read Array.It is notnecessary to program the array
Status Register bit DQ5 returns ’1’ if there has been with 00h first as the P/E.C.will automatically do this
an erase failure. In such a situation, the Toggle bit before erasing it to FFh. Read operations after the
DQ2 can be used to determine which block is not sixth rising edge of W or E output the Status Reg-
correctly erased. In the case of erase failure, a ister bits. During the execution of the erase by the
Read/Reset RD instruction is necessary in order to P/E.C., Data Polling bit DQ7 returns ’0’, then ’1’ on
reset the P/E.C. completion. The Toggle bits DQ2 and DQ6 toggle
Chip Erase(CE) Instruction. This instructionuses during erase operation and stop when erase is
six write cycles. The Erase Set-up command 80h completed.After completion the Status Register bit
is written to address AAAAh in the Byte-wide con- DQ5 returns ’1’ if there has been an Erase Failure.
figuration or the address 5555h in the Word-wide

13/30
M29F100T, M29F100B

Table 14. Read AC Characteristics

(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)

M29F100T / M29F100B
-70 -90 -120
Symbol Alt Parameter Test Condition VCC = 5V ± 5% VCC = 5V ± 10% V CC = 5V ± 10% Unit
High Speed Standard Standard
Interface Interface Interface
Min Max Min Max Min Max
Address Valid to Next
tAVAV tRC E = VIL, G = VIL 70 90 120 ns
Address Valid
Address Valid to
tAVQV tACC E = VIL, G = VIL 70 90 120 ns
Output Valid
Chip Enable Low to
tELQX (1) tLZ G = VIL 0 0 0 ns
Output Transition
Chip Enable Low to
tELQV (2) tCE G = VIL 70 90 120 ns
Output Valid
Output Enable Low
tGLQX (1) tOLZ E = VIL 0 0 0 ns
to Output Transition
Output Enable Low
tGLQV (2) tOE E = VIL 30 35 50 ns
to Output Valid
Chip Enable High to
tEHQX tOH G = VIL 0 0 0 ns
Output Transition
Chip Enable High to
tEHQZ (1) tHZ G = VIL 20 20 30 ns
Output Hi-Z
Output Enable High
tGHQX tOH E = VIL 0 0 0 ns
to Output Transition
(1) Output Enable High
tGHQZ tDF E = VIL 20 20 30 ns
to Output Hi-Z
Address Transition to
tAXQX tOH E = VIL, G = VIL 0 0 0 ns
Output Transition
tRRB RP Low to Read
tPLYH (1,3) 10 10 10 µs
tREADY Mode
RP High to Chip
tPHEL tRH 50 50 50 ns
Enable Low
tPLPX tRP RP Pulse Width 500 500 500 ns
Chip Enable to BYTE
tELBL tELFL
Switching Low or 5 5 5 ns
tELBH tELFH
High
BYTE Switching Low
tBLQZ tFLQZ to Output 30 40 40 ns
High Z
BYTE Switching
tBHQV tFHQV High to Output 30 40 40 ns
Valid
Notes: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.

14/30
 tAVAV
A0-A15/
VALID
A–1
tAVQV tAXQX

tELQV

E
Figure 6. Read Mode AC Waveforms

tEHQZ

tELQX tEHQX

tGLQV tGHQX

tGLQX tGHQZ
DQ0-DQ7/ VALID
DQ8-DQ15

BYTE

tELBL/tELBH tBLQZ

ADDRESS VALID OUTPUT ENABLE DATA VALID

AND CHIP ENABLE
AI01979B

Note: Write Enable (W) = High

M29F100T, M29F100B

15/30
M29F100T, M29F100B

Table 15. Write AC Characteristics,Write Enable Controlled

(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)

M29F100T / M29F100B
-70 -90 -120
Symbol Alt Parameter Unit
VCC = 5V ± 5% VCC = 5V ± 10% VCC = 5V ± 10%
High Speed Standard Standard
Interface Interface Interface
Min Max Min Max Min Max
tAVAV tWC Address Valid to Next Address Valid 70 90 120 ns
Chip Enable Low to Write Enable
tELWL tCS 0 0 0 ns
Low

Write Enable Low to Write Enable

tWLWH tWP 35 45 50 ns
High
tDVWH tDS Input Valid to Write Enable High 30 45 50 ns
Write Enable High to Input
tWHDX tDH 0 0 0 ns
Transition

Write Enable High to Chip Enable

tWHEH tCH 0 0 0 ns
High
Write Enable High to Write Enable
tWHWL tWPH 20 20 20 ns
Low
tAVWL tAS Address Valid to Write Enable Low 0 0 0 ns

Write Enable Low to Address

tWLAX tAH 45 45 50 ns
Transition
Output Enable High to Write
tGHWL 0 0 0 ns
Enable Low

tVCHEL tVCS VCC High to Chip Enable Low 50 50 50 µs

Write Enable High to Output
tWHGL tOEH 0 0 0 ns
Enable Low
tPHPHH (1,2) tVIDR RP Rise Time to VID 500 500 500 ns
tPLPX tRP RP Pulse Width 500 500 500 ns
(1)
tWHRL tBUSY Program Erase Valid to RB Delay 30 35 50 ns
(1)
tPHWL tRSP RP High to Write Enable Low 4 4 4 µs
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.

Erase Suspend(ES) Instruction.The BlockErase addition to suspending the erase, terminate the
operation may be suspended by this instruction timeout. The Toggle bit DQ6 stops toggling when
which consists of writing the command B0h without the P/E.C. is suspended. The Toggle bits will stop
any specific address. No Coded cycles are re- toggling between 0.1µs and 15µs after the Erase
quired.It permits reading of data from anotherblock Suspend (ES) command has been written. The
and programming in another block while an erase device will then automatically be set to Read Mem-
operation is in progress.Erasesuspend is accepted ory Array mode.When erase is suspended,a Read
only during the Block Erase instruction execution. from blocks being erased will output DQ2 toggling
Writing this command during Erase timeout will, in and DQ6 at ’1’. A Read from a block not being

16/30
 M29F100T, M29F100B

Figure 7. Write AC Waveforms, W Controlled

tAVAV
A0-A15/
VALID
A–1
tWLAX

tAVWL tWHEH

tELWL tWHGL

tGHWL tWLWH

tWHWL

tDVWH tWHDX
DQ0-DQ7/
VALID
DQ8-DQ15

VCC

tVCHEL

RB

tWHRL AI01980B

Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.

erased returns valid data. During suspension the POWER SUPPLY

memory will respond only to the Erase Resume ER
Power Up
and the Program PG instructions. A Program op-
erationcan be initiated during erase suspend in one The memory Command Interfaceis reset on power
of the blocks not being erased. It will result in both up to Read Array. Either E or W must be tied to VIH
DQ2 and DQ6 toggling when the data is being during Power Up to allow maximum security and
programmed. A Read/Reset command will defini- the possibility to write a command on the first rising
tively abort erasure and result in invalid data in the edge of E and W.Any write cycle initiation is blocked
blocks being erased. when Vcc is below VLKO.
Erase Resume (ER) Instruction. If an Erase Sus- Supply Rails
pend instruction was previously executed, the Normal precautions must be taken for supply volt-
erase operation may be resumed by giving the age decoupling; each device in a system should
command 30h, at any address, and without any
have the VCC rail decoupled with a 0.1µF capacitor
Coded cycles.
closeto the VCC and VSS pins.The PCB trace widths
should be sufficient to carry the VCC program and
erase currents required.

17/30
M29F100T, M29F100B

Table 16. Write AC Characteristics, Chip Enable Controlled

(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)

M29F100T / M29F100B
-70 -90 -120
Symbol Alt Parameter Unit
VCC = 5V ± 5% VCC = 5V ± 10% VCC = 5V ± 10%
High Speed Standard Standard
Interface Interface Interface
Min Max Min Max Min Max
Address Valid to Next Address
tAVAV tWC 70 90 120 ns
Valid
Write Enable Low to Chip
tWLEL tWS 0 0 0 ns
Enable Low
Chip Enable Low to Chip Enable
tELEH tCP 35 45 50 ns
High
tDVEH tDS Input Valid to Chip Enable High 30 45 50 ns
Chip Enable High to Input
tEHDX tDH 0 0 0 ns
Transition
Chip Enable High to Write
tEHWH tWH 0 0 0 ns
Enable High
Chip Enable High to Chip
tEHEL tCPH 20 20 20 ns
Enable Low
Address Valid to Chip Enable
tAVEL tAS 0 0 0 ns
Low
Chip Enable Low to Address
tELAX tAH 45 45 50 ns
Transition
Output Enable High Chip
tGHEL 0 0 0 ns
Enable Low

tVCHWL tVCS VCC High to Write Enable Low 50 50 50 µs

Chip Enable High to Output
tEHGL tOEH 0 0 0 ns
Enable Low
(1,2)
tPHPHH tVIDR RP Rise TIme to VID 500 500 500 ns
tPLPX tRP RP Pulse Width 500 500 500 ns

Program Erase Valid to RB

tEHRL (1) tBUSY 30 35 50 ns
Delay
tPHWL (1) tRSP RP High to Write Enable Low 4 4 4 µs
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.

18/30
 M29F100T, M29F100B

Figure 8. Write AC Waveforms, E Controlled

tAVAV
A0-A15/
VALID
A–1
tELAX

tAVEL tEHWH

tWLEL tEHGL

tGHEL tELEH

tEHEL

tDVEH tEHDX
DQ0-DQ7/
VALID
DQ8-DQ15

VCC

tVCHWL

RB

tEHRL AI01981B

Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.

Figure 9. Read and Write AC Characteristics, RP Related

tPHEL

tPHWL

RB

tPLPX
RP
tPHPHH

tPLYH

AI02091

19/30
M29F100T, M29F100B

Table 17. Data Polling and Toggle Bit AC Characteristics (1)

(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)

M29F100T / M29F100B
-70 -90 -120
Symbol Parameter Unit
VCC = 5V ± 5% VCC = 5V ± 10% VCC = 5V ± 10%
High Speed Standard Standard
Interface Interface Interface
Min Max Min Max Min Max
Write Enable High to DQ7 Valid
10 2400 10 2400 10 2400 µs
(Program, W Controlled)
tWHQ7V
Write Enable High to DQ7 Valid
1.0 30 1.0 30 1.0 30 sec
(Chip Erase, W Controlled)
Chip Enable High to DQ7 Valid
(Program, E Controlled)
10 2400 10 2400 10 2400 µs
tEHQ7V
Chip Enable High to DQ7 Valid
1.0 30 1.0 30 1.0 30 sec
(Chip Erase, E Controlled)
Q7 Valid to Output Valid (Data
tQ7VQV 30 35 50 ns
Polling)
Write Enable High to Output Valid
(Program)
10 2400 10 2400 10 2400 µs
tWHQV
Write Enable High to Output Valid
1.0 30 1.0 30 1.0 30 sec
(Chip Erase)
Chip Enable High to Output Valid
10 2400 10 2400 10 2400 µs
(Program)
tEHQV
Chip Enable High to Output Valid
1.0 30 1.0 30 1.0 30 sec
(Chip Erase)
Note: 1. All other timings are defined in Read AC Characteristics table.

20/30
 DATA OUTPUT VALID
A0-A15/
ADDRESS (WITHIN BLOCKS)
A–1
tAVQV

tELQV

tEHQ7V

G
Figure 10. Data Polling DQ7 AC Waveforms

tGLQV

W
tWHQ7V

DQ7 DQ7 VALID

DQ0-DQ6/
IGNORE VALID
DQ8-DQ15
tQ7VQV

LAST WRITE DATA POLLING DATA POLLING (LAST) CYCLE MEMORY

CYCLE OF READ CYCLES ARRAY
PROGRAM READ CYCLE
OR ERASE
INSTRUCTION AI01982B
M29F100T, M29F100B

21/30
M29F100T, M29F100B

Figure 11. Data Polling Flowchart Figure 12. Data Toggle Flowchart

START
START

READ
READ DQ5 & DQ7 DQ2, DQ5 & DQ6
at VALID ADDRESS

DQ7 YES DQ2, DQ6 NO

= =
DATA TOGGLE

NO YES

NO DQ5 NO DQ5
=1 =1
YES YES

READ DQ7 READ DQ2, DQ6

DQ7 YES
= DQ2, DQ6 NO
DATA =
TOGGLE
NO
YES
FAIL PASS
FAIL PASS

AI01369
AI01873

Table 18. Program, Erase Times and Program, Erase Endurance Cycles
(TA = 0 to 70°C; VCC = 5V ± 10% or 5V ± 5%)

M29F100T / M29F100B
Parameter Unit
Typical after
Min Typ
100k W/E Cycles

Chip Erase (Preprogrammed) 0.4 0.6 sec

Chip Erase 1.5 1.7 sec
Boot Block Erase 0.6 sec
Parameter Block Erase 0.5 sec
Main Block (32Kb) Erase 0.9 sec
Main Block (64Kb) Erase 1.0 sec
Chip Program (Byte) 1.4 1.4 sec
Byte Program 11 11 µs
Word Program 20 20 µs
Program/Erase Cycles (per Block) 100,000 cycles

22/30
 A0-A15/
A–1 VALID

tEHQV

tAVQV

tELQV

tGLQV
Figure 13. Data Toggle DQ6, DQ2 AC Waveforms

tWHQV

DQ6,DQ2 STOP TOGGLE VALID

DQ0-DQ1,DQ3-DQ5,DQ7/
IGNORE VALID
DQ8-DQ15

LAST WRITE DATA DATA TOGGLE MEMORY ARRAY

CYCLE OF TOGGLE READ CYCLE READ CYCLE
PROGRAM READ CYCLE
OF ERASE
INSTRUCTION
AI01983B

Note: All other timings are as a normal Read cycle.

M29F100T, M29F100B

23/30
M29F100T, M29F100B

Figure 14. Block Protection Flowchart

START

BLOCK ADDRESS
on A12-A15

W = VIH

Set-up
n=0

G, A9 = V ID,
E = VIL

Wait 4µs

W = VIL

Protect Wait 100µs

W = VIH

E, G = VIH
Verify

VERIFY BLOCK PROTECTION

A0, A6 = VIL ; A1 = V IH; A9 = VID
A12-A15 IDENTIFY BLOCK

E = VIL

Wait 4µs

G = VIL

Wait 60ns

VERIFY BLOCK
PROTECT STATUS

DATA NO
=
01h
YES

A9 = VIH
++n NO
= 25
PASS
YES

A9 = V IH

FAIL

AI01984C

24/30
 M29F100T, M29F100B

Figure 15. All Blocks Unprotecting Flowchart

START

PROTECT
ALL BLOCKS

n =0
Set-up

W = V IH

E, G, A9 = VID
A12, A15 = V IH

Wait 4µs

W = VIL

Wait 10ms Unprotect

W = V IH

E, G = VIH Verify

E, A0 = V IL; A1, A6 = V IH; A9 = V ID

A12-A15 IDENTIFY BLOCK NEXT
BLOCK

Wait 4µs

G = VIL

Wait 60ns

VERIFY BLOCK
PROTECT STATUS

NO DATA YES
=
00h

NO ++n LAST NO
= 1000 BLK.

YES YES

A9 = VIH A9 = VIH

FAIL PASS

AI01985D

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M29F100T, M29F100B

ORDERING INFORMATION SCHEME

Example: M29F100T -70 X N 1 TR

OperatingVoltage Option
F 5V R Reverse
Pinout
TR Tape & Reel
Packing

Array Matrix Speed Power Supplies Package Temp. Range

T Top Boot -70 70ns blank VCC ± 10% N TSOP48 1 0 to 70 °C
12 x 20mm
B Bottom Boot -90 90ns X VCC ± 5% 6 –40 to 85 °C
M SO44
-120 120ns 3 –40 to 125 °C

M29 F100T and M29F100B are replaced respectively by the new version M29F100BT and
M29F100BB.

Devices are shipped from the factory with the memory content erased (to FFh).

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.

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 M29F100T, M29F100B

TSOP48 Normal Pinout - 48 lead Plastic Thin Small Outline, 12 x 20mm

mm inches
Symb
Typ Min Max Typ Min Max
A 1.20 0.047
A1 0.05 0.15 0.002 0.006
A2 0.95 1.05 0.037 0.041
B 0.17 0.27 0.007 0.011
C 0.10 0.21 0.004 0.008
D 19.80 20.20 0.780 0.795
D1 18.30 18.50 0.720 0.728
E 11.90 12.10 0.469 0.476
e 0.50 - - 0.020 - -
L 0.50 0.70 0.020 0.028

α 0° 5° 0° 5°
N 48 48
CP 0.10 0.004

A2

1 N
e

B
N/2

D1 A
D CP

DIE

TSOP-a A1 α L

Drawing is not to scale.

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M29F100T, M29F100B

TSOP48 Reverse Pinout - 48 lead Plastic Thin Small Outline, 12 x 20mm

mm inches
Symb
Typ Min Max Typ Min Max
A 1.20 0.047
A1 0.05 0.15 0.002 0.006
A2 0.95 1.05 0.037 0.041
B 0.17 0.27 0.007 0.011
C 0.10 0.21 0.004 0.008
D 19.80 20.20 0.780 0.795
D1 18.30 18.50 0.720 0.728
E 11.90 12.10 0.469 0.476
e 0.50 – – 0.020 – –
L 0.50 0.70 0.020 0.028

α 0° 5° 0° 5°
N 48 48
CP 0.10 0.004

A2

1 N
e

B
N/2

D1 A
D CP

DIE

TSOP-b A1 α L

Drawing is not to scale.

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 M29F100T, M29F100B

SO44 - 44 lead Plastic Small Outline, 525 mils body width

mm inches
Symb
Typ Min Max Typ Min Max
A 2.42 2.62 0.095 0.103
A1 0.22 0.23 0.009 0.010
A2 2.25 2.35 0.089 0.093
B 0.50 0.020
C 0.10 0.25 0.004 0.010
D 28.10 28.30 1.106 1.114
E 13.20 13.40 0.520 0.528
e 1.27 0.050
H 15.90 16.10 0.626 0.634
L 0.80 0.031

α 3° 3°
N 44 44
CP 0.10 0.004

A2 A
C
B
e CP

E H
1
A1 α L

SO-b

Drawing is not to scale.

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M29F100T, M29F100B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of
use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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